[U-Boot] [PATCH 0/9] ARM: Support for splashimage om i.MX31-based phycore "eet" variant

[U-Boot] [PATCH 0/9] ARM: Support for splashimage om i.MX31-based phycore "eet" variant

[Guennadi Liakhovetski]

Hi,

this series of patches adds support for the graphics engine on i.MX31 SoC. 
Specifically it allows to display 8-bit BMPs on an OLED display, 
controlled by an SPI s6e63d6 controller from Samsung. A (fixed formatting) 
version of the

From: Mark Jackson <mpfj@mimc.co.uk>
Subject: [PATCH] Add 16bpp BMP support

patch is included for completeness. The cumulative diffstat is

 Makefile                              |    6
 board/imx31_phycore/imx31_phycore.c   |   51 ++
 common/lcd.c                          |  106 ++--
 drivers/gpio/Makefile                 |    3
 drivers/gpio/mx31_gpio.c              |   71 ++
 drivers/spi/mxc_spi.c                 |   99 +++
 drivers/video/Makefile                |    2
 drivers/video/mx3fb.c                 |  866 +++++++++++++++++++++++++++++++++-
 drivers/video/s6e63d6.c               |   68 ++
 include/asm-arm/arch-mx31/mx31-regs.h |   16
 include/asm-arm/arch-mx31/mx31.h      |   10
 include/configs/imx31_phycore.h       |   24
 include/lcd.h                         |   22
 include/s6e63d6.h                     |   37 +
 lib_arm/board.c                       |    7
 15 files changed, 1314 insertions(+), 74 deletions(-)

i.e., most changes go under drivers/video and to common/lcd.c, so, I would 
suggest to collect respective Acks and pull it through the video tree. 
Hence Anatolij is cc'ed on all patches:-) Also many need an Ack from the 
ARM maintainer, so, he is on cc on respective patches and on this one.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 1/9] i.MX31: fix SPI driver for shorter than 32 bit transfers

[Guennadi Liakhovetski]

Fix 8 and 16-bit transfers in mxc_spi driver and a wrong pointer in the 
free routine.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

No SPI custodian, so, Jean-Christophe will have to Ack it?

 drivers/spi/mxc_spi.c |   62 +++++++++++++++++++++++++++++++++++++++---------
 1 files changed, 50 insertions(+), 12 deletions(-)

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 5957ada..9267341 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -85,17 +85,12 @@ static inline void reg_write(unsigned long addr, u32 val)
 	*(volatile unsigned long*)addr = val;
 }
 
-static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
+static u32 spi_xchg_single(struct spi_slave *slave, u32 data,
+			   unsigned long flags)
 {
 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
 
-	if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) {
-		cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
-			MXC_CSPICTRL_BITCOUNT(bitlen - 1);
-		reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
-	}
-
 	reg_write(mxcs->base + MXC_CSPITXDATA, data);
 
 	cfg_reg |= MXC_CSPICTRL_XCH;
@@ -108,13 +103,46 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
 	return reg_read(mxcs->base + MXC_CSPIRXDATA);
 }
 
+/*
+ * bitlen is the total number of bits to be sent. Therefore, if you have to send
+ * using < 32-bit words, you have to send each single word individually. If
+ * bitlen > 32 we assume you meant to send 32-bit words...
+ */
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-		void *din, unsigned long flags)
+	     void *din, unsigned long flags)
 {
-	int n_blks = (bitlen + 31) / 32;
+	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+	int n_blks = bitlen / 32;
 	u32 *out_l, *in_l;
 	int i;
 
+	mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
+		MXC_CSPICTRL_BITCOUNT(bitlen - 1);
+
+	reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
+
+	if (bitlen <= 8) {
+		u32 iword, oword = *(const u8 *)dout;
+
+		iword = spi_xchg_single(slave, oword, flags);
+		*(u8 *)din = iword;
+		return 0;
+	}
+
+	if (bitlen <= 16) {
+		u32 iword, oword = *(const u16 *)dout;
+
+		if ((int)dout & 1 || (int)din & 1) {
+			printf("Error: unaligned buffers in: %p, out: %p\n",
+			       din, dout);
+			return 1;
+		}
+
+		iword = spi_xchg_single(slave, oword, flags);
+		*(u16 *)din = iword;
+		return 0;
+	}
+
 	if ((int)dout & 3 || (int)din & 3) {
 		printf("Error: unaligned buffers in: %p, out: %p\n", din, dout);
 		return 1;
@@ -122,8 +150,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 
 	for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
 	     i < n_blks;
-	     i++, in_l++, out_l++, bitlen -= 32)
-		*in_l = spi_xchg_single(slave, *out_l, bitlen);
+	     i++, in_l++, out_l++)
+		*in_l = spi_xchg_single(slave, *out_l, flags);
+
+	if (bitlen & 31) {
+		/* Exchange the residue, treat data as 32 bits */
+		mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
+			MXC_CSPICTRL_BITCOUNT((bitlen & 31) - 1);
+		reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
+
+		*in_l = spi_xchg_single(slave, *out_l, flags);
+	}
 
 	return 0;
 }
@@ -169,7 +206,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 
 void spi_free_slave(struct spi_slave *slave)
 {
-	free(slave);
+	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+	free(mxcs);
 }
 
 int spi_claim_bus(struct spi_slave *slave)
-- 
1.5.4

[U-Boot] [PATCH 2/9] i.MX31: add a simple gpio driver

[Guennadi Liakhovetski]

This is a minimal driver, so far only managing output. It will
be used by the mxc_spi.c driver.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Jean-Christophe: also an ack from you, please.

 drivers/gpio/Makefile            |    3 +-
 drivers/gpio/mx31_gpio.c         |   71 ++++++++++++++++++++++++++++++++++++++
 include/asm-arm/arch-mx31/mx31.h |    9 +++++
 3 files changed, 82 insertions(+), 1 deletions(-)
 create mode 100644 drivers/gpio/mx31_gpio.c

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index dd618ed..ce049e4 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk
 
 LIB 	:= $(obj)libgpio.a
 
-COBJS-$(CONFIG_PCA953X)	+= pca953x.o
+COBJS-$(CONFIG_PCA953X)		+= pca953x.o
+COBJS-$(CONFIG_MX31_GPIO)	+= mx31_gpio.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)
diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c
new file mode 100644
index 0000000..871601f
--- /dev/null
+++ b/drivers/gpio/mx31_gpio.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DEXN Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+/* GPIO port description */
+static unsigned long gpio_ports[] = {
+	[0] = 0x53fcc000,
+	[1] = 0x53fd0000,
+	[2] = 0x53fa4000,
+};
+
+void mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction)
+{
+	unsigned int port = gpio >> 5;
+	u32 l;
+
+	if (port > sizeof(gpio_ports) / sizeof(gpio_ports[0]) - 1)
+		return;
+
+	gpio &= 0x1f;
+
+	l = __REG(gpio_ports[port] + 4);
+	switch (direction) {
+	case MX31_GPIO_DIRECTION_OUT:
+		l |= 1 << gpio;
+		break;
+	case MX31_GPIO_DIRECTION_IN:
+		l &= ~(1 << gpio);
+	}
+	__REG(gpio_ports[port] + 4) = l;
+}
+
+void mx31_gpio_set(unsigned int gpio, unsigned int value)
+{
+	unsigned int port = gpio >> 5;
+	u32 l;
+
+	if (port > sizeof(gpio_ports) / sizeof(gpio_ports[0]) - 1)
+		return;
+
+	gpio &= 0x1f;
+
+	l = __REG(gpio_ports[port] + 0);
+	if (value)
+		l |= 1 << gpio;
+	else
+		l &= ~(1 << gpio);
+	__REG(gpio_ports[port] + 0) = l;
+}
diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h
index 0552c27..fb8d8c0 100644
--- a/include/asm-arm/arch-mx31/mx31.h
+++ b/include/asm-arm/arch-mx31/mx31.h
@@ -27,4 +27,13 @@
 extern u32 mx31_get_ipg_clk(void);
 extern void mx31_gpio_mux(unsigned long mode);
 
+enum mx31_gpio_direction {
+	MX31_GPIO_DIRECTION_IN,
+	MX31_GPIO_DIRECTION_OUT,
+};
+
+extern void mx31_gpio_direction(unsigned int gpio,
+				enum mx31_gpio_direction direction);
+extern void mx31_gpio_set(unsigned int gpio, unsigned int value);
+
 #endif /* __ASM_ARCH_MX31_H */
-- 
1.5.4

[U-Boot] [PATCH 3/9] i.MX31: support GPIO as a chip-select in the mxc_spi driver

[Guennadi Liakhovetski]

Some SPI devices have special requirements on chip-select handling.
With this patch we can use a GPIO as a chip-select and strictly follow
the SPI_XFER_BEGIN and SPI_XFER_END flags.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Jean-Christophe: one more for you to ack.

 drivers/spi/mxc_spi.c |   35 +++++++++++++++++++++++++++++------
 1 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 9267341..eacd36c 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -32,6 +32,8 @@
 
 #else
 
+#include <asm/arch/mx31.h>
+
 #define MXC_CSPIRXDATA		0x00
 #define MXC_CSPITXDATA		0x04
 #define MXC_CSPICTRL		0x08
@@ -68,6 +70,7 @@ struct mxc_spi_slave {
 	struct spi_slave slave;
 	unsigned long	base;
 	u32		ctrl_reg;
+	int		gpio;
 };
 
 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
@@ -91,6 +94,9 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data,
 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
 
+	if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
+		mx31_gpio_set(mxcs->gpio, !!(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
+
 	reg_write(mxcs->base + MXC_CSPITXDATA, data);
 
 	cfg_reg |= MXC_CSPICTRL_XCH;
@@ -100,6 +106,9 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data,
 	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
 		;
 
+	if (mxcs->gpio > 0 && (flags & SPI_XFER_END))
+		mx31_gpio_set(mxcs->gpio, !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
+
 	return reg_read(mxcs->base + MXC_CSPIRXDATA);
 }
 
@@ -175,10 +184,28 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	unsigned int ctrl_reg;
 	struct mxc_spi_slave *mxcs;
 
-	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) ||
-	    cs > 3)
+	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]))
+		return NULL;
+
+	mxcs = malloc(sizeof(struct mxc_spi_slave));
+	if (!mxcs)
 		return NULL;
 
+	/*
+	 * Some SPI devices require active chip-select over multiple
+	 * transactions, we achieve this using a GPIO. Still, the SPI
+	 * controller has to be configured to use one of its own chipselects.
+	 * To use this feature you have to call spi_setup_slave() with
+	 * cs = internal_cs | (gpio << 8), and you have to use some unused
+	 * on this SPI controller cs between 0 and 3.
+	 */
+	if (cs > 3) {
+		mxcs->gpio = cs >> 8;
+		cs &= 3;
+		mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT);
+	} else
+		mxcs->gpio = -1;
+
 	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
 		MXC_CSPICTRL_BITCOUNT(31) |
 		MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
@@ -192,10 +219,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (mode & SPI_CS_HIGH)
 		ctrl_reg |= MXC_CSPICTRL_SSPOL;
 
-	mxcs = malloc(sizeof(struct mxc_spi_slave));
-	if (!mxcs)
-		return NULL;
-
 	mxcs->slave.bus = bus;
 	mxcs->slave.cs = cs;
 	mxcs->base = spi_bases[bus];
-- 
1.5.4

[U-Boot] [PATCH 4/9] A driver for the S6E63D6 SPI display controller from Samsung

[Guennadi Liakhovetski]

This is a driver for the S6E63D6 SPI OLED display controller from Samsung. 
It only provides access to controller's registers so the client can freely 
configure it.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---
 drivers/video/Makefile  |    1 +
 drivers/video/s6e63d6.c |   68 +++++++++++++++++++++++++++++++++++++++++++++++
 include/s6e63d6.h       |   36 +++++++++++++++++++++++++
 3 files changed, 105 insertions(+), 0 deletions(-)
 create mode 100644 drivers/video/s6e63d6.c
 create mode 100644 include/s6e63d6.h

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7fba29f..a7dc74c 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_SED156X) += sed156x.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
 COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
+COBJS-$(CONFIG_DISPLAY_S6E63D6) += s6e63d6.o
 COBJS-y += videomodes.o
 
 COBJS	:= $(COBJS-y)
diff --git a/drivers/video/s6e63d6.c b/drivers/video/s6e63d6.c
new file mode 100644
index 0000000..27ff976
--- /dev/null
+++ b/drivers/video/s6e63d6.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DEXN Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <spi.h>
+#include <s6e63d6.h>
+
+/* Hardware selected value - 0 or 0x4 */
+#define ID 0
+
+/*
+ * Each transfer is performed as:
+ * 1. chip-select active
+ * 2. send 8-bit start code
+ * 3. send 16-bit data
+ * 4. chip-select inactive
+ */
+static int send_word(struct spi_slave *spi, u8 rs, u16 data)
+{
+	u32 buf8 = 0x70 | ID | (rs & 2);
+	u32 buf16 = cpu_to_le16(data);
+	u32 buf_in;
+	int err;
+
+	err = spi_xfer(spi, 8, &buf8, &buf_in, SPI_XFER_BEGIN);
+	if (err)
+		return err;
+	return spi_xfer(spi, 16, &buf16, &buf_in, SPI_XFER_END);
+}
+
+/* Index and param differ in Register Select bit */
+int s6e63d6_index(struct s6e63d6 *data, u8 idx)
+{
+	return send_word(data->slave, 0, idx);
+}
+
+int s6e63d6_param(struct s6e63d6 *data, u16 param)
+{
+	return send_word(data->slave, 2, param);
+}
+
+int s6e63d6_init(struct s6e63d6 *data)
+{
+	data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3);
+	if (!data->slave)
+		return 1;
+
+	return 0;
+}
diff --git a/include/s6e63d6.h b/include/s6e63d6.h
new file mode 100644
index 0000000..9665dc5
--- /dev/null
+++ b/include/s6e63d6.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DEXN Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _S6E63D6_H_
+#define _S6E63D6_H_
+
+struct s6e63d6 {
+	unsigned int bus;
+	unsigned int cs;
+	struct spi_slave *slave;
+};
+
+extern int s6e63d6_init(struct s6e63d6 *);
+extern int s6e63d6_index(struct s6e63d6 *, u8);
+extern int s6e63d6_param(struct s6e63d6 *, u16);
+
+#endif
-- 
1.5.4

[U-Boot] [PATCH 5/9] ARM: remove unused variable

[Guennadi Liakhovetski]

The "size" variable in start_armboot() in lib_arm/board.c is only really 
used in
#if !defined(CONFIG_SYS_NO_FLASH)
case, remove where unused.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

This one actually doesn't have to be in this series, so, it can go 
separately over the ARM tree.

 lib_arm/board.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib_arm/board.c b/lib_arm/board.c
index 964f5cc..2257b2e 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -287,7 +287,7 @@ void start_armboot (void)
 {
 	init_fnc_t **init_fnc_ptr;
 	char *s;
-#if !defined(CONFIG_SYS_NO_FLASH) || defined (CONFIG_VFD) || defined(CONFIG_LCD)
+#if !defined(CONFIG_SYS_NO_FLASH)
 	ulong size;
 #endif
 #if defined(CONFIG_VFD) || defined(CONFIG_LCD)
@@ -328,7 +328,7 @@ void start_armboot (void)
 	 */
 	/* bss_end is defined in the board-specific linker script */
 	addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
-	size = vfd_setmem (addr);
+	vfd_setmem (addr);
 	gd->fb_base = addr;
 #endif /* CONFIG_VFD */
 
@@ -343,7 +343,7 @@ void start_armboot (void)
 		 */
 		/* bss_end is defined in the board-specific linker script */
 		addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
-		size = lcd_setmem (addr);
+		lcd_setmem (addr);
 		gd->fb_base = addr;
 	}
 #endif /* CONFIG_LCD */
-- 
1.5.4

[U-Boot] [PATCH 6/9] Add 16bpp BMP support

[Guennadi Liakhovetski]

From: Mark Jackson <mpfj@mimc.co.uk>

This patch adds 16bpp BMP support to the common lcd code.

Use CONFIG_BMP_16BPP and set LCD_BPP to LCD_COLOR16 to enable the code.

At the moment it's only been tested on the MIMC200 AVR32 board, but extending
this to other platforms should be a simple task !!

Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---
 common/lcd.c |   49 +++++++++++++++++++++++++++++++++++++++----------
 1 files changed, 39 insertions(+), 10 deletions(-)

diff --git a/common/lcd.c b/common/lcd.c
index 5f73247..14a0d01 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -84,7 +84,7 @@ extern void lcd_enable (void);
 static void *lcd_logo (void);
 
 
-#if LCD_BPP == LCD_COLOR8
+#if (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
 extern void lcd_setcolreg (ushort regno,
 				ushort red, ushort green, ushort blue);
 #endif
@@ -656,7 +656,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 
 	bpix = NBITS(panel_info.vl_bpix);
 
-	if ((bpix != 1) && (bpix != 8)) {
+	if ((bpix != 1) && (bpix != 8) && (bpix != 16)) {
 		printf ("Error: %d bit/pixel mode not supported by U-Boot\n",
 			bpix);
 		return 1;
@@ -738,17 +738,46 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
 	fb   = (uchar *) (lcd_base +
 		(y + height - 1) * lcd_line_length + x);
-	for (i = 0; i < height; ++i) {
-		WATCHDOG_RESET();
-		for (j = 0; j < width ; j++)
+
+	switch (bpix) {
+	case 1: /* pass through */
+	case 8:
+		for (i = 0; i < height; ++i) {
+			WATCHDOG_RESET();
+			for (j = 0; j < width ; j++)
 #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
-			*(fb++) = *(bmap++);
+				*(fb++) = *(bmap++);
 #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
-			*(fb++)=255-*(bmap++);
+				*(fb++)=255-*(bmap++);
 #endif
-		bmap += (width - padded_line);
-		fb   -= (width + lcd_line_length);
-	}
+			bmap += (width - padded_line);
+			fb   -= (width + lcd_line_length);
+		}
+		break;
+
+#if defined(CONFIG_BMP_16BPP)
+	case 16:
+		for (i = 0; i < height; ++i) {
+			WATCHDOG_RESET();
+			for (j = 0; j < width; j++) {
+#if defined(CONFIG_ATMEL_LCD_BGR555)
+				*(fb++) = ((bmap[0] & 0x1f) << 2) | (bmap[1] & 0x03);
+				*(fb++) = (bmap[0] & 0xe0) | ((bmap[1] & 0x7c) >> 2);
+				bmap += 2;
+#else
+				*(fb++) = *(bmap++);
+				*(fb++) = *(bmap++);
+#endif
+			}
+			bmap += (padded_line - width) * 2;
+			fb   -= (width * 2 + lcd_line_length);
+		}
+		break;
+#endif /* CONFIG_BMP_16BPP */
+
+	default:
+		break;
+	};
 
 	return (0);
 }
-- 
1.5.4

[U-Boot] [PATCH 7/9] LCD: support 8bpp BMPs on 16bpp displays

[Guennadi Liakhovetski]

This patch also simplifies some ifdefs in lcd.c, introduces a generic
vidinfo_t, which new drivers are encouraged to use and old drivers to switch
over to.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---
 common/lcd.c  |   56 ++++++++++++++++++++++++++++++++------------------------
 include/lcd.h |   21 +++++++++++++--------
 2 files changed, 45 insertions(+), 32 deletions(-)

diff --git a/common/lcd.c b/common/lcd.c
index 14a0d01..ef0d488 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -622,19 +622,15 @@ void bitmap_plot (int x, int y)
  */
 int lcd_display_bitmap(ulong bmp_image, int x, int y)
 {
-#ifdef CONFIG_ATMEL_LCD
-	uint *cmap;
-#elif !defined(CONFIG_MCC200)
-	ushort *cmap;
-#endif
+	ushort *cmap = NULL, *cmap_base = NULL;
 	ushort i, j;
 	uchar *fb;
 	bmp_image_t *bmp=(bmp_image_t *)bmp_image;
 	uchar *bmap;
 	ushort padded_line;
-	unsigned long width, height;
+	unsigned long width, height, byte_width;
 	unsigned long pwidth = panel_info.vl_col;
-	unsigned colors,bpix;
+	unsigned colors, bpix, bmp_bpix;
 	unsigned long compression;
 #if defined(CONFIG_PXA250)
 	struct pxafb_info *fbi = &panel_info.pxa;
@@ -647,22 +643,24 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		(bmp->header.signature[1]=='M'))) {
 		printf ("Error: no valid bmp image at %lx\n", bmp_image);
 		return 1;
-}
+	}
 
 	width = le32_to_cpu (bmp->header.width);
 	height = le32_to_cpu (bmp->header.height);
-	colors = 1<<le16_to_cpu (bmp->header.bit_count);
+	bmp_bpix = le16_to_cpu(bmp->header.bit_count);
+	colors = 1 << bmp_bpix;
 	compression = le32_to_cpu (bmp->header.compression);
 
 	bpix = NBITS(panel_info.vl_bpix);
 
 	if ((bpix != 1) && (bpix != 8) && (bpix != 16)) {
-		printf ("Error: %d bit/pixel mode not supported by U-Boot\n",
-			bpix);
+		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
+			bpix, bmp_bpix);
 		return 1;
 	}
 
-	if (bpix != le16_to_cpu(bmp->header.bit_count)) {
+	/* We support displaying 8bpp BMPs on 16bpp LCDs */
+	if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16)) {
 		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
 			bpix,
 			le16_to_cpu(bmp->header.bit_count));
@@ -674,17 +672,17 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 
 #if !defined(CONFIG_MCC200)
 	/* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
-	if (bpix==8) {
+	if (bmp_bpix == 8) {
 #if defined(CONFIG_PXA250)
 		cmap = (ushort *)fbi->palette;
 #elif defined(CONFIG_MPC823)
 		cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
-#elif defined(CONFIG_ATMEL_LCD)
-		cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0));
-#else
-# error "Don't know location of color map"
+#elif !defined(CONFIG_ATMEL_LCD)
+		cmap = panel_info.cmap;
 #endif
 
+		cmap_base = cmap;
+
 		/* Set color map */
 		for (i=0; i<colors; ++i) {
 			bmp_color_table_entry_t cte = bmp->color_table[i];
@@ -698,10 +696,10 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 #else
 			*cmap = colreg;
 #endif
-#if defined(CONFIG_PXA250)
-			cmap++;
-#elif defined(CONFIG_MPC823)
+#if defined(CONFIG_MPC823)
 			cmap--;
+#else
+			cmap++;
 #endif
 #else /* CONFIG_ATMEL_LCD */
 			lcd_setcolreg(i, cte.red, cte.green, cte.blue);
@@ -739,19 +737,29 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	fb   = (uchar *) (lcd_base +
 		(y + height - 1) * lcd_line_length + x);
 
-	switch (bpix) {
+	switch (bmp_bpix) {
 	case 1: /* pass through */
 	case 8:
+		if (bpix != 16)
+			byte_width = width;
+		else
+			byte_width = width * 2;
+
 		for (i = 0; i < height; ++i) {
 			WATCHDOG_RESET();
 			for (j = 0; j < width ; j++)
+				if (bpix!=16) {
 #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
-				*(fb++) = *(bmap++);
+					*(fb++) = *(bmap++);
 #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
-				*(fb++)=255-*(bmap++);
+					*(fb++) = 255 - *(bmap++);
 #endif
+				} else {
+					*(uint16_t *)fb = cmap_base[*(bmap++)];
+					fb += sizeof(uint16_t) / sizeof(*fb);
+				}
 			bmap += (width - padded_line);
-			fb   -= (width + lcd_line_length);
+			fb   -= (byte_width + lcd_line_length);
 		}
 		break;
 
diff --git a/include/lcd.h b/include/lcd.h
index 512221e..f054cac 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -148,14 +148,6 @@ typedef struct vidinfo {
 
 extern vidinfo_t panel_info;
 
-#elif defined(CONFIG_MCC200)
-typedef struct vidinfo {
-	ushort	vl_col;		/* Number of columns (i.e. 160) */
-	ushort	vl_row;		/* Number of rows (i.e. 100) */
-
-	u_char	vl_bpix;	/* Bits per pixel, 0 = 1 */
-} vidinfo_t;
-
 #elif defined(CONFIG_ATMEL_LCD)
 
 typedef struct vidinfo {
@@ -183,6 +175,19 @@ typedef struct vidinfo {
 
 extern vidinfo_t panel_info;
 
+#else
+
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 160) */
+	ushort	vl_row;		/* Number of rows (i.e. 100) */
+
+	u_char	vl_bpix;	/* Bits per pixel, 0 = 1 */
+
+	ushort	*cmap;		/* Pointer to the colormap */
+
+	void	*priv;		/* Pointer to driver-specific data */
+} vidinfo_t;
+
 #endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */
 
 /* Video functions */
-- 
1.5.4

[U-Boot] [PATCH 8/9] video: add a i.MX31 framebuffer driver only for bitmaps so far

[Guennadi Liakhovetski]

Add a driver for the Synchronous Display Controller and the Display
Interface on i.MX31, using IPU for DMA channel setup. So far only
displaying of bitmaps is supported, no text output.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---
 drivers/video/Makefile |    1 +
 drivers/video/mx3fb.c  |  865 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 866 insertions(+), 0 deletions(-)
 create mode 100644 drivers/video/mx3fb.c

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index a7dc74c..2d3711e 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_SED156X) += sed156x.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
 COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
 COBJS-$(CONFIG_DISPLAY_S6E63D6) += s6e63d6.o
+COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
 COBJS-y += videomodes.o
 
 COBJS	:= $(COBJS-y)
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
new file mode 100644
index 0000000..df5193f
--- /dev/null
+++ b/drivers/video/mx3fb.c
@@ -0,0 +1,865 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DEXN Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <lcd.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+#include <asm/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *lcd_base;			/* Start of framebuffer memory	*/
+void *lcd_console_address;	/* Start of console buffer	*/
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
+
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+void lcd_panel_disable(void)
+{
+}
+
+#define msleep(a) udelay(a * 1000)
+
+#define XRES		240
+#define YRES		320
+#define PANEL_TYPE	IPU_PANEL_TFT
+#define PIXEL_CLK	185925
+#define PIXEL_FMT	IPU_PIX_FMT_RGB666
+#define H_START_WIDTH	9		/* left_margin */
+#define H_SYNC_WIDTH	1		/* hsync_len */
+#define H_END_WIDTH	(16 + 1)	/* right_margin + hsync_len */
+#define V_START_WIDTH	7		/* upper_margin */
+#define V_SYNC_WIDTH	1		/* vsync_len */
+#define V_END_WIDTH	(9 + 1)		/* lower_margin + vsync_len */
+#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
+#define IF_CONF		0
+#define IF_CLK_DIV	0x175
+
+#define LCD_COLOR_IPU	LCD_COLOR16
+
+static ushort colormap[256];
+
+vidinfo_t panel_info = {
+	.vl_col		= XRES,
+	.vl_row		= YRES,
+	.vl_bpix	= LCD_COLOR_IPU,
+	.cmap		= colormap,
+};
+
+#define BIT_PER_PIXEL	NBITS(LCD_COLOR_IPU)
+
+/* IPU DMA Controller channel definitions. */
+enum ipu_channel {
+	IDMAC_IC_0 = 0,		/* IC (encoding task) to memory */
+	IDMAC_IC_1 = 1,		/* IC (viewfinder task) to memory */
+	IDMAC_ADC_0 = 1,
+	IDMAC_IC_2 = 2,
+	IDMAC_ADC_1 = 2,
+	IDMAC_IC_3 = 3,
+	IDMAC_IC_4 = 4,
+	IDMAC_IC_5 = 5,
+	IDMAC_IC_6 = 6,
+	IDMAC_IC_7 = 7,		/* IC (sensor data) to memory */
+	IDMAC_IC_8 = 8,
+	IDMAC_IC_9 = 9,
+	IDMAC_IC_10 = 10,
+	IDMAC_IC_11 = 11,
+	IDMAC_IC_12 = 12,
+	IDMAC_IC_13 = 13,
+	IDMAC_SDC_0 = 14,	/* Background synchronous display data */
+	IDMAC_SDC_1 = 15,	/* Foreground data (overlay) */
+	IDMAC_SDC_2 = 16,
+	IDMAC_SDC_3 = 17,
+	IDMAC_ADC_2 = 18,
+	IDMAC_ADC_3 = 19,
+	IDMAC_ADC_4 = 20,
+	IDMAC_ADC_5 = 21,
+	IDMAC_ADC_6 = 22,
+	IDMAC_ADC_7 = 23,
+	IDMAC_PF_0 = 24,
+	IDMAC_PF_1 = 25,
+	IDMAC_PF_2 = 26,
+	IDMAC_PF_3 = 27,
+	IDMAC_PF_4 = 28,
+	IDMAC_PF_5 = 29,
+	IDMAC_PF_6 = 30,
+	IDMAC_PF_7 = 31,
+};
+
+/* More formats can be copied from the Linux driver if needed */
+enum pixel_fmt {
+	/* 2 bytes */
+	IPU_PIX_FMT_RGB565,
+	IPU_PIX_FMT_RGB666,
+	IPU_PIX_FMT_BGR666,
+	/* 3 bytes */
+	IPU_PIX_FMT_RGB24,
+};
+
+struct pixel_fmt_cfg {
+	u32	b0;
+	u32	b1;
+	u32	b2;
+	u32	acc;
+};
+
+static struct pixel_fmt_cfg fmt_cfg[] = {
+	[IPU_PIX_FMT_RGB24] = {
+		0x1600AAAA, 0x00E05555, 0x00070000, 3,
+	},
+	[IPU_PIX_FMT_RGB666] = {
+		0x0005000F, 0x000B000F, 0x0011000F, 1,
+	},
+	[IPU_PIX_FMT_BGR666] = {
+		0x0011000F, 0x000B000F, 0x0005000F, 1,
+	},
+	[IPU_PIX_FMT_RGB565] = {
+		0x0004003F, 0x000A000F, 0x000F003F, 1,
+	}
+};
+
+enum ipu_panel {
+	IPU_PANEL_SHARP_TFT,
+	IPU_PANEL_TFT,
+};
+
+/* IPU Common registers */
+/* IPU_CONF and its bits already defined in mx31-regs.h */
+#define IPU_CHA_BUF0_RDY	(0x04 + IPU_BASE)
+#define IPU_CHA_BUF1_RDY	(0x08 + IPU_BASE)
+#define IPU_CHA_DB_MODE_SEL	(0x0C + IPU_BASE)
+#define IPU_CHA_CUR_BUF		(0x10 + IPU_BASE)
+#define IPU_FS_PROC_FLOW	(0x14 + IPU_BASE)
+#define IPU_FS_DISP_FLOW	(0x18 + IPU_BASE)
+#define IPU_TASKS_STAT		(0x1C + IPU_BASE)
+#define IPU_IMA_ADDR		(0x20 + IPU_BASE)
+#define IPU_IMA_DATA		(0x24 + IPU_BASE)
+#define IPU_INT_CTRL_1		(0x28 + IPU_BASE)
+#define IPU_INT_CTRL_2		(0x2C + IPU_BASE)
+#define IPU_INT_CTRL_3		(0x30 + IPU_BASE)
+#define IPU_INT_CTRL_4		(0x34 + IPU_BASE)
+#define IPU_INT_CTRL_5		(0x38 + IPU_BASE)
+#define IPU_INT_STAT_1		(0x3C + IPU_BASE)
+#define IPU_INT_STAT_2		(0x40 + IPU_BASE)
+#define IPU_INT_STAT_3		(0x44 + IPU_BASE)
+#define IPU_INT_STAT_4		(0x48 + IPU_BASE)
+#define IPU_INT_STAT_5		(0x4C + IPU_BASE)
+#define IPU_BRK_CTRL_1		(0x50 + IPU_BASE)
+#define IPU_BRK_CTRL_2		(0x54 + IPU_BASE)
+#define IPU_BRK_STAT		(0x58 + IPU_BASE)
+#define IPU_DIAGB_CTRL		(0x5C + IPU_BASE)
+
+/* Image Converter Registers */
+#define IC_CONF			(0x88 + IPU_BASE)
+#define IC_PRP_ENC_RSC		(0x8C + IPU_BASE)
+#define IC_PRP_VF_RSC		(0x90 + IPU_BASE)
+#define IC_PP_RSC		(0x94 + IPU_BASE)
+#define IC_CMBP_1		(0x98 + IPU_BASE)
+#define IC_CMBP_2		(0x9C + IPU_BASE)
+#define PF_CONF			(0xA0 + IPU_BASE)
+#define IDMAC_CONF		(0xA4 + IPU_BASE)
+#define IDMAC_CHA_EN		(0xA8 + IPU_BASE)
+#define IDMAC_CHA_PRI		(0xAC + IPU_BASE)
+#define IDMAC_CHA_BUSY		(0xB0 + IPU_BASE)
+
+/* Image Converter Register bits */
+#define IC_CONF_PRPENC_EN	0x00000001
+#define IC_CONF_PRPENC_CSC1	0x00000002
+#define IC_CONF_PRPENC_ROT_EN	0x00000004
+#define IC_CONF_PRPVF_EN	0x00000100
+#define IC_CONF_PRPVF_CSC1	0x00000200
+#define IC_CONF_PRPVF_CSC2	0x00000400
+#define IC_CONF_PRPVF_CMB	0x00000800
+#define IC_CONF_PRPVF_ROT_EN	0x00001000
+#define IC_CONF_PP_EN		0x00010000
+#define IC_CONF_PP_CSC1		0x00020000
+#define IC_CONF_PP_CSC2		0x00040000
+#define IC_CONF_PP_CMB		0x00080000
+#define IC_CONF_PP_ROT_EN	0x00100000
+#define IC_CONF_IC_GLB_LOC_A	0x10000000
+#define IC_CONF_KEY_COLOR_EN	0x20000000
+#define IC_CONF_RWS_EN		0x40000000
+#define IC_CONF_CSI_MEM_WR_EN	0x80000000
+
+/* SDC Registers */
+#define SDC_COM_CONF		(0xB4 + IPU_BASE)
+#define SDC_GW_CTRL		(0xB8 + IPU_BASE)
+#define SDC_FG_POS		(0xBC + IPU_BASE)
+#define SDC_BG_POS		(0xC0 + IPU_BASE)
+#define SDC_CUR_POS		(0xC4 + IPU_BASE)
+#define SDC_PWM_CTRL		(0xC8 + IPU_BASE)
+#define SDC_CUR_MAP		(0xCC + IPU_BASE)
+#define SDC_HOR_CONF		(0xD0 + IPU_BASE)
+#define SDC_VER_CONF		(0xD4 + IPU_BASE)
+#define SDC_SHARP_CONF_1	(0xD8 + IPU_BASE)
+#define SDC_SHARP_CONF_2	(0xDC + IPU_BASE)
+
+/* Register bits */
+#define SDC_COM_TFT_COLOR	0x00000001UL
+#define SDC_COM_FG_EN		0x00000010UL
+#define SDC_COM_GWSEL		0x00000020UL
+#define SDC_COM_GLB_A		0x00000040UL
+#define SDC_COM_KEY_COLOR_G	0x00000080UL
+#define SDC_COM_BG_EN		0x00000200UL
+#define SDC_COM_SHARP		0x00001000UL
+
+#define SDC_V_SYNC_WIDTH_L	0x00000001UL
+
+/* Display Interface registers */
+#define DI_DISP_IF_CONF		(0x0124 + IPU_BASE)
+#define DI_DISP_SIG_POL		(0x0128 + IPU_BASE)
+#define DI_SER_DISP1_CONF	(0x012C + IPU_BASE)
+#define DI_SER_DISP2_CONF	(0x0130 + IPU_BASE)
+#define DI_HSP_CLK_PER		(0x0134 + IPU_BASE)
+#define DI_DISP0_TIME_CONF_1	(0x0138 + IPU_BASE)
+#define DI_DISP0_TIME_CONF_2	(0x013C + IPU_BASE)
+#define DI_DISP0_TIME_CONF_3	(0x0140 + IPU_BASE)
+#define DI_DISP1_TIME_CONF_1	(0x0144 + IPU_BASE)
+#define DI_DISP1_TIME_CONF_2	(0x0148 + IPU_BASE)
+#define DI_DISP1_TIME_CONF_3	(0x014C + IPU_BASE)
+#define DI_DISP2_TIME_CONF_1	(0x0150 + IPU_BASE)
+#define DI_DISP2_TIME_CONF_2	(0x0154 + IPU_BASE)
+#define DI_DISP2_TIME_CONF_3	(0x0158 + IPU_BASE)
+#define DI_DISP3_TIME_CONF	(0x015C + IPU_BASE)
+#define DI_DISP0_DB0_MAP	(0x0160 + IPU_BASE)
+#define DI_DISP0_DB1_MAP	(0x0164 + IPU_BASE)
+#define DI_DISP0_DB2_MAP	(0x0168 + IPU_BASE)
+#define DI_DISP0_CB0_MAP	(0x016C + IPU_BASE)
+#define DI_DISP0_CB1_MAP	(0x0170 + IPU_BASE)
+#define DI_DISP0_CB2_MAP	(0x0174 + IPU_BASE)
+#define DI_DISP1_DB0_MAP	(0x0178 + IPU_BASE)
+#define DI_DISP1_DB1_MAP	(0x017C + IPU_BASE)
+#define DI_DISP1_DB2_MAP	(0x0180 + IPU_BASE)
+#define DI_DISP1_CB0_MAP	(0x0184 + IPU_BASE)
+#define DI_DISP1_CB1_MAP	(0x0188 + IPU_BASE)
+#define DI_DISP1_CB2_MAP	(0x018C + IPU_BASE)
+#define DI_DISP2_DB0_MAP	(0x0190 + IPU_BASE)
+#define DI_DISP2_DB1_MAP	(0x0194 + IPU_BASE)
+#define DI_DISP2_DB2_MAP	(0x0198 + IPU_BASE)
+#define DI_DISP2_CB0_MAP	(0x019C + IPU_BASE)
+#define DI_DISP2_CB1_MAP	(0x01A0 + IPU_BASE)
+#define DI_DISP2_CB2_MAP	(0x01A4 + IPU_BASE)
+#define DI_DISP3_B0_MAP		(0x01A8 + IPU_BASE)
+#define DI_DISP3_B1_MAP		(0x01AC + IPU_BASE)
+#define DI_DISP3_B2_MAP		(0x01B0 + IPU_BASE)
+#define DI_DISP_ACC_CC		(0x01B4 + IPU_BASE)
+#define DI_DISP_LLA_CONF	(0x01B8 + IPU_BASE)
+#define DI_DISP_LLA_DATA	(0x01BC + IPU_BASE)
+
+/* DI_DISP_SIG_POL bits */
+#define DI_D3_VSYNC_POL		(1 << 28)
+#define DI_D3_HSYNC_POL		(1 << 27)
+#define DI_D3_DRDY_SHARP_POL	(1 << 26)
+#define DI_D3_CLK_POL		(1 << 25)
+#define DI_D3_DATA_POL		(1 << 24)
+
+/* DI_DISP_IF_CONF bits */
+#define DI_D3_CLK_IDLE		(1 << 26)
+#define DI_D3_CLK_SEL		(1 << 25)
+#define DI_D3_DATAMSK		(1 << 24)
+
+#define IOMUX_PADNUM_MASK	0x1ff
+#define IOMUX_GPIONUM_SHIFT	9
+#define IOMUX_GPIONUM_MASK	(0xff << IOMUX_GPIONUM_SHIFT)
+
+#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
+
+#define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode)
+
+enum lcd_pin {
+	MX31_PIN_D3_SPL		= IOMUX_PIN(0xff,  19),
+	MX31_PIN_D3_CLS		= IOMUX_PIN(0xff,  20),
+	MX31_PIN_D3_REV		= IOMUX_PIN(0xff,  21),
+	MX31_PIN_CONTRAST	= IOMUX_PIN(0xff,  22),
+	MX31_PIN_VSYNC3		= IOMUX_PIN(0xff,  23),
+
+	MX31_PIN_DRDY0		= IOMUX_PIN(0xff,  33),
+	MX31_PIN_FPSHIFT	= IOMUX_PIN(0xff,  34),
+	MX31_PIN_HSYNC		= IOMUX_PIN(0xff,  35),
+
+	MX31_PIN_LD17		= IOMUX_PIN(0xff,  37),
+	MX31_PIN_LD16		= IOMUX_PIN(0xff,  38),
+	MX31_PIN_LD15		= IOMUX_PIN(0xff,  39),
+	MX31_PIN_LD14		= IOMUX_PIN(0xff,  40),
+	MX31_PIN_LD13		= IOMUX_PIN(0xff,  41),
+	MX31_PIN_LD12		= IOMUX_PIN(0xff,  42),
+	MX31_PIN_LD11		= IOMUX_PIN(0xff,  43),
+	MX31_PIN_LD10		= IOMUX_PIN(0xff,  44),
+	MX31_PIN_LD9		= IOMUX_PIN(0xff,  45),
+	MX31_PIN_LD8		= IOMUX_PIN(0xff,  46),
+	MX31_PIN_LD7		= IOMUX_PIN(0xff,  47),
+	MX31_PIN_LD6		= IOMUX_PIN(0xff,  48),
+	MX31_PIN_LD5		= IOMUX_PIN(0xff,  49),
+	MX31_PIN_LD4		= IOMUX_PIN(0xff,  50),
+	MX31_PIN_LD3		= IOMUX_PIN(0xff,  51),
+	MX31_PIN_LD2		= IOMUX_PIN(0xff,  52),
+	MX31_PIN_LD1		= IOMUX_PIN(0xff,  53),
+	MX31_PIN_LD0		= IOMUX_PIN(0xff,  54),
+};
+
+struct chan_param_mem_planar {
+	/* Word 0 */
+	u32	xv:10;
+	u32	yv:10;
+	u32	xb:12;
+
+	u32	yb:12;
+	u32	res1:2;
+	u32	nsb:1;
+	u32	lnpb:6;
+	u32	ubo_l:11;
+
+	u32	ubo_h:15;
+	u32	vbo_l:17;
+
+	u32	vbo_h:9;
+	u32	res2:3;
+	u32	fw:12;
+	u32	fh_l:8;
+
+	u32	fh_h:4;
+	u32	res3:28;
+
+	/* Word 1 */
+	u32	eba0;
+
+	u32	eba1;
+
+	u32	bpp:3;
+	u32	sl:14;
+	u32	pfs:3;
+	u32	bam:3;
+	u32	res4:2;
+	u32	npb:6;
+	u32	res5:1;
+
+	u32	sat:2;
+	u32	res6:30;
+} __attribute__ ((packed));
+
+struct chan_param_mem_interleaved {
+	/* Word 0 */
+	u32	xv:10;
+	u32	yv:10;
+	u32	xb:12;
+
+	u32	yb:12;
+	u32	sce:1;
+	u32	res1:1;
+	u32	nsb:1;
+	u32	lnpb:6;
+	u32	sx:10;
+	u32	sy_l:1;
+
+	u32	sy_h:9;
+	u32	ns:10;
+	u32	sm:10;
+	u32	sdx_l:3;
+
+	u32	sdx_h:2;
+	u32	sdy:5;
+	u32	sdrx:1;
+	u32	sdry:1;
+	u32	sdr1:1;
+	u32	res2:2;
+	u32	fw:12;
+	u32	fh_l:8;
+
+	u32	fh_h:4;
+	u32	res3:28;
+
+	/* Word 1 */
+	u32	eba0;
+
+	u32	eba1;
+
+	u32	bpp:3;
+	u32	sl:14;
+	u32	pfs:3;
+	u32	bam:3;
+	u32	res4:2;
+	u32	npb:6;
+	u32	res5:1;
+
+	u32	sat:2;
+	u32	scc:1;
+	u32	ofs0:5;
+	u32	ofs1:5;
+	u32	ofs2:5;
+	u32	ofs3:5;
+	u32	wid0:3;
+	u32	wid1:3;
+	u32	wid2:3;
+
+	u32	wid3:3;
+	u32	dec_sel:1;
+	u32	res6:28;
+} __attribute__ ((packed));
+
+union chan_param_mem {
+	struct chan_param_mem_planar		pp;
+	struct chan_param_mem_interleaved	ip;
+};
+
+static inline u32 reg_read(unsigned long reg)
+{
+	return __REG(reg);
+}
+
+static inline void reg_write(u32 value, unsigned long reg)
+{
+	__REG(reg) = value;
+}
+
+/**
+ * sdc_init_panel() - initialize a synchronous LCD panel.
+ * @mx3fb:		mx3fb context.
+ * @panel:		panel type.
+ * @pixel_clk:		desired pixel clock frequency in Hz.
+ * @width:		width of panel in pixels.
+ * @height:		height of panel in pixels.
+ * @pixel_fmt:		pixel format of buffer as FOURCC ASCII code.
+ * @h_start_width:	number of pixel clocks between the HSYNC signal pulse
+ *			and the start of valid data.
+ * @h_sync_width:	width of the HSYNC signal in units of pixel clocks.
+ * @h_end_width:	number of pixel clocks between the end of valid data
+ *			and the HSYNC signal for next line.
+ * @v_start_width:	number of lines between the VSYNC signal pulse and the
+ *			start of valid data.
+ * @v_sync_width:	width of the VSYNC signal in units of lines
+ * @v_end_width:	number of lines between the end of valid data and the
+ *			VSYNC signal for next frame.
+ * @sig:		bitfield of signal polarities for LCD interface.
+ * @return:		0 on success or negative error code on failure.
+ */
+static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt)
+{
+	u32 reg;
+	uint32_t old_conf;
+
+	/* Init panel size and blanking periods */
+	reg = ((H_SYNC_WIDTH - 1) << 26) |
+		((u32)(width + H_START_WIDTH + H_END_WIDTH - 1) << 16);
+	reg_write(reg, SDC_HOR_CONF);
+
+	reg = ((V_SYNC_WIDTH - 1) << 26) | SDC_V_SYNC_WIDTH_L |
+		((u32)(height + V_START_WIDTH + V_END_WIDTH - 1) << 16);
+	reg_write(reg, SDC_VER_CONF);
+
+	switch (PANEL_TYPE) {
+	case IPU_PANEL_SHARP_TFT:
+		reg_write(0x00FD0102L, SDC_SHARP_CONF_1);
+		reg_write(0x00F500F4L, SDC_SHARP_CONF_2);
+		reg_write(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		break;
+	case IPU_PANEL_TFT:
+		reg_write(SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Init clocking */
+
+	/*
+	 * Calculate divider: fractional part is 4 bits so simply multiple by
+	 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
+	 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
+	 */
+
+	reg_write((((IF_CLK_DIV / 8) - 1) << 22) |
+			IF_CLK_DIV, DI_DISP3_TIME_CONF);
+
+	/* DI settings */
+	old_conf = reg_read(DI_DISP_IF_CONF) & 0x78FFFFFF;
+	reg_write(old_conf | IF_CONF, DI_DISP_IF_CONF);
+
+	old_conf = reg_read(DI_DISP_SIG_POL) & 0xE0FFFFFF;
+	reg_write(old_conf | SIG_POL, DI_DISP_SIG_POL);
+
+	reg_write(fmt_cfg[pixel_fmt].b0, DI_DISP3_B0_MAP);
+	reg_write(fmt_cfg[pixel_fmt].b1, DI_DISP3_B1_MAP);
+	reg_write(fmt_cfg[pixel_fmt].b2, DI_DISP3_B2_MAP);
+	reg_write(reg_read(DI_DISP_ACC_CC) |
+		  ((fmt_cfg[pixel_fmt].acc - 1) << 12), DI_DISP_ACC_CC);
+
+	return 0;
+}
+
+static void ipu_ch_param_set_size(union chan_param_mem *params,
+				  uint32_t pixel_fmt, uint16_t width,
+				  uint16_t height, uint16_t stride)
+{
+	params->pp.fw		= width - 1;
+	params->pp.fh_l		= height - 1;
+	params->pp.fh_h		= (height - 1) >> 8;
+	params->pp.sl		= stride - 1;
+
+	/* See above, for further formats see tge Linux driver */
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_RGB565:
+		params->ip.bpp	= 2;
+		params->ip.pfs	= 4;
+		params->ip.npb	= 7;
+		params->ip.sat	= 2;		/* SAT = 32-bit access */
+		params->ip.ofs0	= 0;		/* Red bit offset */
+		params->ip.ofs1	= 5;		/* Green bit offset */
+		params->ip.ofs2	= 11;		/* Blue bit offset */
+		params->ip.ofs3	= 16;		/* Alpha bit offset */
+		params->ip.wid0	= 4;		/* Red bit width - 1 */
+		params->ip.wid1	= 5;		/* Green bit width - 1 */
+		params->ip.wid2	= 4;		/* Blue bit width - 1 */
+		break;
+	case IPU_PIX_FMT_RGB24:
+		params->ip.bpp	= 1;		/* 24 BPP & RGB PFS */
+		params->ip.pfs	= 4;
+		params->ip.npb	= 7;
+		params->ip.sat	= 2;		/* SAT = 32-bit access */
+		params->ip.ofs0	= 16;		/* Red bit offset */
+		params->ip.ofs1	= 8;		/* Green bit offset */
+		params->ip.ofs2	= 0;		/* Blue bit offset */
+		params->ip.ofs3	= 24;		/* Alpha bit offset */
+		params->ip.wid0	= 7;		/* Red bit width - 1 */
+		params->ip.wid1	= 7;		/* Green bit width - 1 */
+		params->ip.wid2	= 7;		/* Blue bit width - 1 */
+		break;
+	default:
+		break;
+	}
+
+	params->pp.nsb = 1;
+}
+
+static void ipu_ch_param_set_buffer(union chan_param_mem *params,
+				    void *buf0, void *buf1)
+{
+	params->pp.eba0 = (u32)buf0;
+	params->pp.eba1 = (u32)buf1;
+}
+
+static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
+				uint32_t num_words)
+{
+	for (; num_words > 0; num_words--) {
+		reg_write(addr, IPU_IMA_ADDR);
+		reg_write(*data++, IPU_IMA_DATA);
+		addr++;
+		if ((addr & 0x7) == 5) {
+			addr &= ~0x7;	/* set to word 0 */
+			addr += 8;	/* increment to next row */
+		}
+	}
+}
+
+static uint32_t bpp_to_pixfmt(int bpp)
+{
+	switch (bpp) {
+	case 16:
+		return IPU_PIX_FMT_RGB565;
+	default:
+		return 0;
+	}
+}
+
+static uint32_t dma_param_addr(enum ipu_channel channel)
+{
+	/* Channel Parameter Memory */
+	return 0x10000 | (channel << 4);
+}
+
+static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
+{
+	union chan_param_mem params = {};
+	uint32_t reg;
+	uint32_t stride_bytes;
+
+	stride_bytes = (XRES * ((BIT_PER_PIXEL + 7) / 8) + 3) & ~3;
+
+	/* Build parameter memory data for DMA channel */
+	ipu_ch_param_set_size(&params, bpp_to_pixfmt(BIT_PER_PIXEL), XRES, YRES, stride_bytes);
+	ipu_ch_param_set_buffer(&params, fbmem, NULL);
+	params.pp.bam = 0;
+	/* Some channels (rotation) have restriction on burst length */
+
+	switch (channel) {
+	case IDMAC_SDC_0:
+		/* In original code only IPU_PIX_FMT_RGB565 was setting burst */
+		params.pp.npb = 16 - 1;
+	default:
+		break;
+	}
+
+	ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
+
+	/* Disable double-buffering */
+	reg = reg_read(IPU_CHA_DB_MODE_SEL);
+	reg &= ~(1UL << channel);
+	reg_write(reg, IPU_CHA_DB_MODE_SEL);
+}
+
+static void ipu_channel_set_priority(enum ipu_channel channel,
+				     int prio)
+{
+	u32 reg = reg_read(IDMAC_CHA_PRI);
+
+	if (prio)
+		reg |= 1UL << channel;
+	else
+		reg &= ~(1UL << channel);
+
+	reg_write(reg, IDMAC_CHA_PRI);
+}
+
+/**
+ * ipu_enable_channel() - enable an IPU channel.
+ * @channel:	channel ID.
+ * @return:	0 on success or negative error code on failure.
+ */
+static int ipu_enable_channel(enum ipu_channel channel)
+{
+	uint32_t reg;
+
+	/* Reset to buffer 0 */
+	reg_write(1UL << channel, IPU_CHA_CUR_BUF);
+
+	switch (channel) {
+	case IDMAC_SDC_0:
+		ipu_channel_set_priority(channel, 1);
+	default:
+		break;
+	}
+
+	reg = reg_read(IDMAC_CHA_EN);
+	reg_write(reg | (1UL << channel), IDMAC_CHA_EN);
+
+	return 0;
+}
+
+static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
+{
+	uint32_t reg;
+
+	reg = reg_read(IPU_CHA_BUF0_RDY);
+	if (reg & (1UL << channel))
+		return -EACCES;
+
+	/* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
+	reg_write(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
+	reg_write((u32)buf, IPU_IMA_DATA);
+
+	return 0;
+}
+
+static int idmac_tx_submit(enum ipu_channel channel, void *buf)
+{
+	int ret;
+
+	ipu_init_channel_buffer(channel, buf);
+
+
+	/* ipu_idmac.c::ipu_submit_channel_buffers() */
+	ret = ipu_update_channel_buffer(channel, buf);
+	if (ret < 0)
+		return ret;
+
+	/* ipu_idmac.c::ipu_select_buffer() */
+	/* Mark buffer 0 as ready. */
+	reg_write(1UL << channel, IPU_CHA_BUF0_RDY);
+
+
+	ret = ipu_enable_channel(channel);
+	return ret;
+}
+
+static void sdc_enable_channel(void *fbmem)
+{
+	int ret;
+	u32 reg;
+
+	ret = idmac_tx_submit(IDMAC_SDC_0, fbmem);
+
+	/* mx3fb.c::sdc_fb_init() */
+	if (ret >= 0) {
+		reg = reg_read(SDC_COM_CONF);
+		reg_write(reg | SDC_COM_BG_EN, SDC_COM_CONF);
+	}
+
+	/*
+	 * Attention! Without this msleep the channel keeps generating
+	 * interrupts. Next sdc_set_brightness() is going to be called
+	 * from mx3fb_blank().
+	 */
+	msleep(2);
+}
+
+/**
+ * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
+ * @fbi:	framebuffer information pointer.
+ * @return:	0 on success or negative error code on failure.
+ */
+static int mx3fb_set_par(void *fbmem)
+{
+	int ret;
+
+	ret = sdc_init_panel(XRES, YRES, PIXEL_FMT);
+	if (ret < 0)
+		return ret;
+
+	reg_write((H_START_WIDTH << 16) | V_START_WIDTH, SDC_BG_POS);
+
+	return 0;
+}
+
+/* References in this function refer to respective Linux kernel sources */
+void lcd_enable (void)
+{
+	u32 reg;
+
+	/* pcm037.c::mxc_board_init() */
+
+	/* Display Interface #3 */
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC));
+
+
+	/* ipu_idmac.c::ipu_probe() */
+
+	/* Start the clock */
+	__REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22);
+
+
+	/* ipu_idmac.c::ipu_idmac_init() */
+
+	/* Service request counter to maximum - shouldn't be needed */
+	reg_write(0x00000070, IDMAC_CONF);
+
+
+	/* ipu_idmac.c::ipu_init_channel() */
+
+	/* Enable IPU sub modules */
+	reg = reg_read(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
+	reg_write(reg, IPU_CONF);
+
+
+	/* mx3fb.c::init_fb_chan() */
+
+	/* set Display Interface clock period */
+	reg_write(0x00100010L, DI_HSP_CLK_PER);
+	/* Might need to trigger HSP clock change - see 44.3.3.8.5 */
+
+
+	/* mx3fb.c::sdc_set_brightness() */
+
+	/* This might be board-specific */
+	reg_write(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
+
+
+	/* mx3fb.c::sdc_set_global_alpha() */
+
+	/* Use global - not per-pixel - Alpha-blending */
+	reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL;
+	reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
+
+	reg = reg_read(SDC_COM_CONF);
+	reg_write(reg | SDC_COM_GLB_A, SDC_COM_CONF);
+
+
+	/* mx3fb.c::sdc_set_color_key() */
+
+	/* Disable colour-keying for background */
+	reg = reg_read(SDC_COM_CONF) &
+		~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
+	reg_write(reg, SDC_COM_CONF);
+
+
+	mx3fb_set_par(lcd_base);
+
+	sdc_enable_channel(lcd_base);
+
+	/* Linux driver calls sdc_set_brightness() here again, once is enough for us */
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	u32 mem_len = XRES * YRES * BIT_PER_PIXEL / 8;
+	/*
+	 * We rely on fbmem being a physical address, i.e., either MMU off,
+	 * or 1-to-1 mapping. Might want to add some virt2phys here.
+	 */
+	if (!lcdbase)
+		return;
+
+	memset(lcdbase, 0, mem_len);
+}
+
+ulong calc_fbsize(void)
+{
+	return ((panel_info.vl_col * panel_info.vl_row *
+		NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
+}
+
+int overwrite_console (void)
+{
+	/* Keep stdout / stderr on serial, our LCD is for splashscreen only */
+	return 1;
+}
-- 
1.5.4

[U-Boot] [PATCH 9/9] ARM: add an "eet" variant of the imx31_phycore board

[Guennadi Liakhovetski]

The "eet" variant of the imx31_phycore board has an OLED display, using a
s6e63d6 display controller on the first SPI interface, using GPIO57 as a
chip-select for it. With this configuration you can display 256 colour BMP
images in 16-bit RGB (RGB565) LCD mode.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Jean-Christophe: another ack, please.

 Makefile                              |    6 +++-
 board/imx31_phycore/imx31_phycore.c   |   51 +++++++++++++++++++++++++++++++++
 include/asm-arm/arch-mx31/mx31-regs.h |   16 ++++++++++
 include/configs/imx31_phycore.h       |   23 +++++++++++++++
 4 files changed, 95 insertions(+), 1 deletions(-)

diff --git a/Makefile b/Makefile
index 787c5f2..6151e2c 100644
--- a/Makefile
+++ b/Makefile
@@ -3025,8 +3025,12 @@ apollon_config		: unconfig
 imx31_litekit_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
 
+imx31_phycore_eet_config \
 imx31_phycore_config	: unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
+	@if [ -n "$(findstring imx31_phycore_eet_config,$@)" ]; then			\
+		echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h;	\
+	fi
+	@$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31
 
 mx31ads_config		: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
index 4c64cb9..c70353d 100644
--- a/board/imx31_phycore/imx31_phycore.c
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -23,6 +23,7 @@
 
 
 #include <common.h>
+#include <s6e63d6.h>
 #include <asm/arch/mx31.h>
 #include <asm/arch/mx31-regs.h>
 
@@ -66,6 +67,56 @@ int board_init (void)
 	return 0;
 }
 
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_DISPLAY_S6E63D6
+	struct s6e63d6 data = {
+		.cs = 2 | (57 << 8),
+		.bus = 0,
+	};
+	int ret;
+
+	/* SPI1 */
+	mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
+	mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
+	mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
+	mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
+	mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
+	mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
+
+	/* start SPI1 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
+
+	/* GPIO 57 */
+	/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
+	mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
+
+	/* SPI1 CS2 is free */
+	ret = s6e63d6_init(&data);
+	if (ret)
+		return ret;
+
+	/*
+	 * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
+	 * OLED display connected to a S6E63D6 SPI display controller in the
+	 * 18 bit RGB mode
+	 */
+	s6e63d6_index(&data, 2);
+	s6e63d6_param(&data, 0x0182);
+	s6e63d6_index(&data, 3);
+	s6e63d6_param(&data, 0x8130);
+	s6e63d6_index(&data, 0x10);
+	s6e63d6_param(&data, 0x0000);
+	s6e63d6_index(&data, 5);
+	s6e63d6_param(&data, 0x0001);
+	s6e63d6_index(&data, 0x22);
+#endif
+	return 0;
+}
+#endif
+
 int checkboard (void)
 {
 	printf("Board: Phytec phyCore i.MX31\n");
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index e736052..dcc0805 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -124,7 +124,14 @@
 #define MUX_CTL_CSPI2_SS0	0x85
 #define MUX_CTL_CSPI2_SS1	0x86
 #define MUX_CTL_CSPI2_SS2	0x87
+#define MUX_CTL_CSPI1_SS2	0x88
+#define MUX_CTL_CSPI1_SCLK	0x89
+#define MUX_CTL_CSPI1_SPI_RDY	0x8a
 #define MUX_CTL_CSPI2_MOSI	0x8b
+#define MUX_CTL_CSPI1_MOSI	0x8c
+#define MUX_CTL_CSPI1_MISO	0x8d
+#define MUX_CTL_CSPI1_SS0	0x8e
+#define MUX_CTL_CSPI1_SS1	0x8f
 
 /*
  * Helper macros for the MUX_[contact name]__[pin function] macros
@@ -150,6 +157,15 @@
 	IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
 
+#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
+#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
+#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
+#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
+	IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
+#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
+
 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
 
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index f0d28ee..257a2f9 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -178,4 +178,27 @@
 #undef CONFIG_JFFS2_CMDLINE
 #define CONFIG_JFFS2_DEV	"nor0"
 
+/* EET platform additions */
+#ifdef CONFIG_IMX31_PHYCORE_EET
+#define BOARD_LATE_INIT
+
+#define CONFIG_MX31_GPIO				1
+
+#define CONFIG_HARD_SPI				1
+#define CONFIG_MXC_SPI				1
+#define CONFIG_CMD_SPI
+
+#define CONFIG_DISPLAY_S6E63D6			1
+
+#define CONFIG_LCD				1
+#define CONFIG_VIDEO_MX3			1
+#define CONFIG_SYS_WHITE_ON_BLACK		1
+#define LCD_BPP					LCD_COLOR8
+#define	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+
+#define	CONFIG_SPLASH_SCREEN			1
+#define CONFIG_CMD_BMP				1
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.5.4

[U-Boot] [PATCH 4/9] A driver for the S6E63D6 SPI display controller from Samsung

[Magnus Lilja]

Hi

2009/2/4 Guennadi Liakhovetski <lg@denx.de>:
> This is a driver for the S6E63D6 SPI OLED display controller from Samsung.
> It only provides access to controller's registers so the client can freely
> configure it.
>
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
>  drivers/video/Makefile  |    1 +
>  drivers/video/s6e63d6.c |   68 +++++++++++++++++++++++++++++++++++++++++++++++
>  include/s6e63d6.h       |   36 +++++++++++++++++++++++++
>  3 files changed, 105 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/video/s6e63d6.c
>  create mode 100644 include/s6e63d6.h
>
> diff --git a/drivers/video/Makefile b/drivers/video/Makefile
> index 7fba29f..a7dc74c 100644
> --- a/drivers/video/Makefile
> +++ b/drivers/video/Makefile
> @@ -34,6 +34,7 @@ COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
>  COBJS-$(CONFIG_SED156X) += sed156x.o
>  COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
>  COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
> +COBJS-$(CONFIG_DISPLAY_S6E63D6) += s6e63d6.o
>  COBJS-y += videomodes.o
>
>  COBJS  := $(COBJS-y)
> diff --git a/drivers/video/s6e63d6.c b/drivers/video/s6e63d6.c
> new file mode 100644
> index 0000000..27ff976
> --- /dev/null
> +++ b/drivers/video/s6e63d6.c
> @@ -0,0 +1,68 @@
> +/*
> + * Copyright (C) 2009
> + * Guennadi Liakhovetski, DEXN Software Engineering, <lg@denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <spi.h>
> +#include <s6e63d6.h>
> +
> +/* Hardware selected value - 0 or 0x4 */
> +#define ID 0
> +
> +/*
> + * Each transfer is performed as:
> + * 1. chip-select active
> + * 2. send 8-bit start code
> + * 3. send 16-bit data
> + * 4. chip-select inactive
> + */
> +static int send_word(struct spi_slave *spi, u8 rs, u16 data)
> +{
> +       u32 buf8 = 0x70 | ID | (rs & 2);
> +       u32 buf16 = cpu_to_le16(data);
> +       u32 buf_in;
> +       int err;
> +
> +       err = spi_xfer(spi, 8, &buf8, &buf_in, SPI_XFER_BEGIN);
> +       if (err)
> +               return err;
> +       return spi_xfer(spi, 16, &buf16, &buf_in, SPI_XFER_END);
> +}
> +
> +/* Index and param differ in Register Select bit */
> +int s6e63d6_index(struct s6e63d6 *data, u8 idx)
> +{
> +       return send_word(data->slave, 0, idx);
> +}
> +
> +int s6e63d6_param(struct s6e63d6 *data, u16 param)
> +{
> +       return send_word(data->slave, 2, param);
> +}
> +
> +int s6e63d6_init(struct s6e63d6 *data)
> +{
> +       data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3);
> +       if (!data->slave)
> +               return 1;
> +
> +       return 0;
> +}
> diff --git a/include/s6e63d6.h b/include/s6e63d6.h
> new file mode 100644
> index 0000000..9665dc5
> --- /dev/null
> +++ b/include/s6e63d6.h
> @@ -0,0 +1,36 @@
> +/*
> + * Copyright (C) 2009
> + * Guennadi Liakhovetski, DEXN Software Engineering, <lg@denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#ifndef _S6E63D6_H_
> +#define _S6E63D6_H_
> +
> +struct s6e63d6 {
> +       unsigned int bus;
> +       unsigned int cs;
> +       struct spi_slave *slave;
> +};
> +
> +extern int s6e63d6_init(struct s6e63d6 *);
> +extern int s6e63d6_index(struct s6e63d6 *, u8);
> +extern int s6e63d6_param(struct s6e63d6 *, u16);

'extern' not needed.

Also, personally I prefer to have the parameter names in the
prototypes as well, not just the data types.


Regards, Magnus

[U-Boot] [PATCH 2/9] i.MX31: add a simple gpio driver

[Magnus Lilja]

Hi

2009/2/4 Guennadi Liakhovetski <lg@denx.de>:
> This is a minimal driver, so far only managing output. It will
> be used by the mxc_spi.c driver.
>
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
>
> Jean-Christophe: also an ack from you, please.
>
>  drivers/gpio/Makefile            |    3 +-
>  drivers/gpio/mx31_gpio.c         |   71 ++++++++++++++++++++++++++++++++++++++
>  include/asm-arm/arch-mx31/mx31.h |    9 +++++
>  3 files changed, 82 insertions(+), 1 deletions(-)
>  create mode 100644 drivers/gpio/mx31_gpio.c
>
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index dd618ed..ce049e4 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk
>
>  LIB    := $(obj)libgpio.a
>
> -COBJS-$(CONFIG_PCA953X)        += pca953x.o
> +COBJS-$(CONFIG_PCA953X)                += pca953x.o
> +COBJS-$(CONFIG_MX31_GPIO)      += mx31_gpio.o

Might want to sort these in alphabetically order.

...

> diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h
> index 0552c27..fb8d8c0 100644
> --- a/include/asm-arm/arch-mx31/mx31.h
> +++ b/include/asm-arm/arch-mx31/mx31.h
> @@ -27,4 +27,13 @@
>  extern u32 mx31_get_ipg_clk(void);
>  extern void mx31_gpio_mux(unsigned long mode);

'extern' is not needed here. Some header files seems to have extern
while some don't.

>
> +enum mx31_gpio_direction {
> +       MX31_GPIO_DIRECTION_IN,
> +       MX31_GPIO_DIRECTION_OUT,
> +};
> +
> +extern void mx31_gpio_direction(unsigned int gpio,
> +                               enum mx31_gpio_direction direction);
> +extern void mx31_gpio_set(unsigned int gpio, unsigned int value);

'extern' is not needed here.


Regards, Magnus

[U-Boot] [PATCH 8/9] video: add a i.MX31 framebuffer driver only for bitmaps so far

[Magnus Lilja]

Hi

2009/2/4 Guennadi Liakhovetski <lg@denx.de>:
> Add a driver for the Synchronous Display Controller and the Display
> Interface on i.MX31, using IPU for DMA channel setup. So far only
> displaying of bitmaps is supported, no text output.
>
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
>  drivers/video/Makefile |    1 +
>  drivers/video/mx3fb.c  |  865 ++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 866 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/video/mx3fb.c
....
> +/**
> + * ipu_enable_channel() - enable an IPU channel.
> + * @channel:   channel ID.
> + * @return:    0 on success or negative error code on failure.
> + */
> +static int ipu_enable_channel(enum ipu_channel channel)
> +{
> +       uint32_t reg;
> +
> +       /* Reset to buffer 0 */
> +       reg_write(1UL << channel, IPU_CHA_CUR_BUF);
> +
> +       switch (channel) {
> +       case IDMAC_SDC_0:
> +               ipu_channel_set_priority(channel, 1);

Missing break?

> +       default:
> +               break;
> +       }
> +
> +       reg = reg_read(IDMAC_CHA_EN);
> +       reg_write(reg | (1UL << channel), IDMAC_CHA_EN);
> +
> +       return 0;
> +}
> +
> +static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
> +{
> +       uint32_t reg;
> +
> +       reg = reg_read(IPU_CHA_BUF0_RDY);
> +       if (reg & (1UL << channel))
> +               return -EACCES;
> +
> +       /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
> +       reg_write(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
> +       reg_write((u32)buf, IPU_IMA_DATA);
> +
> +       return 0;
> +}
> +
> +static int idmac_tx_submit(enum ipu_channel channel, void *buf)
> +{
> +       int ret;
> +
> +       ipu_init_channel_buffer(channel, buf);
> +
> +
> +       /* ipu_idmac.c::ipu_submit_channel_buffers() */
> +       ret = ipu_update_channel_buffer(channel, buf);
> +       if (ret < 0)
> +               return ret;
> +
> +       /* ipu_idmac.c::ipu_select_buffer() */
> +       /* Mark buffer 0 as ready. */
> +       reg_write(1UL << channel, IPU_CHA_BUF0_RDY);
> +
> +
> +       ret = ipu_enable_channel(channel);
> +       return ret;
> +}
> +
> +static void sdc_enable_channel(void *fbmem)
> +{
> +       int ret;
> +       u32 reg;
> +
> +       ret = idmac_tx_submit(IDMAC_SDC_0, fbmem);
> +
> +       /* mx3fb.c::sdc_fb_init() */
> +       if (ret >= 0) {
> +               reg = reg_read(SDC_COM_CONF);
> +               reg_write(reg | SDC_COM_BG_EN, SDC_COM_CONF);
> +       }
> +
> +       /*
> +        * Attention! Without this msleep the channel keeps generating
> +        * interrupts. Next sdc_set_brightness() is going to be called
> +        * from mx3fb_blank().
> +        */
> +       msleep(2);
> +}
> +
> +/**
> + * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
> + * @fbi:       framebuffer information pointer.
> + * @return:    0 on success or negative error code on failure.
> + */
> +static int mx3fb_set_par(void *fbmem)
> +{
> +       int ret;
> +
> +       ret = sdc_init_panel(XRES, YRES, PIXEL_FMT);
> +       if (ret < 0)
> +               return ret;
> +
> +       reg_write((H_START_WIDTH << 16) | V_START_WIDTH, SDC_BG_POS);
> +
> +       return 0;
> +}
> +
> +/* References in this function refer to respective Linux kernel sources */
> +void lcd_enable (void)
> +{
> +       u32 reg;
> +
> +       /* pcm037.c::mxc_board_init() */

Strance comment in a generic file.

> +
> +       /* Display Interface #3 */
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC));
> +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC));

The above seems board specific, although most of these pins can only
function as IPU pins or SDMA_DEBUG.

> +
> +
> +       /* ipu_idmac.c::ipu_probe() */

More odd comments in this functions (more below).

> +
> +       /* Start the clock */
> +       __REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22);
> +
> +
> +       /* ipu_idmac.c::ipu_idmac_init() */
> +
> +       /* Service request counter to maximum - shouldn't be needed */
> +       reg_write(0x00000070, IDMAC_CONF);
> +
> +
> +       /* ipu_idmac.c::ipu_init_channel() */
> +
> +       /* Enable IPU sub modules */
> +       reg = reg_read(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
> +       reg_write(reg, IPU_CONF);
> +
> +
> +       /* mx3fb.c::init_fb_chan() */
> +
> +       /* set Display Interface clock period */
> +       reg_write(0x00100010L, DI_HSP_CLK_PER);
> +       /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
> +
> +
> +       /* mx3fb.c::sdc_set_brightness() */
> +
> +       /* This might be board-specific */
> +       reg_write(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
> +
> +
> +       /* mx3fb.c::sdc_set_global_alpha() */
> +
> +       /* Use global - not per-pixel - Alpha-blending */
> +       reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL;
> +       reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
> +
> +       reg = reg_read(SDC_COM_CONF);
> +       reg_write(reg | SDC_COM_GLB_A, SDC_COM_CONF);
> +
> +
> +       /* mx3fb.c::sdc_set_color_key() */
> +
> +       /* Disable colour-keying for background */
> +       reg = reg_read(SDC_COM_CONF) &
> +               ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
> +       reg_write(reg, SDC_COM_CONF);
> +
> +
> +       mx3fb_set_par(lcd_base);
> +
> +       sdc_enable_channel(lcd_base);
> +
> +       /* Linux driver calls sdc_set_brightness() here again, once is enough for us */
> +}
> +
> +void lcd_ctrl_init(void *lcdbase)
> +{
> +       u32 mem_len = XRES * YRES * BIT_PER_PIXEL / 8;
> +       /*
> +        * We rely on fbmem being a physical address, i.e., either MMU off,
> +        * or 1-to-1 mapping. Might want to add some virt2phys here.
> +        */
> +       if (!lcdbase)
> +               return;
> +
> +       memset(lcdbase, 0, mem_len);
> +}
> +
> +ulong calc_fbsize(void)
> +{
> +       return ((panel_info.vl_col * panel_info.vl_row *
> +               NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
> +}
> +
> +int overwrite_console (void)
> +{
> +       /* Keep stdout / stderr on serial, our LCD is for splashscreen only */
> +       return 1;
> +}
> --
> 1.5.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>


Regards, Magnus

[U-Boot] [PATCH 8/9] video: add a i.MX31 framebuffer driver only for bitmaps so far

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Magnus Lilja wrote:

> > +       switch (channel) {
> > +       case IDMAC_SDC_0:
> > +               ipu_channel_set_priority(channel, 1);
> 
> Missing break?

You don't mean inserting a break here would change anything, do you?

> > +       default:
> > +               break;
> > +       }

[snip]

> > +/* References in this function refer to respective Linux kernel sources */
> > +void lcd_enable (void)
> > +{
> > +       u32 reg;
> > +
> > +       /* pcm037.c::mxc_board_init() */
> 
> Strance comment in a generic file.

"Strance"? See just 5 lines above.

> > +       /* Display Interface #3 */
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC));
> > +       mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC));
> 
> The above seems board specific, although most of these pins can only
> function as IPU pins or SDMA_DEBUG.

Well, I think, SDC LCD functions are only available on one pin each, so, 
you have no choice. Just looked through and haven't found any 
alternatives.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 2/9] i.MX31: add a simple gpio driver

[Anatolij Gustschin]

Hello Guennadi,

> diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c
> new file mode 100644
> index 0000000..871601f
> --- /dev/null
> +++ b/drivers/gpio/mx31_gpio.c
> @@ -0,0 +1,71 @@
> +/*
> + * Copyright (C) 2009
> + * Guennadi Liakhovetski, DEXN Software Engineering, <lg@denx.de>

please fix: s/DEXN/DENX/

Best regards,
Anatolij

[U-Boot] [PATCH 8/9] video: add a i.MX31 framebuffer driver only for bitmaps so far

[Magnus Lilja]

Hi

2009/2/4 Guennadi Liakhovetski <lg@denx.de>:
> On Wed, 4 Feb 2009, Magnus Lilja wrote:
>
>> > +       switch (channel) {
>> > +       case IDMAC_SDC_0:
>> > +               ipu_channel_set_priority(channel, 1);
>>
>> Missing break?
>
> You don't mean inserting a break here would change anything, do you?

Not in this code but when the next developer adds a case
IDMAC_MMM_NNN: after the existing case it's easy to forget to add that
missing break.

>
>> > +       default:
>> > +               break;
>> > +       }
>
> [snip]
>
>> > +/* References in this function refer to respective Linux kernel sources */
>> > +void lcd_enable (void)
>> > +{
>> > +       u32 reg;
>> > +
>> > +       /* pcm037.c::mxc_board_init() */
>>
>> Strance comment in a generic file.
>
> "Strance"? See just 5 lines above.

Ok, I missed that comment. ("Strance" => "Strange")


Thanks, Magnus

[U-Boot] [PATCH 3/9] i.MX31: support GPIO as a chip-select in the mxc_spi driver

[Anatolij Gustschin]

Hello Guennadi,

> diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
> index 9267341..eacd36c 100644
> --- a/drivers/spi/mxc_spi.c
> +++ b/drivers/spi/mxc_spi.c
<snip>
> @@ -91,6 +94,9 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data,
>  	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
>  	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
>  
> +	if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
> +		mx31_gpio_set(mxcs->gpio, !!(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));

above line to long (> 80 chars).

Also you add mx31_gpio_* calls from the new mx31 GPIO driver to
this driver unconditionally. I think, this will break linking
for imx31_litekit and mx31ads boards as these boards include the
mxc_spi driver but do not define CONFIG_MX31_GPIO. How can we
separate this? Or am I missing something?

> @@ -100,6 +106,9 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data,
>  	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
>  		;
>  
> +	if (mxcs->gpio > 0 && (flags & SPI_XFER_END))
> +		mx31_gpio_set(mxcs->gpio, !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));

above line to long (> 80 chars).

Best regargs,
Anatolij

[U-Boot] [PATCH 3/9] i.MX31: support GPIO as a chip-select in the mxc_spi driver

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Anatolij Gustschin wrote:

> Hello Guennadi,
> 
> > diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
> > index 9267341..eacd36c 100644
> > --- a/drivers/spi/mxc_spi.c
> > +++ b/drivers/spi/mxc_spi.c
> <snip>
> > @@ -91,6 +94,9 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data,
> >  	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
> >  	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
> >  
> > +	if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
> > +		mx31_gpio_set(mxcs->gpio, !!(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
> 
> above line to long (> 80 chars).
> 
> Also you add mx31_gpio_* calls from the new mx31 GPIO driver to
> this driver unconditionally. I think, this will break linking
> for imx31_litekit and mx31ads boards as these boards include the
> mxc_spi driver but do not define CONFIG_MX31_GPIO. How can we
> separate this? Or am I missing something?
> 
> > @@ -100,6 +106,9 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data,
> >  	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
> >  		;
> >  
> > +	if (mxcs->gpio > 0 && (flags & SPI_XFER_END))
> > +		mx31_gpio_set(mxcs->gpio, !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
> 
> above line to long (> 80 chars).

Right, will fix all above.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 2/9] i.MX31: add a simple gpio driver

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Anatolij Gustschin wrote:

> Hello Guennadi,
> 
> > diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c
> > new file mode 100644
> > index 0000000..871601f
> > --- /dev/null
> > +++ b/drivers/gpio/mx31_gpio.c
> > @@ -0,0 +1,71 @@
> > +/*
> > + * Copyright (C) 2009
> > + * Guennadi Liakhovetski, DEXN Software Engineering, <lg@denx.de>
> 
> please fix: s/DEXN/DENX/

Oops, * copypaste = 4 occurrences in 3 patches:-(

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 8/9] video: add a i.MX31 framebuffer driver only for bitmaps so far

[Wolfgang Denk]

Dear Guennadi Liakhovetski,

In message <Pine.LNX.4.64.0902042031420.6279@axis700.grange> you wrote:
> On Wed, 4 Feb 2009, Magnus Lilja wrote:
> 
> > > +       switch (channel) {
> > > +       case IDMAC_SDC_0:
> > > +               ipu_channel_set_priority(channel, 1);
> > 
> > Missing break?
> 
> You don't mean inserting a break here would change anything, do you?

Yes, it would change the code considerably: it would make clear what
the intentions of the programmer were.

Please do what has been asked for.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The use of COBOL cripples the mind; its teaching  should,  therefore,
be regarded as a criminal offence.
          -- Edsger W. Dijkstra, SIGPLAN Notices, Volume 17, Number 5

[U-Boot] [PATCH 9/9] ARM: add an "eet" variant of the imx31_phycore board

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:00 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> The "eet" variant of the imx31_phycore board has an OLED display, using a
> s6e63d6 display controller on the first SPI interface, using GPIO57 as a
> chip-select for it. With this configuration you can display 256 colour BMP
> images in 16-bit RGB (RGB565) LCD mode.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
> 
> Jean-Christophe: another ack, please.
> 
>  Makefile                              |    6 +++-
>  board/imx31_phycore/imx31_phycore.c   |   51 +++++++++++++++++++++++++++++++++
>  include/asm-arm/arch-mx31/mx31-regs.h |   16 ++++++++++
>  include/configs/imx31_phycore.h       |   23 +++++++++++++++
>  4 files changed, 95 insertions(+), 1 deletions(-)
> 
> diff --git a/Makefile b/Makefile
> index 787c5f2..6151e2c 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -3025,8 +3025,12 @@ apollon_config		: unconfig
>  imx31_litekit_config	: unconfig
>  	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
>  
> +imx31_phycore_eet_config \
>  imx31_phycore_config	: unconfig
> -	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
> +	@if [ -n "$(findstring imx31_phycore_eet_config,$@)" ]; then			\
maybe just search for eet will be simplest
> +		echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h;	\
> +	fi
> +	@$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31
>  
>  mx31ads_config		: unconfig
>  	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
> diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
> index 4c64cb9..c70353d 100644
> --- a/board/imx31_phycore/imx31_phycore.c
> +++ b/board/imx31_phycore/imx31_phycore.c
> @@ -23,6 +23,7 @@
>  
>  
>  #include <common.h>
> +#include <s6e63d6.h>
>  #include <asm/arch/mx31.h>
>  #include <asm/arch/mx31-regs.h>
>  
> @@ -66,6 +67,56 @@ int board_init (void)
>  	return 0;
>  }
>  
> +#ifdef BOARD_LATE_INIT
CONFIG_?
> +int board_late_init(void)
> +{

Best Regards,
J.

[U-Boot] [PATCH 1/9] i.MX31: fix SPI driver for shorter than 32 bit transfers

[Wolfgang Denk]

Dear Guennadi Liakhovetski,

In message <Pine.LNX.4.64.0902041536070.6279@axis700.grange> you wrote:
> Fix 8 and 16-bit transfers in mxc_spi driver and a wrong pointer in the 
> free routine.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
...
>  	for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
>  	     i < n_blks;
> -	     i++, in_l++, out_l++, bitlen -= 32)
> -		*in_l = spi_xchg_single(slave, *out_l, bitlen);
> +	     i++, in_l++, out_l++)
> +		*in_l = spi_xchg_single(slave, *out_l, flags);

Please use TABs for indentation, and add curly braces because of the
multi-line for construct.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"There are three principal ways to lose money: wine, women, and engi-
neers. While the first two are more pleasant, the third is by far the
more certain."                           - Baron Rothschild, ca. 1800

[U-Boot] [PATCH 5/9] ARM: remove unused variable

[Jean-Christophe PLAGNIOL-VILLARD]

On 17:59 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> The "size" variable in start_armboot() in lib_arm/board.c is only really 
> used in
> #if !defined(CONFIG_SYS_NO_FLASH)
> case, remove where unused.
> 
why not remove it
in the CONFIG_SYS_NO_FLASH you can not use it at all

Best Regards,
J.

[U-Boot] [PATCH 3/9] i.MX31: support GPIO as a chip-select in the mxc_spi driver

[Wolfgang Denk]

Dear Guennadi Liakhovetski,

In message <Pine.LNX.4.64.0902041539490.6279@axis700.grange> you wrote:
> Some SPI devices have special requirements on chip-select handling.
> With this patch we can use a GPIO as a chip-select and strictly follow
> the SPI_XFER_BEGIN and SPI_XFER_END flags.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
...
> +	if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
> +		mx31_gpio_set(mxcs->gpio, !!(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
> +

If you really need the '!!' then I consider the code to be broken.

Omit?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A woman should have compassion.
	-- Kirk, "Catspaw", stardate 3018.2

[U-Boot] [PATCH 4/9] A driver for the S6E63D6 SPI display controller from Samsung

[Wolfgang Denk]

Dear Guennadi Liakhovetski,

In message <Pine.LNX.4.64.0902041540350.6279@axis700.grange> you wrote:
> This is a driver for the S6E63D6 SPI OLED display controller from Samsung. 
> It only provides access to controller's registers so the client can freely 
> configure it.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
...
> diff --git a/drivers/video/Makefile b/drivers/video/Makefile
> index 7fba29f..a7dc74c 100644
> --- a/drivers/video/Makefile
> +++ b/drivers/video/Makefile
> @@ -34,6 +34,7 @@ COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
>  COBJS-$(CONFIG_SED156X) += sed156x.o
>  COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
>  COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
> +COBJS-$(CONFIG_DISPLAY_S6E63D6) += s6e63d6.o

Please keep lists sorted.

And maybe we can omit the "DISPLAY_" part?

> +++ b/drivers/video/s6e63d6.c
...
> +/* Hardware selected value - 0 or 0x4 */
> +#define ID 0

Should this go into the board config file?

> +/* Index and param differ in Register Select bit */
> +int s6e63d6_index(struct s6e63d6 *data, u8 idx)
> +{
> +	return send_word(data->slave, 0, idx);
> +}
> +
> +int s6e63d6_param(struct s6e63d6 *data, u16 param)
> +{
> +	return send_word(data->slave, 2, param);
> +}
> +
> +int s6e63d6_init(struct s6e63d6 *data)
> +{
> +	data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3);
> +	if (!data->slave)
> +		return 1;
> +
> +	return 0;
> +}

static? or inline?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Substitute "damn" every time you're inclined to write "very"; your
editor will delete it and the writing will be just as it should be.
                - Mark Twain

[U-Boot] [PATCH 4/9] A driver for the S6E63D6 SPI display controller from Samsung

[Wolfgang Denk]

In message <59b21cf20902041054n747c67d4r1c99724978321586@mail.gmail.com> Magnus Lilja wrote:
...
> > +extern int s6e63d6_init(struct s6e63d6 *);
> > +extern int s6e63d6_index(struct s6e63d6 *, u8);
> > +extern int s6e63d6_param(struct s6e63d6 *, u16);
> 
> 'extern' not needed.
> 
> Also, personally I prefer to have the parameter names in the
> prototypes as well, not just the data types.

Strongly supported!

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
My play was a complete success.  The audience was a failure.

[U-Boot] [PATCH 1/9] i.MX31: fix SPI driver for shorter than 32 bit transfers

[Scott Wood]

On Wed, Feb 04, 2009 at 10:30:32PM +0100, Wolfgang Denk wrote:
> Dear Guennadi Liakhovetski,
> 
> In message <Pine.LNX.4.64.0902041536070.6279@axis700.grange> you wrote:
> > Fix 8 and 16-bit transfers in mxc_spi driver and a wrong pointer in the 
> > free routine.
> > 
> > Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> > ---
> ...
> >  	for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
> >  	     i < n_blks;
> > -	     i++, in_l++, out_l++, bitlen -= 32)
> > -		*in_l = spi_xchg_single(slave, *out_l, bitlen);
> > +	     i++, in_l++, out_l++)
> > +		*in_l = spi_xchg_single(slave, *out_l, flags);
> 
> Please use TABs for indentation, and add curly braces because of the
> multi-line for construct.

I think you mistook the continuation line for the for-body?  Why would
you want to TAB the continuation line, making it even less distinct from
the body of the for-statement?

Besides, the above patch doesn't change formatting in any way.

That said, it could certainly use most of the loop content being moved
into the body.

-Scott

[U-Boot] [PATCH 1/9] i.MX31: fix SPI driver for shorter than 32 bit transfers

[Wolfgang Denk]

Dear Scott Wood,

In message <20090204214259.GA7238@ld0162-tx32.am.freescale.net> you wrote:
>
> > > +	     i++, in_l++, out_l++)
> > > +		*in_l = spi_xchg_single(slave, *out_l, flags);
> > 
> > Please use TABs for indentation, and add curly braces because of the
> > multi-line for construct.
> 
> I think you mistook the continuation line for the for-body?  Why would
> you want to TAB the continuation line, making it even less distinct from
> the body of the for-statement?

Your're right. 

Guennadi, please ignore this part.

> Besides, the above patch doesn't change formatting in any way.

That doesn't mean it should not be fixed if it was wrong :-)

> That said, it could certainly use most of the loop content being moved
> into the body.

Indeed - that woul dbe much easier to read.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
What kind of love is that?  Not to be loved; never to have shown love.
	-- Commissioner Nancy Hedford, "Metamorphosis",
	   stardate 3219.8

[U-Boot] [PATCH 6/9] Add 16bpp BMP support

[Wolfgang Denk]

Dear Guennadi Liakhovetski,

In message <Pine.LNX.4.64.0902041743530.6279@axis700.grange> you wrote:
> From: Mark Jackson <mpfj@mimc.co.uk>
> 
> This patch adds 16bpp BMP support to the common lcd code.
> 
> Use CONFIG_BMP_16BPP and set LCD_BPP to LCD_COLOR16 to enable the code.
> 
> At the moment it's only been tested on the MIMC200 AVR32 board, but extending
> this to other platforms should be a simple task !!
> 
> Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
>  common/lcd.c |   49 +++++++++++++++++++++++++++++++++++++++----------
>  1 files changed, 39 insertions(+), 10 deletions(-)

No comment? Please explain why you repost this here?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If all the Chinese simultaneously jumped into the Pacific  off  a  10
foot platform erected 10 feet off their coast, it would cause a tidal
wave that would destroy everything in this country west of Nebraska.

[U-Boot] [PATCH 6/9] Add 16bpp BMP support

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Wolfgang Denk wrote:

> Dear Guennadi Liakhovetski,
> 
> In message <Pine.LNX.4.64.0902041743530.6279@axis700.grange> you wrote:
> > From: Mark Jackson <mpfj@mimc.co.uk>
> > 
> > This patch adds 16bpp BMP support to the common lcd code.
> > 
> > Use CONFIG_BMP_16BPP and set LCD_BPP to LCD_COLOR16 to enable the code.
> > 
> > At the moment it's only been tested on the MIMC200 AVR32 board, but extending
> > this to other platforms should be a simple task !!
> > 
> > Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
> > Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> > ---
> >  common/lcd.c |   49 +++++++++++++++++++++++++++++++++++++++----------
> >  1 files changed, 39 insertions(+), 10 deletions(-)
> 
> No comment? Please explain why you repost this here?

I explained it in [PATCH 0/9]:

<quote>
A (fixed formatting) version of the

From: Mark Jackson <mpfj@mimc.co.uk>
Subject: [PATCH] Add 16bpp BMP support

patch is included for completeness. 
</quote>

but you're right, would be better to explain it in a non-commit comment to 
this patch.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 9/9] ARM: add an "eet" variant of the imx31_phycore board

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Jean-Christophe PLAGNIOL-VILLARD wrote:

> On 18:00 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> > The "eet" variant of the imx31_phycore board has an OLED display, using a
> > s6e63d6 display controller on the first SPI interface, using GPIO57 as a
> > chip-select for it. With this configuration you can display 256 colour BMP
> > images in 16-bit RGB (RGB565) LCD mode.
> > 
> > Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> > ---
> > 
> > Jean-Christophe: another ack, please.
> > 
> >  Makefile                              |    6 +++-
> >  board/imx31_phycore/imx31_phycore.c   |   51 +++++++++++++++++++++++++++++++++
> >  include/asm-arm/arch-mx31/mx31-regs.h |   16 ++++++++++
> >  include/configs/imx31_phycore.h       |   23 +++++++++++++++
> >  4 files changed, 95 insertions(+), 1 deletions(-)
> > 
> > diff --git a/Makefile b/Makefile
> > index 787c5f2..6151e2c 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -3025,8 +3025,12 @@ apollon_config		: unconfig
> >  imx31_litekit_config	: unconfig
> >  	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
> >  
> > +imx31_phycore_eet_config \
> >  imx31_phycore_config	: unconfig
> > -	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
> > +	@if [ -n "$(findstring imx31_phycore_eet_config,$@)" ]; then			\
> maybe just search for eet will be simplest

simplest for whom?

> > +		echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h;	\
> > +	fi
> > +	@$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31
> >  
> >  mx31ads_config		: unconfig
> >  	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
> > diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
> > index 4c64cb9..c70353d 100644
> > --- a/board/imx31_phycore/imx31_phycore.c
> > +++ b/board/imx31_phycore/imx31_phycore.c
> > @@ -23,6 +23,7 @@
> >  
> >  
> >  #include <common.h>
> > +#include <s6e63d6.h>
> >  #include <asm/arch/mx31.h>
> >  #include <asm/arch/mx31-regs.h>
> >  
> > @@ -66,6 +67,56 @@ int board_init (void)
> >  	return 0;
> >  }
> >  
> > +#ifdef BOARD_LATE_INIT
> CONFIG_?

grep?:

$ grep -r BOARD_LATE_INIT lib*
lib_arm/board.c:#ifdef BOARD_LATE_INIT
lib_nios2/board.c:#if defined(CONFIG_BOARD_LATE_INIT)
lib_sh/board.c:#ifdef BOARD_LATE_INIT
lib_sparc/board.c:#if defined(CONFIG_BOARD_LATE_INIT)

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 9/9] ARM: add an "eet" variant of the imx31_phycore board

[Jean-Christophe PLAGNIOL-VILLARD]

On 23:17 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> On Wed, 4 Feb 2009, Jean-Christophe PLAGNIOL-VILLARD wrote:
> 
> > On 18:00 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> > > The "eet" variant of the imx31_phycore board has an OLED display, using a
> > > s6e63d6 display controller on the first SPI interface, using GPIO57 as a
> > > chip-select for it. With this configuration you can display 256 colour BMP
> > > images in 16-bit RGB (RGB565) LCD mode.
> > > 
> > > Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> > > ---
> > > 
> > > Jean-Christophe: another ack, please.
> > > 
> > >  Makefile                              |    6 +++-
> > >  board/imx31_phycore/imx31_phycore.c   |   51 +++++++++++++++++++++++++++++++++
> > >  include/asm-arm/arch-mx31/mx31-regs.h |   16 ++++++++++
> > >  include/configs/imx31_phycore.h       |   23 +++++++++++++++
> > >  4 files changed, 95 insertions(+), 1 deletions(-)
> > > 
> > > diff --git a/Makefile b/Makefile
> > > index 787c5f2..6151e2c 100644
> > > --- a/Makefile
> > > +++ b/Makefile
> > > @@ -3025,8 +3025,12 @@ apollon_config		: unconfig
> > >  imx31_litekit_config	: unconfig
> > >  	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
> > >  
> > > +imx31_phycore_eet_config \
> > >  imx31_phycore_config	: unconfig
> > > -	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
> > > +	@if [ -n "$(findstring imx31_phycore_eet_config,$@)" ]; then			\
> > maybe just search for eet will be simplest
> 
> simplest for whom?
> 
> > > +		echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h;	\
> > > +	fi
> > > +	@$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31
> > >  
> > >  mx31ads_config		: unconfig
> > >  	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
> > > diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
> > > index 4c64cb9..c70353d 100644
> > > --- a/board/imx31_phycore/imx31_phycore.c
> > > +++ b/board/imx31_phycore/imx31_phycore.c
> > > @@ -23,6 +23,7 @@
> > >  
> > >  
> > >  #include <common.h>
> > > +#include <s6e63d6.h>
> > >  #include <asm/arch/mx31.h>
> > >  #include <asm/arch/mx31-regs.h>
> > >  
> > > @@ -66,6 +67,56 @@ int board_init (void)
> > >  	return 0;
> > >  }
> > >  
> > > +#ifdef BOARD_LATE_INIT
> > CONFIG_?
> 
> grep?:
> 
> $ grep -r BOARD_LATE_INIT lib*
> lib_arm/board.c:#ifdef BOARD_LATE_INIT
that a bug CONFIG_BOARD_LATE_INIT is supposed
> lib_nios2/board.c:#if defined(CONFIG_BOARD_LATE_INIT)
> lib_sh/board.c:#ifdef BOARD_LATE_INIT
ditto on the SH

Best Regards,
J.

[U-Boot] [PATCH 4/9] A driver for the S6E63D6 SPI display controller from Samsung

[Anatolij Gustschin]

Hi Guennadi,

> +struct s6e63d6 {
> +	unsigned int bus;
> +	unsigned int cs;
> +	struct spi_slave *slave;
> +};

could we use "bus" and "cs" from struct spi_slave? "struct spi_slave"
declares them already. Maybe we should drop struct s6e63d6 entirely and use
struct spi_slave instead?

Best regards,
Anatolij

[U-Boot] [PATCH 5/9] ARM: remove unused variable

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Jean-Christophe PLAGNIOL-VILLARD wrote:

> On 17:59 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> > The "size" variable in start_armboot() in lib_arm/board.c is only really 
> > used in
> > #if !defined(CONFIG_SYS_NO_FLASH)
> > case, remove where unused.
> > 
> why not remove it
> in the CONFIG_SYS_NO_FLASH you can not use it at all

Sorry? remove what? the "size" variable? Have a look at the code - it is 
_used_ if CONFIG_SYS_NO_FLASH is _not_ defined, and so it is also defined 
for this case. Or have I misunderstood you?

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 9/9] ARM: add an "eet" variant of the imx31_phycore board

[Wolfgang Denk]

Dear Guennadi Liakhovetski,

In message <Pine.LNX.4.64.0902042316110.6279@axis700.grange> you wrote:
>
> > > +#ifdef BOARD_LATE_INIT
> > CONFIG_?
> 
> grep?:
> 
> $ grep -r BOARD_LATE_INIT lib*
> lib_arm/board.c:#ifdef BOARD_LATE_INIT
> lib_nios2/board.c:#if defined(CONFIG_BOARD_LATE_INIT)
> lib_sh/board.c:#ifdef BOARD_LATE_INIT
> lib_sparc/board.c:#if defined(CONFIG_BOARD_LATE_INIT)

Good idea to search - so you can fix the other occurances, too.

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Children begin by loving their parents. After a time they judge them.
Rarely, if ever, do they forgive them.                  - Oscar Wilde

[U-Boot] [PATCH 4/9] A driver for the S6E63D6 SPI display controller from Samsung

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Wolfgang Denk wrote:

> Dear Guennadi Liakhovetski,
> 
> In message <Pine.LNX.4.64.0902041540350.6279@axis700.grange> you wrote:
> > This is a driver for the S6E63D6 SPI OLED display controller from Samsung. 
> > It only provides access to controller's registers so the client can freely 
> > configure it.
> > 
> > Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ...
> > diff --git a/drivers/video/Makefile b/drivers/video/Makefile
> > index 7fba29f..a7dc74c 100644
> > --- a/drivers/video/Makefile
> > +++ b/drivers/video/Makefile
> > @@ -34,6 +34,7 @@ COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
> >  COBJS-$(CONFIG_SED156X) += sed156x.o
> >  COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
> >  COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
> > +COBJS-$(CONFIG_DISPLAY_S6E63D6) += s6e63d6.o
> 
> Please keep lists sorted.
> 
> And maybe we can omit the "DISPLAY_" part?

Well, I tried to follow the CONFIG_VIDEO_* style, but can remove, sure.

> > +++ b/drivers/video/s6e63d6.c
> ...
> > +/* Hardware selected value - 0 or 0x4 */
> > +#define ID 0
> 
> Should this go into the board config file?

Can do.

> > +/* Index and param differ in Register Select bit */
> > +int s6e63d6_index(struct s6e63d6 *data, u8 idx)
> > +{
> > +	return send_word(data->slave, 0, idx);
> > +}
> > +
> > +int s6e63d6_param(struct s6e63d6 *data, u16 param)
> > +{
> > +	return send_word(data->slave, 2, param);
> > +}
> > +
> > +int s6e63d6_init(struct s6e63d6 *data)
> > +{
> > +	data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3);
> > +	if (!data->slave)
> > +		return 1;
> > +
> > +	return 0;
> > +}
> 
> static? or inline?

Neither, nor. It is declared in the header in this patch and called in 
[PATCH 9/9].

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 3/9] i.MX31: support GPIO as a chip-select in the mxc_spi driver

[Jean-Christophe PLAGNIOL-VILLARD]

On 17:59 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> Some SPI devices have special requirements on chip-select handling.
> With this patch we can use a GPIO as a chip-select and strictly follow
> the SPI_XFER_BEGIN and SPI_XFER_END flags.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
> 
> Jean-Christophe: one more for you to ack.
> 
>  drivers/spi/mxc_spi.c |   35 +++++++++++++++++++++++++++++------
>  1 files changed, 29 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
> index 9267341..eacd36c 100644
> --- a/drivers/spi/mxc_spi.c
> +++ b/drivers/spi/mxc_spi.c
> @@ -32,6 +32,8 @@
>  
>  #else
>  
> +#include <asm/arch/mx31.h>
> +
>  #define MXC_CSPIRXDATA		0x00
>  #define MXC_CSPITXDATA		0x04
>  #define MXC_CSPICTRL		0x08
> @@ -68,6 +70,7 @@ struct mxc_spi_slave {
>  	struct spi_slave slave;
>  	unsigned long	base;
>  	u32		ctrl_reg;
> +	int		gpio;
>  };
>  
>  static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
> @@ -91,6 +94,9 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data,
>  	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
>  	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
>  
> +	if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
> +		mx31_gpio_set(mxcs->gpio, !!(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
> +
>  	reg_write(mxcs->base + MXC_CSPITXDATA, data);
>  
>  	cfg_reg |= MXC_CSPICTRL_XCH;
> @@ -100,6 +106,9 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data,
>  	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
>  		;
>  
> +	if (mxcs->gpio > 0 && (flags & SPI_XFER_END))
> +		mx31_gpio_set(mxcs->gpio, !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
> +
>  	return reg_read(mxcs->base + MXC_CSPIRXDATA);
>  }
>  
> @@ -175,10 +184,28 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
>  	unsigned int ctrl_reg;
>  	struct mxc_spi_slave *mxcs;
>  
> -	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) ||
> -	    cs > 3)
> +	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]))
> +		return NULL;
> +
> +	mxcs = malloc(sizeof(struct mxc_spi_slave));
> +	if (!mxcs)
>  		return NULL;
>  
> +	/*
> +	 * Some SPI devices require active chip-select over multiple
> +	 * transactions, we achieve this using a GPIO. Still, the SPI
> +	 * controller has to be configured to use one of its own chipselects.
> +	 * To use this feature you have to call spi_setup_slave() with
> +	 * cs = internal_cs | (gpio << 8), and you have to use some unused
> +	 * on this SPI controller cs between 0 and 3.
> +	 */
> +	if (cs > 3) {
> +		mxcs->gpio = cs >> 8;
> +		cs &= 3;
> +		mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT);
> +	} else
> +		mxcs->gpio = -1;
> +
why not add a callback for the chipselect instead
as example if you have to use a gpio extender it will simplest to implent
instead of hack the SPI driver

Best Regars,
J.

[U-Boot] [PATCH 5/9] ARM: remove unused variable

[Jean-Christophe PLAGNIOL-VILLARD]

On 23:20 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> On Wed, 4 Feb 2009, Jean-Christophe PLAGNIOL-VILLARD wrote:
> 
> > On 17:59 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> > > The "size" variable in start_armboot() in lib_arm/board.c is only really 
> > > used in
> > > #if !defined(CONFIG_SYS_NO_FLASH)
> > > case, remove where unused.
> > > 
> > why not remove it
> > in the CONFIG_SYS_NO_FLASH you can not use it at all
> 
why not do this

Best Regards,
J.
---
diff --git a/lib_arm/board.c b/lib_arm/board.c
index 2358beb..9afd15f 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -275,9 +275,6 @@ void start_armboot (void)
 {
 	init_fnc_t **init_fnc_ptr;
 	char *s;
-#if !defined(CONFIG_SYS_NO_FLASH) || defined (CONFIG_VFD) || defined(CONFIG_LCD)
-	ulong size;
-#endif
 #if defined(CONFIG_VFD) || defined(CONFIG_LCD)
 	unsigned long addr;
 #endif
@@ -303,8 +300,7 @@ void start_armboot (void)
 
 #ifndef CONFIG_SYS_NO_FLASH
 	/* configure available FLASH banks */
-	size = flash_init ();
-	display_flash_config (size);
+	display_flash_config (flash_init ());
 #endif /* CONFIG_SYS_NO_FLASH */
 
 #ifdef CONFIG_VFD
@@ -316,7 +312,7 @@ void start_armboot (void)
 	 */
 	/* bss_end is defined in the board-specific linker script */
 	addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
-	size = vfd_setmem (addr);
+	vfd_setmem (addr);
 	gd->fb_base = addr;
 #endif /* CONFIG_VFD */
 
@@ -331,7 +327,7 @@ void start_armboot (void)
 		 */
 		/* bss_end is defined in the board-specific linker script */
 		addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
-		size = lcd_setmem (addr);
+		lcd_setmem (addr);
 		gd->fb_base = addr;
 	}
 #endif /* CONFIG_LCD */

[U-Boot] [PATCH 4/9] A driver for the S6E63D6 SPI display controller from Samsung

[Jean-Christophe PLAGNIOL-VILLARD]

On 17:59 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> This is a driver for the S6E63D6 SPI OLED display controller from Samsung. 
> It only provides access to controller's registers so the client can freely 
> configure it.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
>  drivers/video/Makefile  |    1 +
>  drivers/video/s6e63d6.c |   68 +++++++++++++++++++++++++++++++++++++++++++++++
>  include/s6e63d6.h       |   36 +++++++++++++++++++++++++
>  3 files changed, 105 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/video/s6e63d6.c
>  create mode 100644 include/s6e63d6.h
> 
> diff --git a/drivers/video/Makefile b/drivers/video/Makefile
> index 7fba29f..a7dc74c 100644
> --- a/drivers/video/Makefile
> +++ b/drivers/video/Makefile
> @@ -34,6 +34,7 @@ COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
>  COBJS-$(CONFIG_SED156X) += sed156x.o
>  COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
>  COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o
> +COBJS-$(CONFIG_DISPLAY_S6E63D6) += s6e63d6.o
>  COBJS-y += videomodes.o
>  
>  COBJS	:= $(COBJS-y)
> diff --git a/drivers/video/s6e63d6.c b/drivers/video/s6e63d6.c
> new file mode 100644
> index 0000000..27ff976
> --- /dev/null
> +++ b/drivers/video/s6e63d6.c
> @@ -0,0 +1,68 @@
> +/*
> + * Copyright (C) 2009
> + * Guennadi Liakhovetski, DEXN Software Engineering, <lg@denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <spi.h>
> +#include <s6e63d6.h>
> +
> +/* Hardware selected value - 0 or 0x4 */
> +#define ID 0
Why hardcoded?
> +
> +/*
> + * Each transfer is performed as:
> + * 1. chip-select active
> + * 2. send 8-bit start code
> + * 3. send 16-bit data
> + * 4. chip-select inactive
> + */
> +static int send_word(struct spi_slave *spi, u8 rs, u16 data)
> +{
> +	u32 buf8 = 0x70 | ID | (rs & 2);
why?
> +	u32 buf16 = cpu_to_le16(data);
> +	u32 buf_in;
> +	int err;
> +
> +	err = spi_xfer(spi, 8, &buf8, &buf_in, SPI_XFER_BEGIN);
> +	if (err)
> +		return err;
> +	return spi_xfer(spi, 16, &buf16, &buf_in, SPI_XFER_END);
> +}
> +
Best Regards,
J.

[U-Boot] [PATCH 6/9] Add 16bpp BMP support

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:00 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> From: Mark Jackson <mpfj@mimc.co.uk>
> 
> This patch adds 16bpp BMP support to the common lcd code.
> 
> Use CONFIG_BMP_16BPP and set LCD_BPP to LCD_COLOR16 to enable the code.
> 
> At the moment it's only been tested on the MIMC200 AVR32 board, but extending
> this to other platforms should be a simple task !!
> 
> Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
I'll check on at91

Best Regards,
J.

[U-Boot] [PATCH 1/9] i.MX31: fix SPI driver for shorter than 32 bit transfers

[Jean-Christophe PLAGNIOL-VILLARD]

On 17:59 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> Fix 8 and 16-bit transfers in mxc_spi driver and a wrong pointer in the 
> free routine.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
> 
> No SPI custodian, so, Jean-Christophe will have to Ack it?
I'd like to have Mike and Haaward ack too
I'd take a look tomorow

Best Regards,
J.

[U-Boot] [PATCH 2/9] i.MX31: add a simple gpio driver

[Jean-Christophe PLAGNIOL-VILLARD]

On 17:59 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> This is a minimal driver, so far only managing output. It will
> be used by the mxc_spi.c driver.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
> 
> Jean-Christophe: also an ack from you, please.
I'd like to see a gpio_lib one day to simplify gpio use in u-boot

> 
>  drivers/gpio/Makefile            |    3 +-
>  drivers/gpio/mx31_gpio.c         |   71 ++++++++++++++++++++++++++++++++++++++
>  include/asm-arm/arch-mx31/mx31.h |    9 +++++
>  3 files changed, 82 insertions(+), 1 deletions(-)
>  create mode 100644 drivers/gpio/mx31_gpio.c
> 
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index dd618ed..ce049e4 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk
>  
>  LIB 	:= $(obj)libgpio.a
>  
> -COBJS-$(CONFIG_PCA953X)	+= pca953x.o
> +COBJS-$(CONFIG_PCA953X)		+= pca953x.o
> +COBJS-$(CONFIG_MX31_GPIO)	+= mx31_gpio.o
>  
>  COBJS	:= $(COBJS-y)
>  SRCS 	:= $(COBJS:.o=.c)
> diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c
> new file mode 100644
> index 0000000..871601f
> --- /dev/null
> +++ b/drivers/gpio/mx31_gpio.c
> @@ -0,0 +1,71 @@
> +/*
> + * Copyright (C) 2009
> + * Guennadi Liakhovetski, DEXN Software Engineering, <lg@denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <asm/arch/mx31.h>
> +#include <asm/arch/mx31-regs.h>
> +
> +/* GPIO port description */
> +static unsigned long gpio_ports[] = {
> +	[0] = 0x53fcc000,
> +	[1] = 0x53fd0000,
> +	[2] = 0x53fa4000,
hardcoded?
> +};
> +
> +void mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction)
						enum? do we really need this?
> +{
> +	unsigned int port = gpio >> 5;
> +	u32 l;
> +
> +	if (port > sizeof(gpio_ports) / sizeof(gpio_ports[0]) - 1)
ARRAY_SIZE?
> +		return;
> +
> +	gpio &= 0x1f;
> +
> +	l = __REG(gpio_ports[port] + 4);
> +	switch (direction) {
> +	case MX31_GPIO_DIRECTION_OUT:
> +		l |= 1 << gpio;
> +		break;
> +	case MX31_GPIO_DIRECTION_IN:
> +		l &= ~(1 << gpio);
> +	}
> +	__REG(gpio_ports[port] + 4) = l;
> +}
Best Regards,
J.

[U-Boot] [PATCH 7/9] LCD: support 8bpp BMPs on 16bpp displays

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:00 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> This patch also simplifies some ifdefs in lcd.c, introduces a generic
> vidinfo_t, which new drivers are encouraged to use and old drivers to switch
> over to.
> 
IMHO you will need to fix the other drivers too

I'll test on at91

Best Regards,
J.

[U-Boot] [PATCH 6/9] Add 16bpp BMP support

[Anatolij Gustschin]

Hello Guennadi,

>  #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
> -			*(fb++) = *(bmap++);
> +				*(fb++) = *(bmap++);
>  #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
> -			*(fb++)=255-*(bmap++);
> +				*(fb++)=255-*(bmap++);

please add space around '=' and '-' here.

> +#if defined(CONFIG_ATMEL_LCD_BGR555)
> +				*(fb++) = ((bmap[0] & 0x1f) << 2) | (bmap[1] & 0x03);
> +				*(fb++) = (bmap[0] & 0xe0) | ((bmap[1] & 0x7c) >> 2);

both lines above to long (> 80), please fix.

Thanks,
Anatolij

[U-Boot] [PATCH 6/9] Add 16bpp BMP support

[Anatolij Gustschin]

Anatolij Gustschin wrote:
> Hello Guennadi,
> 
>>  #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
>> -			*(fb++) = *(bmap++);
>> +				*(fb++) = *(bmap++);
>>  #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
>> -			*(fb++)=255-*(bmap++);
>> +				*(fb++)=255-*(bmap++);
> 
> please add space around '=' and '-' here.

Ah, ignore this part as this is addressed in the next patch 7/9.

Thanks,
Anatolij

[U-Boot] [PATCH 1/9] i.MX31: fix SPI driver for shorter than 32 bit transfers

[Mike Frysinger]

On Wednesday 04 February 2009 17:39:45 Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 17:59 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> > Fix 8 and 16-bit transfers in mxc_spi driver and a wrong pointer in the
> > free routine.
> >
> > Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> > ---
> >
> > No SPI custodian, so, Jean-Christophe will have to Ack it?
>
> I'd like to have Mike and Haaward ack too

i dont have any arm hardware let alone familiar with any hardware-level things 
like the SPI controller.  so from a quick high level look ...

does this controller actually support transfers that arent a multiple of 8 ?  
if the smallest increment you can do is 8bits, then you should be rejecting 
anything that isnt a multiple of it rather than holding the user's hand.  as 
for the assumption that "more than 32bits means do 32bit transfers", that 
sounds plain wrong to me.  u-boot should do exactly as instructed and nothing 
more/less.  so if the user tries to send 40bits, that better be 40bits and not 
64bits.

the spi_free_slave() change looks correct ... not that it should change the 
generated code as spi_slave is the first member of mxc_spi_slave, so they'll 
be the same pointer and gcc will do the right thing.
-mike
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[U-Boot] MPC8548_eTSEC to Marvell 88E1145 E0 version Phy Initialization

[Ajeesh Kumar]

 
Hello,

We have a custom board with MPC8548E processor.
eTSECn are connected to a Marvell 88E1145 PHY(Quad PHY- 4 Ports) chip.
Connection is of type RGMII.
Also, we are able to read all the PHY addresses and registers.
But the contents are not according to our usage, this is due to the default
h/w configuration pins on PHY chip.
We also read in the Marvell data sheet that PHY chip is register
configurable too. 
But during initialization ( under drivers/tsec.c)  below,  even though I'm
giving {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
It is not reflecting in the register after system boots up.

What might be the problem?? Please help me in this regard.

static struct phy_info phy_info_M88E1145 = {
        0x01410cd,
        "Marvell 88E1145",
        4,
        (struct phy_cmd[]){     /* config */
                           /* Reset the PHY */
                           {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},

                           /* Errata E0, E1 */
                           {29, 0x001b, NULL},
                           {30, 0x418f, NULL},
                           {29, 0x0016, NULL},
                           {30, 0xa2da, NULL},

                           /*Configure the PHY*/
                           {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT,
NULL},
                           {MIIM_STATUS, miim_read, NULL},
                           {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
                           {MIIM_88E1011_PHY_SCR,
MIIM_88E1011_PHY_MDI_X_AUTO,NULL},
                           {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
                           {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
                           {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
                           {miim_end,}
                           },
        (struct phy_cmd[]){     /* startup */
                           /* Status is read once to clear old link state */
                           {MIIM_STATUS, miim_read, NULL},
                           /* Auto-negotiate */
                           {MIIM_STATUS, miim_read, &mii_parse_sr},
 
{MIIM_88E1111_PHY_LED_CONTROL,MIIM_88E1111_PHY_LED_DIRECT, NULL},
                           /* Read the Status */
                           {MIIM_88E1011_PHY_STATUS,
miim_read,&mii_parse_88E1011_psr},
                           {miim_end,}
                           },
        (struct phy_cmd[]){     /* shutdown */
                           {miim_end,}
                           },
};

Thanks,
Ajeesh Kumar


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[U-Boot] [PATCH 1/9] i.MX31: fix SPI driver for shorter than 32 bit transfers

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Mike Frysinger wrote:

> On Wednesday 04 February 2009 17:39:45 Jean-Christophe PLAGNIOL-VILLARD wrote:
> > On 17:59 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> > > Fix 8 and 16-bit transfers in mxc_spi driver and a wrong pointer in the
> > > free routine.
> > >
> > > Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> > > ---
> > >
> > > No SPI custodian, so, Jean-Christophe will have to Ack it?
> >
> > I'd like to have Mike and Haaward ack too
> 
> i dont have any arm hardware let alone familiar with any hardware-level things 
> like the SPI controller.  so from a quick high level look ...
> 
> does this controller actually support transfers that arent a multiple of 8 ?  

Yes, it does.

> if the smallest increment you can do is 8bits, then you should be rejecting 
> anything that isnt a multiple of it rather than holding the user's hand.  as 
> for the assumption that "more than 32bits means do 32bit transfers", that 
> sounds plain wrong to me.  u-boot should do exactly as instructed and nothing 
> more/less.  so if the user tries to send 40bits, that better be 40bits and not 
> 64bits.

That's what my patch would do, but it is actually unclear to me what you 
should do for 40 bits? Do you want to send 32 + 8 or 20 + 20 or?.. In 
fact, I would reject if (bitlen > 32 && (bitlen & 31)). But, for example, 
mpc8xxx_spi.c also first sends data in 32-bit chunks, and then the rest. 
But I just noticed there is another bug in my driver, the bit-length in 
the control register is set wrongly if (bitlen > 32). Also, the function 
can be simplified by putting the 32-bit loop bofore residue transfer. I'll 
change both in the next revision.

> the spi_free_slave() change looks correct ... not that it should change the 
> generated code as spi_slave is the first member of mxc_spi_slave, so they'll 
> be the same pointer and gcc will do the right thing.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 3/9] i.MX31: support GPIO as a chip-select in the mxc_spi driver

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Jean-Christophe PLAGNIOL-VILLARD wrote:

> On 17:59 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> >  
> > +	/*
> > +	 * Some SPI devices require active chip-select over multiple
> > +	 * transactions, we achieve this using a GPIO. Still, the SPI
> > +	 * controller has to be configured to use one of its own chipselects.
> > +	 * To use this feature you have to call spi_setup_slave() with
> > +	 * cs = internal_cs | (gpio << 8), and you have to use some unused
> > +	 * on this SPI controller cs between 0 and 3.
> > +	 */
> > +	if (cs > 3) {
> > +		mxcs->gpio = cs >> 8;
> > +		cs &= 3;
> > +		mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT);
> > +	} else
> > +		mxcs->gpio = -1;
> > +
> why not add a callback for the chipselect instead
> as example if you have to use a gpio extender it will simplest to implent
> instead of hack the SPI driver

and how shall I pass this callback to

struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
			unsigned int max_hz, unsigned int mode)

?

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 4/9] A driver for the S6E63D6 SPI display controller from Samsung

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Anatolij Gustschin wrote:

> Hi Guennadi,
> 
> > +struct s6e63d6 {
> > +	unsigned int bus;
> > +	unsigned int cs;
> > +	struct spi_slave *slave;
> > +};
> 
> could we use "bus" and "cs" from struct spi_slave? "struct spi_slave"
> declares them already. Maybe we should drop struct s6e63d6 entirely and use
> struct spi_slave instead?

No, cs and bus here are input parameters, set up by the caller to 
s6e63d6_init() and used by the latter to setup the SPI-slave. slave is 
driver-"private" field, the caller doesn't need to know what is under 
s6e63d6.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 4/9] A driver for the S6E63D6 SPI display controller from Samsung

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Jean-Christophe PLAGNIOL-VILLARD wrote:

> On 17:59 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> > +
> > +/*
> > + * Each transfer is performed as:
> > + * 1. chip-select active
> > + * 2. send 8-bit start code
> > + * 3. send 16-bit data
> > + * 4. chip-select inactive
> > + */
> > +static int send_word(struct spi_slave *spi, u8 rs, u16 data)
> > +{
> > +	u32 buf8 = 0x70 | ID | (rs & 2);
> why?

That's how the start byte looks like:

01110<ID><RS><R/W>

rs is 0 for index or 1 for data, and R/W is 0 for write.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 9/9] ARM: add an "eet" variant of the imx31_phycore board

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Wolfgang Denk wrote:

> Dear Guennadi Liakhovetski,
> 
> In message <Pine.LNX.4.64.0902042316110.6279@axis700.grange> you wrote:
> >
> > > > +#ifdef BOARD_LATE_INIT
> > > CONFIG_?
> > 
> > grep?:
> > 
> > $ grep -r BOARD_LATE_INIT lib*
> > lib_arm/board.c:#ifdef BOARD_LATE_INIT
> > lib_nios2/board.c:#if defined(CONFIG_BOARD_LATE_INIT)
> > lib_sh/board.c:#ifdef BOARD_LATE_INIT
> > lib_sparc/board.c:#if defined(CONFIG_BOARD_LATE_INIT)
> 
> Good idea to search - so you can fix the other occurances, too.

This is outside of the scope of this patch series, so, I'll put it on my 
todo.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 4/9] A driver for the S6E63D6 SPI display controller from Samsung

[Wolfgang Denk]

Dear Guennadi Liakhovetski,

In message <Pine.LNX.4.64.0902051131450.5553@axis700.grange> you wrote:
> On Wed, 4 Feb 2009, Jean-Christophe PLAGNIOL-VILLARD wrote:
> 
> > On 17:59 Wed 04 Feb     , Guennadi Liakhovetski wrote:
> > > +
> > > +/*
> > > + * Each transfer is performed as:
> > > + * 1. chip-select active
> > > + * 2. send 8-bit start code
> > > + * 3. send 16-bit data
> > > + * 4. chip-select inactive
> > > + */
> > > +static int send_word(struct spi_slave *spi, u8 rs, u16 data)
> > > +{
> > > +	u32 buf8 = 0x70 | ID | (rs & 2);
> > why?
> 
> That's how the start byte looks like:
> 
> 01110<ID><RS><R/W>
> 
> rs is 0 for index or 1 for data, and R/W is 0 for write.

Good. Now add this as comment, please?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Question: How does one get fresh air into a Russian church?
Answer:   One clicks on an icon, and a window opens!

[U-Boot] [PATCH 0/9 v2] ARM: Support for splashimage om i.MX31-based phycore "eet" variant

[Guennadi Liakhovetski]

On Wed, 4 Feb 2009, Guennadi Liakhovetski wrote:

Hi again,

this is version 2 of the patch-series, that adds support for the graphics 
engine on i.MX31 SoC. Changes since v1 will be reflected in each single 
patch. And - we still have one more day in the merge window...:-)

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 1/9 v2] i.MX31: fix SPI driver for shorter than 32 bit transfers

[Guennadi Liakhovetski]

Fix 8 and 16-bit transfers in mxc_spi driver and a wrong pointer in the
free routine.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: chose a simpler fix

[U-Boot] [PATCH 2/9 v2] i.MX31: add a simple gpio driver

[Guennadi Liakhovetski]

This is a minimal driver, so far only managing output. It will
be used by the mxc_spi.c driver.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: alphabetical order, typo in copyright fixed, use 
ARRAY_SIZE.

 drivers/gpio/Makefile            |    3 +-
 drivers/gpio/mx31_gpio.c         |   73 ++++++++++++++++++++++++++++++++++++++
 include/asm-arm/arch-mx31/mx31.h |   20 ++++++++++
 3 files changed, 95 insertions(+), 1 deletions(-)
 create mode 100644 drivers/gpio/mx31_gpio.c

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index dd618ed..f10144f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk
 
 LIB 	:= $(obj)libgpio.a
 
-COBJS-$(CONFIG_PCA953X)	+= pca953x.o
+COBJS-$(CONFIG_MX31_GPIO)	+= mx31_gpio.o
+COBJS-$(CONFIG_PCA953X)		+= pca953x.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)
diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c
new file mode 100644
index 0000000..6487e63
--- /dev/null
+++ b/drivers/gpio/mx31_gpio.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+/* GPIO port description */
+static unsigned long gpio_ports[] = {
+	[0] = 0x53fcc000,
+	[1] = 0x53fd0000,
+	[2] = 0x53fa4000,
+};
+
+int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction)
+{
+	unsigned int port = gpio >> 5;
+	u32 l;
+
+	if (port >= ARRAY_SIZE(gpio_ports))
+		return 1;
+
+	gpio &= 0x1f;
+
+	l = __REG(gpio_ports[port] + 4);
+	switch (direction) {
+	case MX31_GPIO_DIRECTION_OUT:
+		l |= 1 << gpio;
+		break;
+	case MX31_GPIO_DIRECTION_IN:
+		l &= ~(1 << gpio);
+	}
+	__REG(gpio_ports[port] + 4) = l;
+
+	return 0;
+}
+
+void mx31_gpio_set(unsigned int gpio, unsigned int value)
+{
+	unsigned int port = gpio >> 5;
+	u32 l;
+
+	if (port > sizeof(gpio_ports) / sizeof(gpio_ports[0]) - 1)
+		return;
+
+	gpio &= 0x1f;
+
+	l = __REG(gpio_ports[port] + 0);
+	if (value)
+		l |= 1 << gpio;
+	else
+		l &= ~(1 << gpio);
+	__REG(gpio_ports[port] + 0) = l;
+}
diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h
index 0552c27..e957d72 100644
--- a/include/asm-arm/arch-mx31/mx31.h
+++ b/include/asm-arm/arch-mx31/mx31.h
@@ -27,4 +27,24 @@
 extern u32 mx31_get_ipg_clk(void);
 extern void mx31_gpio_mux(unsigned long mode);
 
+enum mx31_gpio_direction {
+	MX31_GPIO_DIRECTION_IN,
+	MX31_GPIO_DIRECTION_OUT,
+};
+
+#ifdef CONFIG_MX31_GPIO
+extern int mx31_gpio_direction(unsigned int gpio,
+			       enum mx31_gpio_direction direction);
+extern void mx31_gpio_set(unsigned int gpio, unsigned int value);
+#else
+static inline int mx31_gpio_direction(unsigned int gpio,
+			       enum mx31_gpio_direction direction)
+{
+	return 1;
+}
+static inline void mx31_gpio_set(unsigned int gpio, unsigned int value)
+{
+}
+#endif
+
 #endif /* __ASM_ARCH_MX31_H */
-- 
1.5.4

[U-Boot] [PATCH 3/9 v2] i.MX31: support GPIO as a chip-select in the mxc_spi driver

[Guennadi Liakhovetski]

Some SPI devices have special requirements on chip-select handling.
With this patch we can use a GPIO as a chip-select and strictly follow
the SPI_XFER_BEGIN and SPI_XFER_END flags.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: long lines split, mx31_gpio_* calls now also defined if 
CONFIG_MX31_GPIO is not defined (see patch 2/9), '!!' removed.

 drivers/spi/mxc_spi.c |   47 +++++++++++++++++++++++++++++++++++++++--------
 1 files changed, 39 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index b7bd84b..1341543 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -32,6 +32,8 @@
 
 #else
 
+#include <asm/arch/mx31.h>
+
 #define MXC_CSPIRXDATA		0x00
 #define MXC_CSPITXDATA		0x04
 #define MXC_CSPICTRL		0x08
@@ -68,6 +70,7 @@ struct mxc_spi_slave {
 	struct spi_slave slave;
 	unsigned long	base;
 	u32		ctrl_reg;
+	int		gpio;
 };
 
 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
@@ -85,7 +88,8 @@ static inline void reg_write(unsigned long addr, u32 val)
 	*(volatile unsigned long*)addr = val;
 }
 
-static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
+static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
+			   unsigned long flags)
 {
 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
@@ -96,6 +100,9 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
 		reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
 	}
 
+	if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
+		mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
+
 	reg_write(mxcs->base + MXC_CSPITXDATA, data);
 
 	cfg_reg |= MXC_CSPICTRL_XCH;
@@ -105,6 +112,10 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
 	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
 		;
 
+	if (mxcs->gpio > 0 && (flags & SPI_XFER_END))
+		mx31_gpio_set(mxcs->gpio,
+			      !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
+
 	return reg_read(mxcs->base + MXC_CSPIRXDATA);
 }
 
@@ -123,7 +134,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
 	     i < n_blks;
 	     i++, in_l++, out_l++, bitlen -= 32) {
-		u32 data = spi_xchg_single(slave, *out_l, bitlen);
+		u32 data = spi_xchg_single(slave, *out_l, bitlen, flags);
 
 		/* Check if we're only transfering 8 or 16 bits */
 		if (!i) {
@@ -146,11 +157,35 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 {
 	unsigned int ctrl_reg;
 	struct mxc_spi_slave *mxcs;
+	int ret;
 
-	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) ||
-	    cs > 3)
+	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]))
+		return NULL;
+
+	mxcs = malloc(sizeof(struct mxc_spi_slave));
+	if (!mxcs)
 		return NULL;
 
+	/*
+	 * Some SPI devices require active chip-select over multiple
+	 * transactions, we achieve this using a GPIO. Still, the SPI
+	 * controller has to be configured to use one of its own chipselects.
+	 * To use this feature you have to call spi_setup_slave() with
+	 * cs = internal_cs | (gpio << 8), and you have to use some unused
+	 * on this SPI controller cs between 0 and 3.
+	 */
+	if (cs > 3) {
+		mxcs->gpio = cs >> 8;
+		cs &= 3;
+		ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT);
+		if (ret) {
+			printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
+			return NULL;
+		}
+	} else {
+		mxcs->gpio = -1;
+	}
+
 	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
 		MXC_CSPICTRL_BITCOUNT(31) |
 		MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
@@ -164,10 +199,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (mode & SPI_CS_HIGH)
 		ctrl_reg |= MXC_CSPICTRL_SSPOL;
 
-	mxcs = malloc(sizeof(struct mxc_spi_slave));
-	if (!mxcs)
-		return NULL;
-
 	mxcs->slave.bus = bus;
 	mxcs->slave.cs = cs;
 	mxcs->base = spi_bases[bus];
-- 
1.5.4

[U-Boot] [PATCH 4/9 v2] A driver for the S6E63D6 SPI display controller from Samsung

[Guennadi Liakhovetski]

This is a driver for the S6E63D6 SPI OLED display controller from Samsung.
It only provides access to controller's registers so the client can freely
configure it.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: parameters added in function declarations, alphabetical 
order in Makefile, id made configurable by the user, renamed 
configuration parameter to CONFIG_S6E63D6.

 drivers/video/Makefile  |    1 +
 drivers/video/s6e63d6.c |   70 +++++++++++++++++++++++++++++++++++++++++++++++
 include/s6e63d6.h       |   37 +++++++++++++++++++++++++
 3 files changed, 108 insertions(+), 0 deletions(-)
 create mode 100644 drivers/video/s6e63d6.c
 create mode 100644 include/s6e63d6.h

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7fba29f..84d4cb7 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -28,6 +28,7 @@ LIB	:= $(obj)libvideo.a
 COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o
 COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
+COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
 COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
diff --git a/drivers/video/s6e63d6.c b/drivers/video/s6e63d6.c
new file mode 100644
index 0000000..4a59f05
--- /dev/null
+++ b/drivers/video/s6e63d6.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <spi.h>
+#include <s6e63d6.h>
+
+/*
+ * Each transfer is performed as:
+ * 1. chip-select active
+ * 2. send 8-bit start code
+ * 3. send 16-bit data
+ * 4. chip-select inactive
+ */
+static int send_word(struct s6e63d6 *data, u8 rs, u16 word)
+{
+	u32 buf8 = 0x70 | data->id | (rs & 2);
+	u32 buf16 = cpu_to_le16(word);
+	u32 buf_in;
+	int err;
+
+	err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN);
+	if (err)
+		return err;
+	return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END);
+}
+
+/* Index and param differ in Register Select bit */
+int s6e63d6_index(struct s6e63d6 *data, u8 idx)
+{
+	return send_word(data, 0, idx);
+}
+
+int s6e63d6_param(struct s6e63d6 *data, u16 param)
+{
+	return send_word(data, 2, param);
+}
+
+int s6e63d6_init(struct s6e63d6 *data)
+{
+	if (data->id != 0 && data->id != 4) {
+		printf("s6e63d6: invalid ID %u\n", data->id);
+		return 1;
+	}
+
+	data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3);
+	if (!data->slave)
+		return 1;
+
+	return 0;
+}
diff --git a/include/s6e63d6.h b/include/s6e63d6.h
new file mode 100644
index 0000000..9f17fc0
--- /dev/null
+++ b/include/s6e63d6.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _S6E63D6_H_
+#define _S6E63D6_H_
+
+struct s6e63d6 {
+	unsigned int bus;
+	unsigned int cs;
+	unsigned int id;
+	struct spi_slave *slave;
+};
+
+extern int s6e63d6_init(struct s6e63d6 *data);
+extern int s6e63d6_index(struct s6e63d6 *data, u8 idx);
+extern int s6e63d6_param(struct s6e63d6 *data, u16 param);
+
+#endif
-- 
1.5.4

[U-Boot] [PATCH 5/9 v2] ARM: remove unused variable

[Guennadi Liakhovetski]

The "size" variable in start_armboot() in lib_arm/board.c is only really
used in
#ifndef CONFIG_SYS_NO_FLASH
case, and even there it can be eliminated (thanks to Jean-Christophe
PLAGNIOL-VILLARD for a suggestion.)

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: removed the "size" variable completely.

 lib_arm/board.c |   10 +++-------
 1 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/lib_arm/board.c b/lib_arm/board.c
index 964f5cc..41f7603 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -287,9 +287,6 @@ void start_armboot (void)
 {
 	init_fnc_t **init_fnc_ptr;
 	char *s;
-#if !defined(CONFIG_SYS_NO_FLASH) || defined (CONFIG_VFD) || defined(CONFIG_LCD)
-	ulong size;
-#endif
 #if defined(CONFIG_VFD) || defined(CONFIG_LCD)
 	unsigned long addr;
 #endif
@@ -315,8 +312,7 @@ void start_armboot (void)
 
 #ifndef CONFIG_SYS_NO_FLASH
 	/* configure available FLASH banks */
-	size = flash_init ();
-	display_flash_config (size);
+	display_flash_config (flash_init ());
 #endif /* CONFIG_SYS_NO_FLASH */
 
 #ifdef CONFIG_VFD
@@ -328,7 +324,7 @@ void start_armboot (void)
 	 */
 	/* bss_end is defined in the board-specific linker script */
 	addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
-	size = vfd_setmem (addr);
+	vfd_setmem (addr);
 	gd->fb_base = addr;
 #endif /* CONFIG_VFD */
 
@@ -343,7 +339,7 @@ void start_armboot (void)
 		 */
 		/* bss_end is defined in the board-specific linker script */
 		addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
-		size = lcd_setmem (addr);
+		lcd_setmem (addr);
 		gd->fb_base = addr;
 	}
 #endif /* CONFIG_LCD */
-- 
1.5.4

[U-Boot] [PATCH 6/9 v2] Add 16bpp BMP support

[Guennadi Liakhovetski]

From: Mark Jackson <mpfj@mimc.co.uk>

This patch adds 16bpp BMP support to the common lcd code.

Use CONFIG_BMP_16BPP and set LCD_BPP to LCD_COLOR16 to enable the code.

At the moment it's only been tested on the MIMC200 AVR32 board, but extending
this to other platforms should be a simple task !!

Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: added this comment to explain, that this patch from Mark 
Jackson is included in this patch series for completeness, because future 
patches base on it, long lines split.

 common/lcd.c |   51 +++++++++++++++++++++++++++++++++++++++++----------
 1 files changed, 41 insertions(+), 10 deletions(-)

diff --git a/common/lcd.c b/common/lcd.c
index 5f73247..756b30d 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -84,7 +84,7 @@ extern void lcd_enable (void);
 static void *lcd_logo (void);
 
 
-#if LCD_BPP == LCD_COLOR8
+#if (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
 extern void lcd_setcolreg (ushort regno,
 				ushort red, ushort green, ushort blue);
 #endif
@@ -656,7 +656,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 
 	bpix = NBITS(panel_info.vl_bpix);
 
-	if ((bpix != 1) && (bpix != 8)) {
+	if ((bpix != 1) && (bpix != 8) && (bpix != 16)) {
 		printf ("Error: %d bit/pixel mode not supported by U-Boot\n",
 			bpix);
 		return 1;
@@ -738,17 +738,48 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
 	fb   = (uchar *) (lcd_base +
 		(y + height - 1) * lcd_line_length + x);
-	for (i = 0; i < height; ++i) {
-		WATCHDOG_RESET();
-		for (j = 0; j < width ; j++)
+
+	switch (bpix) {
+	case 1: /* pass through */
+	case 8:
+		for (i = 0; i < height; ++i) {
+			WATCHDOG_RESET();
+			for (j = 0; j < width ; j++)
 #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
-			*(fb++) = *(bmap++);
+				*(fb++) = *(bmap++);
 #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
-			*(fb++)=255-*(bmap++);
+				*(fb++)=255-*(bmap++);
 #endif
-		bmap += (width - padded_line);
-		fb   -= (width + lcd_line_length);
-	}
+			bmap += (width - padded_line);
+			fb   -= (width + lcd_line_length);
+		}
+		break;
+
+#if defined(CONFIG_BMP_16BPP)
+	case 16:
+		for (i = 0; i < height; ++i) {
+			WATCHDOG_RESET();
+			for (j = 0; j < width; j++) {
+#if defined(CONFIG_ATMEL_LCD_BGR555)
+				*(fb++) = ((bmap[0] & 0x1f) << 2) |
+					(bmap[1] & 0x03);
+				*(fb++) = (bmap[0] & 0xe0) |
+					((bmap[1] & 0x7c) >> 2);
+				bmap += 2;
+#else
+				*(fb++) = *(bmap++);
+				*(fb++) = *(bmap++);
+#endif
+			}
+			bmap += (padded_line - width) * 2;
+			fb   -= (width * 2 + lcd_line_length);
+		}
+		break;
+#endif /* CONFIG_BMP_16BPP */
+
+	default:
+		break;
+	};
 
 	return (0);
 }
-- 
1.5.4

[U-Boot] [PATCH 7/9 v2] LCD: support 8bpp BMPs on 16bpp displays

[Guennadi Liakhovetski]

This patch also simplifies some ifdefs in lcd.c, introduces a generic
vidinfo_t, which new drivers are encouraged to use and old drivers to switch
over to.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: no changes.

 common/lcd.c  |   56 ++++++++++++++++++++++++++++++++------------------------
 include/lcd.h |   21 +++++++++++++--------
 2 files changed, 45 insertions(+), 32 deletions(-)

diff --git a/common/lcd.c b/common/lcd.c
index 756b30d..e4ac6c2 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -622,19 +622,15 @@ void bitmap_plot (int x, int y)
  */
 int lcd_display_bitmap(ulong bmp_image, int x, int y)
 {
-#ifdef CONFIG_ATMEL_LCD
-	uint *cmap;
-#elif !defined(CONFIG_MCC200)
-	ushort *cmap;
-#endif
+	ushort *cmap = NULL, *cmap_base = NULL;
 	ushort i, j;
 	uchar *fb;
 	bmp_image_t *bmp=(bmp_image_t *)bmp_image;
 	uchar *bmap;
 	ushort padded_line;
-	unsigned long width, height;
+	unsigned long width, height, byte_width;
 	unsigned long pwidth = panel_info.vl_col;
-	unsigned colors,bpix;
+	unsigned colors, bpix, bmp_bpix;
 	unsigned long compression;
 #if defined(CONFIG_PXA250)
 	struct pxafb_info *fbi = &panel_info.pxa;
@@ -647,22 +643,24 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		(bmp->header.signature[1]=='M'))) {
 		printf ("Error: no valid bmp image at %lx\n", bmp_image);
 		return 1;
-}
+	}
 
 	width = le32_to_cpu (bmp->header.width);
 	height = le32_to_cpu (bmp->header.height);
-	colors = 1<<le16_to_cpu (bmp->header.bit_count);
+	bmp_bpix = le16_to_cpu(bmp->header.bit_count);
+	colors = 1 << bmp_bpix;
 	compression = le32_to_cpu (bmp->header.compression);
 
 	bpix = NBITS(panel_info.vl_bpix);
 
 	if ((bpix != 1) && (bpix != 8) && (bpix != 16)) {
-		printf ("Error: %d bit/pixel mode not supported by U-Boot\n",
-			bpix);
+		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
+			bpix, bmp_bpix);
 		return 1;
 	}
 
-	if (bpix != le16_to_cpu(bmp->header.bit_count)) {
+	/* We support displaying 8bpp BMPs on 16bpp LCDs */
+	if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16)) {
 		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
 			bpix,
 			le16_to_cpu(bmp->header.bit_count));
@@ -674,17 +672,17 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 
 #if !defined(CONFIG_MCC200)
 	/* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
-	if (bpix==8) {
+	if (bmp_bpix == 8) {
 #if defined(CONFIG_PXA250)
 		cmap = (ushort *)fbi->palette;
 #elif defined(CONFIG_MPC823)
 		cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
-#elif defined(CONFIG_ATMEL_LCD)
-		cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0));
-#else
-# error "Don't know location of color map"
+#elif !defined(CONFIG_ATMEL_LCD)
+		cmap = panel_info.cmap;
 #endif
 
+		cmap_base = cmap;
+
 		/* Set color map */
 		for (i=0; i<colors; ++i) {
 			bmp_color_table_entry_t cte = bmp->color_table[i];
@@ -698,10 +696,10 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 #else
 			*cmap = colreg;
 #endif
-#if defined(CONFIG_PXA250)
-			cmap++;
-#elif defined(CONFIG_MPC823)
+#if defined(CONFIG_MPC823)
 			cmap--;
+#else
+			cmap++;
 #endif
 #else /* CONFIG_ATMEL_LCD */
 			lcd_setcolreg(i, cte.red, cte.green, cte.blue);
@@ -739,19 +737,29 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	fb   = (uchar *) (lcd_base +
 		(y + height - 1) * lcd_line_length + x);
 
-	switch (bpix) {
+	switch (bmp_bpix) {
 	case 1: /* pass through */
 	case 8:
+		if (bpix != 16)
+			byte_width = width;
+		else
+			byte_width = width * 2;
+
 		for (i = 0; i < height; ++i) {
 			WATCHDOG_RESET();
 			for (j = 0; j < width ; j++)
+				if (bpix!=16) {
 #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
-				*(fb++) = *(bmap++);
+					*(fb++) = *(bmap++);
 #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
-				*(fb++)=255-*(bmap++);
+					*(fb++) = 255 - *(bmap++);
 #endif
+				} else {
+					*(uint16_t *)fb = cmap_base[*(bmap++)];
+					fb += sizeof(uint16_t) / sizeof(*fb);
+				}
 			bmap += (width - padded_line);
-			fb   -= (width + lcd_line_length);
+			fb   -= (byte_width + lcd_line_length);
 		}
 		break;
 
diff --git a/include/lcd.h b/include/lcd.h
index 512221e..f054cac 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -148,14 +148,6 @@ typedef struct vidinfo {
 
 extern vidinfo_t panel_info;
 
-#elif defined(CONFIG_MCC200)
-typedef struct vidinfo {
-	ushort	vl_col;		/* Number of columns (i.e. 160) */
-	ushort	vl_row;		/* Number of rows (i.e. 100) */
-
-	u_char	vl_bpix;	/* Bits per pixel, 0 = 1 */
-} vidinfo_t;
-
 #elif defined(CONFIG_ATMEL_LCD)
 
 typedef struct vidinfo {
@@ -183,6 +175,19 @@ typedef struct vidinfo {
 
 extern vidinfo_t panel_info;
 
+#else
+
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 160) */
+	ushort	vl_row;		/* Number of rows (i.e. 100) */
+
+	u_char	vl_bpix;	/* Bits per pixel, 0 = 1 */
+
+	ushort	*cmap;		/* Pointer to the colormap */
+
+	void	*priv;		/* Pointer to driver-specific data */
+} vidinfo_t;
+
 #endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */
 
 /* Video functions */
-- 
1.5.4

[U-Boot] [PATCH 8/9 v2] video: add a i.MX31 framebuffer driver

[Guennadi Liakhovetski]

Add a driver for the Synchronous Display Controller and the Display
Interface on i.MX31, using IPU for DMA channel setup. So far only
displaying of bitmaps is supported, no text output.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: added breaks, shorter title, splitted long lines, 
unified style.

[U-Boot] [PATCH 9/9 v2] ARM: add an "eet" variant of the imx31_phycore board

[Guennadi Liakhovetski]

The "eet" variant of the imx31_phycore board has an OLED display, using a
s6e63d6 display controller on the first SPI interface, using GPIO57 as a
chip-select for it. With this configuration you can display 256 colour BMP
images in 16-bit RGB (RGB565) LCD mode.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: adjusted to reflect changes in earlier patches: add .id 
field initialisation, configuration parameter renamed to CONFIG_S6E63D6.

 Makefile                              |    6 +++-
 board/imx31_phycore/imx31_phycore.c   |   52 +++++++++++++++++++++++++++++++++
 include/asm-arm/arch-mx31/mx31-regs.h |   16 ++++++++++
 include/configs/imx31_phycore.h       |   23 ++++++++++++++
 4 files changed, 96 insertions(+), 1 deletions(-)

diff --git a/Makefile b/Makefile
index 787c5f2..6151e2c 100644
--- a/Makefile
+++ b/Makefile
@@ -3025,8 +3025,12 @@ apollon_config		: unconfig
 imx31_litekit_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
 
+imx31_phycore_eet_config \
 imx31_phycore_config	: unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
+	@if [ -n "$(findstring imx31_phycore_eet_config,$@)" ]; then			\
+		echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h;	\
+	fi
+	@$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31
 
 mx31ads_config		: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
index 4c64cb9..6b7cbb6 100644
--- a/board/imx31_phycore/imx31_phycore.c
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -23,6 +23,7 @@
 
 
 #include <common.h>
+#include <s6e63d6.h>
 #include <asm/arch/mx31.h>
 #include <asm/arch/mx31-regs.h>
 
@@ -66,6 +67,57 @@ int board_init (void)
 	return 0;
 }
 
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_DISPLAY_S6E63D6
+	struct s6e63d6 data = {
+		.cs = 2 | (57 << 8),
+		.bus = 0,
+		.id = 0,
+	};
+	int ret;
+
+	/* SPI1 */
+	mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
+	mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
+	mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
+	mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
+	mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
+	mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
+
+	/* start SPI1 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
+
+	/* GPIO 57 */
+	/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
+	mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
+
+	/* SPI1 CS2 is free */
+	ret = s6e63d6_init(&data);
+	if (ret)
+		return ret;
+
+	/*
+	 * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
+	 * OLED display connected to a S6E63D6 SPI display controller in the
+	 * 18 bit RGB mode
+	 */
+	s6e63d6_index(&data, 2);
+	s6e63d6_param(&data, 0x0182);
+	s6e63d6_index(&data, 3);
+	s6e63d6_param(&data, 0x8130);
+	s6e63d6_index(&data, 0x10);
+	s6e63d6_param(&data, 0x0000);
+	s6e63d6_index(&data, 5);
+	s6e63d6_param(&data, 0x0001);
+	s6e63d6_index(&data, 0x22);
+#endif
+	return 0;
+}
+#endif
+
 int checkboard (void)
 {
 	printf("Board: Phytec phyCore i.MX31\n");
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index e736052..dcc0805 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -124,7 +124,14 @@
 #define MUX_CTL_CSPI2_SS0	0x85
 #define MUX_CTL_CSPI2_SS1	0x86
 #define MUX_CTL_CSPI2_SS2	0x87
+#define MUX_CTL_CSPI1_SS2	0x88
+#define MUX_CTL_CSPI1_SCLK	0x89
+#define MUX_CTL_CSPI1_SPI_RDY	0x8a
 #define MUX_CTL_CSPI2_MOSI	0x8b
+#define MUX_CTL_CSPI1_MOSI	0x8c
+#define MUX_CTL_CSPI1_MISO	0x8d
+#define MUX_CTL_CSPI1_SS0	0x8e
+#define MUX_CTL_CSPI1_SS1	0x8f
 
 /*
  * Helper macros for the MUX_[contact name]__[pin function] macros
@@ -150,6 +157,15 @@
 	IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
 
+#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
+#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
+#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
+#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
+	IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
+#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
+
 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
 
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index f0d28ee..2dd9e92 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -178,4 +178,27 @@
 #undef CONFIG_JFFS2_CMDLINE
 #define CONFIG_JFFS2_DEV	"nor0"
 
+/* EET platform additions */
+#ifdef CONFIG_IMX31_PHYCORE_EET
+#define BOARD_LATE_INIT
+
+#define CONFIG_MX31_GPIO			1
+
+#define CONFIG_HARD_SPI				1
+#define CONFIG_MXC_SPI				1
+#define CONFIG_CMD_SPI
+
+#define CONFIG_S6E63D6				1
+
+#define CONFIG_LCD				1
+#define CONFIG_VIDEO_MX3			1
+#define CONFIG_SYS_WHITE_ON_BLACK		1
+#define LCD_BPP					LCD_COLOR8
+#define	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+
+#define	CONFIG_SPLASH_SCREEN			1
+#define CONFIG_CMD_BMP				1
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.5.4

[U-Boot] [PATCH 2/9 v2] i.MX31: add a simple gpio driver

[Anatolij Gustschin]

Hi Guennadi,

Guennadi Liakhovetski wrote:

> diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c
> new file mode 100644
> index 0000000..6487e63
> --- /dev/null
> +++ b/drivers/gpio/mx31_gpio.c
<snip>
> +#include <common.h>
> +#include <asm/arch/mx31.h>
> +#include <asm/arch/mx31-regs.h>
> +
> +/* GPIO port description */
> +static unsigned long gpio_ports[] = {
> +	[0] = 0x53fcc000,
> +	[1] = 0x53fd0000,
> +	[2] = 0x53fa4000,
> +};

Ilya send a patch for mx31 GPIO register definitions today
http://lists.denx.de/pipermail/u-boot/2009-February/046884.html

Could you please provide additional patch for drivers/gpio/mx31_gpio.c
based on Ilya's patch to use these GPIOx_BASE macros here and to
use GPIO_DR / GPIO_GDIR for 0 / 4 below? Thanks!

> +void mx31_gpio_set(unsigned int gpio, unsigned int value)
> +{
> +	unsigned int port = gpio >> 5;
> +	u32 l;
> +
> +	if (port > sizeof(gpio_ports) / sizeof(gpio_ports[0]) - 1)

also please change this one to
	if (port >= ARRAY_SIZE(gpio_ports))
too, to be consistent with coding in this file, Thanks!

> +		return;
> +
> +	gpio &= 0x1f;
> +
> +	l = __REG(gpio_ports[port] + 0);
> +	if (value)
> +		l |= 1 << gpio;
> +	else
> +		l &= ~(1 << gpio);
> +	__REG(gpio_ports[port] + 0) = l;
> +}
> diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h
> index 0552c27..e957d72 100644
> --- a/include/asm-arm/arch-mx31/mx31.h
> +++ b/include/asm-arm/arch-mx31/mx31.h
> @@ -27,4 +27,24 @@
>  extern u32 mx31_get_ipg_clk(void);
>  extern void mx31_gpio_mux(unsigned long mode);
>  
> +enum mx31_gpio_direction {
> +	MX31_GPIO_DIRECTION_IN,
> +	MX31_GPIO_DIRECTION_OUT,
> +};
> +
> +#ifdef CONFIG_MX31_GPIO
> +extern int mx31_gpio_direction(unsigned int gpio,
> +			       enum mx31_gpio_direction direction);
________________________^^^^^^^
please remove spaces here, Thanks!

> +extern void mx31_gpio_set(unsigned int gpio, unsigned int value);
> +#else
> +static inline int mx31_gpio_direction(unsigned int gpio,
> +			       enum mx31_gpio_direction direction)
________________________^^^^^^^
please remove spaces here too, Thanks!

Best regards,
Anatolij

[U-Boot] [PATCH 2/9 v2] i.MX31: add a simple gpio driver

[Guennadi Liakhovetski]

On Thu, 5 Feb 2009, Anatolij Gustschin wrote:

> Hi Guennadi,
> 
> Guennadi Liakhovetski wrote:
> 
> > diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c
> > new file mode 100644
> > index 0000000..6487e63
> > --- /dev/null
> > +++ b/drivers/gpio/mx31_gpio.c
> <snip>
> > +#include <common.h>
> > +#include <asm/arch/mx31.h>
> > +#include <asm/arch/mx31-regs.h>
> > +
> > +/* GPIO port description */
> > +static unsigned long gpio_ports[] = {
> > +	[0] = 0x53fcc000,
> > +	[1] = 0x53fd0000,
> > +	[2] = 0x53fa4000,
> > +};
> 
> Ilya send a patch for mx31 GPIO register definitions today
> http://lists.denx.de/pipermail/u-boot/2009-February/046884.html
> 
> Could you please provide additional patch for drivers/gpio/mx31_gpio.c
> based on Ilya's patch to use these GPIOx_BASE macros here and to
> use GPIO_DR / GPIO_GDIR for 0 / 4 below? Thanks!

Do you mean an incremental patch or a v3?

> > diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h
> > index 0552c27..e957d72 100644
> > --- a/include/asm-arm/arch-mx31/mx31.h
> > +++ b/include/asm-arm/arch-mx31/mx31.h
> > @@ -27,4 +27,24 @@
> >  extern u32 mx31_get_ipg_clk(void);
> >  extern void mx31_gpio_mux(unsigned long mode);
> >  
> > +enum mx31_gpio_direction {
> > +	MX31_GPIO_DIRECTION_IN,
> > +	MX31_GPIO_DIRECTION_OUT,
> > +};
> > +
> > +#ifdef CONFIG_MX31_GPIO
> > +extern int mx31_gpio_direction(unsigned int gpio,
> > +			       enum mx31_gpio_direction direction);
> ________________________^^^^^^^
> please remove spaces here, Thanks!

No, these are intentional and correct. They align beginning of the second 
line with the first character after the opening parenthesis.

> > +extern void mx31_gpio_set(unsigned int gpio, unsigned int value);
> > +#else
> > +static inline int mx31_gpio_direction(unsigned int gpio,
> > +			       enum mx31_gpio_direction direction)
> ________________________^^^^^^^
> please remove spaces here too, Thanks!

Ok, this one I just copy-pasted from above, so, it broke alignment.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 1/9] i.MX31: fix SPI driver for shorter than 32 bit transfers

[Mike Frysinger]

On Thursday 05 February 2009 03:28:17 Guennadi Liakhovetski wrote:
> On Wed, 4 Feb 2009, Mike Frysinger wrote:
> > if the smallest increment you can do is 8bits, then you should be
> > rejecting anything that isnt a multiple of it rather than holding the
> > user's hand.  as for the assumption that "more than 32bits means do 32bit
> > transfers", that sounds plain wrong to me.  u-boot should do exactly as
> > instructed and nothing more/less.  so if the user tries to send 40bits,
> > that better be 40bits and not 64bits.
>
> That's what my patch would do, but it is actually unclear to me what you
> should do for 40 bits? Do you want to send 32 + 8 or 20 + 20 or?.. In
> fact, I would reject if (bitlen > 32 && (bitlen & 31)). But, for example,
> mpc8xxx_spi.c also first sends data in 32-bit chunks, and then the rest.
> But I just noticed there is another bug in my driver, the bit-length in
> the control register is set wrongly if (bitlen > 32). Also, the function
> can be simplified by putting the 32-bit loop bofore residue transfer. I'll
> change both in the next revision.

sending out in 32bit chunks and then sending out the remainder with the 
correct size sounds like the most efficient.  there is no requirement in terms 
of how bits get grouped as any sane SPI device should operate properly as data 
is only read when the clock is asserted, and the clock is only asserted when 
actual bits are being shifted.
-mike
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[U-Boot] [PATCH 2/9 v2] i.MX31: add a simple gpio driver

[Anatolij Gustschin]

Guennadi Liakhovetski wrote:

>>> +/* GPIO port description */
>>> +static unsigned long gpio_ports[] = {
>>> +	[0] = 0x53fcc000,
>>> +	[1] = 0x53fd0000,
>>> +	[2] = 0x53fa4000,
>>> +};
>> Ilya send a patch for mx31 GPIO register definitions today
>> http://lists.denx.de/pipermail/u-boot/2009-February/046884.html
>>
>> Could you please provide additional patch for drivers/gpio/mx31_gpio.c
>> based on Ilya's patch to use these GPIOx_BASE macros here and to
>> use GPIO_DR / GPIO_GDIR for 0 / 4 below? Thanks!
> 
> Do you mean an incremental patch or a v3?

yes, an incremental patch, as I don't know when Ilya's patch
will be applied. This way we will be able to use the driver now
(not dependent on Ilya's patch) and fix things later by
applying an incremental patch.

>>> +#ifdef CONFIG_MX31_GPIO
>>> +extern int mx31_gpio_direction(unsigned int gpio,
>>> +			       enum mx31_gpio_direction direction);
>> ________________________^^^^^^^
>> please remove spaces here, Thanks!
> 
> No, these are intentional and correct. They align beginning of the second 
> line with the first character after the opening parenthesis.

yes this is correct, I'm aware of it. But while reviewing the spi patch
an so looking on the code in drivers/spi/mxc_spi.c I noticed that
you also used indentation by tabs in spi_xfer() and spi_setup_slave()
and also in the mx31_gpio_direction() prototype definition. So it
seemed for me that you would prefer to use indentation by tabs here.
So ignore this one please, Sorry.

Thanks,
Anatolij

[U-Boot] [PATCH 3/9 v2] i.MX31: support GPIO as a chip-select in the mxc_spi driver

[Anatolij Gustschin]

Guennadi Liakhovetski wrote:

> diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
> index b7bd84b..1341543 100644
> --- a/drivers/spi/mxc_spi.c
> +++ b/drivers/spi/mxc_spi.c
<snip>
> @@ -105,6 +112,10 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
>  	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
>  		;
>  
> +	if (mxcs->gpio > 0 && (flags & SPI_XFER_END))
> +		mx31_gpio_set(mxcs->gpio,
> +			      !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));

this is a multi-line if statement, I think the preferred coding style
is as follows:
	if (...) {
		/*
		 * multi-line if statement
		 */
		...
	}
please fix, Thanks!

> @@ -146,11 +157,35 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
>  {
>  	unsigned int ctrl_reg;
>  	struct mxc_spi_slave *mxcs;
> +	int ret;
>  
> -	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) ||
> -	    cs > 3)
> +	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]))

please use ARRAY_SIZE() here, too. Thanks!

Best regards,
Anatolij

[U-Boot] [PATCH 4/9 v2] A driver for the S6E63D6 SPI display controller from Samsung

[Anatolij Gustschin]

Guennadi Liakhovetski wrote:

> diff --git a/drivers/video/s6e63d6.c b/drivers/video/s6e63d6.c
> new file mode 100644
> index 0000000..4a59f05
> --- /dev/null
> +++ b/drivers/video/s6e63d6.c
<snip>
> +static int send_word(struct s6e63d6 *data, u8 rs, u16 word)
> +{
> +	u32 buf8 = 0x70 | data->id | (rs & 2);
> +	u32 buf16 = cpu_to_le16(word);
> +	u32 buf_in;
> +	int err;
> +
> +	err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN);
> +	if (err)
> +		return err;
> +	return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END);

please add an empty line between two return statements here, Thanks!

Best regards,
Anatolij

[U-Boot] [PATCH 3/9 v2] i.MX31: support GPIO as a chip-select in the mxc_spi driver

[Guennadi Liakhovetski]

On Thu, 5 Feb 2009, Anatolij Gustschin wrote:

> Guennadi Liakhovetski wrote:
> 
> > diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
> > index b7bd84b..1341543 100644
> > --- a/drivers/spi/mxc_spi.c
> > +++ b/drivers/spi/mxc_spi.c
> <snip>
> > @@ -105,6 +112,10 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
> >  	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
> >  		;
> >  
> > +	if (mxcs->gpio > 0 && (flags & SPI_XFER_END))
> > +		mx31_gpio_set(mxcs->gpio,
> > +			      !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
> 
> this is a multi-line if statement, I think the preferred coding style
> is as follows:
> 	if (...) {
> 		/*
> 		 * multi-line if statement
> 		 */
> 		...
> 	}
> please fix, Thanks!

Sorry, cannot find this in CodingStyle. Can you point me out? What I do 
find there is this example in Chapter 2:

	if (condition)
		printk(KERN_WARNING "Warning this is a long printk with "
						"3 parameters a: %u b: %u "
						"c: %u \n", a, b, c);
	else
		next_statement;

which implicitly (it is given as an example of breaking lines, not 
parenthesising) states the contrary to your proposition.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 4/9 v2] A driver for the S6E63D6 SPI display controller from Samsung

[Guennadi Liakhovetski]

On Thu, 5 Feb 2009, Anatolij Gustschin wrote:

> Guennadi Liakhovetski wrote:
> 
> > diff --git a/drivers/video/s6e63d6.c b/drivers/video/s6e63d6.c
> > new file mode 100644
> > index 0000000..4a59f05
> > --- /dev/null
> > +++ b/drivers/video/s6e63d6.c
> <snip>
> > +static int send_word(struct s6e63d6 *data, u8 rs, u16 word)
> > +{
> > +	u32 buf8 = 0x70 | data->id | (rs & 2);
> > +	u32 buf16 = cpu_to_le16(word);
> > +	u32 buf_in;
> > +	int err;
> > +
> > +	err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN);
> > +	if (err)
> > +		return err;
> > +	return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END);
> 
> please add an empty line between two return statements here, Thanks!

Is this also required by CodingStyle?

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 3/9 v2] i.MX31: support GPIO as a chip-select in the mxc_spi driver

[Anatolij Gustschin]

Guennadi Liakhovetski wrote:
> On Thu, 5 Feb 2009, Anatolij Gustschin wrote:
> 
>> Guennadi Liakhovetski wrote:
>>
>>> diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
>>> index b7bd84b..1341543 100644
>>> --- a/drivers/spi/mxc_spi.c
>>> +++ b/drivers/spi/mxc_spi.c
>> <snip>
>>> @@ -105,6 +112,10 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
>>>  	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
>>>  		;
>>>  
>>> +	if (mxcs->gpio > 0 && (flags & SPI_XFER_END))
>>> +		mx31_gpio_set(mxcs->gpio,
>>> +			      !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
>> this is a multi-line if statement, I think the preferred coding style
>> is as follows:
>> 	if (...) {
>> 		/*
>> 		 * multi-line if statement
>> 		 */
>> 		...
>> 	}
>> please fix, Thanks!
> 
> Sorry, cannot find this in CodingStyle. Can you point me out?

please see appropriate comments in

http://lists.denx.de/pipermail/u-boot/2008-December/044435.html
or in
http://lists.denx.de/pipermail/u-boot/2008-October/042634.html
(search for "Braces around multi-line if-bodies").

> What I do 
> find there is this example in Chapter 2:
> 
> 	if (condition)
> 		printk(KERN_WARNING "Warning this is a long printk with "
> 						"3 parameters a: %u b: %u "
> 						"c: %u \n", a, b, c);
> 	else
> 		next_statement;
> 
> which implicitly (it is given as an example of breaking lines, not 
> parenthesising) states the contrary to your proposition.

Linux CodingStyle mostly applies for U-Boot coding style, but
sometimes there are little differences.

Best regargs,
Anatolij

[U-Boot] [PATCH 4/9 v2] A driver for the S6E63D6 SPI display controller from Samsung

[Anatolij Gustschin]

Guennadi Liakhovetski wrote:

>>> +	err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN);
>>> +	if (err)
>>> +		return err;
>>> +	return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END);
>> please add an empty line between two return statements here, Thanks!
> 
> Is this also required by CodingStyle?

not explicitly, but IMHO, it slightly improves readability and
also will be consistent with style used in s6e63d6_init() some
lines below. It seems to be preferred style in other code, too.

Best regards,
Anatolij

[U-Boot] [PATCH 8/9 v2] video: add a i.MX31 framebuffer driver

[Anatolij Gustschin]

Guennadi Liakhovetski wrote:
> Add a driver for the Synchronous Display Controller and the Display
> Interface on i.MX31, using IPU for DMA channel setup. So far only
> displaying of bitmaps is supported, no text output.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>

mostly looks good, please see some comments below.

> diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
> new file mode 100644
> index 0000000..d9b673e
> --- /dev/null
> +++ b/drivers/video/mx3fb.c
<snip>
> +/**
> + * sdc_init_panel() - initialize a synchronous LCD panel.
> + * @mx3fb:		mx3fb context.
> + * @panel:		panel type.
> + * @pixel_clk:		desired pixel clock frequency in Hz.
> + * @width:		width of panel in pixels.
> + * @height:		height of panel in pixels.
> + * @pixel_fmt:		pixel format of buffer as FOURCC ASCII code.
> + * @h_start_width:	number of pixel clocks between the HSYNC signal pulse
> + *			and the start of valid data.
> + * @h_sync_width:	width of the HSYNC signal in units of pixel clocks.
> + * @h_end_width:	number of pixel clocks between the end of valid data
> + *			and the HSYNC signal for next line.
> + * @v_start_width:	number of lines between the VSYNC signal pulse and the
> + *			start of valid data.
> + * @v_sync_width:	width of the VSYNC signal in units of lines
> + * @v_end_width:	number of lines between the end of valid data and the
> + *			VSYNC signal for next frame.
> + * @sig:		bitfield of signal polarities for LCD interface.
> + * @return:		0 on success or negative error code on failure.
> + */
> +static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt)

function parameters description is from the Linux driver,
however most of them are not present here in U-Boot driver.
Is there any reason you leave the original description here?
Also please replace starting '/**' with '/*'.

<snip>
> +static void ipu_ch_param_set_size(union chan_param_mem *params,
> +				  uint32_t pixel_fmt, uint16_t width,
> +				  uint16_t height, uint16_t stride)
> +{
> +	params->pp.fw		= width - 1;
> +	params->pp.fh_l		= height - 1;
> +	params->pp.fh_h		= (height - 1) >> 8;
> +	params->pp.sl		= stride - 1;
> +
> +	/* See above, for further formats see tge Linux driver */

s/tge/the/
?

<snip>
> +/**
> + * ipu_enable_channel() - enable an IPU channel.
> + * @channel:	channel ID.
> + * @return:	0 on success or negative error code on failure.
> + */
> +static int ipu_enable_channel(enum ipu_channel channel)

just use '/*' here, too.

<snip>
> +/**
> + * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
> + * @fbi:	framebuffer information pointer.
> + * @return:	0 on success or negative error code on failure.
> + */
> +static int mx3fb_set_par(void *fbmem)

use '/*' here, too. Thanks!
Also @fbi description doesn't apply here, 'fbmem' is frame buffer
memory pointer.

Best regards,
Anatolij

[U-Boot] [PATCH 9/9 v2] ARM: add an "eet" variant of the imx31_phycore board

[Anatolij Gustschin]

Guennadi Liakhovetski wrote:

<snip>
> diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
> index 4c64cb9..6b7cbb6 100644
> --- a/board/imx31_phycore/imx31_phycore.c
> +++ b/board/imx31_phycore/imx31_phycore.c
<snip>
> @@ -66,6 +67,57 @@ int board_init (void)
>  	return 0;
>  }
>  
> +#ifdef BOARD_LATE_INIT
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_DISPLAY_S6E63D6

please change this one to CONFIG_S6E63D6, too. Thanks!

Best regards,
Anatolij

[U-Boot] [PATCH 0/9 v3] ARM: Support for splashimage om i.MX31-based phycore "eet" variant

[Guennadi Liakhovetski]

Hi again,

this is version 3 of the patch-series, that adds support for the graphics 
engine on i.MX31 SoC. Changes since v1 and v2 will be reflected in each 
single patch. As all correction requests have been addressed, I hope we 
can get it in on the last day of the merge window (today). Should any 
further problems surface, we can address them in incremental patches.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 1/9 v3] i.MX31: fix SPI driver for shorter than 32 bit transfers

[Guennadi Liakhovetski]

Fix setting the SPI Control register, 8 and 16-bit transfers and a wrong
pointer in the free routine in the mxc_spi driver.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: chose a simpler fix
Changes since v2: fix the simpler fix: v2 worked as long as I just 
resetted the board, powering the board down showed, that v2 wasn't 
sufficient, it has lost the SPI Control register fix from v1.

 drivers/spi/mxc_spi.c |   30 +++++++++++++++++++-----------
 1 files changed, 19 insertions(+), 11 deletions(-)

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 5957ada..3135817 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -90,17 +90,15 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
 
-	if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) {
-		cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
-			MXC_CSPICTRL_BITCOUNT(bitlen - 1);
-		reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
-	}
+	mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
+		MXC_CSPICTRL_BITCOUNT(bitlen - 1);
 
-	reg_write(mxcs->base + MXC_CSPITXDATA, data);
+	if (cfg_reg != mxcs->ctrl_reg)
+		reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
 
-	cfg_reg |= MXC_CSPICTRL_XCH;
+	reg_write(mxcs->base + MXC_CSPITXDATA, data);
 
-	reg_write(mxcs->base + MXC_CSPICTRL, cfg_reg);
+	reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_XCH);
 
 	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
 		;
@@ -122,8 +120,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 
 	for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
 	     i < n_blks;
-	     i++, in_l++, out_l++, bitlen -= 32)
-		*in_l = spi_xchg_single(slave, *out_l, bitlen);
+	     i++, in_l++, out_l++, bitlen -= 32) {
+		u32 data = spi_xchg_single(slave, *out_l, bitlen);
+
+		/* Check if we're only transfering 8 or 16 bits */
+		if (!i) {
+			if (bitlen < 9)
+				*(u8 *)din = data;
+			else if (bitlen < 17)
+				*(u16 *)din = data;
+		}
+	}
 
 	return 0;
 }
@@ -169,7 +176,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 
 void spi_free_slave(struct spi_slave *slave)
 {
-	free(slave);
+	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
+	free(mxcs);
 }
 
 int spi_claim_bus(struct spi_slave *slave)
-- 
1.5.4

[U-Boot] [PATCH 2/9 v3] i.MX31: add a simple gpio driver

[Guennadi Liakhovetski]

This is a minimal driver, so far only managing output. It will
be used by the mxc_spi.c driver.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: alphabetical order, typo in copyright fixed, use 
ARRAY_SIZE.
Changes since v2: fixed wrong indentation in int mx31_gpio_direction() 
declaration.

 drivers/gpio/Makefile            |    3 +-
 drivers/gpio/mx31_gpio.c         |   73 ++++++++++++++++++++++++++++++++++++++
 include/asm-arm/arch-mx31/mx31.h |   20 ++++++++++
 3 files changed, 95 insertions(+), 1 deletions(-)
 create mode 100644 drivers/gpio/mx31_gpio.c

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index dd618ed..f10144f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk
 
 LIB 	:= $(obj)libgpio.a
 
-COBJS-$(CONFIG_PCA953X)	+= pca953x.o
+COBJS-$(CONFIG_MX31_GPIO)	+= mx31_gpio.o
+COBJS-$(CONFIG_PCA953X)		+= pca953x.o
 
 COBJS	:= $(COBJS-y)
 SRCS 	:= $(COBJS:.o=.c)
diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c
new file mode 100644
index 0000000..166deaf
--- /dev/null
+++ b/drivers/gpio/mx31_gpio.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+
+/* GPIO port description */
+static unsigned long gpio_ports[] = {
+	[0] = 0x53fcc000,
+	[1] = 0x53fd0000,
+	[2] = 0x53fa4000,
+};
+
+int mx31_gpio_direction(unsigned int gpio, enum mx31_gpio_direction direction)
+{
+	unsigned int port = gpio >> 5;
+	u32 l;
+
+	if (port >= ARRAY_SIZE(gpio_ports))
+		return 1;
+
+	gpio &= 0x1f;
+
+	l = __REG(gpio_ports[port] + 4);
+	switch (direction) {
+	case MX31_GPIO_DIRECTION_OUT:
+		l |= 1 << gpio;
+		break;
+	case MX31_GPIO_DIRECTION_IN:
+		l &= ~(1 << gpio);
+	}
+	__REG(gpio_ports[port] + 4) = l;
+
+	return 0;
+}
+
+void mx31_gpio_set(unsigned int gpio, unsigned int value)
+{
+	unsigned int port = gpio >> 5;
+	u32 l;
+
+	if (port >= ARRAY_SIZE(gpio_ports))
+		return;
+
+	gpio &= 0x1f;
+
+	l = __REG(gpio_ports[port] + 0);
+	if (value)
+		l |= 1 << gpio;
+	else
+		l &= ~(1 << gpio);
+	__REG(gpio_ports[port] + 0) = l;
+}
diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h
index 0552c27..1d475dd 100644
--- a/include/asm-arm/arch-mx31/mx31.h
+++ b/include/asm-arm/arch-mx31/mx31.h
@@ -27,4 +27,24 @@
 extern u32 mx31_get_ipg_clk(void);
 extern void mx31_gpio_mux(unsigned long mode);
 
+enum mx31_gpio_direction {
+	MX31_GPIO_DIRECTION_IN,
+	MX31_GPIO_DIRECTION_OUT,
+};
+
+#ifdef CONFIG_MX31_GPIO
+extern int mx31_gpio_direction(unsigned int gpio,
+			       enum mx31_gpio_direction direction);
+extern void mx31_gpio_set(unsigned int gpio, unsigned int value);
+#else
+static inline int mx31_gpio_direction(unsigned int gpio,
+				      enum mx31_gpio_direction direction)
+{
+	return 1;
+}
+static inline void mx31_gpio_set(unsigned int gpio, unsigned int value)
+{
+}
+#endif
+
 #endif /* __ASM_ARCH_MX31_H */
-- 
1.5.4

[U-Boot] [PATCH 3/9 v3] i.MX31: support GPIO as a chip-select in the mxc_spi driver

[Guennadi Liakhovetski]

Some SPI devices have special requirements on chip-select handling.
With this patch we can use a GPIO as a chip-select and strictly follow
the SPI_XFER_BEGIN and SPI_XFER_END flags.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: long lines split, mx31_gpio_* calls now also defined if 
CONFIG_MX31_GPIO is not defined (see patch 2/9), '!!' removed.
Changes since v2: added braces in a multiline if, switched to 
ARRAY_SIZE().

 drivers/spi/mxc_spi.c |   48 ++++++++++++++++++++++++++++++++++++++++--------
 1 files changed, 40 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 3135817..524b2e1 100644
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -32,6 +32,8 @@
 
 #else
 
+#include <asm/arch/mx31.h>
+
 #define MXC_CSPIRXDATA		0x00
 #define MXC_CSPITXDATA		0x04
 #define MXC_CSPICTRL		0x08
@@ -68,6 +70,7 @@ struct mxc_spi_slave {
 	struct spi_slave slave;
 	unsigned long	base;
 	u32		ctrl_reg;
+	int		gpio;
 };
 
 static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
@@ -85,7 +88,8 @@ static inline void reg_write(unsigned long addr, u32 val)
 	*(volatile unsigned long*)addr = val;
 }
 
-static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
+static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
+			   unsigned long flags)
 {
 	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
 	unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
@@ -96,6 +100,9 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
 	if (cfg_reg != mxcs->ctrl_reg)
 		reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
 
+	if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
+		mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
+
 	reg_write(mxcs->base + MXC_CSPITXDATA, data);
 
 	reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_XCH);
@@ -103,6 +110,11 @@ static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen)
 	while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
 		;
 
+	if (mxcs->gpio > 0 && (flags & SPI_XFER_END)) {
+		mx31_gpio_set(mxcs->gpio,
+			      !(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
+	}
+
 	return reg_read(mxcs->base + MXC_CSPIRXDATA);
 }
 
@@ -121,7 +133,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 	for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
 	     i < n_blks;
 	     i++, in_l++, out_l++, bitlen -= 32) {
-		u32 data = spi_xchg_single(slave, *out_l, bitlen);
+		u32 data = spi_xchg_single(slave, *out_l, bitlen, flags);
 
 		/* Check if we're only transfering 8 or 16 bits */
 		if (!i) {
@@ -144,11 +156,35 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 {
 	unsigned int ctrl_reg;
 	struct mxc_spi_slave *mxcs;
+	int ret;
 
-	if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) ||
-	    cs > 3)
+	if (bus >= ARRAY_SIZE(spi_bases))
+		return NULL;
+
+	mxcs = malloc(sizeof(struct mxc_spi_slave));
+	if (!mxcs)
 		return NULL;
 
+	/*
+	 * Some SPI devices require active chip-select over multiple
+	 * transactions, we achieve this using a GPIO. Still, the SPI
+	 * controller has to be configured to use one of its own chipselects.
+	 * To use this feature you have to call spi_setup_slave() with
+	 * cs = internal_cs | (gpio << 8), and you have to use some unused
+	 * on this SPI controller cs between 0 and 3.
+	 */
+	if (cs > 3) {
+		mxcs->gpio = cs >> 8;
+		cs &= 3;
+		ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT);
+		if (ret) {
+			printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
+			return NULL;
+		}
+	} else {
+		mxcs->gpio = -1;
+	}
+
 	ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
 		MXC_CSPICTRL_BITCOUNT(31) |
 		MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
@@ -162,10 +198,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (mode & SPI_CS_HIGH)
 		ctrl_reg |= MXC_CSPICTRL_SSPOL;
 
-	mxcs = malloc(sizeof(struct mxc_spi_slave));
-	if (!mxcs)
-		return NULL;
-
 	mxcs->slave.bus = bus;
 	mxcs->slave.cs = cs;
 	mxcs->base = spi_bases[bus];
-- 
1.5.4

[U-Boot] [PATCH 4/9 v3] A driver for the S6E63D6 SPI display controller from Samsung

[Guennadi Liakhovetski]

This is a driver for the S6E63D6 SPI OLED display controller from Samsung.
It only provides access to controller's registers so the client can freely
configure it.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: parameters added in function declarations, alphabetical 
order in Makefile, id made configurable by the user, renamed 
configuration parameter to CONFIG_S6E63D6.
Changes since v2: added a comment, explaining the start byte format, empty 
line added before the final return in a function.

 drivers/video/Makefile  |    1 +
 drivers/video/s6e63d6.c |   76 +++++++++++++++++++++++++++++++++++++++++++++++
 include/s6e63d6.h       |   37 +++++++++++++++++++++++
 3 files changed, 114 insertions(+), 0 deletions(-)
 create mode 100644 drivers/video/s6e63d6.c
 create mode 100644 include/s6e63d6.h

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 7fba29f..84d4cb7 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -28,6 +28,7 @@ LIB	:= $(obj)libvideo.a
 COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o
 COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
+COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
 COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
diff --git a/drivers/video/s6e63d6.c b/drivers/video/s6e63d6.c
new file mode 100644
index 0000000..d163506
--- /dev/null
+++ b/drivers/video/s6e63d6.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <spi.h>
+#include <s6e63d6.h>
+
+/*
+ * Each transfer is performed as:
+ * 1. chip-select active
+ * 2. send 8-bit start code
+ * 3. send 16-bit data
+ * 4. chip-select inactive
+ */
+static int send_word(struct s6e63d6 *data, u8 rs, u16 word)
+{
+	/*
+	 * The start byte looks like (binary):
+	 * 01110<ID><RS><R/W>
+	 * RS is 0 for index or 1 for data, and R/W is 0 for write.
+	 */
+	u32 buf8 = 0x70 | data->id | (rs & 2);
+	u32 buf16 = cpu_to_le16(word);
+	u32 buf_in;
+	int err;
+
+	err = spi_xfer(data->slave, 8, &buf8, &buf_in, SPI_XFER_BEGIN);
+	if (err)
+		return err;
+
+	return spi_xfer(data->slave, 16, &buf16, &buf_in, SPI_XFER_END);
+}
+
+/* Index and param differ in Register Select bit */
+int s6e63d6_index(struct s6e63d6 *data, u8 idx)
+{
+	return send_word(data, 0, idx);
+}
+
+int s6e63d6_param(struct s6e63d6 *data, u16 param)
+{
+	return send_word(data, 2, param);
+}
+
+int s6e63d6_init(struct s6e63d6 *data)
+{
+	if (data->id != 0 && data->id != 4) {
+		printf("s6e63d6: invalid ID %u\n", data->id);
+		return 1;
+	}
+
+	data->slave = spi_setup_slave(data->bus, data->cs, 100000, SPI_MODE_3);
+	if (!data->slave)
+		return 1;
+
+	return 0;
+}
diff --git a/include/s6e63d6.h b/include/s6e63d6.h
new file mode 100644
index 0000000..9f17fc0
--- /dev/null
+++ b/include/s6e63d6.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _S6E63D6_H_
+#define _S6E63D6_H_
+
+struct s6e63d6 {
+	unsigned int bus;
+	unsigned int cs;
+	unsigned int id;
+	struct spi_slave *slave;
+};
+
+extern int s6e63d6_init(struct s6e63d6 *data);
+extern int s6e63d6_index(struct s6e63d6 *data, u8 idx);
+extern int s6e63d6_param(struct s6e63d6 *data, u16 param);
+
+#endif
-- 
1.5.4

[U-Boot] [PATCH 5/9 v3] ARM: remove unused variable

[Guennadi Liakhovetski]

The "size" variable in start_armboot() in lib_arm/board.c is only really 
used in "#ifndef CONFIG_SYS_NO_FLASH" case, and even there it can be 
eliminated (thanks to Jean-Christophe PLAGNIOL-VILLARD for a suggestion.)

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: removed the "size" variable completely.
Changes since v2: none.

 lib_arm/board.c |   10 +++-------
 1 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/lib_arm/board.c b/lib_arm/board.c
index 964f5cc..41f7603 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -287,9 +287,6 @@ void start_armboot (void)
 {
 	init_fnc_t **init_fnc_ptr;
 	char *s;
-#if !defined(CONFIG_SYS_NO_FLASH) || defined (CONFIG_VFD) || defined(CONFIG_LCD)
-	ulong size;
-#endif
 #if defined(CONFIG_VFD) || defined(CONFIG_LCD)
 	unsigned long addr;
 #endif
@@ -315,8 +312,7 @@ void start_armboot (void)
 
 #ifndef CONFIG_SYS_NO_FLASH
 	/* configure available FLASH banks */
-	size = flash_init ();
-	display_flash_config (size);
+	display_flash_config (flash_init ());
 #endif /* CONFIG_SYS_NO_FLASH */
 
 #ifdef CONFIG_VFD
@@ -328,7 +324,7 @@ void start_armboot (void)
 	 */
 	/* bss_end is defined in the board-specific linker script */
 	addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
-	size = vfd_setmem (addr);
+	vfd_setmem (addr);
 	gd->fb_base = addr;
 #endif /* CONFIG_VFD */
 
@@ -343,7 +339,7 @@ void start_armboot (void)
 		 */
 		/* bss_end is defined in the board-specific linker script */
 		addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
-		size = lcd_setmem (addr);
+		lcd_setmem (addr);
 		gd->fb_base = addr;
 	}
 #endif /* CONFIG_LCD */
-- 
1.5.4

[U-Boot] [PATCH 6/9 v3] Add 16bpp BMP support

[Guennadi Liakhovetski]

From: Mark Jackson <mpfj@mimc.co.uk>

This patch adds 16bpp BMP support to the common lcd code.

Use CONFIG_BMP_16BPP and set LCD_BPP to LCD_COLOR16 to enable the code.

At the moment it's only been tested on the MIMC200 AVR32 board, but extending
this to other platforms should be a simple task !!

Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: added this comment to explain, that this patch from Mark 
Jackson is included in this patch series for completeness, because future 
patches base on it, long lines split.
Changes since v2: none.

 common/lcd.c |   51 +++++++++++++++++++++++++++++++++++++++++----------
 1 files changed, 41 insertions(+), 10 deletions(-)

diff --git a/common/lcd.c b/common/lcd.c
index 5f73247..756b30d 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -84,7 +84,7 @@ extern void lcd_enable (void);
 static void *lcd_logo (void);
 
 
-#if LCD_BPP == LCD_COLOR8
+#if (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16)
 extern void lcd_setcolreg (ushort regno,
 				ushort red, ushort green, ushort blue);
 #endif
@@ -656,7 +656,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 
 	bpix = NBITS(panel_info.vl_bpix);
 
-	if ((bpix != 1) && (bpix != 8)) {
+	if ((bpix != 1) && (bpix != 8) && (bpix != 16)) {
 		printf ("Error: %d bit/pixel mode not supported by U-Boot\n",
 			bpix);
 		return 1;
@@ -738,17 +738,48 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset);
 	fb   = (uchar *) (lcd_base +
 		(y + height - 1) * lcd_line_length + x);
-	for (i = 0; i < height; ++i) {
-		WATCHDOG_RESET();
-		for (j = 0; j < width ; j++)
+
+	switch (bpix) {
+	case 1: /* pass through */
+	case 8:
+		for (i = 0; i < height; ++i) {
+			WATCHDOG_RESET();
+			for (j = 0; j < width ; j++)
 #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
-			*(fb++) = *(bmap++);
+				*(fb++) = *(bmap++);
 #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
-			*(fb++)=255-*(bmap++);
+				*(fb++)=255-*(bmap++);
 #endif
-		bmap += (width - padded_line);
-		fb   -= (width + lcd_line_length);
-	}
+			bmap += (width - padded_line);
+			fb   -= (width + lcd_line_length);
+		}
+		break;
+
+#if defined(CONFIG_BMP_16BPP)
+	case 16:
+		for (i = 0; i < height; ++i) {
+			WATCHDOG_RESET();
+			for (j = 0; j < width; j++) {
+#if defined(CONFIG_ATMEL_LCD_BGR555)
+				*(fb++) = ((bmap[0] & 0x1f) << 2) |
+					(bmap[1] & 0x03);
+				*(fb++) = (bmap[0] & 0xe0) |
+					((bmap[1] & 0x7c) >> 2);
+				bmap += 2;
+#else
+				*(fb++) = *(bmap++);
+				*(fb++) = *(bmap++);
+#endif
+			}
+			bmap += (padded_line - width) * 2;
+			fb   -= (width * 2 + lcd_line_length);
+		}
+		break;
+#endif /* CONFIG_BMP_16BPP */
+
+	default:
+		break;
+	};
 
 	return (0);
 }
-- 
1.5.4

[U-Boot] [PATCH 7/9 v3] LCD: support 8bpp BMPs on 16bpp displays

[Guennadi Liakhovetski]

This patch also simplifies some ifdefs in lcd.c, introduces a generic
vidinfo_t, which new drivers are encouraged to use and old drivers to switch
over to.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: no changes.

 common/lcd.c  |   56 ++++++++++++++++++++++++++++++++------------------------
 include/lcd.h |   21 +++++++++++++--------
 2 files changed, 45 insertions(+), 32 deletions(-)

diff --git a/common/lcd.c b/common/lcd.c
index 756b30d..e4ac6c2 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -622,19 +622,15 @@ void bitmap_plot (int x, int y)
  */
 int lcd_display_bitmap(ulong bmp_image, int x, int y)
 {
-#ifdef CONFIG_ATMEL_LCD
-	uint *cmap;
-#elif !defined(CONFIG_MCC200)
-	ushort *cmap;
-#endif
+	ushort *cmap = NULL, *cmap_base = NULL;
 	ushort i, j;
 	uchar *fb;
 	bmp_image_t *bmp=(bmp_image_t *)bmp_image;
 	uchar *bmap;
 	ushort padded_line;
-	unsigned long width, height;
+	unsigned long width, height, byte_width;
 	unsigned long pwidth = panel_info.vl_col;
-	unsigned colors,bpix;
+	unsigned colors, bpix, bmp_bpix;
 	unsigned long compression;
 #if defined(CONFIG_PXA250)
 	struct pxafb_info *fbi = &panel_info.pxa;
@@ -647,22 +643,24 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 		(bmp->header.signature[1]=='M'))) {
 		printf ("Error: no valid bmp image at %lx\n", bmp_image);
 		return 1;
-}
+	}
 
 	width = le32_to_cpu (bmp->header.width);
 	height = le32_to_cpu (bmp->header.height);
-	colors = 1<<le16_to_cpu (bmp->header.bit_count);
+	bmp_bpix = le16_to_cpu(bmp->header.bit_count);
+	colors = 1 << bmp_bpix;
 	compression = le32_to_cpu (bmp->header.compression);
 
 	bpix = NBITS(panel_info.vl_bpix);
 
 	if ((bpix != 1) && (bpix != 8) && (bpix != 16)) {
-		printf ("Error: %d bit/pixel mode not supported by U-Boot\n",
-			bpix);
+		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
+			bpix, bmp_bpix);
 		return 1;
 	}
 
-	if (bpix != le16_to_cpu(bmp->header.bit_count)) {
+	/* We support displaying 8bpp BMPs on 16bpp LCDs */
+	if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16)) {
 		printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n",
 			bpix,
 			le16_to_cpu(bmp->header.bit_count));
@@ -674,17 +672,17 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 
 #if !defined(CONFIG_MCC200)
 	/* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
-	if (bpix==8) {
+	if (bmp_bpix == 8) {
 #if defined(CONFIG_PXA250)
 		cmap = (ushort *)fbi->palette;
 #elif defined(CONFIG_MPC823)
 		cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
-#elif defined(CONFIG_ATMEL_LCD)
-		cmap = (uint *) (panel_info.mmio + ATMEL_LCDC_LUT(0));
-#else
-# error "Don't know location of color map"
+#elif !defined(CONFIG_ATMEL_LCD)
+		cmap = panel_info.cmap;
 #endif
 
+		cmap_base = cmap;
+
 		/* Set color map */
 		for (i=0; i<colors; ++i) {
 			bmp_color_table_entry_t cte = bmp->color_table[i];
@@ -698,10 +696,10 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 #else
 			*cmap = colreg;
 #endif
-#if defined(CONFIG_PXA250)
-			cmap++;
-#elif defined(CONFIG_MPC823)
+#if defined(CONFIG_MPC823)
 			cmap--;
+#else
+			cmap++;
 #endif
 #else /* CONFIG_ATMEL_LCD */
 			lcd_setcolreg(i, cte.red, cte.green, cte.blue);
@@ -739,19 +737,29 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	fb   = (uchar *) (lcd_base +
 		(y + height - 1) * lcd_line_length + x);
 
-	switch (bpix) {
+	switch (bmp_bpix) {
 	case 1: /* pass through */
 	case 8:
+		if (bpix != 16)
+			byte_width = width;
+		else
+			byte_width = width * 2;
+
 		for (i = 0; i < height; ++i) {
 			WATCHDOG_RESET();
 			for (j = 0; j < width ; j++)
+				if (bpix!=16) {
 #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
-				*(fb++) = *(bmap++);
+					*(fb++) = *(bmap++);
 #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
-				*(fb++)=255-*(bmap++);
+					*(fb++) = 255 - *(bmap++);
 #endif
+				} else {
+					*(uint16_t *)fb = cmap_base[*(bmap++)];
+					fb += sizeof(uint16_t) / sizeof(*fb);
+				}
 			bmap += (width - padded_line);
-			fb   -= (width + lcd_line_length);
+			fb   -= (byte_width + lcd_line_length);
 		}
 		break;
 
diff --git a/include/lcd.h b/include/lcd.h
index 512221e..f054cac 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -148,14 +148,6 @@ typedef struct vidinfo {
 
 extern vidinfo_t panel_info;
 
-#elif defined(CONFIG_MCC200)
-typedef struct vidinfo {
-	ushort	vl_col;		/* Number of columns (i.e. 160) */
-	ushort	vl_row;		/* Number of rows (i.e. 100) */
-
-	u_char	vl_bpix;	/* Bits per pixel, 0 = 1 */
-} vidinfo_t;
-
 #elif defined(CONFIG_ATMEL_LCD)
 
 typedef struct vidinfo {
@@ -183,6 +175,19 @@ typedef struct vidinfo {
 
 extern vidinfo_t panel_info;
 
+#else
+
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 160) */
+	ushort	vl_row;		/* Number of rows (i.e. 100) */
+
+	u_char	vl_bpix;	/* Bits per pixel, 0 = 1 */
+
+	ushort	*cmap;		/* Pointer to the colormap */
+
+	void	*priv;		/* Pointer to driver-specific data */
+} vidinfo_t;
+
 #endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */
 
 /* Video functions */
-- 
1.5.4

[U-Boot] [PATCH 8/9 v3] video: add an i.MX31 framebuffer driver

[Guennadi Liakhovetski]

Add a driver for the Synchronous Display Controller and the Display
Interface on i.MX31, using IPU for DMA channel setup. So far only
displaying of bitmaps is supported, no text output.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: added breaks, shorter title, splitted long lines, 
unified style.
Changes since v2: fixed comment formatting, function parameters in 
comments, a typo in a comment, and removed an unused parameter from 
mx3fb_set_par()

 drivers/video/Makefile |    1 +
 drivers/video/mx3fb.c  |  856 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 857 insertions(+), 0 deletions(-)
 create mode 100644 drivers/video/mx3fb.c

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 84d4cb7..bc00852 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -31,6 +31,7 @@ COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
 COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
 COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o
+COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_SED156X) += sed156x.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
new file mode 100644
index 0000000..1e1d507
--- /dev/null
+++ b/drivers/video/mx3fb.c
@@ -0,0 +1,856 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <lcd.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+#include <asm/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void *lcd_base;			/* Start of framebuffer memory	*/
+void *lcd_console_address;	/* Start of console buffer	*/
+
+int lcd_line_length;
+int lcd_color_fg;
+int lcd_color_bg;
+
+short console_col;
+short console_row;
+
+void lcd_initcolregs(void)
+{
+}
+
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+}
+
+void lcd_disable(void)
+{
+}
+
+void lcd_panel_disable(void)
+{
+}
+
+#define msleep(a) udelay(a * 1000)
+
+#define XRES		240
+#define YRES		320
+#define PANEL_TYPE	IPU_PANEL_TFT
+#define PIXEL_CLK	185925
+#define PIXEL_FMT	IPU_PIX_FMT_RGB666
+#define H_START_WIDTH	9		/* left_margin */
+#define H_SYNC_WIDTH	1		/* hsync_len */
+#define H_END_WIDTH	(16 + 1)	/* right_margin + hsync_len */
+#define V_START_WIDTH	7		/* upper_margin */
+#define V_SYNC_WIDTH	1		/* vsync_len */
+#define V_END_WIDTH	(9 + 1)		/* lower_margin + vsync_len */
+#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
+#define IF_CONF		0
+#define IF_CLK_DIV	0x175
+
+#define LCD_COLOR_IPU	LCD_COLOR16
+
+static ushort colormap[256];
+
+vidinfo_t panel_info = {
+	.vl_col		= XRES,
+	.vl_row		= YRES,
+	.vl_bpix	= LCD_COLOR_IPU,
+	.cmap		= colormap,
+};
+
+#define BIT_PER_PIXEL	NBITS(LCD_COLOR_IPU)
+
+/* IPU DMA Controller channel definitions. */
+enum ipu_channel {
+	IDMAC_IC_0 = 0,		/* IC (encoding task) to memory */
+	IDMAC_IC_1 = 1,		/* IC (viewfinder task) to memory */
+	IDMAC_ADC_0 = 1,
+	IDMAC_IC_2 = 2,
+	IDMAC_ADC_1 = 2,
+	IDMAC_IC_3 = 3,
+	IDMAC_IC_4 = 4,
+	IDMAC_IC_5 = 5,
+	IDMAC_IC_6 = 6,
+	IDMAC_IC_7 = 7,		/* IC (sensor data) to memory */
+	IDMAC_IC_8 = 8,
+	IDMAC_IC_9 = 9,
+	IDMAC_IC_10 = 10,
+	IDMAC_IC_11 = 11,
+	IDMAC_IC_12 = 12,
+	IDMAC_IC_13 = 13,
+	IDMAC_SDC_0 = 14,	/* Background synchronous display data */
+	IDMAC_SDC_1 = 15,	/* Foreground data (overlay) */
+	IDMAC_SDC_2 = 16,
+	IDMAC_SDC_3 = 17,
+	IDMAC_ADC_2 = 18,
+	IDMAC_ADC_3 = 19,
+	IDMAC_ADC_4 = 20,
+	IDMAC_ADC_5 = 21,
+	IDMAC_ADC_6 = 22,
+	IDMAC_ADC_7 = 23,
+	IDMAC_PF_0 = 24,
+	IDMAC_PF_1 = 25,
+	IDMAC_PF_2 = 26,
+	IDMAC_PF_3 = 27,
+	IDMAC_PF_4 = 28,
+	IDMAC_PF_5 = 29,
+	IDMAC_PF_6 = 30,
+	IDMAC_PF_7 = 31,
+};
+
+/* More formats can be copied from the Linux driver if needed */
+enum pixel_fmt {
+	/* 2 bytes */
+	IPU_PIX_FMT_RGB565,
+	IPU_PIX_FMT_RGB666,
+	IPU_PIX_FMT_BGR666,
+	/* 3 bytes */
+	IPU_PIX_FMT_RGB24,
+};
+
+struct pixel_fmt_cfg {
+	u32	b0;
+	u32	b1;
+	u32	b2;
+	u32	acc;
+};
+
+static struct pixel_fmt_cfg fmt_cfg[] = {
+	[IPU_PIX_FMT_RGB24] = {
+		0x1600AAAA, 0x00E05555, 0x00070000, 3,
+	},
+	[IPU_PIX_FMT_RGB666] = {
+		0x0005000F, 0x000B000F, 0x0011000F, 1,
+	},
+	[IPU_PIX_FMT_BGR666] = {
+		0x0011000F, 0x000B000F, 0x0005000F, 1,
+	},
+	[IPU_PIX_FMT_RGB565] = {
+		0x0004003F, 0x000A000F, 0x000F003F, 1,
+	}
+};
+
+enum ipu_panel {
+	IPU_PANEL_SHARP_TFT,
+	IPU_PANEL_TFT,
+};
+
+/* IPU Common registers */
+/* IPU_CONF and its bits already defined in mx31-regs.h */
+#define IPU_CHA_BUF0_RDY	(0x04 + IPU_BASE)
+#define IPU_CHA_BUF1_RDY	(0x08 + IPU_BASE)
+#define IPU_CHA_DB_MODE_SEL	(0x0C + IPU_BASE)
+#define IPU_CHA_CUR_BUF		(0x10 + IPU_BASE)
+#define IPU_FS_PROC_FLOW	(0x14 + IPU_BASE)
+#define IPU_FS_DISP_FLOW	(0x18 + IPU_BASE)
+#define IPU_TASKS_STAT		(0x1C + IPU_BASE)
+#define IPU_IMA_ADDR		(0x20 + IPU_BASE)
+#define IPU_IMA_DATA		(0x24 + IPU_BASE)
+#define IPU_INT_CTRL_1		(0x28 + IPU_BASE)
+#define IPU_INT_CTRL_2		(0x2C + IPU_BASE)
+#define IPU_INT_CTRL_3		(0x30 + IPU_BASE)
+#define IPU_INT_CTRL_4		(0x34 + IPU_BASE)
+#define IPU_INT_CTRL_5		(0x38 + IPU_BASE)
+#define IPU_INT_STAT_1		(0x3C + IPU_BASE)
+#define IPU_INT_STAT_2		(0x40 + IPU_BASE)
+#define IPU_INT_STAT_3		(0x44 + IPU_BASE)
+#define IPU_INT_STAT_4		(0x48 + IPU_BASE)
+#define IPU_INT_STAT_5		(0x4C + IPU_BASE)
+#define IPU_BRK_CTRL_1		(0x50 + IPU_BASE)
+#define IPU_BRK_CTRL_2		(0x54 + IPU_BASE)
+#define IPU_BRK_STAT		(0x58 + IPU_BASE)
+#define IPU_DIAGB_CTRL		(0x5C + IPU_BASE)
+
+/* Image Converter Registers */
+#define IC_CONF			(0x88 + IPU_BASE)
+#define IC_PRP_ENC_RSC		(0x8C + IPU_BASE)
+#define IC_PRP_VF_RSC		(0x90 + IPU_BASE)
+#define IC_PP_RSC		(0x94 + IPU_BASE)
+#define IC_CMBP_1		(0x98 + IPU_BASE)
+#define IC_CMBP_2		(0x9C + IPU_BASE)
+#define PF_CONF			(0xA0 + IPU_BASE)
+#define IDMAC_CONF		(0xA4 + IPU_BASE)
+#define IDMAC_CHA_EN		(0xA8 + IPU_BASE)
+#define IDMAC_CHA_PRI		(0xAC + IPU_BASE)
+#define IDMAC_CHA_BUSY		(0xB0 + IPU_BASE)
+
+/* Image Converter Register bits */
+#define IC_CONF_PRPENC_EN	0x00000001
+#define IC_CONF_PRPENC_CSC1	0x00000002
+#define IC_CONF_PRPENC_ROT_EN	0x00000004
+#define IC_CONF_PRPVF_EN	0x00000100
+#define IC_CONF_PRPVF_CSC1	0x00000200
+#define IC_CONF_PRPVF_CSC2	0x00000400
+#define IC_CONF_PRPVF_CMB	0x00000800
+#define IC_CONF_PRPVF_ROT_EN	0x00001000
+#define IC_CONF_PP_EN		0x00010000
+#define IC_CONF_PP_CSC1		0x00020000
+#define IC_CONF_PP_CSC2		0x00040000
+#define IC_CONF_PP_CMB		0x00080000
+#define IC_CONF_PP_ROT_EN	0x00100000
+#define IC_CONF_IC_GLB_LOC_A	0x10000000
+#define IC_CONF_KEY_COLOR_EN	0x20000000
+#define IC_CONF_RWS_EN		0x40000000
+#define IC_CONF_CSI_MEM_WR_EN	0x80000000
+
+/* SDC Registers */
+#define SDC_COM_CONF		(0xB4 + IPU_BASE)
+#define SDC_GW_CTRL		(0xB8 + IPU_BASE)
+#define SDC_FG_POS		(0xBC + IPU_BASE)
+#define SDC_BG_POS		(0xC0 + IPU_BASE)
+#define SDC_CUR_POS		(0xC4 + IPU_BASE)
+#define SDC_PWM_CTRL		(0xC8 + IPU_BASE)
+#define SDC_CUR_MAP		(0xCC + IPU_BASE)
+#define SDC_HOR_CONF		(0xD0 + IPU_BASE)
+#define SDC_VER_CONF		(0xD4 + IPU_BASE)
+#define SDC_SHARP_CONF_1	(0xD8 + IPU_BASE)
+#define SDC_SHARP_CONF_2	(0xDC + IPU_BASE)
+
+/* Register bits */
+#define SDC_COM_TFT_COLOR	0x00000001UL
+#define SDC_COM_FG_EN		0x00000010UL
+#define SDC_COM_GWSEL		0x00000020UL
+#define SDC_COM_GLB_A		0x00000040UL
+#define SDC_COM_KEY_COLOR_G	0x00000080UL
+#define SDC_COM_BG_EN		0x00000200UL
+#define SDC_COM_SHARP		0x00001000UL
+
+#define SDC_V_SYNC_WIDTH_L	0x00000001UL
+
+/* Display Interface registers */
+#define DI_DISP_IF_CONF		(0x0124 + IPU_BASE)
+#define DI_DISP_SIG_POL		(0x0128 + IPU_BASE)
+#define DI_SER_DISP1_CONF	(0x012C + IPU_BASE)
+#define DI_SER_DISP2_CONF	(0x0130 + IPU_BASE)
+#define DI_HSP_CLK_PER		(0x0134 + IPU_BASE)
+#define DI_DISP0_TIME_CONF_1	(0x0138 + IPU_BASE)
+#define DI_DISP0_TIME_CONF_2	(0x013C + IPU_BASE)
+#define DI_DISP0_TIME_CONF_3	(0x0140 + IPU_BASE)
+#define DI_DISP1_TIME_CONF_1	(0x0144 + IPU_BASE)
+#define DI_DISP1_TIME_CONF_2	(0x0148 + IPU_BASE)
+#define DI_DISP1_TIME_CONF_3	(0x014C + IPU_BASE)
+#define DI_DISP2_TIME_CONF_1	(0x0150 + IPU_BASE)
+#define DI_DISP2_TIME_CONF_2	(0x0154 + IPU_BASE)
+#define DI_DISP2_TIME_CONF_3	(0x0158 + IPU_BASE)
+#define DI_DISP3_TIME_CONF	(0x015C + IPU_BASE)
+#define DI_DISP0_DB0_MAP	(0x0160 + IPU_BASE)
+#define DI_DISP0_DB1_MAP	(0x0164 + IPU_BASE)
+#define DI_DISP0_DB2_MAP	(0x0168 + IPU_BASE)
+#define DI_DISP0_CB0_MAP	(0x016C + IPU_BASE)
+#define DI_DISP0_CB1_MAP	(0x0170 + IPU_BASE)
+#define DI_DISP0_CB2_MAP	(0x0174 + IPU_BASE)
+#define DI_DISP1_DB0_MAP	(0x0178 + IPU_BASE)
+#define DI_DISP1_DB1_MAP	(0x017C + IPU_BASE)
+#define DI_DISP1_DB2_MAP	(0x0180 + IPU_BASE)
+#define DI_DISP1_CB0_MAP	(0x0184 + IPU_BASE)
+#define DI_DISP1_CB1_MAP	(0x0188 + IPU_BASE)
+#define DI_DISP1_CB2_MAP	(0x018C + IPU_BASE)
+#define DI_DISP2_DB0_MAP	(0x0190 + IPU_BASE)
+#define DI_DISP2_DB1_MAP	(0x0194 + IPU_BASE)
+#define DI_DISP2_DB2_MAP	(0x0198 + IPU_BASE)
+#define DI_DISP2_CB0_MAP	(0x019C + IPU_BASE)
+#define DI_DISP2_CB1_MAP	(0x01A0 + IPU_BASE)
+#define DI_DISP2_CB2_MAP	(0x01A4 + IPU_BASE)
+#define DI_DISP3_B0_MAP		(0x01A8 + IPU_BASE)
+#define DI_DISP3_B1_MAP		(0x01AC + IPU_BASE)
+#define DI_DISP3_B2_MAP		(0x01B0 + IPU_BASE)
+#define DI_DISP_ACC_CC		(0x01B4 + IPU_BASE)
+#define DI_DISP_LLA_CONF	(0x01B8 + IPU_BASE)
+#define DI_DISP_LLA_DATA	(0x01BC + IPU_BASE)
+
+/* DI_DISP_SIG_POL bits */
+#define DI_D3_VSYNC_POL		(1 << 28)
+#define DI_D3_HSYNC_POL		(1 << 27)
+#define DI_D3_DRDY_SHARP_POL	(1 << 26)
+#define DI_D3_CLK_POL		(1 << 25)
+#define DI_D3_DATA_POL		(1 << 24)
+
+/* DI_DISP_IF_CONF bits */
+#define DI_D3_CLK_IDLE		(1 << 26)
+#define DI_D3_CLK_SEL		(1 << 25)
+#define DI_D3_DATAMSK		(1 << 24)
+
+#define IOMUX_PADNUM_MASK	0x1ff
+#define IOMUX_GPIONUM_SHIFT	9
+#define IOMUX_GPIONUM_MASK	(0xff << IOMUX_GPIONUM_SHIFT)
+
+#define IOMUX_PIN(gpionum, padnum) ((padnum) & IOMUX_PADNUM_MASK)
+
+#define IOMUX_MODE_L(pin, mode) IOMUX_MODE(((pin) + 0xc) ^ 3, mode)
+
+enum lcd_pin {
+	MX31_PIN_D3_SPL		= IOMUX_PIN(0xff,  19),
+	MX31_PIN_D3_CLS		= IOMUX_PIN(0xff,  20),
+	MX31_PIN_D3_REV		= IOMUX_PIN(0xff,  21),
+	MX31_PIN_CONTRAST	= IOMUX_PIN(0xff,  22),
+	MX31_PIN_VSYNC3		= IOMUX_PIN(0xff,  23),
+
+	MX31_PIN_DRDY0		= IOMUX_PIN(0xff,  33),
+	MX31_PIN_FPSHIFT	= IOMUX_PIN(0xff,  34),
+	MX31_PIN_HSYNC		= IOMUX_PIN(0xff,  35),
+
+	MX31_PIN_LD17		= IOMUX_PIN(0xff,  37),
+	MX31_PIN_LD16		= IOMUX_PIN(0xff,  38),
+	MX31_PIN_LD15		= IOMUX_PIN(0xff,  39),
+	MX31_PIN_LD14		= IOMUX_PIN(0xff,  40),
+	MX31_PIN_LD13		= IOMUX_PIN(0xff,  41),
+	MX31_PIN_LD12		= IOMUX_PIN(0xff,  42),
+	MX31_PIN_LD11		= IOMUX_PIN(0xff,  43),
+	MX31_PIN_LD10		= IOMUX_PIN(0xff,  44),
+	MX31_PIN_LD9		= IOMUX_PIN(0xff,  45),
+	MX31_PIN_LD8		= IOMUX_PIN(0xff,  46),
+	MX31_PIN_LD7		= IOMUX_PIN(0xff,  47),
+	MX31_PIN_LD6		= IOMUX_PIN(0xff,  48),
+	MX31_PIN_LD5		= IOMUX_PIN(0xff,  49),
+	MX31_PIN_LD4		= IOMUX_PIN(0xff,  50),
+	MX31_PIN_LD3		= IOMUX_PIN(0xff,  51),
+	MX31_PIN_LD2		= IOMUX_PIN(0xff,  52),
+	MX31_PIN_LD1		= IOMUX_PIN(0xff,  53),
+	MX31_PIN_LD0		= IOMUX_PIN(0xff,  54),
+};
+
+struct chan_param_mem_planar {
+	/* Word 0 */
+	u32	xv:10;
+	u32	yv:10;
+	u32	xb:12;
+
+	u32	yb:12;
+	u32	res1:2;
+	u32	nsb:1;
+	u32	lnpb:6;
+	u32	ubo_l:11;
+
+	u32	ubo_h:15;
+	u32	vbo_l:17;
+
+	u32	vbo_h:9;
+	u32	res2:3;
+	u32	fw:12;
+	u32	fh_l:8;
+
+	u32	fh_h:4;
+	u32	res3:28;
+
+	/* Word 1 */
+	u32	eba0;
+
+	u32	eba1;
+
+	u32	bpp:3;
+	u32	sl:14;
+	u32	pfs:3;
+	u32	bam:3;
+	u32	res4:2;
+	u32	npb:6;
+	u32	res5:1;
+
+	u32	sat:2;
+	u32	res6:30;
+} __attribute__ ((packed));
+
+struct chan_param_mem_interleaved {
+	/* Word 0 */
+	u32	xv:10;
+	u32	yv:10;
+	u32	xb:12;
+
+	u32	yb:12;
+	u32	sce:1;
+	u32	res1:1;
+	u32	nsb:1;
+	u32	lnpb:6;
+	u32	sx:10;
+	u32	sy_l:1;
+
+	u32	sy_h:9;
+	u32	ns:10;
+	u32	sm:10;
+	u32	sdx_l:3;
+
+	u32	sdx_h:2;
+	u32	sdy:5;
+	u32	sdrx:1;
+	u32	sdry:1;
+	u32	sdr1:1;
+	u32	res2:2;
+	u32	fw:12;
+	u32	fh_l:8;
+
+	u32	fh_h:4;
+	u32	res3:28;
+
+	/* Word 1 */
+	u32	eba0;
+
+	u32	eba1;
+
+	u32	bpp:3;
+	u32	sl:14;
+	u32	pfs:3;
+	u32	bam:3;
+	u32	res4:2;
+	u32	npb:6;
+	u32	res5:1;
+
+	u32	sat:2;
+	u32	scc:1;
+	u32	ofs0:5;
+	u32	ofs1:5;
+	u32	ofs2:5;
+	u32	ofs3:5;
+	u32	wid0:3;
+	u32	wid1:3;
+	u32	wid2:3;
+
+	u32	wid3:3;
+	u32	dec_sel:1;
+	u32	res6:28;
+} __attribute__ ((packed));
+
+union chan_param_mem {
+	struct chan_param_mem_planar		pp;
+	struct chan_param_mem_interleaved	ip;
+};
+
+static inline u32 reg_read(unsigned long reg)
+{
+	return __REG(reg);
+}
+
+static inline void reg_write(u32 value, unsigned long reg)
+{
+	__REG(reg) = value;
+}
+
+/*
+ * sdc_init_panel() - initialize a synchronous LCD panel.
+ * @width:		width of panel in pixels.
+ * @height:		height of panel in pixels.
+ * @pixel_fmt:		pixel format of buffer as FOURCC ASCII code.
+ * @return:		0 on success or negative error code on failure.
+ */
+static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt)
+{
+	u32 reg;
+	uint32_t old_conf;
+
+	/* Init panel size and blanking periods */
+	reg = ((H_SYNC_WIDTH - 1) << 26) |
+		((u32)(width + H_START_WIDTH + H_END_WIDTH - 1) << 16);
+	reg_write(reg, SDC_HOR_CONF);
+
+	reg = ((V_SYNC_WIDTH - 1) << 26) | SDC_V_SYNC_WIDTH_L |
+		((u32)(height + V_START_WIDTH + V_END_WIDTH - 1) << 16);
+	reg_write(reg, SDC_VER_CONF);
+
+	switch (PANEL_TYPE) {
+	case IPU_PANEL_SHARP_TFT:
+		reg_write(0x00FD0102L, SDC_SHARP_CONF_1);
+		reg_write(0x00F500F4L, SDC_SHARP_CONF_2);
+		reg_write(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		break;
+	case IPU_PANEL_TFT:
+		reg_write(SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Init clocking */
+
+	/*
+	 * Calculate divider: fractional part is 4 bits so simply multiple by
+	 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
+	 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
+	 */
+
+	reg_write((((IF_CLK_DIV / 8) - 1) << 22) |
+			IF_CLK_DIV, DI_DISP3_TIME_CONF);
+
+	/* DI settings */
+	old_conf = reg_read(DI_DISP_IF_CONF) & 0x78FFFFFF;
+	reg_write(old_conf | IF_CONF, DI_DISP_IF_CONF);
+
+	old_conf = reg_read(DI_DISP_SIG_POL) & 0xE0FFFFFF;
+	reg_write(old_conf | SIG_POL, DI_DISP_SIG_POL);
+
+	reg_write(fmt_cfg[pixel_fmt].b0, DI_DISP3_B0_MAP);
+	reg_write(fmt_cfg[pixel_fmt].b1, DI_DISP3_B1_MAP);
+	reg_write(fmt_cfg[pixel_fmt].b2, DI_DISP3_B2_MAP);
+	reg_write(reg_read(DI_DISP_ACC_CC) |
+		  ((fmt_cfg[pixel_fmt].acc - 1) << 12), DI_DISP_ACC_CC);
+
+	return 0;
+}
+
+static void ipu_ch_param_set_size(union chan_param_mem *params,
+				  uint32_t pixel_fmt, uint16_t width,
+				  uint16_t height, uint16_t stride)
+{
+	params->pp.fw		= width - 1;
+	params->pp.fh_l		= height - 1;
+	params->pp.fh_h		= (height - 1) >> 8;
+	params->pp.sl		= stride - 1;
+
+	/* See above, for further formats see the Linux driver */
+	switch (pixel_fmt) {
+	case IPU_PIX_FMT_RGB565:
+		params->ip.bpp	= 2;
+		params->ip.pfs	= 4;
+		params->ip.npb	= 7;
+		params->ip.sat	= 2;		/* SAT = 32-bit access */
+		params->ip.ofs0	= 0;		/* Red bit offset */
+		params->ip.ofs1	= 5;		/* Green bit offset */
+		params->ip.ofs2	= 11;		/* Blue bit offset */
+		params->ip.ofs3	= 16;		/* Alpha bit offset */
+		params->ip.wid0	= 4;		/* Red bit width - 1 */
+		params->ip.wid1	= 5;		/* Green bit width - 1 */
+		params->ip.wid2	= 4;		/* Blue bit width - 1 */
+		break;
+	case IPU_PIX_FMT_RGB24:
+		params->ip.bpp	= 1;		/* 24 BPP & RGB PFS */
+		params->ip.pfs	= 4;
+		params->ip.npb	= 7;
+		params->ip.sat	= 2;		/* SAT = 32-bit access */
+		params->ip.ofs0	= 16;		/* Red bit offset */
+		params->ip.ofs1	= 8;		/* Green bit offset */
+		params->ip.ofs2	= 0;		/* Blue bit offset */
+		params->ip.ofs3	= 24;		/* Alpha bit offset */
+		params->ip.wid0	= 7;		/* Red bit width - 1 */
+		params->ip.wid1	= 7;		/* Green bit width - 1 */
+		params->ip.wid2	= 7;		/* Blue bit width - 1 */
+		break;
+	default:
+		break;
+	}
+
+	params->pp.nsb = 1;
+}
+
+static void ipu_ch_param_set_buffer(union chan_param_mem *params,
+				    void *buf0, void *buf1)
+{
+	params->pp.eba0 = (u32)buf0;
+	params->pp.eba1 = (u32)buf1;
+}
+
+static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
+				uint32_t num_words)
+{
+	for (; num_words > 0; num_words--) {
+		reg_write(addr, IPU_IMA_ADDR);
+		reg_write(*data++, IPU_IMA_DATA);
+		addr++;
+		if ((addr & 0x7) == 5) {
+			addr &= ~0x7;	/* set to word 0 */
+			addr += 8;	/* increment to next row */
+		}
+	}
+}
+
+static uint32_t bpp_to_pixfmt(int bpp)
+{
+	switch (bpp) {
+	case 16:
+		return IPU_PIX_FMT_RGB565;
+	default:
+		return 0;
+	}
+}
+
+static uint32_t dma_param_addr(enum ipu_channel channel)
+{
+	/* Channel Parameter Memory */
+	return 0x10000 | (channel << 4);
+}
+
+static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
+{
+	union chan_param_mem params = {};
+	uint32_t reg;
+	uint32_t stride_bytes;
+
+	stride_bytes = (XRES * ((BIT_PER_PIXEL + 7) / 8) + 3) & ~3;
+
+	/* Build parameter memory data for DMA channel */
+	ipu_ch_param_set_size(&params, bpp_to_pixfmt(BIT_PER_PIXEL),
+			      XRES, YRES, stride_bytes);
+	ipu_ch_param_set_buffer(&params, fbmem, NULL);
+	params.pp.bam = 0;
+	/* Some channels (rotation) have restriction on burst length */
+
+	switch (channel) {
+	case IDMAC_SDC_0:
+		/* In original code only IPU_PIX_FMT_RGB565 was setting burst */
+		params.pp.npb = 16 - 1;
+		break;
+	default:
+		break;
+	}
+
+	ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
+
+	/* Disable double-buffering */
+	reg = reg_read(IPU_CHA_DB_MODE_SEL);
+	reg &= ~(1UL << channel);
+	reg_write(reg, IPU_CHA_DB_MODE_SEL);
+}
+
+static void ipu_channel_set_priority(enum ipu_channel channel,
+				     int prio)
+{
+	u32 reg = reg_read(IDMAC_CHA_PRI);
+
+	if (prio)
+		reg |= 1UL << channel;
+	else
+		reg &= ~(1UL << channel);
+
+	reg_write(reg, IDMAC_CHA_PRI);
+}
+
+/*
+ * ipu_enable_channel() - enable an IPU channel.
+ * @channel:	channel ID.
+ * @return:	0 on success or negative error code on failure.
+ */
+static int ipu_enable_channel(enum ipu_channel channel)
+{
+	uint32_t reg;
+
+	/* Reset to buffer 0 */
+	reg_write(1UL << channel, IPU_CHA_CUR_BUF);
+
+	switch (channel) {
+	case IDMAC_SDC_0:
+		ipu_channel_set_priority(channel, 1);
+		break;
+	default:
+		break;
+	}
+
+	reg = reg_read(IDMAC_CHA_EN);
+	reg_write(reg | (1UL << channel), IDMAC_CHA_EN);
+
+	return 0;
+}
+
+static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
+{
+	uint32_t reg;
+
+	reg = reg_read(IPU_CHA_BUF0_RDY);
+	if (reg & (1UL << channel))
+		return -EACCES;
+
+	/* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
+	reg_write(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
+	reg_write((u32)buf, IPU_IMA_DATA);
+
+	return 0;
+}
+
+static int idmac_tx_submit(enum ipu_channel channel, void *buf)
+{
+	int ret;
+
+	ipu_init_channel_buffer(channel, buf);
+
+
+	/* ipu_idmac.c::ipu_submit_channel_buffers() */
+	ret = ipu_update_channel_buffer(channel, buf);
+	if (ret < 0)
+		return ret;
+
+	/* ipu_idmac.c::ipu_select_buffer() */
+	/* Mark buffer 0 as ready. */
+	reg_write(1UL << channel, IPU_CHA_BUF0_RDY);
+
+
+	ret = ipu_enable_channel(channel);
+	return ret;
+}
+
+static void sdc_enable_channel(void *fbmem)
+{
+	int ret;
+	u32 reg;
+
+	ret = idmac_tx_submit(IDMAC_SDC_0, fbmem);
+
+	/* mx3fb.c::sdc_fb_init() */
+	if (ret >= 0) {
+		reg = reg_read(SDC_COM_CONF);
+		reg_write(reg | SDC_COM_BG_EN, SDC_COM_CONF);
+	}
+
+	/*
+	 * Attention! Without this msleep the channel keeps generating
+	 * interrupts. Next sdc_set_brightness() is going to be called
+	 * from mx3fb_blank().
+	 */
+	msleep(2);
+}
+
+/*
+ * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
+ * @return:	0 on success or negative error code on failure.
+ */
+static int mx3fb_set_par(void)
+{
+	int ret;
+
+	ret = sdc_init_panel(XRES, YRES, PIXEL_FMT);
+	if (ret < 0)
+		return ret;
+
+	reg_write((H_START_WIDTH << 16) | V_START_WIDTH, SDC_BG_POS);
+
+	return 0;
+}
+
+/* References in this function refer to respective Linux kernel sources */
+void lcd_enable(void)
+{
+	u32 reg;
+
+	/* pcm037.c::mxc_board_init() */
+
+	/* Display Interface #3 */
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD0, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD1, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD2, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD4, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD5, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD6, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD7, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD8, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD9, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD10, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD11, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD12, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD13, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD14, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD15, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD16, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_LD17, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_VSYNC3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_HSYNC, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_FPSHIFT, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_DRDY0, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_REV, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_CONTRAST, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_SPL, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE_L(MX31_PIN_D3_CLS, MUX_CTL_FUNC));
+
+
+	/* ipu_idmac.c::ipu_probe() */
+
+	/* Start the clock */
+	__REG(CCM_CGR1) = __REG(CCM_CGR1) | (3 << 22);
+
+
+	/* ipu_idmac.c::ipu_idmac_init() */
+
+	/* Service request counter to maximum - shouldn't be needed */
+	reg_write(0x00000070, IDMAC_CONF);
+
+
+	/* ipu_idmac.c::ipu_init_channel() */
+
+	/* Enable IPU sub modules */
+	reg = reg_read(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
+	reg_write(reg, IPU_CONF);
+
+
+	/* mx3fb.c::init_fb_chan() */
+
+	/* set Display Interface clock period */
+	reg_write(0x00100010L, DI_HSP_CLK_PER);
+	/* Might need to trigger HSP clock change - see 44.3.3.8.5 */
+
+
+	/* mx3fb.c::sdc_set_brightness() */
+
+	/* This might be board-specific */
+	reg_write(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
+
+
+	/* mx3fb.c::sdc_set_global_alpha() */
+
+	/* Use global - not per-pixel - Alpha-blending */
+	reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL;
+	reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
+
+	reg = reg_read(SDC_COM_CONF);
+	reg_write(reg | SDC_COM_GLB_A, SDC_COM_CONF);
+
+
+	/* mx3fb.c::sdc_set_color_key() */
+
+	/* Disable colour-keying for background */
+	reg = reg_read(SDC_COM_CONF) &
+		~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
+	reg_write(reg, SDC_COM_CONF);
+
+
+	mx3fb_set_par();
+
+	sdc_enable_channel(lcd_base);
+
+	/*
+	 * Linux driver calls sdc_set_brightness() here again,
+	 * once is enough for us
+	 */
+}
+
+void lcd_ctrl_init(void *lcdbase)
+{
+	u32 mem_len = XRES * YRES * BIT_PER_PIXEL / 8;
+	/*
+	 * We rely on lcdbase being a physical address, i.e., either MMU off,
+	 * or 1-to-1 mapping. Might want to add some virt2phys here.
+	 */
+	if (!lcdbase)
+		return;
+
+	memset(lcdbase, 0, mem_len);
+}
+
+ulong calc_fbsize(void)
+{
+	return ((panel_info.vl_col * panel_info.vl_row *
+		NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
+}
+
+int overwrite_console(void)
+{
+	/* Keep stdout / stderr on serial, our LCD is for splashscreen only */
+	return 1;
+}
-- 
1.5.4

[U-Boot] [PATCH 9/9 v3] ARM: add an "eet" variant of the imx31_phycore board

[Guennadi Liakhovetski]

The "eet" variant of the imx31_phycore board has an OLED display, using a
s6e63d6 display controller on the first SPI interface, using GPIO57 as a
chip-select for it. With this configuration you can display 256 colour BMP
images in 16-bit RGB (RGB565) LCD mode.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---

Changes since v1: adjusted to reflect changes in earlier patches: add .id 
field initialisation, configuration parameter renamed to CONFIG_S6E63D6.
Changes since v2: fixed the left-over CONFIG_DISPLAY_S6E63D6 parameter.

 Makefile                              |    6 +++-
 board/imx31_phycore/imx31_phycore.c   |   52 +++++++++++++++++++++++++++++++++
 include/asm-arm/arch-mx31/mx31-regs.h |   16 ++++++++++
 include/configs/imx31_phycore.h       |   23 ++++++++++++++
 4 files changed, 96 insertions(+), 1 deletions(-)

diff --git a/Makefile b/Makefile
index 787c5f2..6151e2c 100644
--- a/Makefile
+++ b/Makefile
@@ -3025,8 +3025,12 @@ apollon_config		: unconfig
 imx31_litekit_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
 
+imx31_phycore_eet_config \
 imx31_phycore_config	: unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
+	@if [ -n "$(findstring imx31_phycore_eet_config,$@)" ]; then			\
+		echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h;	\
+	fi
+	@$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31
 
 mx31ads_config		: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
index 6b78194..9456468 100644
--- a/board/imx31_phycore/imx31_phycore.c
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -23,6 +23,7 @@
 
 
 #include <common.h>
+#include <s6e63d6.h>
 #include <asm/arch/mx31.h>
 #include <asm/arch/mx31-regs.h>
 
@@ -69,6 +70,57 @@ int board_init (void)
 	return 0;
 }
 
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_S6E63D6
+	struct s6e63d6 data = {
+		.cs = 2 | (57 << 8),
+		.bus = 0,
+		.id = 0,
+	};
+	int ret;
+
+	/* SPI1 */
+	mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
+	mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
+	mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
+	mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
+	mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
+	mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
+
+	/* start SPI1 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
+
+	/* GPIO 57 */
+	/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
+	mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
+
+	/* SPI1 CS2 is free */
+	ret = s6e63d6_init(&data);
+	if (ret)
+		return ret;
+
+	/*
+	 * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
+	 * OLED display connected to a S6E63D6 SPI display controller in the
+	 * 18 bit RGB mode
+	 */
+	s6e63d6_index(&data, 2);
+	s6e63d6_param(&data, 0x0182);
+	s6e63d6_index(&data, 3);
+	s6e63d6_param(&data, 0x8130);
+	s6e63d6_index(&data, 0x10);
+	s6e63d6_param(&data, 0x0000);
+	s6e63d6_index(&data, 5);
+	s6e63d6_param(&data, 0x0001);
+	s6e63d6_index(&data, 0x22);
+#endif
+	return 0;
+}
+#endif
+
 int checkboard (void)
 {
 	printf("Board: Phytec phyCore i.MX31\n");
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index e736052..dcc0805 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -124,7 +124,14 @@
 #define MUX_CTL_CSPI2_SS0	0x85
 #define MUX_CTL_CSPI2_SS1	0x86
 #define MUX_CTL_CSPI2_SS2	0x87
+#define MUX_CTL_CSPI1_SS2	0x88
+#define MUX_CTL_CSPI1_SCLK	0x89
+#define MUX_CTL_CSPI1_SPI_RDY	0x8a
 #define MUX_CTL_CSPI2_MOSI	0x8b
+#define MUX_CTL_CSPI1_MOSI	0x8c
+#define MUX_CTL_CSPI1_MISO	0x8d
+#define MUX_CTL_CSPI1_SS0	0x8e
+#define MUX_CTL_CSPI1_SS1	0x8f
 
 /*
  * Helper macros for the MUX_[contact name]__[pin function] macros
@@ -150,6 +157,15 @@
 	IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
 
+#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
+#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
+#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
+#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
+	IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
+#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
+
 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
 
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index f0d28ee..2dd9e92 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -178,4 +178,27 @@
 #undef CONFIG_JFFS2_CMDLINE
 #define CONFIG_JFFS2_DEV	"nor0"
 
+/* EET platform additions */
+#ifdef CONFIG_IMX31_PHYCORE_EET
+#define BOARD_LATE_INIT
+
+#define CONFIG_MX31_GPIO			1
+
+#define CONFIG_HARD_SPI				1
+#define CONFIG_MXC_SPI				1
+#define CONFIG_CMD_SPI
+
+#define CONFIG_S6E63D6				1
+
+#define CONFIG_LCD				1
+#define CONFIG_VIDEO_MX3			1
+#define CONFIG_SYS_WHITE_ON_BLACK		1
+#define LCD_BPP					LCD_COLOR8
+#define	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+
+#define	CONFIG_SPLASH_SCREEN			1
+#define CONFIG_CMD_BMP				1
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.5.4

[U-Boot] [PATCH 4/9 v3] A driver for the S6E63D6 SPI display controller from Samsung

[Anatolij Gustschin]

Guennadi Liakhovetski wrote:
> This is a driver for the S6E63D6 SPI OLED display controller from Samsung.
> It only provides access to controller's registers so the client can freely
> configure it.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
<snip>
>  drivers/video/Makefile  |    1 +
>  drivers/video/s6e63d6.c |   76 +++++++++++++++++++++++++++++++++++++++++++++++
>  include/s6e63d6.h       |   37 +++++++++++++++++++++++
>  3 files changed, 114 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/video/s6e63d6.c
>  create mode 100644 include/s6e63d6.h

Applied to u-boot-video/master.

Thanks,
Anatolij

[U-Boot] [PATCH 6/9 v3] Add 16bpp BMP support

[Anatolij Gustschin]

Guennadi Liakhovetski wrote:
> From: Mark Jackson <mpfj@mimc.co.uk>
> 
> This patch adds 16bpp BMP support to the common lcd code.
> 
> Use CONFIG_BMP_16BPP and set LCD_BPP to LCD_COLOR16 to enable the code.
> 
> At the moment it's only been tested on the MIMC200 AVR32 board, but extending
> this to other platforms should be a simple task !!
> 
> Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
> 
> Changes since v1: added this comment to explain, that this patch from Mark 
> Jackson is included in this patch series for completeness, because future 
> patches base on it, long lines split.
> Changes since v2: none.
> 
>  common/lcd.c |   51 +++++++++++++++++++++++++++++++++++++++++----------
>  1 files changed, 41 insertions(+), 10 deletions(-)

Applied to u-boot-video/master.

Thanks,
Anatolij

[U-Boot] [PATCH 7/9 v3] LCD: support 8bpp BMPs on 16bpp displays

[Anatolij Gustschin]

Guennadi Liakhovetski wrote:
> This patch also simplifies some ifdefs in lcd.c, introduces a generic
> vidinfo_t, which new drivers are encouraged to use and old drivers to switch
> over to.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
> 
> Changes since v1: no changes.
> 
>  common/lcd.c  |   56 ++++++++++++++++++++++++++++++++------------------------
>  include/lcd.h |   21 +++++++++++++--------
>  2 files changed, 45 insertions(+), 32 deletions(-)

Applied to u-boot-video/master.

Also fixed some style issues by additionally applying a trivial
patch below.

Note that I consider this horrible ifdef mess in common/lcd.c
as a bug (not your bug!) that should be fixed before 2009.03-rc1
or even earlier. pxa, mpc823 and atmel LCD drivers provide
lcd_setcolreg() for color map setting and it could be used in
lcd_display_bitmap() instead of duplicating the color map
setting code for platforms in question. Other LCD drivers
should provide own/controller-specific lcd_setcolreg().

I will try to help fixing these bugs, but I can not test the
code as I do not have the hardware.

Thanks,
Anatolij

diff --git a/common/lcd.c b/common/lcd.c
index e4ac6c2..6ce14d2 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -747,8 +747,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 
 		for (i = 0; i < height; ++i) {
 			WATCHDOG_RESET();
-			for (j = 0; j < width ; j++)
-				if (bpix!=16) {
+			for (j = 0; j < width; j++) {
+				if (bpix != 16) {
 #if defined(CONFIG_PXA250) || defined(CONFIG_ATMEL_LCD)
 					*(fb++) = *(bmap++);
 #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
@@ -758,6 +758,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 					*(uint16_t *)fb = cmap_base[*(bmap++)];
 					fb += sizeof(uint16_t) / sizeof(*fb);
 				}
+			}
 			bmap += (width - padded_line);
 			fb   -= (byte_width + lcd_line_length);
 		}

[U-Boot] [PATCH 8/9 v3] video: add an i.MX31 framebuffer driver

[Anatolij Gustschin]

Guennadi Liakhovetski wrote:
> Add a driver for the Synchronous Display Controller and the Display
> Interface on i.MX31, using IPU for DMA channel setup. So far only
> displaying of bitmaps is supported, no text output.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
<snip>
>  drivers/video/Makefile |    1 +
>  drivers/video/mx3fb.c  |  856 ++++++++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 857 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/video/mx3fb.c

Applied to u-boot-video/master.

Thanks,
Anatolij

[U-Boot] [PATCH 7/9 v3] LCD: support 8bpp BMPs on 16bpp displays

[Guennadi Liakhovetski]

On Fri, 6 Feb 2009, Anatolij Gustschin wrote:

> Guennadi Liakhovetski wrote:
> > This patch also simplifies some ifdefs in lcd.c, introduces a generic
> > vidinfo_t, which new drivers are encouraged to use and old drivers to switch
> > over to.
> > 
> > Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> > ---
> > 
> > Changes since v1: no changes.
> > 
> >  common/lcd.c  |   56 ++++++++++++++++++++++++++++++++------------------------
> >  include/lcd.h |   21 +++++++++++++--------
> >  2 files changed, 45 insertions(+), 32 deletions(-)
> 
> Applied to u-boot-video/master.
> 
> Also fixed some style issues by additionally applying a trivial
> patch below.
> 
> Note that I consider this horrible ifdef mess in common/lcd.c
> as a bug (not your bug!) that should be fixed before 2009.03-rc1
> or even earlier. pxa, mpc823 and atmel LCD drivers provide
> lcd_setcolreg() for color map setting and it could be used in
> lcd_display_bitmap() instead of duplicating the color map
> setting code for platforms in question. Other LCD drivers
> should provide own/controller-specific lcd_setcolreg().

That's why I introduced a generic vidinfo_t with only members in it, used 
by the generic code (lcd.c,...), a pointer to a colour map and a "void 
*priv" pointer for driver-specific data. It shouldn't be too difficult to 
migrate all in-tree users to this or a similar scheme. This alone would 
eliminate a few ifdefs, but maybe you have a better idea how to do this.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 0/9 v3] ARM: Support for splashimage om i.MX31-based phycore "eet" variant

[Anatolij Gustschin]

Hello all,

On Friday 06 February 2009 10:37:23 am Guennadi Liakhovetski wrote:
> Hi again,
>
> this is version 3 of the patch-series, that adds support for the graphics
> engine on i.MX31 SoC. Changes since v1 and v2 will be reflected in each
> single patch. As all correction requests have been addressed, I hope we
> can get it in on the last day of the merge window (today). Should any
> further problems surface, we can address them in incremental patches.

I applied following patches

[PATCH 4/9 v3] A driver for the S6E63D6 SPI display controller from Samsung
[PATCH 6/9 v3] Add 16bpp BMP support
[PATCH 7/9 v3] LCD: support 8bpp BMPs on 16bpp displays
[PATCH 8/9 v3] video: add an i.MX31 framebuffer driver

to the u-boot-video/master branch.

Jean-Christophe, do you prefer to push other patches from this
series (1/9, 2/9, 3/9, 5/9, 9/9) to the arm tree or should I push
them to the video tree? I need an ACK from you in the latter case.

Thanks,
Anatolij

[U-Boot] [PATCH 0/9 v3] ARM: Support for splashimage om i.MX31-based phycore "eet" variant

[Guennadi Liakhovetski]

On Fri, 6 Feb 2009, Anatolij Gustschin wrote:

> Hello all,
> 
> On Friday 06 February 2009 10:37:23 am Guennadi Liakhovetski wrote:
> > Hi again,
> >
> > this is version 3 of the patch-series, that adds support for the graphics
> > engine on i.MX31 SoC. Changes since v1 and v2 will be reflected in each
> > single patch. As all correction requests have been addressed, I hope we
> > can get it in on the last day of the merge window (today). Should any
> > further problems surface, we can address them in incremental patches.
> 
> I applied following patches
> 
> [PATCH 4/9 v3] A driver for the S6E63D6 SPI display controller from Samsung
> [PATCH 6/9 v3] Add 16bpp BMP support
> [PATCH 7/9 v3] LCD: support 8bpp BMPs on 16bpp displays
> [PATCH 8/9 v3] video: add an i.MX31 framebuffer driver
> 
> to the u-boot-video/master branch.
> 
> Jean-Christophe, do you prefer to push other patches from this
> series (1/9, 2/9, 3/9, 5/9, 9/9) to the arm tree or should I push
> them to the video tree? I need an ACK from you in the latter case.

As I said in one of the first versions of this series, it should better be 
pushed via one tree completely, because otherwise cross-dependencies will 
break things, or you'll have to imply a specific merge order, which isn't 
nice either.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 9/9 v3] ARM: add an "eet" variant of the imx31_phycore board

[Jean-Christophe PLAGNIOL-VILLARD]

On 10:38 Fri 06 Feb     , Guennadi Liakhovetski wrote:
> The "eet" variant of the imx31_phycore board has an OLED display, using a
> s6e63d6 display controller on the first SPI interface, using GPIO57 as a
> chip-select for it. With this configuration you can display 256 colour BMP
> images in 16-bit RGB (RGB565) LCD mode.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
> 
> Changes since v1: adjusted to reflect changes in earlier patches: add .id 
> field initialisation, configuration parameter renamed to CONFIG_S6E63D6.
> Changes since v2: fixed the left-over CONFIG_DISPLAY_S6E63D6 parameter.
> 
>  Makefile                              |    6 +++-
>  board/imx31_phycore/imx31_phycore.c   |   52 +++++++++++++++++++++++++++++++++
>  include/asm-arm/arch-mx31/mx31-regs.h |   16 ++++++++++
>  include/configs/imx31_phycore.h       |   23 ++++++++++++++
>  4 files changed, 96 insertions(+), 1 deletions(-)
> 
> diff --git a/Makefile b/Makefile
> index 787c5f2..6151e2c 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -3025,8 +3025,12 @@ apollon_config		: unconfig
>  imx31_litekit_config	: unconfig
>  	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
>  
> +imx31_phycore_eet_config \
>  imx31_phycore_config	: unconfig
> -	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
> +	@if [ -n "$(findstring imx31_phycore_eet_config,$@)" ]; then			\
> +		echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h;	\
> +	fi
One question I'll send within few minutes the dcc support for arm
if you wish to use it in eet

you may create a
imx31_phycore_eet_dcc_config
config will you create a new if [ -n "(findstring imx31_phycore_eet_dcc_config...
to handle and so duplicate code

or just do this
	@if [ -n "$(findstring _eet_,$@)" ]; then			\
		echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h;	\
	fi
	@if [ -n "$(findstring _dcc_,$@)" ]; then			\
		echo "#define CONFIG_DCC" >> $(obj)include/config.h;	\
	fi
??
I'll suggest to add a README file to describe the board and it's
specifications when it's possible maybe
> +	@$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31
>  
>  mx31ads_config		: unconfig
>  	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
> diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
> index 6b78194..9456468 100644
> --- a/board/imx31_phycore/imx31_phycore.c
> +++ b/board/imx31_phycore/imx31_phycore.c
> @@ -23,6 +23,7 @@
>  
>  
>  #include <common.h>
> +#include <s6e63d6.h>
>  #include <asm/arch/mx31.h>
>  #include <asm/arch/mx31-regs.h>
>  
> @@ -69,6 +70,57 @@ int board_init (void)
>  	return 0;
>  }
>  
> +#ifdef BOARD_LATE_INIT
> +int board_late_init(void)
> +{
> +#ifdef CONFIG_S6E63D6
> +	struct s6e63d6 data = {
> +		.cs = 2 | (57 << 8),
why??
> +		.bus = 0,
> +		.id = 0,
> +	};
> +	int ret;
> +
Best Regards,
J.

[U-Boot] [PATCH 5/9 v3] ARM: remove unused variable

[Jean-Christophe PLAGNIOL-VILLARD]

On 10:37 Fri 06 Feb     , Guennadi Liakhovetski wrote:
> The "size" variable in start_armboot() in lib_arm/board.c is only really 
> used in "#ifndef CONFIG_SYS_NO_FLASH" case, and even there it can be 
> eliminated (thanks to Jean-Christophe PLAGNIOL-VILLARD for a suggestion.)
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
Ack will be apply on arm soon

Best Regards,
J.

[U-Boot] [PATCH 3/9 v3] i.MX31: support GPIO as a chip-select in the mxc_spi driver

[Jean-Christophe PLAGNIOL-VILLARD]

On 10:37 Fri 06 Feb     , Guennadi Liakhovetski wrote:
> Some SPI devices have special requirements on chip-select handling.
> With this patch we can use a GPIO as a chip-select and strictly follow
> the SPI_XFER_BEGIN and SPI_XFER_END flags.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---

> 
> Changes since v1: long lines split, mx31_gpio_* calls now also defined if 
> CONFIG_MX31_GPIO is not defined (see patch 2/9), '!!' removed.
> Changes since v2: added braces in a multiline if, switched to 
> ARRAY_SIZE().
> 
> @@ -144,11 +156,35 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
>  {
Personnaly I tking we main need to replace the unsigned int cs by a callback
or add one to allow us to use other gpio or I2C extender with having to this
the spi driver

Best Regards,
J.

[U-Boot] [PATCH 2/9 v3] i.MX31: add a simple gpio driver

[Jean-Christophe PLAGNIOL-VILLARD]

On 10:37 Fri 06 Feb     , Guennadi Liakhovetski wrote:
> This is a minimal driver, so far only managing output. It will
> be used by the mxc_spi.c driver.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
> 
> Changes since v1: alphabetical order, typo in copyright fixed, use 
> ARRAY_SIZE.
> Changes since v2: fixed wrong indentation in int mx31_gpio_direction() 
> declaration.
> 
>  drivers/gpio/Makefile            |    3 +-
>  drivers/gpio/mx31_gpio.c         |   73 ++++++++++++++++++++++++++++++++++++++
>  include/asm-arm/arch-mx31/mx31.h |   20 ++++++++++
>  3 files changed, 95 insertions(+), 1 deletions(-)
>  create mode 100644 drivers/gpio/mx31_gpio.c
> 
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index dd618ed..f10144f 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk
>  
>  LIB 	:= $(obj)libgpio.a
>  
> -COBJS-$(CONFIG_PCA953X)	+= pca953x.o
> +COBJS-$(CONFIG_MX31_GPIO)	+= mx31_gpio.o
> +COBJS-$(CONFIG_PCA953X)		+= pca953x.o
>  
>  COBJS	:= $(COBJS-y)
>  SRCS 	:= $(COBJS:.o=.c)
> diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c
> new file mode 100644
> index 0000000..166deaf
> --- /dev/null
> +++ b/drivers/gpio/mx31_gpio.c
> @@ -0,0 +1,73 @@
> +/*
> + * Copyright (C) 2009
> + * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +#include <common.h>
> +#include <asm/arch/mx31.h>
> +#include <asm/arch/mx31-regs.h>
> +
> +/* GPIO port description */
> +static unsigned long gpio_ports[] = {
> +	[0] = 0x53fcc000,
> +	[1] = 0x53fd0000,
> +	[2] = 0x53fa4000,
> +};
I'll add qong patch before yours
please fix it

Best Regards,
J.

[U-Boot] [PATCH 1/9 v3] i.MX31: fix SPI driver for shorter than 32 bit transfers

[Jean-Christophe PLAGNIOL-VILLARD]

 +
> +		/* Check if we're only transfering 8 or 16 bits */
> +		if (!i) {
> +			if (bitlen < 9)
> +				*(u8 *)din = data;
> +			else if (bitlen < 17)
> +				*(u16 *)din = data;
> +		}
> +	}
>  
>  	return 0;
>  }
> @@ -169,7 +176,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
>  
>  void spi_free_slave(struct spi_slave *slave)
>  {
> -	free(slave);
> +	struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
> +	free(mxcs);
please add an empty line
>  }
Best Regards,
J.

[U-Boot] [PATCH 0/9 v3] ARM: Support for splashimage om i.MX31-based phycore "eet" variant

[Jean-Christophe PLAGNIOL-VILLARD]

On 18:25 Fri 06 Feb     , Anatolij Gustschin wrote:
> Hello all,
> 
> On Friday 06 February 2009 10:37:23 am Guennadi Liakhovetski wrote:
> > Hi again,
> >
> > this is version 3 of the patch-series, that adds support for the graphics
> > engine on i.MX31 SoC. Changes since v1 and v2 will be reflected in each
> > single patch. As all correction requests have been addressed, I hope we
> > can get it in on the last day of the merge window (today). Should any
> > further problems surface, we can address them in incremental patches.
> 
> I applied following patches
> 
> [PATCH 4/9 v3] A driver for the S6E63D6 SPI display controller from Samsung
> [PATCH 6/9 v3] Add 16bpp BMP support
> [PATCH 7/9 v3] LCD: support 8bpp BMPs on 16bpp displays
> [PATCH 8/9 v3] video: add an i.MX31 framebuffer driver
> 
> to the u-boot-video/master branch.
> 
> Jean-Christophe, do you prefer to push other patches from this
> series (1/9, 2/9, 3/9, 5/9, 9/9) to the arm tree or should I push
> them to the video tree? I need an ACK from you in the latter case.
I've no problem with it I'll add the on the patch and let you manage them

It's more a video patch series than a arm one

Best Regards,
J.

[U-Boot] [PATCH 4/9 v3] A driver for the S6E63D6 SPI display controller from Samsung

[Wolfgang Denk]

Dear Anatolij,

In message <498C596B.2030301@denx.de> you wrote:
> Guennadi Liakhovetski wrote:
> > This is a driver for the S6E63D6 SPI OLED display controller from Samsung.
> > It only provides access to controller's registers so the client can freely
> > configure it.
> > 
> > Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> > ---
> <snip>
> >  drivers/video/Makefile  |    1 +
> >  drivers/video/s6e63d6.c |   76 +++++++++++++++++++++++++++++++++++++++++++++++
> >  include/s6e63d6.h       |   37 +++++++++++++++++++++++
> >  3 files changed, 114 insertions(+), 0 deletions(-)
> >  create mode 100644 drivers/video/s6e63d6.c
> >  create mode 100644 include/s6e63d6.h
> 
> Applied to u-boot-video/master.


Do you plan to send a pull request soon?  Please do - I would like to
have a v2009.03-rc1 out soon.  Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
An armed society is a polite society.

[U-Boot] [PATCH 2/9 v3] i.MX31: add a simple gpio driver

[Anatolij Gustschin]

Jean-Christophe PLAGNIOL-VILLARD wrote:

> On 10:37 Fri 06 Feb     , Guennadi Liakhovetski wrote:
>> This is a minimal driver, so far only managing output. It will
>> be used by the mxc_spi.c driver.
>>
>> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
>> ---

>> diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c
>> new file mode 100644
>> index 0000000..166deaf
>> --- /dev/null
>> +++ b/drivers/gpio/mx31_gpio.c
>> @@ -0,0 +1,73 @@
>> +/*
>> + * Copyright (C) 2009
>> + * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>> + * MA 02111-1307 USA
>> + */
>> +#include <common.h>
>> +#include <asm/arch/mx31.h>
>> +#include <asm/arch/mx31-regs.h>
>> +
>> +/* GPIO port description */
>> +static unsigned long gpio_ports[] = {
>> +	[0] = 0x53fcc000,
>> +	[1] = 0x53fd0000,
>> +	[2] = 0x53fa4000,
>> +};
> I'll add qong patch before yours
> please fix it

there is v4 of this patch:

http://lists.denx.de/pipermail/u-boot/2009-February/047097.html

Jean-Christophe, do you ACK it now?

Best regards,
Anatolij

[U-Boot] [PATCH 9/9 v3] ARM: add an "eet" variant of the imx31_phycore board

[Anatolij Gustschin]

Hi Guennadi,

On Friday 06 February 2009 10:38:01 am Guennadi Liakhovetski wrote:
> The "eet" variant of the imx31_phycore board has an OLED display, using a
> s6e63d6 display controller on the first SPI interface, using GPIO57 as a
> chip-select for it. With this configuration you can display 256 colour BMP
> images in 16-bit RGB (RGB565) LCD mode.
>
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
>
> Changes since v1: adjusted to reflect changes in earlier patches: add .id
> field initialisation, configuration parameter renamed to CONFIG_S6E63D6.
> Changes since v2: fixed the left-over CONFIG_DISPLAY_S6E63D6 parameter.

can you please address comments from Jean-Christophe to this 9/9 v3 patch?
I'm steel waiting for ACK from Jean-Christophe for 1/9 v4,  2/9 v4 and 9/9 v3
patches from this series.

Best regards,
Anatolij

[U-Boot] [PATCH 9/9 v4] ARM: add an "eet" variant of the imx31_phycore board

[Guennadi Liakhovetski]

The "eet" variant of the imx31_phycore board has an OLED display, using a
s6e63d6 display controller on the first SPI interface, using GPIO57 as a
chip-select for it. With this configuration you can display 256 colour BMP
images in 16-bit RGB (RGB565) LCD mode.

Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
---
On Mon, 23 Feb 2009, Anatolij Gustschin wrote:

> can you please address comments from Jean-Christophe to this 9/9 v3 patch?
> I'm steel waiting for ACK from Jean-Christophe for 1/9 v4,  2/9 v4 and 9/9 v3
> patches from this series.

Oops, sorry, I was sure I had sent it already.

Changes since v1: adjusted to reflect changes in earlier patches: add .id 
field initialisation, configuration parameter renamed to CONFIG_S6E63D6.
Changes since v2: fixed the left-over CONFIG_DISPLAY_S6E63D6 parameter.
Changes since v3: added a comment to clarify the SPI chipselect value.

 Makefile                              |    6 +++-
 board/imx31_phycore/imx31_phycore.c   |   57 +++++++++++++++++++++++++++++++++
 include/asm-arm/arch-mx31/mx31-regs.h |   16 +++++++++
 include/configs/imx31_phycore.h       |   23 +++++++++++++
 4 files changed, 101 insertions(+), 1 deletions(-)

diff --git a/Makefile b/Makefile
index 787c5f2..6151e2c 100644
--- a/Makefile
+++ b/Makefile
@@ -3025,8 +3025,12 @@ apollon_config		: unconfig
 imx31_litekit_config	: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
 
+imx31_phycore_eet_config \
 imx31_phycore_config	: unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
+	@if [ -n "$(findstring imx31_phycore_eet_config,$@)" ]; then			\
+		echo "#define CONFIG_IMX31_PHYCORE_EET" >> $(obj)include/config.h;	\
+	fi
+	@$(MKCONFIG) -a imx31_phycore arm arm1136 imx31_phycore NULL mx31
 
 mx31ads_config		: unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31
diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c
index 4c64cb9..0cfa172 100644
--- a/board/imx31_phycore/imx31_phycore.c
+++ b/board/imx31_phycore/imx31_phycore.c
@@ -23,6 +23,7 @@
 
 
 #include <common.h>
+#include <s6e63d6.h>
 #include <asm/arch/mx31.h>
 #include <asm/arch/mx31-regs.h>
 
@@ -66,6 +67,62 @@ int board_init (void)
 	return 0;
 }
 
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+#ifdef CONFIG_S6E63D6
+	struct s6e63d6 data = {
+		/*
+		 * See comment in mxc_spi.c::decode_cs() for .cs field format.
+		 * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect
+		 * 2 of the SPI controller #1, since it is unused.
+		 */
+		.cs = 2 | (57 << 8),
+		.bus = 0,
+		.id = 0,
+	};
+	int ret;
+
+	/* SPI1 */
+	mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK);
+	mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B);
+	mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI);
+	mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO);
+	mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B);
+	mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B);
+	mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B);
+
+	/* start SPI1 clock */
+	__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2);
+
+	/* GPIO 57 */
+	/* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */
+	mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO));
+
+	/* SPI1 CS2 is free */
+	ret = s6e63d6_init(&data);
+	if (ret)
+		return ret;
+
+	/*
+	 * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC
+	 * OLED display connected to a S6E63D6 SPI display controller in the
+	 * 18 bit RGB mode
+	 */
+	s6e63d6_index(&data, 2);
+	s6e63d6_param(&data, 0x0182);
+	s6e63d6_index(&data, 3);
+	s6e63d6_param(&data, 0x8130);
+	s6e63d6_index(&data, 0x10);
+	s6e63d6_param(&data, 0x0000);
+	s6e63d6_index(&data, 5);
+	s6e63d6_param(&data, 0x0001);
+	s6e63d6_index(&data, 0x22);
+#endif
+	return 0;
+}
+#endif
+
 int checkboard (void)
 {
 	printf("Board: Phytec phyCore i.MX31\n");
diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h
index e736052..dcc0805 100644
--- a/include/asm-arm/arch-mx31/mx31-regs.h
+++ b/include/asm-arm/arch-mx31/mx31-regs.h
@@ -124,7 +124,14 @@
 #define MUX_CTL_CSPI2_SS0	0x85
 #define MUX_CTL_CSPI2_SS1	0x86
 #define MUX_CTL_CSPI2_SS2	0x87
+#define MUX_CTL_CSPI1_SS2	0x88
+#define MUX_CTL_CSPI1_SCLK	0x89
+#define MUX_CTL_CSPI1_SPI_RDY	0x8a
 #define MUX_CTL_CSPI2_MOSI	0x8b
+#define MUX_CTL_CSPI1_MOSI	0x8c
+#define MUX_CTL_CSPI1_MISO	0x8d
+#define MUX_CTL_CSPI1_SS0	0x8e
+#define MUX_CTL_CSPI1_SS1	0x8f
 
 /*
  * Helper macros for the MUX_[contact name]__[pin function] macros
@@ -150,6 +157,15 @@
 	IOMUX_MODE(MUX_CTL_CSPI2_SPI_RDY, MUX_CTL_FUNC)
 #define MUX_CSPI2_SCLK__CSPI2_CLK IOMUX_MODE(MUX_CTL_CSPI2_SCLK, MUX_CTL_FUNC)
 
+#define MUX_CSPI1_SS0__CSPI1_SS0_B IOMUX_MODE(MUX_CTL_CSPI1_SS0, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS1__CSPI1_SS1_B IOMUX_MODE(MUX_CTL_CSPI1_SS1, MUX_CTL_FUNC)
+#define MUX_CSPI1_SS2__CSPI1_SS2_B IOMUX_MODE(MUX_CTL_CSPI1_SS2, MUX_CTL_FUNC)
+#define MUX_CSPI1_MOSI__CSPI1_MOSI IOMUX_MODE(MUX_CTL_CSPI1_MOSI, MUX_CTL_FUNC)
+#define MUX_CSPI1_MISO__CSPI1_MISO IOMUX_MODE(MUX_CTL_CSPI1_MISO, MUX_CTL_FUNC)
+#define MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B \
+	IOMUX_MODE(MUX_CTL_CSPI1_SPI_RDY, MUX_CTL_FUNC)
+#define MUX_CSPI1_SCLK__CSPI1_CLK IOMUX_MODE(MUX_CTL_CSPI1_SCLK, MUX_CTL_FUNC)
+
 #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1)
 #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1)
 
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index f0d28ee..2dd9e92 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -178,4 +178,27 @@
 #undef CONFIG_JFFS2_CMDLINE
 #define CONFIG_JFFS2_DEV	"nor0"
 
+/* EET platform additions */
+#ifdef CONFIG_IMX31_PHYCORE_EET
+#define BOARD_LATE_INIT
+
+#define CONFIG_MX31_GPIO			1
+
+#define CONFIG_HARD_SPI				1
+#define CONFIG_MXC_SPI				1
+#define CONFIG_CMD_SPI
+
+#define CONFIG_S6E63D6				1
+
+#define CONFIG_LCD				1
+#define CONFIG_VIDEO_MX3			1
+#define CONFIG_SYS_WHITE_ON_BLACK		1
+#define LCD_BPP					LCD_COLOR8
+#define	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+
+#define	CONFIG_SPLASH_SCREEN			1
+#define CONFIG_CMD_BMP				1
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.5.4

[U-Boot] [PATCH 4/9 v3] A driver for the S6E63D6 SPI display controller from Samsung

[Anatolij Gustschin]

Dear Wolfgang,

Wolfgang Denk wrote:
> Dear Anatolij,
> 
> In message <498C596B.2030301@denx.de> you wrote:
>> Guennadi Liakhovetski wrote:
>>> This is a driver for the S6E63D6 SPI OLED display controller from Samsung.
>>> It only provides access to controller's registers so the client can freely
>>> configure it.
>>>
>>> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
>>> ---
>> <snip>
>>>  drivers/video/Makefile  |    1 +
>>>  drivers/video/s6e63d6.c |   76 +++++++++++++++++++++++++++++++++++++++++++++++
>>>  include/s6e63d6.h       |   37 +++++++++++++++++++++++
>>>  3 files changed, 114 insertions(+), 0 deletions(-)
>>>  create mode 100644 drivers/video/s6e63d6.c
>>>  create mode 100644 include/s6e63d6.h
>> Applied to u-boot-video/master.
> 
> 
> Do you plan to send a pull request soon?  Please do - I would like to
> have a v2009.03-rc1 out soon.  Thanks.

I'm still waiting for ACK for patches 1/9 v4, 2/9 v4, 9/9 v4 from this
series. I'm going to send a pull request after Jean-Christophe ACK them.
Patch 3/9 v4 was already ACKed, but I cannot apply it as it applies on
top of 1/9 v4.

Best regards,
Anatolij

[U-Boot] [PATCH 4/9 v3] A driver for the S6E63D6 SPI display controller from Samsung

[Wolfgang Denk]

Dear Jean-Christophe,

In message <49A2A105.6070709@denx.de> Anatolij Gustschin wrote:
> 
> > Do you plan to send a pull request soon?  Please do - I would like to
> > have a v2009.03-rc1 out soon.  Thanks.
> 
> I'm still waiting for ACK for patches 1/9 v4, 2/9 v4, 9/9 v4 from this
> series. I'm going to send a pull request after Jean-Christophe ACK them.
> Patch 3/9 v4 was already ACKed, but I cannot apply it as it applies on
> top of 1/9 v4.

Could you please handle these patches ASAP?

I would like to see some progress here, but we're blocked waiting for
your ACKs (or NAKs).

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"It's when they say 2 + 2 = 5 that I begin to argue."    - Eric Pepke

[U-Boot] [PATCH 2/9 v3] i.MX31: add a simple gpio driver

[Jean-Christophe PLAGNIOL-VILLARD]

On 11:58 Mon 23 Feb     , Anatolij Gustschin wrote:
> Jean-Christophe PLAGNIOL-VILLARD wrote:
> 
> > On 10:37 Fri 06 Feb     , Guennadi Liakhovetski wrote:
> >> This is a minimal driver, so far only managing output. It will
> >> be used by the mxc_spi.c driver.
> >>
> >> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> >> ---
> 
> >> diff --git a/drivers/gpio/mx31_gpio.c b/drivers/gpio/mx31_gpio.c
> >> new file mode 100644
> >> index 0000000..166deaf
> >> --- /dev/null
> >> +++ b/drivers/gpio/mx31_gpio.c
> >> @@ -0,0 +1,73 @@
> >> +/*
> >> + * Copyright (C) 2009
> >> + * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
> >> + *
> >> + * See file CREDITS for list of people who contributed to this
> >> + * project.
> >> + *
> >> + * This program is free software; you can redistribute it and/or
> >> + * modify it under the terms of the GNU General Public License as
> >> + * published by the Free Software Foundation; either version 2 of
> >> + * the License, or (at your option) any later version.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >> + * GNU General Public License for more details.
> >> + *
> >> + * You should have received a copy of the GNU General Public License
> >> + * along with this program; if not, write to the Free Software
> >> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> >> + * MA 02111-1307 USA
> >> + */
> >> +#include <common.h>
> >> +#include <asm/arch/mx31.h>
> >> +#include <asm/arch/mx31-regs.h>
> >> +
> >> +/* GPIO port description */
> >> +static unsigned long gpio_ports[] = {
> >> +	[0] = 0x53fcc000,
> >> +	[1] = 0x53fd0000,
> >> +	[2] = 0x53fa4000,
> >> +};
> > I'll add qong patch before yours
> > please fix it
> 
> there is v4 of this patch:
> 
> http://lists.denx.de/pipermail/u-boot/2009-February/047097.html
> 
> Jean-Christophe, do you ACK it now?
you ahte it this V4

Best Regards,
J.

[U-Boot] [PATCH 2/9 v3] i.MX31: add a simple gpio driver

[Jean-Christophe PLAGNIOL-VILLARD]

> >> +static unsigned long gpio_ports[] = {
> >> +	[0] = 0x53fcc000,
> >> +	[1] = 0x53fd0000,
> >> +	[2] = 0x53fa4000,
> >> +};
> > I'll add qong patch before yours
> > please fix it
> 
> there is v4 of this patch:
> 
> http://lists.denx.de/pipermail/u-boot/2009-February/047097.html
> 
> Jean-Christophe, do you ACK it now?
ok Ack for the V4

Best Regards,
J.

[U-Boot] [PATCH 9/9 v4] ARM: add an "eet" variant of the imx31_phycore board

[Jean-Christophe PLAGNIOL-VILLARD]

On 13:34 Mon 23 Feb     , Guennadi Liakhovetski wrote:
> The "eet" variant of the imx31_phycore board has an OLED display, using a
> s6e63d6 display controller on the first SPI interface, using GPIO57 as a
> chip-select for it. With this configuration you can display 256 colour BMP
> images in 16-bit RGB (RGB565) LCD mode.
> 
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
> On Mon, 23 Feb 2009, Anatolij Gustschin wrote:
> 
> > can you please address comments from Jean-Christophe to this 9/9 v3 patch?
> > I'm steel waiting for ACK from Jean-Christophe for 1/9 v4,  2/9 v4 and 9/9 v3
> > patches from this series.
> 
> Oops, sorry, I was sure I had sent it already.
> 
> Changes since v1: adjusted to reflect changes in earlier patches: add .id 
> field initialisation, configuration parameter renamed to CONFIG_S6E63D6.
> Changes since v2: fixed the left-over CONFIG_DISPLAY_S6E63D6 parameter.
> Changes since v3: added a comment to clarify the SPI chipselect value.
> 
>  Makefile                              |    6 +++-
>  board/imx31_phycore/imx31_phycore.c   |   57 +++++++++++++++++++++++++++++++++
>  include/asm-arm/arch-mx31/mx31-regs.h |   16 +++++++++
>  include/configs/imx31_phycore.h       |   23 +++++++++++++
>  4 files changed, 101 insertions(+), 1 deletions(-)
> 
> diff --git a/Makefile b/Makefile
> index 787c5f2..6151e2c 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -3025,8 +3025,12 @@ apollon_config		: unconfig
>  imx31_litekit_config	: unconfig
>  	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_litekit NULL mx31
>  
> +imx31_phycore_eet_config \
>  imx31_phycore_config	: unconfig
> -	@$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31
> +	@if [ -n "$(findstring imx31_phycore_eet_config,$@)" ]; then			\
please do replace with
	@if [ -n "$(findstring _eet_,$@)" ]; then			\

And Ack

Best Regards,
J.

[U-Boot] [PATCH 9/9 v4] ARM: add an "eet" variant of the imx31_phycore board

[Anatolij Gustschin]

On Monday 23 February 2009 01:34:32 pm Guennadi Liakhovetski wrote:
> The "eet" variant of the imx31_phycore board has an OLED display, using a
> s6e63d6 display controller on the first SPI interface, using GPIO57 as a
> chip-select for it. With this configuration you can display 256 colour BMP
> images in 16-bit RGB (RGB565) LCD mode.
>
> Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
> ---
>
> On Mon, 23 Feb 2009, Anatolij Gustschin wrote:
> > can you please address comments from Jean-Christophe to this 9/9 v3
> > patch? I'm steel waiting for ACK from Jean-Christophe for 1/9 v4,  2/9 v4
> > and 9/9 v3 patches from this series.
>
> Oops, sorry, I was sure I had sent it already.
>
> Changes since v1: adjusted to reflect changes in earlier patches: add .id
> field initialisation, configuration parameter renamed to CONFIG_S6E63D6.
> Changes since v2: fixed the left-over CONFIG_DISPLAY_S6E63D6 parameter.
> Changes since v3: added a comment to clarify the SPI chipselect value.
>
>  Makefile                              |    6 +++-
>  board/imx31_phycore/imx31_phycore.c   |   57
> +++++++++++++++++++++++++++++++++ include/asm-arm/arch-mx31/mx31-regs.h |  
> 16 +++++++++
>  include/configs/imx31_phycore.h       |   23 +++++++++++++
>  4 files changed, 101 insertions(+), 1 deletions(-)

Applied to u-boot-video/master,
also fixed by s/imx31_phycore_eet_config,/_eet_,/

Thanks,
Anatolij