From: Pieter <phenning@vastech.co.za>
To: u-boot@lists.denx.de
Subject: [U-Boot] Vitesse Phy not recognized VSC8211
Date: Tue, 17 Feb 2009 11:27:58 +0200 [thread overview]
Message-ID: <499A831E.3020307@vastech.co.za> (raw)
In-Reply-To: <49990551.3090503@gmail.com>
hendrik wrote:
> Andy Fleming wrote:
>
>> On Fri, Feb 13, 2009 at 6:36 AM, hendrik <hendrik.vastech@gmail.com> wrote:
>>
>>
>>> Hi all
>>>
>>> When i included the struct as is the my board with the MPC8548 ver1 cpu
>>> worked correctly but the board with ver2 CPU does not work.
>>> A would appeciate any help
>>>
>>>
>> In what way does it "not work"? the cpu version shouldn't affect PHY
>> recognition. Is the board different? Does it have different PHYs?
>>
>>
>
> On both boards (CPU v1 and CPU v2 ) the phys are detected as the Vitesse
> VSC821, but someware in the the "miiphy_register" function in
> miiphyutil.c thinkgs go wrong on the board with the v2 CPU. The first
> symptom was the mesage:
>
> miiphy_register: non unique device name ""
>
> on deeper investigation i found that the phy names were jumbled garbage,
> as the lines below show: the NET name should reed Tsec0.
>
> PHY is Vitesse VSC8211 (fc4b1)
> miiphy_register: added '??m@??v|??\x06
??n', read=0x1ffb2e7c,
> write=0x1ffb2e14
>
> after a bit more digging I now thing the problem is in the Memory
> manager of the CPU but i do not know how to go about finding the
> problem. My first step is to look at the DDR setup then try to
> understand the differences between the v1 and v2 CPUs
>
> If you have any links or help i would greatly appreciate it.
>
>
> thanks hedrik
>
The jumbled contents found when looking for the phy name does not have
anything to do with the phy code, it does however relate to differences
between CPU rev1 and rev2 behaviour when using the BDI debugger.
U-boot 2009 checks to see if the L2 cache is enabled ( not caring if it
is configured as SRAM or cache) and then moves the L2 base address
register if CONFIG_SYS_INIT_L2_ADDR is defined and
if (l2cache->l2ctl & 0x00010000 && l2srbar >= CONFIG_SYS_FLASH_BASE)
which is probably true when booting CPU rev using a BDI.
undefine CONFIG_SYS_INIT_L2_ADDR and your problem should disappear
pieter
-------------- next part --------------
A non-text attachment was scrubbed...
Name: smime.p7s
Type: application/x-pkcs7-signature
Size: 2722 bytes
Desc: S/MIME Cryptographic Signature
Url : http://lists.denx.de/pipermail/u-boot/attachments/20090217/648c2232/attachment.bin
prev parent reply other threads:[~2009-02-17 9:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-02-13 12:36 [U-Boot] Vitesse Phy not recognized VSC8211 hendrik
2009-02-13 17:50 ` Andy Fleming
2009-02-16 6:18 ` hendrik
2009-02-17 9:27 ` Pieter [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=499A831E.3020307@vastech.co.za \
--to=phenning@vastech.co.za \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox