[U-Boot] [PATCH 2/2] LPC2468 example board

Remco Poelstra
2009-04-28T13:54:37Z

Added example board for LPC2468 processor

Signed-off-by: Remco Poelstra <remco.poelstra+u-boot at duran-audio.com
---
From ab9ef1e9c2bd8f04612429461baa5c24dbc52266 Mon Sep 17 00:00:00 2001
From: Remco Poelstra <remco.poelstra@duran-audio.com>
Date: Tue, 28 Apr 2009 15:04:33 +0200
Subject: [PATCH] Added example board for LPC2468 processor

---
board/LPC2468/LPC2468.c | 65 +++++
board/LPC2468/Makefile | 55 +++++
board/LPC2468/config.mk | 29 +++
board/LPC2468/flash.c | 255 +++++++++++++++++++
board/LPC2468/lowlevel_init.c | 445 ++++++++++++++++++++++++++++++++++
board/LPC2468/nand.c | 63 +++++
board/LPC2468/u-boot.lds | 55 +++++
include/asm-arm/arch-lpc24xx/immap.h | 142 ++++++++++-
include/configs/LPC2468.h | 220 +++++++++++++++++
9 files changed, 1319 insertions(+), 10 deletions(-)
create mode 100644 board/LPC2468/LPC2468.c
create mode 100755 board/LPC2468/Makefile
create mode 100755 board/LPC2468/config.mk
create mode 100644 board/LPC2468/flash.c
create mode 100644 board/LPC2468/lowlevel_init.c
create mode 100755 board/LPC2468/nand.c
create mode 100755 board/LPC2468/u-boot.lds
create mode 100644 include/configs/LPC2468.h

diff --git a/board/LPC2468/LPC2468.c b/board/LPC2468/LPC2468.c
new file mode 100644
index 0000000..498885f
--- /dev/null
+++ b/board/LPC2468/LPC2468.c
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
+ * Armadillo board HT1070
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <clps7111.h>
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ /* arch number MACH_TYPE_ARMADILLO - not official */
+ gd->bd->bi_arch_number = 1339;
+
+ /* location of boot parameters */
+ gd->bd->bi_boot_params = 0xA0000100;
+
+ return 0;
+}
+
+int print_cpuinfo (void)
+{
+ printf ("CPU: LPC2468 (ARM7tdmi-s from NXP)\n"
+ " running at 57.6 MHz (12 MHz crystal)\n");
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return (0);
+}
diff --git a/board/LPC2468/Makefile b/board/LPC2468/Makefile
new file mode 100755
index 0000000..19a2cd7
--- /dev/null
+++ b/board/LPC2468/Makefile
@@ -0,0 +1,55 @@
+
+#######################################################################
+#
+# Copyright (C) 2000, 2001, 2002, 2003
+# The LEOX team <team@leox.org>, http://www.leox.org
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# LEOX.org is about the development of free hardware and software resources
+# for system on chip.
+#
+# Description: U-Boot port on the LEOX's ELPT860 CPU board
+# ~~~~~~~~~~~
+#
+#######################################################################
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+#######################################################################
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o nand.o flash.o lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/LPC2468/config.mk b/board/LPC2468/config.mk
new file mode 100755
index 0000000..6dc9e0b
--- /dev/null
+++ b/board/LPC2468/config.mk
@@ -0,0 +1,29 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#address where u-boot will be relocated
+TEXT_BASE = 0xA1f80000
diff --git a/board/LPC2468/flash.c b/board/LPC2468/flash.c
new file mode 100644
index 0000000..9d61b43
--- /dev/null
+++ b/board/LPC2468/flash.c
@@ -0,0 +1,255 @@
+/*
+ * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
+ *
+ * (C) Copyright 2009 Duran Audio B.V. <www.duran-audio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * 18-03-2009 Updated for U-boot 2009.3
+ * by Remco Poelstra <remco.poelstra+u-boot@duran-audio.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define SST_BASEADDR 0x80000000
+#define SST_ADDR1 SST_BASEADDR + (0x5555<<1)
+#define SST_ADDR2 SST_BASEADDR + (0x2AAA<<1)
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+extern void iap_entry (unsigned long *command, unsigned long *result);
+
+extern int lpc24xx_copy_buffer_to_flash (flash_info_t *, ulong);
+extern int lpc24xx_flash_erase (flash_info_t *, int, int);
+extern int lpc24xx_write_buff (flash_info_t *, uchar *, ulong, ulong);
+
+/*-----------------------------------------------------------------------
+ *
+ */
+
+void write_word_sst (ulong addr, ushort data)
+{
+ ushort tmp;
+
+ writew (0x00AA, SST_ADDR1);
+ writew (0x0055, SST_ADDR2);
+ writew (0x00A0, SST_ADDR1);
+ writew (data, addr);
+ /* do data polling */
+ do {
+ tmp = readw (addr);
+ } while (tmp != data);
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+ulong flash_init (void)
+{
+ int j, k;
+ ulong size = 0;
+ ulong flashbase = 0;
+
+ flash_info[0].flash_id = (PHILIPS_LPC2468 & FLASH_VENDMASK);
+ flash_info[0].size = 0x007D000; /* 512 - 12 KB */
+ flash_info[0].sector_count = 27;
+ memset (flash_info[0].protect, 0, 27);
+ flashbase = 0x00000000;
+ for (j = 0, k = 0; j < 8; j++, k++) {
+ flash_info[0].start[k] = flashbase;
+ flashbase += 0x00001000;
+ }
+ for (j = 0; j < 14; j++, k++) {
+ flash_info[0].start[k] = flashbase;
+ flashbase += 0x00008000;
+ }
+ for (j = 0; j < 5; j++, k++) {
+ flash_info[0].start[k] = flashbase;
+ flashbase += 0x00001000;
+ }
+ size += flash_info[0].size;
+
+ flash_info[1].flash_id = (SST_MANUFACT & FLASH_VENDMASK);
+ flash_info[1].size = 0x00400000; /* 4 MB */
+ flash_info[1].sector_count = 1024;
+ memset (flash_info[1].protect, 0, 1024);
+ flashbase = SST_BASEADDR;
+ for (j = 0; j < 1024; j++) {
+ flash_info[1].start[j] = flashbase;
+ flashbase += 0x1000; /* 4 KB sectors */
+ }
+ size += flash_info[1].size;
+
+ /* Protect monitor and environment sectors */
+ flash_protect (FLAG_PROTECT_SET,
+ 0x0, 0x0 + monitor_flash_len - 1, &flash_info[0]);
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ flash_protect (FLAG_PROTECT_SET,
+ CONFIG_ENV_ADDR,
+ CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
+#endif
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+ int erased = 0;
+ unsigned long j;
+ unsigned long count;
+ unsigned char *p;
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case (SST_MANUFACT & FLASH_VENDMASK):
+ printf ("SST: ");
+ break;
+ case (PHILIPS_LPC2468 & FLASH_VENDMASK):
+ printf ("Philips: ");
+ break;
+ default:
+ printf ("Unknown Vendor ");
+ break;
+ }
+
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+ if ((i % 5) == 0) {
+ printf ("\n ");
+ }
+ if (i < (info->sector_count - 1)) {
+ count = info->start[i + 1] - info->start[i];
+ } else {
+ count = info->start[0] + info->size - info->start[i];
+ }
+ p = (unsigned char *)(info->start[i]);
+ erased = 1;
+ for (j = 0; j < count; j++) {
+ if (*p != 0xFF) {
+ erased = 0;
+ break;
+ }
+ p++;
+ }
+ printf (" %08lX%s%s", info->start[i],
+ info->protect[i] ? " RO" : " ",
+ erased ? " E" : " ");
+ }
+ printf ("\n");
+}
+
+int flash_erase_sst (flash_info_t * info, int s_first, int s_last)
+{
+ int i;
+
+ for (i = s_first; i <= s_last; i++) {
+ writel (0x00AA, SST_ADDR1);
+ writel (0x0055, SST_ADDR2);
+ writel (0x0080, SST_ADDR1);
+ writel (0x00AA, SST_ADDR1);
+ writel (0x0055, SST_ADDR2);
+ writel (0x0030, info->start[i]);
+ /* wait for erase to finish */
+ udelay (25000);
+ }
+
+ return ERR_OK;
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case (SST_MANUFACT & FLASH_VENDMASK):
+ return flash_erase_sst (info, s_first, s_last);
+ case (PHILIPS_LPC2468 & FLASH_VENDMASK):
+ return lpc24xx_flash_erase (info, s_first, s_last);
+ default:
+ return ERR_PROTECTED;
+ }
+ return ERR_PROTECTED;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ *
+ * cnt is in bytes
+ */
+
+int write_buff_sst (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ushort tmp;
+ ulong i;
+ uchar *src_org;
+ uchar *dst_org;
+ ulong cnt_org = cnt;
+ int ret = ERR_OK;
+
+ src_org = src;
+ dst_org = (uchar *) addr;
+
+ if (addr & 1) { /* if odd address */
+ tmp = *((uchar *) (addr - 1)); /* little endian */
+ tmp |= (*src << 8);
+ write_word_sst (addr - 1, tmp);
+ addr += 1;
+ cnt -= 1;
+ src++;
+ }
+ while (cnt > 1) {
+ tmp = ((*(src + 1)) << 8) + (*src); /* little endian */
+ write_word_sst (addr, tmp);
+ addr += 2;
+ src += 2;
+ cnt -= 2;
+ }
+ if (cnt > 0) {
+ tmp = (*((uchar *) (addr + 1))) << 8;
+ tmp |= *src;
+ write_word_sst (addr, tmp);
+ }
+
+ for (i = 0; i < cnt_org; i++) {
+ if (*dst_org != *src_org) {
+ printf ("Write failed. Byte %lX differs\n", i);
+ ret = ERR_PROG_ERROR;
+ break;
+ }
+ dst_org++;
+ src_org++;
+ }
+
+ return ret;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case (SST_MANUFACT & FLASH_VENDMASK):
+ return write_buff_sst (info, src, addr, cnt);
+ case (PHILIPS_LPC2468 & FLASH_VENDMASK):
+ return lpc24xx_write_buff (info, src, addr, cnt);
+ default:
+ return ERR_PROG_ERROR;
+ }
+ return ERR_PROG_ERROR;
+}
diff --git a/board/LPC2468/lowlevel_init.c b/board/LPC2468/lowlevel_init.c
new file mode 100644
index 0000000..f7d7698
--- /dev/null
+++ b/board/LPC2468/lowlevel_init.c
@@ -0,0 +1,445 @@
+/*
+ * (C) Copyright 2006-2007 Embedded Artists AB <www.embeddedartists.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <exports.h>
+#include <asm/arch/immap.h>
+#include <asm/io.h>
+
+/******************************************************************************
+ * Defines, macros, and typedefs
+ *****************************************************************************/
+
+#define USE_USB 1
+
+#define PLL_MValue (CONFIG_PLL_MVALUE-1)
+#define PLL_NValue (CONFIG_PLL_NVALUE-1)
+#define CCLKDivValue (CONFIG_PLL_CLKDIV-1)
+#define USBCLKDivValue (CONFIG_PLL_USBCLKDIV-1)
+
+#define Fcco ((2*CONFIG_PLL_MVALUE*CONFIG_FOSC) / CONFIG_PLL_NVALUE)
+#define Fcclk (Fcco / CONFIG_PLL_CLKDIV)
+#define Fpclk (Fcclk / CONFIG_FPCLK_DIV)
+#define MAM_SETTING 1 /* 0=disabled,
+ 1=partly enabled (enabled for code prefetch,
+ but not for data),
+ 2=fully enabled */
+#define MEM_MAP 2 /*When executing from RAM, MAM_MAP should always be 2*/
+#define SDRAM_BASE_ADDR 0xA0000000
+#define FASTIO_BASE_ADDR 0x3FFF8000
+
+/* Helper macros */
+#define BFS32(reg,value) writel( (readl(reg)|=(value)) ,reg)
+#define BFC32(reg,value) writel( (readl(reg)&=(~value)) ,reg)
+
+/*****************************************************************************
+ *
+ * Description:
+ * Delay execution by a specified number of milliseconds by using
+ * timer #1. A polled implementation.
+ *
+ * Params:
+ * [in] delayInMs - the number of milliseconds to delay.
+ *
+ ****************************************************************************/
+void delayMs (unsigned short delayInMs)
+{
+ timer_2468_t *timer=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.timer1);
+ /*
+ * setup timer #1 for delay
+ */
+ writel (0x02, &(timer->tcr)); /*stop and reset timer */
+ writel (0x00, &(timer->pr)); /*set prescaler to zero */
+ writel (delayInMs * (Fpclk / 1000), &(timer->mr0));
+
+ writel (0xff, &(timer->ir)); /*reset all interrrupt flags */
+ writel (0x04, &(timer->mcr)); /*stop timer on match */
+ writel (0x01, &(timer->tcr)); /*start timer */
+
+ /*wait until delay time has elapsed */
+ while (readl (&(timer->tcr)) & 0x01) ;
+
+}
+
+/******************************************************************************
+** Function name: GPIOinit
+**
+** Descriptions: Sets all GPIO ports to a known state
+** parameters: None
+** Returned value: None
+**
+******************************************************************************/
+static void GPIOinit (void)
+{
+ pin_connect_2468_t *pin_connect=
+ &(((immap_t *)CONFIG_SYS_IMMAP)->apb.pin_connect);
+ gpio_2468_t *gpio=
+ &(((immap_t *)CONFIG_SYS_IMMAP)->apb.gpio);
+ fastio_2468_t *fio=(fastio_2468_t *)FASTIO_BASE_ADDR;
+
+ writel (0, &(pin_connect->pinsel0));
+ writel (0, &(pin_connect->pinsel1));
+ writel (0, &(pin_connect->pinsel2));
+ writel (0, &(pin_connect->pinsel3));
+ writel (0, &(pin_connect->pinsel4));
+ writel (0, &(pin_connect->pinsel5));
+ writel (0, &(pin_connect->pinsel6));
+ writel (0, &(pin_connect->pinsel7));
+ writel (0, &(pin_connect->pinsel8));
+ writel (0, &(pin_connect->pinsel9));
+ writel (0, &(pin_connect->pinsel10));
+
+ writel (0, &(gpio->iodir0));
+ writel (0, &(gpio->iodir1));
+ writel (0xffffffff, &(gpio->ioset0));
+ writel (0xffffffff, &(gpio->ioset1));
+
+ writel (0, &(fio->fio0dir));
+ writel (0, &(fio->fio1dir));
+ writel (0, &(fio->fio2dir));
+ writel (0, &(fio->fio3dir));
+ writel (0, &(fio->fio4dir));
+
+ writel (0xffffffff, &(fio->fio0set));
+ writel (0xffffffff, &(fio->fio1set));
+ writel (0xffffffff, &(fio->fio2set));
+ writel (0, &(fio->fio3set));
+ writel (0xffffffff, &(fio->fio4set));
+}
+
+/******************************************************************************
+** Function name: VICinit
+**
+** Descriptions: Initialize the VIC to a known state
+** parameters: None
+** Returned value: None
+**
+******************************************************************************/
+static void VICinit (void)
+{
+ vic_2468_t *vic=&(((immap_t *)CONFIG_SYS_IMMAP)->ahb.vic);
+ /*initialize VIC */
+ writel (0xffffffff, &(vic->vicinenclr)); /* Disable ALL interrupts */
+ writel (0, &(vic->vicprotect)); /* Setup interrupt controller */
+ writel (0, &(vic->vicaddr));
+ writel (0, &(vic->vicintselect));
+ writel (0, &(vic->vicvectaddr0)); /* Set the vector address */
+ writel (0, &(vic->vicvectaddr1));
+ writel (0, &(vic->vicvectaddr2));
+ writel (0, &(vic->vicvectaddr3));
+ writel (0, &(vic->vicvectaddr4));
+ writel (0, &(vic->vicvectaddr5));
+ writel (0, &(vic->vicvectaddr6));
+ writel (0, &(vic->vicvectaddr7));
+ writel (0, &(vic->vicvectaddr8));
+ writel (0, &(vic->vicvectaddr9));
+ writel (0, &(vic->vicvectaddr10));
+ writel (0, &(vic->vicvectaddr11));
+ writel (0, &(vic->vicvectaddr12));
+ writel (0, &(vic->vicvectaddr13));
+ writel (0, &(vic->vicvectaddr14));
+ writel (0, &(vic->vicvectaddr15));
+ writel (0, &(vic->vicvectaddr16));
+ writel (0, &(vic->vicvectaddr17));
+ writel (0, &(vic->vicvectaddr18));
+ writel (0, &(vic->vicvectaddr19));
+ writel (0, &(vic->vicvectaddr20));
+ writel (0, &(vic->vicvectaddr21));
+ writel (0, &(vic->vicvectaddr22));
+ writel (0, &(vic->vicvectaddr23));
+ writel (0, &(vic->vicvectaddr24));
+ writel (0, &(vic->vicvectaddr25));
+ writel (0, &(vic->vicvectaddr26));
+ writel (0, &(vic->vicvectaddr27));
+ writel (0, &(vic->vicvectaddr28));
+ writel (0, &(vic->vicvectaddr29));
+ writel (0, &(vic->vicvectaddr30));
+ writel (0, &(vic->vicvectaddr31));
+ writel (0xf, &(vic->vicvectprio0));
+ writel (0xf, &(vic->vicvectprio1));
+ writel (0xf, &(vic->vicvectprio2));
+ writel (0xf, &(vic->vicvectprio3));
+ writel (0xf, &(vic->vicvectprio4));
+ writel (0xf, &(vic->vicvectprio5));
+ writel (0xf, &(vic->vicvectprio6));
+ writel (0xf, &(vic->vicvectprio7));
+ writel (0xf, &(vic->vicvectprio8));
+ writel (0xf, &(vic->vicvectprio9));
+ writel (0xf, &(vic->vicvectprio10));
+ writel (0xf, &(vic->vicvectprio11));
+ writel (0xf, &(vic->vicvectprio12));
+ writel (0xf, &(vic->vicvectprio13));
+ writel (0xf, &(vic->vicvectprio14));
+ writel (0xf, &(vic->vicvectprio15));
+ writel (0xf, &(vic->vicvectprio16));
+ writel (0xf, &(vic->vicvectprio17));
+ writel (0xf, &(vic->vicvectprio18));
+ writel (0xf, &(vic->vicvectprio19));
+ writel (0xf, &(vic->vicvectprio20));
+ writel (0xf, &(vic->vicvectprio21));
+ writel (0xf, &(vic->vicvectprio22));
+ writel (0xf, &(vic->vicvectprio23));
+ writel (0xf, &(vic->vicvectprio24));
+ writel (0xf, &(vic->vicvectprio25));
+ writel (0xf, &(vic->vicvectprio26));
+ writel (0xf, &(vic->vicvectprio27));
+ writel (0xf, &(vic->vicvectprio28));
+ writel (0xf, &(vic->vicvectprio29));
+ writel (0xf, &(vic->vicvectprio30));
+ writel (0xf, &(vic->vicvectprio31));
+}
+
+/*****************************************************************************
+** Function name: ConfigurePLL
+**
+** Descriptions: Configure the PLL
+** parameters: None
+** Returned value: None
+**
+*****************************************************************************/
+void ConfigurePLL (void)
+{
+ sys_con_2468_t *sys_con=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con);
+
+ volatile unsigned long MValue;
+ volatile unsigned long NValue;
+ if (readl (&(sys_con->pllstat)) & (1 << 25)) {
+
+ writel (1, &(sys_con->pllcon)); /* Enable PLL, disconnected */
+ writel (0xaa, &(sys_con->pllfeed));
+ writel (0x55, &(sys_con->pllfeed));
+ }
+
+ writel (0, &(sys_con->pllcon)); /* Disable PLL, disconnected */
+ writel (0xaa, &(sys_con->pllfeed));
+ writel (0x55, &(sys_con->pllfeed));
+ BFS32 (&(sys_con->scs), 0x20); /* Enable main OSC */
+
+ /* Wait until main OSC is usable */
+ while (!(readl (&(sys_con->scs)) & 0x40));
+
+ /* select main OSC, 12MHz, as the PLL clock source */
+ writel (0x1, &(sys_con->clksrcsel));
+ writel (PLL_MValue | (PLL_NValue << 16), &(sys_con->pllcfg));
+ writel (0xaa, &(sys_con->pllfeed));
+ writel (0x55, &(sys_con->pllfeed));
+ writel (1, &(sys_con->pllcon)); /* Enable PLL, disconnected */
+ writel (0xaa, &(sys_con->pllfeed));
+ writel (0x55, &(sys_con->pllfeed));
+ writel (CCLKDivValue, &(sys_con->cclkcfg)); /*Set clock divider*/
+
+#if USE_USB
+ /* usbclk = 288 MHz/6 = 48 MHz */
+ writel (USBCLKDivValue, &(sys_con->usbclkcfg));
+#endif
+
+ /* Check lock bit status */
+ while (((readl (&(sys_con->pllstat)) & (1 << 26)) == 0));
+
+ MValue = readl (&(sys_con->pllstat)) & 0x00007FFF;
+ NValue = (readl (&(sys_con->pllstat)) & 0x00FF0000) >> 16;
+
+ while ((MValue != PLL_MValue) && (NValue != PLL_NValue)) ;
+
+ writel (3, &(sys_con->pllcon)); /* enable and connect */
+ writel (0xaa, &(sys_con->pllfeed));
+ writel (0x55, &(sys_con->pllfeed));
+ /* Check connect bit status */
+ while (((readl (&(sys_con->pllstat)) & (1 << 25)) == 0));
+}
+
+/****************************************************************************
+** Function name: ConfigureEMC
+**
+** Descriptions: Configure EMC for external SDRAM, NAND and NOR FLASH
+** parameters: None
+** Returned value: None
+**
+****************************************************************************/
+void ConfigureEMC (void)
+{
+ ext_mem_2468_t *emc=&(((immap_t *)CONFIG_SYS_IMMAP)->ahb.ext_mem);
+ pin_connect_2468_t *pin_connect=
+ &(((immap_t *)CONFIG_SYS_IMMAP)->apb.pin_connect);
+ sys_con_2468_t *sys_con=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con);
+
+ volatile unsigned int i, dummy = dummy;
+
+ writel (0x00000001, &(emc->control));
+ BFS32 (&(sys_con->pconp), 0x00000800); /* Turn on EMC PCLK */
+
+ /* CS2 & CS3 not used PINSEL4 = 0x50000000; */
+ writel (0x05050555, &(pin_connect->pinsel5));
+ writel (0x55555555, &(pin_connect->pinsel6));
+ writel (0x55555555, &(pin_connect->pinsel8));
+ writel (0x50555555, &(pin_connect->pinsel9));
+
+ /*all registers... */
+ writel (2, &(emc->dynrp)); /*>20ns = 2 clk */
+ writel (3, &(emc->dynras)); /*>45ns = 3 clk */
+ writel (7, &(emc->dynsrex)); /*>80-100ns = 6 clk */
+ writel (2, &(emc->dynapr));
+ writel (5, &(emc->dyndal)); /*2 clk */
+ writel (1, &(emc->dynwr)); /*2 clk */
+ writel (5, &(emc->dynrc)); /*>65ns = 4 clk */
+ writel (5, &(emc->dynrfc)); /*>80-100ns = 6 clk */
+ writel (7, &(emc->dynxsr)); /*>80-100ns = 6 clk */
+ writel (1, &(emc->dynrrd)); /*>15ns = 1-2 clk */
+ writel (2, &(emc->dynmrd)); /*2 clk */
+ writel (1, &(emc->dynreadconfig)); /*or 1,2,3 */
+ writel (0x00000303, &(emc->dynrascas0));
+ writel (0x00000680, &(emc->dynconfig0));
+
+ /*wait 100mS */
+ delayMs (100);
+
+ /*Send command: NOP */
+ writel (0x00000183, &(emc->dyncontrol));
+
+ /*wait 200mS */
+ delayMs (200);
+
+ /*Send command: PRECHARGE-ALL, shortest possible refresh period */
+ writel (0x00000103, &(emc->dyncontrol));
+ writel (0x00000002, &(emc->dynrefresh));
+
+ /*wait 128 ABH clock cycles */
+ for (i = 0; i < 0x40; i++)
+ asm volatile (" nop");
+
+ /*Set correct refresh period */
+ writel (28, &(emc->dynrefresh));
+
+ /*Send command: MODE */
+ writel (0x00000083, &(emc->dyncontrol));
+
+ /*Set mode register in SDRAM */
+ dummy = *((volatile unsigned int *)(SDRAM_BASE_ADDR | (0x33 << 12)));
+
+ /*Send command: NORMAL */
+ writel (0x00000000, &(emc->dyncontrol));
+
+ /*Enable buffer */
+ BFS32 (&(emc->dynconfig0), 0x00080000);
+
+ /*initial system delay */
+ delayMs (1);
+
+ writel (0x2, &(emc->statwaitwen0));
+ writel (0x2, &(emc->statwaitoen0));
+ writel (0x1f, &(emc->statwaitrd0));
+ writel (0x1f, &(emc->statwaitpage0));
+ writel (0x1f, &(emc->statwaitwr0));
+ writel (0xf, &(emc->statwaitturn0));
+ writel (0x00000081, &(emc->statconfig0));
+ writel (0x2, &(emc->statwaitwen1));
+ writel (0x2, &(emc->statwaitoen1));
+ writel (0x8, &(emc->statwaitrd1));
+ writel (0x1f, &(emc->statwaitpage1));
+ writel (0x8, &(emc->statwaitwr1));
+ writel (0xf, &(emc->statwaitturn1));
+ writel (0x00000080, &(emc->statconfig1));
+}
+
+/*****************************************************************************
+ *
+ * Description:
+ * Initialize system functions and GPIO
+ *
+ ****************************************************************************/
+void lowlevel_init (void)
+{
+ sys_con_2468_t *sys_con=&(((immap_t *)CONFIG_SYS_IMMAP)->apb.sys_con);
+
+ /**************************************************************************
+ * Remap vectors for RAM execution
+ **************************************************************************/
+
+ writel (1, &(sys_con->memmap));
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* move vectors to beginning of SRAM */
+ asm volatile
+ (" mov r2, #0x40000000 \n"
+ " mov r0, #0x00000000 \n"
+ " ldmneia r0!, {r3-r10} \n"
+ " stmneia r2!, {r3-r10} \n"
+ " ldmneia r0, {r3-r9} \n"
+ " stmneia r2, {r3-r9} \n":::"r0",
+ "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10");
+#else
+ /* move vectors to beginning of SRAM */
+ asm volatile
+ (" mov r2, #0x40000000 \n"
+ " mov r0, #0xa1000000 \n"
+ " ldmneia r0!, {r3-r10} \n"
+ " stmneia r2!, {r3-r10} \n"
+ " ldmneia r0, {r3-r9} \n"
+ " stmneia r2, {r3-r9} \n":::"r0",
+ "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10");
+#endif
+
+ /*initialize the exception vector mapping */
+ writel (MEM_MAP, (&sys_con->memmap));
+
+#if USE_USB
+ BFS32 (&(sys_con->pconp), 0x80000000); /* Turn On USB PCLK */
+#endif
+
+ ConfigurePLL ();
+
+ /* Set system timers for each component */
+
+#if (Fpclk / (Fcclk / 4)) == 1
+ writel (0x00000000, &(sys_con->pclksel0)); /* PCLK is 1/4 CCLK */
+ writel (0x00000000, &(sys_con->pclksel1));
+#endif
+
+#if (Fpclk / (Fcclk / 4)) == 2
+ writel (0xAAAAAAAA, &(sys_con->pclksel0)); /* PCLK is 1/2 CCLK */
+ writel (0xAAAAAAAA, &(sys_con->pclksel1));
+#endif
+
+#if (Fpclk / (Fcclk / 4)) == 4
+ writel (0x55555555, &(sys_con->pclksel0)); /*PCLK is the same as CCLK*/
+ writel (0x55555555, &(sys_con->pclksel1));
+#endif
+
+ /* Set memory accelerater module */
+ writel (0, &(sys_con->mamcr));
+ writel (4, &(sys_con->mamtim));
+
+ /*Init GPIO */
+ GPIOinit ();
+
+ /*initialize VIC */
+ VICinit ();
+
+ /*short delay */
+ delayMs (10);
+
+ /*************************************************************************
+ * Initialize external memory interface (EMC)
+ ************************************************************************/
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ ConfigureEMC ();
+#endif
+}
diff --git a/board/LPC2468/nand.c b/board/LPC2468/nand.c
new file mode 100755
index 0000000..dbbfe36
--- /dev/null
+++ b/board/LPC2468/nand.c
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2009 Duran Audio B.V. <www.duran-audio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * 18-03-2009 Updated for U-boot 2009.3
+ * by Remco Poelstra <remco.poelstra+u-boot@duran-audio.com>
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+
+/*
+ * CLE at A20
+ * ALE at A19
+ */
+#define MASK_CLE (1l<<20)
+#define MASK_ALE (1l<<19)
+
+static void cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+
+ ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
+ if (ctrl & NAND_CLE)
+ IO_ADDR_W |= MASK_CLE;
+ if (ctrl & NAND_ALE)
+ IO_ADDR_W |= MASK_ALE;
+ this->IO_ADDR_W = (void *)IO_ADDR_W;
+ }
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ /* IO_ADDR_R and IO_ADDR_W set by nand-driver using CFG_NAND_BASE */
+ nand->dev_ready = 0;
+ nand->cmd_ctrl = cmd_ctrl;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->chip_delay = 25; /* us */
+ nand->options = NAND_SAMSUNG_LP_OPTIONS;
+
+ return 0;
+}
diff --git a/board/LPC2468/u-boot.lds b/board/LPC2468/u-boot.lds
new file mode 100755
index 0000000..64d946c
--- /dev/null
+++ b/board/LPC2468/u-boot.lds
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm720t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/include/asm-arm/arch-lpc24xx/immap.h b/include/asm-arm/arch-lpc24xx/immap.h
index ab25dd5..0841230 100644
--- a/include/asm-arm/arch-lpc24xx/immap.h
+++ b/include/asm-arm/arch-lpc24xx/immap.h
@@ -94,7 +94,15 @@ typedef struct rtc_2468 {
} rtc_2468_t;

typedef struct gpio_2468 {
- u8 fixme[0x4000];
+ u32 iopin0;
+ u32 ioset0;
+ u32 iodir0;
+ u32 ioclr0;
+ u32 iopin1;
+ u32 ioset1;
+ u32 iodir1;
+ u32 ioclr1;
+ u8 notused[0x3fe0];
} gpio_2468_t;

typedef struct pin_connect_2468 {
@@ -120,7 +128,7 @@ typedef struct pin_connect_2468 {
u32 pinmode7;
u32 pinmode8;
u32 pinmode9;
- u8 fixme[0x3fa8];
+ u8 notused[0x3fa8];
} pin_connect_2468_t;

typedef struct ssp1_2468 {
@@ -179,21 +187,37 @@ typedef struct mmc_2468 {
u8 fixme[0x4000];
} mmc_2468_t;

-typedef struct sys_con_2468 {
- u8 notused1[0x40];
+typedef struct sys_con_2468 { // c000
+ u32 mamcr; /*Memory Accelerator configuration register*/
+ u32 mamtim; /*Memory Accelerator timing register*/
+ u8 notused1[0x38];
u32 memmap; /*Memory mapping control register c040*/
- u8 notused2[0x80];
+ u8 notused2[0x3c];
+ u32 pllcon; /*PLL control register c080*/
+ u32 pllcfg; /*PLL configuration register c084*/
+ u32 pllstat; /*PLL status register c088*/
+ u32 pllfeed; /*PLL feed register c08c*/
+ u8 notused3[0x30];
+ u32 pcon; /*Power control register c0c0*/
u32 pconp; /*Power control for peripherals register c0c4*/
- u8 notused3[0x7c];
+ u8 notused4[0x3c];
+ u32 cclkcfg; /*CPU clock configuration register c104*/
+ u32 usbclkcfg; /*USB clock configuration register c108*/
+ u32 clksrcsel; /*Clock source select register c10c*/
+ u8 notused5[0x30];
u32 extint; /*External interrupt flag register c140*/
+ u32 intwake; /*Interrupt wakeup register c144*/
u32 extmode; /*External interrupt mode resgister c148*/
u32 extpolar; /*External interrupt polarity register c14c*/
- u8 notused4[0x30];
+ u8 notused6[0x30];
u32 rsid; /*Reset source identification register c180*/
u32 cspr; /*Code security protection register c184*/
- u8 notused5[0x18];
+ u8 notused7[0x18];
u32 scs; /*System control and status register c1a0*/
- u8 notused6[0x3e5c];
+ u32 irctrim; /*IRC trim register c1a4*/
+ u32 pclksel0; /*Peripheral clock selection register 0 c1a8*/
+ u32 pclksel1; /*Peripheral clock selection register 1 c1ac*/
+ u8 notused8[0x3e50];
} sys_con_2468_t;

@@ -258,7 +282,72 @@ typedef struct gpdma__2468 {
} gpdma_2468_t;

typedef struct ext_mem_2468 {
- u8 fixme[0x4000];
+ u32 control; /*Controls operation of the memory controller*/
+ u32 status; /*Provides EMC status*/
+ u32 config; /*Configures operation of the memorycontroller*/
+ u8 notused1[0x14];
+ u32 dyncontrol; /*Controls dynamic memory operation*/
+ u32 dynrefresh; /*Configures dynamic refresh operation*/
+ u32 dynreadconfig; /*Configures the dynamic memory read strategy*/
+ u32 notused2;
+ u32 dynrp; /*Selects the precharge command period*/
+ u32 dynras; /*Selects the active to precharge command period*/
+ u32 dynsrex; /*Selects the self-refresh time*/
+ u32 dynapr; /*Selects the last-data-out to active command time*/
+ u32 dyndal; /*Selects the data-in to active command time*/
+ u32 dynwr; /*Selects the write recovery time*/
+ u32 dynrc; /*Selects the active to active command period*/
+ u32 dynrfc; /*Selects the auto-refresh period*/
+ u32 dynxsr; /*Selects the exit self-refresh to active command time*/
+ u32 dynrrd; /*Selects the active ank A to active bank B latency*/
+ u32 dynmrd; /*Selects the load mode register to active command time*/
+ u8 notused3[0xa4];
+ u32 dynconfig0; /*Configuration information for dyn memory CS 0*/
+ u32 dynrascas0; /*Selects the RAs and CAS latency fos CS 0*/
+ u8 notused4[0x18];
+ u32 dynconfig1; /*Configuration information for dyn memory CS 1*/
+ u32 dynrascas1; /*Selects the RAs and CAS latency fos CS 1*/
+ u8 notused5[0x18];
+ u32 dynconfig2; /*Configuration information for dyn memory CS 2*/
+ u32 dynrascas2; /*Selects the RAs and CAS latency fos CS 2*/
+ u8 notused6[0x18];
+ u32 dynconfig3; /*Configuration information for dyn memory CS 3*/
+ u32 dynrascas3; /*Selects the RAs and CAS latency fos CS 3*/
+ u8 notused7[0x98];
+ u32 statconfig0; /*Memory configuration for static CS 0*/
+ u32 statwaitwen0; /*Selects the delay from CS 0 to WE*/
+ u32 statwaitoen0; /*Selects the delay from CS 0 OE*/
+ u32 statwaitrd0; /*Selects the delay from CS 0 to a read access*/
+ u32 statwaitpage0; /*Selects the delay for async page mode for CS 0*/
+ u32 statwaitwr0; /*Selects the delay from CS 0 to a write access*/
+ u32 statwaitturn0; /*Selects the # of bus turnaround cycles for CS 0*/
+ u8 notused8[0x4];
+ u32 statconfig1; /*Memory configuration for static CS 1*/
+ u32 statwaitwen1; /*Selects the delay from CS 1 to WE*/
+ u32 statwaitoen1; /*Selects the delay from CS 1 OE*/
+ u32 statwaitrd1; /*Selects the delay from CS 1 to a read access*/
+ u32 statwaitpage1; /*Selects the delay for async page mode for CS 1*/
+ u32 statwaitwr1; /*Selects the delay from CS 1 to a write access*/
+ u32 statwaitturn1; /*Selects the # of bus turnaround cycles for CS 1*/
+ u8 notused9[0x4];
+ u32 statconfig2; /*Memory configuration for static CS 2*/
+ u32 statwaitwen2; /*Selects the delay from CS 2 to WE*/
+ u32 statwaitoen2; /*Selects the delay from CS 2 OE*/
+ u32 statwaitrd2; /*Selects the delay from CS 2 to a read access*/
+ u32 statwaitpage2; /*Selects the delay for async page mode for CS 2*/
+ u32 statwaitwr2; /*Selects the delay from CS 2 to a write access*/
+ u32 statwaitturn2; /*Selects the # of bus turnaround cycles for CS 2*/
+ u8 notused10[0x4];
+ u32 statconfig3; /*Memory configuration for static CS 3*/
+ u32 satwaitwen3; /*Selects the delay from CS 3 to WE*/
+ u32 statwaitoen3; /*Selects the delay from CS 3 OE*/
+ u32 statwaitrd3; /*Selects the delay from CS 3 to a read access*/
+ u32 statwaitpage3; /*Selects the delay for async page mode for CS 3*/
+ u32 statwaitwr3; /*Selects the delay from CS 3 to a write access*/
+ u32 statwaitturn3; /*Selects the # of bus turnaround cycles for CS 3*/
+ u8 notused11[0x604];
+ u32 extwait;
+ u8 notused12[0x377c];
} ext_mem_2468_t;

typedef struct usb_2468 {
@@ -350,6 +439,39 @@ typedef struct vic_2468 {
u32 vicaddr; /*Vector address register for active interrupt*/
} vic_2468_t;

+typedef struct fastio_2468 {
+ u32 fio0dir; /*Fast IO 0 port direction register*/
+ u8 notused1[0xc];
+ u32 fio0mask; /*Fast IO 0 mask register*/
+ u32 fio0pin; /*Fast IO 0 pin value register*/
+ u32 fio0set; /*Fast IO 0 output set register*/
+ u32 fio0clr; /*Fast IO 0 output clear register*/
+ u32 fio1dir; /*Fast IO 1 port direction register*/
+ u8 notused2[0xc];
+ u32 fio1mask; /*Fast IO 1 mask register*/
+ u32 fio1pin; /*Fast IO 1 pin value register*/
+ u32 fio1set; /*Fast IO 1 output set register*/
+ u32 fio1clr; /*Fast IO 1 output clear register*/
+ u32 fio2dir; /*Fast IO 2 port direction register*/
+ u8 notused3[0xc];
+ u32 fio2mask; /*Fast IO 2 mask register*/
+ u32 fio2pin; /*Fast IO 2 pin value register*/
+ u32 fio2set; /*Fast IO 2 output set register*/
+ u32 fio2clr; /*Fast IO 2 output clear register*/
+ u32 fio3dir; /*Fast IO 3 port direction register*/
+ u8 notused4[0xc];
+ u32 fio3mask; /*Fast IO 3 mask register*/
+ u32 fio3pin; /*Fast IO 3 pin value register*/
+ u32 fio3set; /*Fast IO 3 output set register*/
+ u32 fio3clr; /*Fast IO 3 output clear register*/
+ u32 fio4dir; /*Fast IO 4 port direction register*/
+ u8 notused5[0xc];
+ u32 fio4mask; /*Fast IO 4 mask register*/
+ u32 fio4pin; /*Fast IO 4 pin value register*/
+ u32 fio4set; /*Fast IO 4 output set register*/
+ u32 fio4clr; /*Fast IO 4 output clear register*/
+} fastio_2468_t;
+
typedef struct apb_2468 { /*Peripheral bus memory layout*/
watchdog2468_t watchdog;
timer_2468_t timer0;
diff --git a/include/configs/LPC2468.h b/include/configs/LPC2468.h
new file mode 100644
index 0000000..67680ca
--- /dev/null
+++ b/include/configs/LPC2468.h
@@ -0,0 +1,220 @@
+/*
+ * (C) Copyright 2008
+ * Embedded Artists AB, Sweden <www.EmbeddedArtists.com>
+ *
+ * Configuation settings for the LPC2468 OEM Board, 16 bit databus.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_LPC2468
+
+/*
+ * If we are developing, we might want to start armboot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ */
+#if 0
+#define CONFIG_INIT_CRITICAL /* undef for developing */
+#endif
+
+#undef CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
+#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
+#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
+
+/* Clock settings */
+
+/* Crystal frequency */
+#define CONFIG_FOSC 12000000
+
+/*
+ * Fcco = 2*M*Fosc / N
+ *
+ * Fcco = 288000000 -> M = 12, N = 1
+ *
+ * PLLCFG (MSEL) = (M-1)
+ * PLLCFG (NSEL) = (N-1)
+ */
+#define CONFIG_PLL_MVALUE 12
+#define CONFIG_PLL_NVALUE 1
+
+/*
+ * Fcclk = Fcco / CLKDIV
+ * CLKDIV must be an even number
+ *
+ * CCLKCFG = CLKDIV-1 (odd number must be written to register)
+ * CLKDIV = 4 -> Fcclk = 72 MHz (if Fcco = 288 MHz)
+ * CLKDIV = 6 -> Fcclk = 48 MHz (if Fcco = 288 MHz)
+ */
+#define CONFIG_PLL_CLKDIV 4
+
+/*
+ * The USB clock must be 48 MHz
+ * Fusb = Fcco / USBCLKDIV
+ * USBCLKCFG = (USBCLKDIV-1)
+ */
+#define CONFIG_PLL_USBCLKDIV 6
+
+/*
+ * Periperhal clock divider, i.e. Fpclk = Fcclk / divider
+ * Valid values are 1, 2, or 4
+ */
+#define CONFIG_FPCLK_DIV 1
+
+#define CONFIG_USE_IRQ /* use irq for mci interface */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_LPC2468_SERIAL
+#define CONFIG_SERIAL 1 /* we use Serial line 1 */
+
+#define CONFIG_LPC2468_ETH
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_BOOTD
+#define CONFIG_CMD_NAND
+
+#define CONFIG_BOOTARGS\
+ "root=/dev/ram initrd=0xa1800000,4000k console=ttyS0,115200N8"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /*undef to save memory*/
+#define CONFIG_SYS_CBSIZE 256 /*Console I/O Buffer Size*/
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16 /*max number of command args*/
+#define CFG_BARGSIZE CFG_CBSIZE /*Boot Argument Buffer Size*/
+
+#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest works on */
+/* 31.5 MB in DRAM, U-boot is relocated after this location*/
+#define CONFIG_SYS_MEMTEST_END 0xA1F80000
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_SYS_IMMAP 0xE0000000
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+/* default load address for kernel img is here*/
+#define CONFIG_SYS_LOAD_ADDR 0xA0008000
+
+#define CLK_FCCO ((2*CONFIG_PLL_MVALUE*CONFIG_FOSC) / CONFIG_PLL_NVALUE)
+
+#define CFG_SYS_CLK_FREQ (CLK_FCCO / CONFIG_PLL_CLKDIV)/* Hz */
+#define ODCONFIG_SYS_HZ 200000 /* decrementer freq in Hz */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (8*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0xA0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB SDRAM */
+
+#define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */
+#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks*/
+#define CONFIG_SYS_MAX_FLASH_SECT1024 /* max number of sectors on one chip*/
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
+
+/*
+ * Linux tags
+ */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/*
+ * NAND Flash
+ */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_NAND_BASE 0x81000000
+
+
+/*
+ * Default environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ipaddr=192.168.3.2" \
+ "netmask=255.255.255.0" \
+ "serverip=192.168.3.1" \
+ "ethaddr=00:1a:f1:00:00:00"
+
+/*
+ * Control where environment is stored
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (0x0 + 0x7C000) /*Addr of Environment Sector*/
+#define CONFIG_ENV_SIZE 0x1000 /*Total Size of Environment Sector(4k)*/
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT "LPC2468 # "
+
+#endif /* __CONFIG_H */
--
1.6.2.4