[U-Boot] [PATCH] Coldfire: I2C: Update I2CFDR frequency divider 0x0E value from 192 to 204

[Richard Retanubun <RichardRetanubun@RuggedCom.com>]

Hi TC,
> Richard,
> 
> Nak.
> 
> The divider and fdr value are predefined in the 5271 reference manual.
I know, that's why I said this is empirical evidence, not mathematical :)
> 
> The bus clock is 50Mhz and the CONFIG_SYS_I2C_SPEED is set to 80000.
This is the default for the M5271EVB, yes, but I've modded mine to have the bus clock at 75 MHz, and CONFIG_SYS_I2C_SPEED set to 4000000
(bus clock 75MHz being the Max speed supported by the M5271).

What I observed is that although there are two divider value that claims to divide by 192 (namely {192, 14} and {192, 49},
my empirical experiments shows that for the setup described above, 49 (listed after 14, and never picked) results
in a closer approximation. So we have two options:

1. Reorder the table entry so that {192, 49} is listed before {192, 14} and hence picked. (this is confusing though)
2. Assign 14 to a value it is observed to divide by (div-by-204) in the setup I described above.
3. Remove the {192, 14} entry, so that {192, 49} is picked. (this does not match the documentation)

I opted for the 2nd option because having two identical divider entries and having only the first one listed picked seems redundant.

I am not claiming that the divider value that I assign from {192, 14} to {204, 14} will be true for ALL i2c controllers in all Coldfires,
that depends if the same circuit and silicon is stamped on them, I was hoping that the freescale folks can help us with that :)

Regards,

- Richard