[U-Boot] MPC8572E I2C bus speed after emulator reset

[U-Boot] MPC8572E I2C bus speed after emulator reset

[Scott Coulter]

Hi everyone,

I am seeing a strange issue that someone may have bumped into before.  I
am running a modified version of Freescale's v2008.10 U-boot release
from the December 2008 LTIB package on our 8572E based board.  Under
normal reset conditions (power up or reset switch), the board boots and
runs fine including loading and running linux.

If however I connect a JTAG emulator (WindRiver probe) and reset the
target using the "inn" command, which should reset the core without
loading any registers, and follow up with a "go" command which starts
the core fetching from the reset vector, the read of the DIMM SPD data
fails.  Further analysis shows that the serial EEPROM doesn't answer the
bell because the I2C bus clock is running at something close to 4MHz
instead of the 400KHz specified.

While the target is in this state, I can use the emulator to jack up the
I2C divider to its max (0x3F) and run a dummy I2C read.  Changing the
divider does have an effect on the I2C clock frequency.  It is almost as
though the input clock to the I2C block is running way too fast.  From
the Freescale documentation, the I2C clock is half the CCB clock.  The
UART prints without problem so the baud rate dividers and CCB clock
frequency would seem to be all right.  The U-boot banner portion which
reads all of the clock ratios is not different between and hard reset
and an emulator reset.  A read of the PORPLLSR returns the correct
ratios even when the I2C clock speed is way off.

I have an older version of U-boot for the board which is based of the
initial port that Kumar did (no MP support, etc.).  With this version of
U-boot in flash, the "inn" "go" sequence works fine.  The only thing
that I can think of is that the older U-boot has a different init
sequence.

Does anyone know of way to ensure that the I2C input clock is stable
before attempting I2C operations?

Thanks in advance,

Scott





___________________________________________________________________

  Scott N. Coulter
  Senior Software Engineer
  
  Cyclone Microsystems          
  370 James Street              Phone:  203.786.5536 ext. 118
  New Haven, CT 06513-3051      Email:  scott.coulter at cyclone.com
  U.S.A.                        Web:    http://www.cyclone.com
___________________________________________________________________

[U-Boot] MPC8572E I2C bus speed after emulator reset

[Timur Tabi]

On Fri, Mar 27, 2009 at 11:52 AM, Scott Coulter
<scott.coulter@cyclone.com> wrote:

> I have an older version of U-boot for the board which is based of the
> initial port that Kumar did (no MP support, etc.). ?With this version of
> U-boot in flash, the "inn" "go" sequence works fine. ?The only thing
> that I can think of is that the older U-boot has a different init
> sequence.

You're right, it does.  I wrote the new code. :-)

Previously, U-Boot programmed the same values into the FDR and DFSR
registers, regardless of the input clock rate or whatever divider the
SOC used.  CONFIG_SYS_I2C_SPEED was ignored.

The new code uses a lookup table to determine the best values for FDR
and DFSR for a given input clock rate.  It tries to take into account
the actual divider that your specific SOC uses.  This is done in
function get_clocks().  It's possible that the divider is
miscalculated.

> Does anyone know of way to ensure that the I2C input clock is stable
> before attempting I2C operations?

What is the value of CONFIG_SYS_I2C_SPEED in your board header file?

What values does function set_i2c_bus_speed() in fsl_i2c.c program
into the FDR and DFSR registers?

-- 
Timur Tabi
Linux kernel developer at Freescale

[U-Boot] MPC8572E I2C bus speed after emulator reset

[Scott Coulter]

Hi Timur,

> What is the value of CONFIG_SYS_I2C_SPEED in your board header file?
 
#define CONFIG_SYS_I2C_SPEED		400000

> What values does function set_i2c_bus_speed() in fsl_i2c.c program
> into the FDR and DFSR registers?

According to my printfs and the emulator readback of the values, the
code is putting a 0x6 into the FDR and a 0x1 into the DFSR.  These
values appear to be identical with either a hard reset or an emulator
reset.

Thanks,
Scott

___________________________________________________________________

  Scott N. Coulter
  Senior Software Engineer
  
  Cyclone Microsystems          
  370 James Street              Phone:  203.786.5536 ext. 118
  New Haven, CT 06513-3051      Email:  scott.coulter at cyclone.com
  U.S.A.                        Web:    http://www.cyclone.com
___________________________________________________________________

[U-Boot] MPC8572E I2C bus speed after emulator reset

[Timur Tabi]

Scott Coulter wrote:
> Hi Timur,
> 
>> What is the value of CONFIG_SYS_I2C_SPEED in your board header file?
>  
> #define CONFIG_SYS_I2C_SPEED		400000

So far, so good.

>> What values does function set_i2c_bus_speed() in fsl_i2c.c program
>> into the FDR and DFSR registers?
> 
> According to my printfs and the emulator readback of the values, the
> code is putting a 0x6 into the FDR and a 0x1 into the DFSR.  These
> values appear to be identical with either a hard reset or an emulator
> reset.

According to the 8572E RM, the default values for DFSR and FDR are 0x10
and 0x00.  The values above represent, according to the table, a divider
of 768.  The RM also says that I2C clock is 1/2 CCB, so that means that
your CCB should be 400,000 * 768 * 2 = 614MHz.  Is that right?

-- 
Timur Tabi
Linux kernel developer at Freescale