* [U-Boot] What to do for a working BIOSEMU and ATI_RADEON_FB environment?
@ 2009-03-28 15:26 Markus Rathgeb
2009-03-28 23:25 ` Anatolij Gustschin
2009-03-29 15:21 ` Jon Smirl
0 siblings, 2 replies; 7+ messages in thread
From: Markus Rathgeb @ 2009-03-28 15:26 UTC (permalink / raw)
To: u-boot
Hi!
I own a phytec's pcm-030 with the shipped baseboard pcm-973.
I would like to use a radeon 9200 pci card in the slot on the baseboard.
I have done a git checkout of the u-boot and I am using the 'board
support patch for phyCORE-MPC5200B-tiny?' from the mailing list.
To provide the necessary informations here some outputs the u-boot command line:
=================
uboot> pci
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.18.00 0x1002 0x5c63 Display controller 0x00
00.18.01 0x1002 0x5c43 Display controller 0x80
00.1a.00 0x1057 0x5809 Bridge device 0x80
uboot> pci header 00.1a.00
vendor ID = 0x1057
device ID = 0x5809
command register = 0x0006
status register = 0x22a0
revision ID = 0x00
class code = 0x06 (Bridge device)
sub class code = 0x80
programming interface = 0x00
cache line = 0x08
latency time = 0xf8
header type = 0x00
BIST = 0x00
base address 0 = 0xf0000000
base address 1 = 0x00000008
base address 2 = 0x00000000
base address 3 = 0x00000000
base address 4 = 0x00000000
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x0000
sub system ID = 0x0000
expansion ROM base address = 0x00000000
interrupt line = 0x00
interrupt pin = 0x00
min Grant = 0x00
max Latency = 0x00
uboot> pci display 00.1a.00 0 40
00000000: 58091057 22a00006 06800000 0000f808
00000010: f0000000 00000008 00000000 00000000
00000020: 00000000 00000000 00000000 00000000
00000030: 00000000 00000000 00000000 00000000
00000040: 00000000 00000000 00000000 00000000
00000050: 00000000 00000000 00000000 00000000
00000060: 00000000 00000000 00000000 00000000
00000070: 00000000 00000000 00000000 00000000
00000080: 00000000 00000000 00000000 00000000
00000090: 00000000 00000000 00000000 00000000
000000a0: 00000000 00000000 00000000 00000000
000000b0: 00000000 00000000 00000000 00000000
000000c0: 00000000 00000000 00000000 00000000
000000d0: 00000000 00000000 00000000 00000000
000000e0: 00000000 00000000 00000000 00000000
000000f0: 00000000 00000000 00000000 00000000
uboot> pci header 00.18.00
vendor ID = 0x1002
device ID = 0x5c63
command register = 0x0007
status register = 0x0290
revision ID = 0x01
class code = 0x03 (Display controller)
sub class code = 0x00
programming interface = 0x00
cache line = 0x08
latency time = 0x80
header type = 0x80
BIST = 0x00
base address 0 = 0x40000008
base address 1 = 0x50000001
base address 2 = 0x44000000
base address 3 = 0x00000000
base address 4 = 0x00000000
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x0001
sub system ID = 0x0001
expansion ROM base address = 0x00000000
interrupt line = 0xff
interrupt pin = 0x01
min Grant = 0x08
max Latency = 0x00
uboot> pci display 00.18.00 0 40
00000000: 5c631002 02900007 03000001 00808008
00000010: 40000008 50000001 44000000 00000000
00000020: 00000000 00000000 00000000 00010001
00000030: 00000000 00000050 00000000 000801ff
00000040: 00000000 00000000 00000000 00010001
00000050: 06020001 00000000 00205002 4f000210
00000060: 00000200 00000000 00000000 00000000
00000070: 00000000 00000000 00000000 00000000
00000080: 00000005 00000000 00000000 00000000
00000090: 00000000 00000000 00000000 00000000
000000a0: 00000000 00000000 00000000 00000000
000000b0: 00000000 00000000 00000000 00000000
000000c0: 00000000 00000000 00000000 00000000
000000d0: 00000000 00000000 00000000 00000000
000000e0: 00000000 00000000 00000000 00000000
000000f0: 00000000 00000000 00000000 00000000
uboot> pci header 00.18.01
vendor ID = 0x1002
device ID = 0x5c43
command register = 0x0006
status register = 0x0290
revision ID = 0x01
class code = 0x03 (Display controller)
sub class code = 0x80
programming interface = 0x00
cache line = 0x08
latency time = 0x80
header type = 0x00
BIST = 0x00
base address 0 = 0x48000008
base address 1 = 0x4c000000
base address 2 = 0x00000000
base address 3 = 0x00000000
base address 4 = 0x00000000
base address 5 = 0x00000000
cardBus CIS pointer = 0x00000000
sub system vendor ID = 0x0001
sub system ID = 0x0000
expansion ROM base address = 0x00000000
interrupt line = 0xff
interrupt pin = 0x00
min Grant = 0x08
max Latency = 0x00
uboot> pci display 00.18.01 0 40
00000000: 5c431002 02900006 03800001 00008008
00000010: 48000008 4c000000 00000000 00000000
00000020: 00000000 00000000 00000000 00000001
00000030: 00000000 00000050 00000000 000800ff
00000040: 00000000 00000000 00000000 00000000
00000050: 06020001 00000000 00205002 4f000210
00000060: 00000200 00000000 00000000 00000000
00000070: 00000000 00000000 00000000 00000000
00000080: 00000000 00000000 00000000 00000000
00000090: 00000000 00000000 00000000 00000000
000000a0: 00000000 00000000 00000000 00000000
000000b0: 00000000 00000000 00000000 00000000
000000c0: 00000000 00000000 00000000 00000000
000000d0: 00000000 00000000 00000000 00000000
000000e0: 00000000 00000000 00000000 00000000
000000f0: 00000000 00000000 00000000 00000000
=================
Then I prepared to access the following memory addresses:
00.1a.00: BAR0, BAR1, BAR2
uboot> md 0xf0000000 1
f0000000: 0000f000 ....
uboot> md 0x00000008 1
00000008: 00c43004 ..0.
uboot> md 0x00000000 1
00000000: 12c40044 ...D
00.18.00: BAR0, BAR1, BAR2
uboot> md 0x40000008 1
40000008: --> hang
uboot> md 0x50000001 1
50000001: 00000000 ....
uboot> md 0x44000000 1
44000000: 00000000 ....
00.18.00: BAR0, BAR1, BAR2
uboot> md 0x48000008 1
48000008: --> hang
uboot> md 0x4c000000 1
4c000000: 00000000 ....
uboot> md 0x00000000 1
00000000: 12c40044 ...D
But this should be okay, because the card requieres some "BIOS"
initialization code to be run (i believe).
See: http://lists.denx.de/pipermail/u-boot/2004-November/007754.html
Then I added the following lines to u-boot configuration file for
phyCORE-MPC5200B-tiny?:
#define CONFIG_VIDEO
#ifdef CONFIG_VIDEO
#define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
#define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
#define VIDEO_IO_OFFSET CONFIG_PCI_IO_BUS
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VIDEO_LOGO
#define CONFIG_CFB_CONSOLE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CMD_BMP
#endif
(Is VIDEO_IO_OFFSET okay? Is CONFIG_SYS_ISA_IO_BASE_ADDRESS needed?)
When I start the board with that u-boot configuration (I define DEBUG
in ./video/ati_radeon_fb.c) I get the following messages:
CPU: MPC5200B v2.2, Core v1.4 at 400 MHz
Bus 133.333 MHz, IPB 133.333 MHz, PCI 33.333 MHz
Board: phyCORE-MPC5200B-tiny
I2C: ready
DRAM: 64 MB
SP: 0x03e45758
FLASH: 16 MB
PCI: Bus Dev VenId DevId Class Int
00 18 1002 5c63 0300 ff
00 18 1002 5c43 0380 ff
00 1a 1057 5809 0680 00
ATI Radeon video card (1002, 5c63) found @(0:24:0)
videoboot: Booting PCI video card bus 0, function 0, device 24
radeonfb: Found 0k of SDRAM 64 bits wide videoram
Radeon: framebuffer base phy address 0x40000000,MMIO base phy address
0x44000000,framebuffer local base 0xfb400000.
640x480x8 31kHz 59Hz
Cursor Start 4004b000 Pattern Start 4004c000
Then the system hangs again.
I prepare to find the line that is responsible and believe it is
in the file './video/ati_radeon_fb.c'
in the function 'void *video_hw_init(void)'
When the video memory will be accessed.
/* Clear video memory (only visible screen area) */
i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
vm = (unsigned int *) pGD->pciBase;
while (i--)
*vm++ = 0; <-- HERE !!
So, what can I do?
Can somebody help me.
Something to say about the baseboard from the patch set of the current BSP.
There is the device tree changed (pcm030.dts) with this comment:
===========
The regular shipped PCM-973 baseboard has only processor's IRQ0 routed as
INT A to the single slot.
This means, the interrupt routing map must be much smaller to get a correct
behaviour.
The current DTS also contains a second slot definition, that was never present
on this type of baseboard.
-----------------------------------------------------------------------------
Attention: The restriction in available interrupt channels prevent the usage
of multi function PCI devices! Its impossible to use other functions than the
first one, if the other functions are using INT B...INT D for their interrupt.
-----------------------------------------------------------------------------
It seems the PCM-973 supports three additional (not soldered) resistors, to
route the missed INT B... INT D signals to processor's IRQ1...IRQ3. This need
some help from the manufacturer to find resistor's right locations.
--> Unresolved yet.
===========
But the device tree is not the problem at this step, or am I missing something?
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] What to do for a working BIOSEMU and ATI_RADEON_FB environment?
2009-03-28 15:26 [U-Boot] What to do for a working BIOSEMU and ATI_RADEON_FB environment? Markus Rathgeb
@ 2009-03-28 23:25 ` Anatolij Gustschin
2009-03-28 23:35 ` Anatolij Gustschin
2009-03-29 15:21 ` Jon Smirl
1 sibling, 1 reply; 7+ messages in thread
From: Anatolij Gustschin @ 2009-03-28 23:25 UTC (permalink / raw)
To: u-boot
Hi Markus,
Markus Rathgeb wrote:
<snip>
> Then I added the following lines to u-boot configuration file for
> phyCORE-MPC5200B-tiny?:
>
> #define CONFIG_VIDEO
> #ifdef CONFIG_VIDEO
> #define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */
> #define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */
> #define VIDEO_IO_OFFSET CONFIG_PCI_IO_BUS
> #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
> #define CONFIG_VIDEO_SW_CURSOR
> #define CONFIG_VIDEO_LOGO
> #define CONFIG_CFB_CONSOLE
> #define CONFIG_SPLASH_SCREEN
> #define CONFIG_VGA_AS_SINGLE_DEVICE
> #define CONFIG_CMD_BMP
> #endif
>
> (Is VIDEO_IO_OFFSET okay? Is CONFIG_SYS_ISA_IO_BASE_ADDRESS needed?)
VIDEO_IO_OFFSET seems to be Ok. CONFIG_SYS_ISA_IO_BASE_ADDRESS is not
really needed, but ati_radeon_fb.c driver can't be compiled without
it currently.
<snip>
> I prepare to find the line that is responsible and believe it is
> in the file './video/ati_radeon_fb.c'
> in the function 'void *video_hw_init(void)'
> When the video memory will be accessed.
>
> /* Clear video memory (only visible screen area) */
> i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
> vm = (unsigned int *) pGD->pciBase;
> while (i--)
> *vm++ = 0; <-- HERE !!
>
> So, what can I do?
Try to define CONFIG_PCI_IO_BUS and CONFIG_PCI_IO_PHYS in
'include/configs/pcm030.h' as follows:
#define CONFIG_PCI_IO_BUS 0x00000000
#define CONFIG_PCI_IO_PHYS 0x50000000
Best regards,
Anatolij
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] What to do for a working BIOSEMU and ATI_RADEON_FB environment?
2009-03-28 23:25 ` Anatolij Gustschin
@ 2009-03-28 23:35 ` Anatolij Gustschin
2009-03-29 10:00 ` Markus Rathgeb
0 siblings, 1 reply; 7+ messages in thread
From: Anatolij Gustschin @ 2009-03-28 23:35 UTC (permalink / raw)
To: u-boot
Anatolij Gustschin wrote:
> <snip>
>> I prepare to find the line that is responsible and believe it is
>> in the file './video/ati_radeon_fb.c'
>> in the function 'void *video_hw_init(void)'
>> When the video memory will be accessed.
>>
>> /* Clear video memory (only visible screen area) */
>> i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
>> vm = (unsigned int *) pGD->pciBase;
>> while (i--)
>> *vm++ = 0; <-- HERE !!
>>
>> So, what can I do?
>
> Try to define CONFIG_PCI_IO_BUS and CONFIG_PCI_IO_PHYS in
> 'include/configs/pcm030.h' as follows:
>
> #define CONFIG_PCI_IO_BUS 0x00000000
> #define CONFIG_PCI_IO_PHYS 0x50000000
I forgot to mention that you additionally have to define
VIDEO_IO_OFFSET as CONFIG_PCI_IO_PHYS than. So try to use
#define CONFIG_PCI_IO_BUS 0x00000000
#define CONFIG_PCI_IO_PHYS 0x50000000
#define VIDEO_IO_OFFSET CONFIG_PCI_IO_PHYS
Best regards,
Anatolij
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] What to do for a working BIOSEMU and ATI_RADEON_FB environment?
2009-03-28 23:35 ` Anatolij Gustschin
@ 2009-03-29 10:00 ` Markus Rathgeb
2009-03-30 15:07 ` Anatolij Gustschin
0 siblings, 1 reply; 7+ messages in thread
From: Markus Rathgeb @ 2009-03-29 10:00 UTC (permalink / raw)
To: u-boot
Thanks a lot Anatolij!
I have done the following changes:
============
--- include/configs/pcm030.h.org 2009-03-28 18:15:31.000000000 +0100
+++ include/configs/pcm030.h 2009-03-29 10:49:52.000000000 +0200
@@ -156,8 +156,8 @@
#define CONFIG_PCI_MEM_BUS 0x40000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
-#define CONFIG_PCI_IO_BUS 0x50000000
-#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_BUS 0x00000000
+#define CONFIG_PCI_IO_PHYS 0x50000000
#define CONFIG_PCI_IO_SIZE 0x01000000
#define CONFIG_SYS_XLB_PIPELINING 1
@@ -247,8 +247,8 @@
# define CONFIG_SYS_RAMBOOT 1
#endif
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_MONITOR_LEN (1024 << 10) /* Reserve 1024 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------------
@@ -460,4 +460,18 @@
#define OF_SOC "soc5200 at f0000000"
#define OF_STDOUT_PATH "/soc5200 at f0000000/serial@2400"
+#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+ #define CONFIG_BIOSEMU /* x86 bios emulator
for vga bios */
+ #define CONFIG_ATI_RADEON_FB /* use radeon
framebuffer driver */
+ #define VIDEO_IO_OFFSET CONFIG_PCI_IO_PHYS
+ #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+ #define CONFIG_VIDEO_SW_CURSOR
+ #define CONFIG_VIDEO_LOGO
+ #define CONFIG_CFB_CONSOLE
+ #define CONFIG_SPLASH_SCREEN
+ #define CONFIG_VGA_AS_SINGLE_DEVICE
+ #define CONFIG_CMD_BMP
+#endif
+
#endif /* __CONFIG_H */
============
So, I see now the u-boot on the monitor. More tests will follow.
I changed also CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_MALLOC_LEN.
I do not know, what are the minimum values that are working.
But 128 and 256 for CONFIG_SYS_MALLOC_LEN are to small and with the
above values it is working - so it is okay for me.
Where can I read more about that options (and the options for video)?
Are there documentations or should I read the source code (that is no
problem, but it will be cost a lot of time)?
Thanks again.
Greats,
Markus
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] What to do for a working BIOSEMU and ATI_RADEON_FB environment?
2009-03-28 15:26 [U-Boot] What to do for a working BIOSEMU and ATI_RADEON_FB environment? Markus Rathgeb
2009-03-28 23:25 ` Anatolij Gustschin
@ 2009-03-29 15:21 ` Jon Smirl
2009-03-29 15:23 ` Jon Smirl
1 sibling, 1 reply; 7+ messages in thread
From: Jon Smirl @ 2009-03-29 15:21 UTC (permalink / raw)
To: u-boot
On Sat, Mar 28, 2009 at 11:26 AM, Markus Rathgeb <maggu2810@web.de> wrote:
> Hi!
>
> I own a phytec's pcm-030 with the shipped baseboard pcm-973.
> I would like to use a radeon 9200 pci card in the slot on the baseboard.
>
> I have done a git checkout of the u-boot and I am using the 'board
> support patch for phyCORE-MPC5200B-tiny?' from the mailing list.
>
> To provide the necessary informations here some outputs the u-boot command line:
>
> =================
> uboot> pci
> Scanning PCI devices on bus 0
> BusDevFun ?VendorId ? DeviceId ? Device Class ? ? ? Sub-Class
> _____________________________________________________________
> 00.18.00 ? 0x1002 ? ? 0x5c63 ? ? Display controller ? ? ?0x00
> 00.18.01 ? 0x1002 ? ? 0x5c43 ? ? Display controller ? ? ?0x80
> 00.1a.00 ? 0x1057 ? ? 0x5809 ? ? Bridge device ? ? ? ? ? 0x80
>
> uboot> pci header 00.1a.00
> ?vendor ID = ? ? ? ? ? ? ? ? ? 0x1057
> ?device ID = ? ? ? ? ? ? ? ? ? 0x5809
> ?command register = ? ? ? ? ? ?0x0006
> ?status register = ? ? ? ? ? ? 0x22a0
> ?revision ID = ? ? ? ? ? ? ? ? 0x00
> ?class code = ? ? ? ? ? ? ? ? ?0x06 (Bridge device)
> ?sub class code = ? ? ? ? ? ? ?0x80
> ?programming interface = ? ? ? 0x00
> ?cache line = ? ? ? ? ? ? ? ? ?0x08
> ?latency time = ? ? ? ? ? ? ? ?0xf8
> ?header type = ? ? ? ? ? ? ? ? 0x00
> ?BIST = ? ? ? ? ? ? ? ? ? ? ? ?0x00
> ?base address 0 = ? ? ? ? ? ? ?0xf0000000
> ?base address 1 = ? ? ? ? ? ? ?0x00000008
> ?base address 2 = ? ? ? ? ? ? ?0x00000000
> ?base address 3 = ? ? ? ? ? ? ?0x00000000
> ?base address 4 = ? ? ? ? ? ? ?0x00000000
> ?base address 5 = ? ? ? ? ? ? ?0x00000000
> ?cardBus CIS pointer = ? ? ? ? 0x00000000
> ?sub system vendor ID = ? ? ? ?0x0000
> ?sub system ID = ? ? ? ? ? ? ? 0x0000
> ?expansion ROM base address = ?0x00000000
> ?interrupt line = ? ? ? ? ? ? ?0x00
> ?interrupt pin = ? ? ? ? ? ? ? 0x00
> ?min Grant = ? ? ? ? ? ? ? ? ? 0x00
> ?max Latency = ? ? ? ? ? ? ? ? 0x00
>
> uboot> pci display 00.1a.00 0 40
> 00000000: 58091057 22a00006 06800000 0000f808
> 00000010: f0000000 00000008 00000000 00000000
> 00000020: 00000000 00000000 00000000 00000000
> 00000030: 00000000 00000000 00000000 00000000
> 00000040: 00000000 00000000 00000000 00000000
> 00000050: 00000000 00000000 00000000 00000000
> 00000060: 00000000 00000000 00000000 00000000
> 00000070: 00000000 00000000 00000000 00000000
> 00000080: 00000000 00000000 00000000 00000000
> 00000090: 00000000 00000000 00000000 00000000
> 000000a0: 00000000 00000000 00000000 00000000
> 000000b0: 00000000 00000000 00000000 00000000
> 000000c0: 00000000 00000000 00000000 00000000
> 000000d0: 00000000 00000000 00000000 00000000
> 000000e0: 00000000 00000000 00000000 00000000
> 000000f0: 00000000 00000000 00000000 00000000
>
> uboot> pci header 00.18.00
> ?vendor ID = ? ? ? ? ? ? ? ? ? 0x1002
> ?device ID = ? ? ? ? ? ? ? ? ? 0x5c63
> ?command register = ? ? ? ? ? ?0x0007
> ?status register = ? ? ? ? ? ? 0x0290
> ?revision ID = ? ? ? ? ? ? ? ? 0x01
> ?class code = ? ? ? ? ? ? ? ? ?0x03 (Display controller)
> ?sub class code = ? ? ? ? ? ? ?0x00
> ?programming interface = ? ? ? 0x00
> ?cache line = ? ? ? ? ? ? ? ? ?0x08
> ?latency time = ? ? ? ? ? ? ? ?0x80
> ?header type = ? ? ? ? ? ? ? ? 0x80
> ?BIST = ? ? ? ? ? ? ? ? ? ? ? ?0x00
> ?base address 0 = ? ? ? ? ? ? ?0x40000008
> ?base address 1 = ? ? ? ? ? ? ?0x50000001
> ?base address 2 = ? ? ? ? ? ? ?0x44000000
> ?base address 3 = ? ? ? ? ? ? ?0x00000000
> ?base address 4 = ? ? ? ? ? ? ?0x00000000
> ?base address 5 = ? ? ? ? ? ? ?0x00000000
> ?cardBus CIS pointer = ? ? ? ? 0x00000000
> ?sub system vendor ID = ? ? ? ?0x0001
> ?sub system ID = ? ? ? ? ? ? ? 0x0001
> ?expansion ROM base address = ?0x00000000
> ?interrupt line = ? ? ? ? ? ? ?0xff
> ?interrupt pin = ? ? ? ? ? ? ? 0x01
> ?min Grant = ? ? ? ? ? ? ? ? ? 0x08
> ?max Latency = ? ? ? ? ? ? ? ? 0x00
>
> uboot> pci display 00.18.00 0 40
> 00000000: 5c631002 02900007 03000001 00808008
> 00000010: 40000008 50000001 44000000 00000000
> 00000020: 00000000 00000000 00000000 00010001
> 00000030: 00000000 00000050 00000000 000801ff
> 00000040: 00000000 00000000 00000000 00010001
> 00000050: 06020001 00000000 00205002 4f000210
> 00000060: 00000200 00000000 00000000 00000000
> 00000070: 00000000 00000000 00000000 00000000
> 00000080: 00000005 00000000 00000000 00000000
> 00000090: 00000000 00000000 00000000 00000000
> 000000a0: 00000000 00000000 00000000 00000000
> 000000b0: 00000000 00000000 00000000 00000000
> 000000c0: 00000000 00000000 00000000 00000000
> 000000d0: 00000000 00000000 00000000 00000000
> 000000e0: 00000000 00000000 00000000 00000000
> 000000f0: 00000000 00000000 00000000 00000000
>
> uboot> pci header 00.18.01
> ?vendor ID = ? ? ? ? ? ? ? ? ? 0x1002
> ?device ID = ? ? ? ? ? ? ? ? ? 0x5c43
> ?command register = ? ? ? ? ? ?0x0006
> ?status register = ? ? ? ? ? ? 0x0290
> ?revision ID = ? ? ? ? ? ? ? ? 0x01
> ?class code = ? ? ? ? ? ? ? ? ?0x03 (Display controller)
> ?sub class code = ? ? ? ? ? ? ?0x80
> ?programming interface = ? ? ? 0x00
> ?cache line = ? ? ? ? ? ? ? ? ?0x08
> ?latency time = ? ? ? ? ? ? ? ?0x80
> ?header type = ? ? ? ? ? ? ? ? 0x00
> ?BIST = ? ? ? ? ? ? ? ? ? ? ? ?0x00
> ?base address 0 = ? ? ? ? ? ? ?0x48000008
> ?base address 1 = ? ? ? ? ? ? ?0x4c000000
> ?base address 2 = ? ? ? ? ? ? ?0x00000000
> ?base address 3 = ? ? ? ? ? ? ?0x00000000
> ?base address 4 = ? ? ? ? ? ? ?0x00000000
> ?base address 5 = ? ? ? ? ? ? ?0x00000000
> ?cardBus CIS pointer = ? ? ? ? 0x00000000
> ?sub system vendor ID = ? ? ? ?0x0001
> ?sub system ID = ? ? ? ? ? ? ? 0x0000
> ?expansion ROM base address = ?0x00000000
> ?interrupt line = ? ? ? ? ? ? ?0xff
> ?interrupt pin = ? ? ? ? ? ? ? 0x00
> ?min Grant = ? ? ? ? ? ? ? ? ? 0x08
> ?max Latency = ? ? ? ? ? ? ? ? 0x00
>
> uboot> pci display 00.18.01 0 40
> 00000000: 5c431002 02900006 03800001 00008008
> 00000010: 48000008 4c000000 00000000 00000000
> 00000020: 00000000 00000000 00000000 00000001
> 00000030: 00000000 00000050 00000000 000800ff
> 00000040: 00000000 00000000 00000000 00000000
> 00000050: 06020001 00000000 00205002 4f000210
> 00000060: 00000200 00000000 00000000 00000000
> 00000070: 00000000 00000000 00000000 00000000
> 00000080: 00000000 00000000 00000000 00000000
> 00000090: 00000000 00000000 00000000 00000000
> 000000a0: 00000000 00000000 00000000 00000000
> 000000b0: 00000000 00000000 00000000 00000000
> 000000c0: 00000000 00000000 00000000 00000000
> 000000d0: 00000000 00000000 00000000 00000000
> 000000e0: 00000000 00000000 00000000 00000000
> 000000f0: 00000000 00000000 00000000 00000000
> =================
>
> Then I prepared to access the following memory addresses:
>
> 00.1a.00: BAR0, BAR1, BAR2
> uboot> md 0xf0000000 1
> f0000000: 0000f000 ? ?....
> uboot> md 0x00000008 1
> 00000008: 00c43004 ? ?..0.
> uboot> md 0x00000000 1
> 00000000: 12c40044 ? ?...D
>
> 00.18.00: BAR0, BAR1, BAR2
> uboot> md 0x40000008 1
> 40000008: --> hang
> uboot> md 0x50000001 1
> 50000001: 00000000 ? ?....
> uboot> md 0x44000000 1
> 44000000: 00000000 ? ?....
>
> 00.18.00: BAR0, BAR1, BAR2
> uboot> md 0x48000008 1
> 48000008: --> hang
> uboot> md 0x4c000000 1
> 4c000000: 00000000 ? ?....
> uboot> md 0x00000000 1
> 00000000: 12c40044 ? ?...D
>
> But this should be okay, because the card requieres some ?"BIOS"
> initialization code to be run (i believe).
> See: http://lists.denx.de/pipermail/u-boot/2004-November/007754.html
>
>
> Then I added the following lines to u-boot configuration file for
> phyCORE-MPC5200B-tiny?:
>
> #define CONFIG_VIDEO
> #ifdef CONFIG_VIDEO
> ? ? ? ?#define CONFIG_BIOSEMU ? ? ? ? ? ? ? ? ?/* x86 bios emulator for vga bios */
> ? ? ? ?#define CONFIG_ATI_RADEON_FB ? ? ? ? ? ?/* use radeon framebuffer driver */
> ? ? ? ?#define VIDEO_IO_OFFSET ? ? ? ? ? ? ? ? CONFIG_PCI_IO_BUS
> ? ? ? ?#define CONFIG_SYS_ISA_IO_BASE_ADDRESS ?VIDEO_IO_OFFSET
> ? ? ? ?#define CONFIG_VIDEO_SW_CURSOR
> ? ? ? ?#define CONFIG_VIDEO_LOGO
> ? ? ? ?#define CONFIG_CFB_CONSOLE
> ? ? ? ?#define CONFIG_SPLASH_SCREEN
> ? ? ? ?#define CONFIG_VGA_AS_SINGLE_DEVICE
> ? ? ? ?#define CONFIG_CMD_BMP
> #endif
>
> (Is VIDEO_IO_OFFSET okay? Is CONFIG_SYS_ISA_IO_BASE_ADDRESS needed?)
>
> When I start the board with that u-boot configuration (I define DEBUG
> in ./video/ati_radeon_fb.c) I get the following messages:
>
> CPU: ? MPC5200B v2.2, Core v1.4 at 400 MHz
> ? ? ? Bus 133.333 MHz, IPB 133.333 MHz, PCI 33.333 MHz
> Board: phyCORE-MPC5200B-tiny
> I2C: ? ready
> DRAM: ?64 MB
> SP: ? ?0x03e45758
> FLASH: 16 MB
> PCI: ? Bus Dev VenId DevId Class Int
> ? ? ? ?00 ?18 ?1002 ?5c63 ?0300 ?ff
> ? ? ? ?00 ?18 ?1002 ?5c43 ?0380 ?ff
> ? ? ? ?00 ?1a ?1057 ?5809 ?0680 ?00
> ATI Radeon video card (1002, 5c63) found @(0:24:0)
> videoboot: Booting PCI video card bus 0, function 0, device 24
> radeonfb: Found 0k of SDRAM 64 bits wide videoram
> Radeon: framebuffer base phy address 0x40000000,MMIO base phy address
> 0x44000000,framebuffer local base 0xfb400000.
> 640x480x8 31kHz 59Hz
> Cursor Start 4004b000 Pattern Start 4004c000
>
> Then the system hangs again.
>
> I prepare to find the line that is responsible and believe it is
> in the file './video/ati_radeon_fb.c'
> in the function 'void *video_hw_init(void)'
> When the video memory will be accessed.
>
> ? ? ? ?/* Clear video memory (only visible screen area) */
> ? ? ? ?i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
> ? ? ? ?vm = (unsigned int *) pGD->pciBase;
> ? ? ? ?while (i--)
> ? ? ? ? ? ? ? ?*vm++ = 0; <-- HERE !!
This is hanging on a write to the PCI bus. Print out the vm pointer
and make sure it is pointing to an area that is mapped into memory.
To investigate further exit the code before trying to write. Use
u-boot commands to then probe the memory and make sure everything is
setup. Running the video BIOS may have reprogrammed the BARs.
I've also noticed that the u-boot code is not setting up the PCI
controller to cause a machine exception on a read/write to an invalid
address. Or maybe the machine check is happening and u-boot is
hanging when it tries to handle it. You may be getting a machine check
on this write, and then u-boot goes off in the weeds trying to process
it.
I don't have a PCI capable baseboard so I can't try this.
>
> So, what can I do?
> Can somebody help me.
>
>
>
>
>
> Something to say about the baseboard from the patch set of the current BSP.
> There is the device tree changed (pcm030.dts) with this comment:
>
> ===========
> The regular shipped PCM-973 baseboard has only processor's IRQ0 routed as
> INT A to the single slot.
>
> This means, the interrupt routing map must be much smaller to get a correct
> behaviour.
>
> The current DTS also contains a second slot definition, that was never present
> on this type of baseboard.
>
> -----------------------------------------------------------------------------
> Attention: The restriction in available interrupt channels prevent the usage
> of multi function PCI devices! Its impossible to use other functions than the
> first one, if the other functions are using INT B...INT D for their interrupt.
> -----------------------------------------------------------------------------
>
> It seems the PCM-973 supports three additional (not soldered) resistors, to
> route the missed INT B... INT D signals to processor's IRQ1...IRQ3. This need
> some help from the manufacturer to find resistor's right locations.
> ?--> Unresolved yet.
> ===========
>
> But the device tree is not the problem at this step, or am I missing something?
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
--
Jon Smirl
jonsmirl at gmail.com
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] What to do for a working BIOSEMU and ATI_RADEON_FB environment?
2009-03-29 15:21 ` Jon Smirl
@ 2009-03-29 15:23 ` Jon Smirl
0 siblings, 0 replies; 7+ messages in thread
From: Jon Smirl @ 2009-03-29 15:23 UTC (permalink / raw)
To: u-boot
2009/3/29 Jon Smirl <jonsmirl@gmail.com>:
> On Sat, Mar 28, 2009 at 11:26 AM, Markus Rathgeb <maggu2810@web.de> wrote:
>> Hi!
>>
>> I own a phytec's pcm-030 with the shipped baseboard pcm-973.
>> I would like to use a radeon 9200 pci card in the slot on the baseboard.
BTW what you are doing will definitely work if you can get it
debugged. I have used a similar setup on my Efika but it doesn't run
u-boot.
--
Jon Smirl
jonsmirl at gmail.com
^ permalink raw reply [flat|nested] 7+ messages in thread
* [U-Boot] What to do for a working BIOSEMU and ATI_RADEON_FB environment?
2009-03-29 10:00 ` Markus Rathgeb
@ 2009-03-30 15:07 ` Anatolij Gustschin
0 siblings, 0 replies; 7+ messages in thread
From: Anatolij Gustschin @ 2009-03-30 15:07 UTC (permalink / raw)
To: u-boot
Markus Rathgeb wrote:
> -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
> -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
> +#define CONFIG_SYS_MONITOR_LEN (1024 << 10) /* Reserve 1024 kB for Monitor */
> +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
<snip>
> I changed also CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_MALLOC_LEN.
> I do not know, what are the minimum values that are working.
> But 128 and 256 for CONFIG_SYS_MALLOC_LEN are to small and with the
> above values it is working - so it is okay for me.
CONFIG_SYS_MONITOR_LEN could probably be 384 kB or 512 kB. It
depends on included (configured) drivers and U-Boot commands.
1024 kB is too big here, i think. 1024 kB for CONFIG_SYS_MALLOC_LEN
is OK.
> Where can I read more about that options (and the options for video)?
> Are there documentations or should I read the source code (that is no
> problem, but it will be cost a lot of time)?
u-boot/README contains a description of these options. Video
related options are described there too. README also describes
"videomode" U-Boot environment variable for selection of display
resolution and color depth.
Best regards,
Anatolij
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2009-03-30 15:07 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-03-28 15:26 [U-Boot] What to do for a working BIOSEMU and ATI_RADEON_FB environment? Markus Rathgeb
2009-03-28 23:25 ` Anatolij Gustschin
2009-03-28 23:35 ` Anatolij Gustschin
2009-03-29 10:00 ` Markus Rathgeb
2009-03-30 15:07 ` Anatolij Gustschin
2009-03-29 15:21 ` Jon Smirl
2009-03-29 15:23 ` Jon Smirl
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