[U-Boot] [PATCH 1/2] rtl8169: fix cache coherency problem

[U-Boot] [PATCH 1/2] rtl8169: fix cache coherency problem

[Yoshihiro Shimoda]

Fix the problem that cannot access actual data when CPU data cache enabled.

Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
---
 drivers/net/rtl8169.c |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletions(-)

diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index e9f6391..b441ec4 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -420,6 +420,8 @@ static int rtl_recv(struct eth_device *dev)
 	ioaddr = dev->iobase;

 	cur_rx = tpc->cur_rx;
+	flush_cache((unsigned long)&tpc->RxDescArray[cur_rx],
+			sizeof(struct RxDesc));
 	if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) {
 		if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) {
 			unsigned char rxdata[RX_BUF_LEN];
@@ -437,6 +439,8 @@ static int rtl_recv(struct eth_device *dev)
 					cpu_to_le32(OWNbit + RX_BUF_SIZE);
 			tpc->RxDescArray[cur_rx].buf_addr =
 				cpu_to_le32((unsigned long)tpc->RxBufferRing[cur_rx]);
+			flush_cache((unsigned long)tpc->RxBufferRing[cur_rx],
+					RX_BUF_SIZE);
 		} else {
 			puts("Error Rx");
 		}
@@ -478,6 +482,7 @@ static int rtl_send(struct eth_device *dev, volatile void *packet, int length)
 	/* point to the current txb incase multiple tx_rings are used */
 	ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
 	memcpy(ptxb, (char *)packet, (int)length);
+	flush_cache((unsigned long)ptxb, length);

 	while (len < ETH_ZLEN)
 		ptxb[len++] = '\0';
@@ -497,7 +502,10 @@ static int rtl_send(struct eth_device *dev, volatile void *packet, int length)

 	tpc->cur_tx++;
 	to = currticks() + TX_TIMEOUT;
-	while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
+	do {
+		flush_cache((unsigned long)&tpc->TxDescArray[entry],
+				sizeof(struct TxDesc));
+	} while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit)
 				&& (currticks() < to));	/* wait */

 	if (currticks() >= to) {
@@ -639,6 +647,7 @@ static void rtl8169_init_ring(struct eth_device *dev)
 		tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
 		tpc->RxDescArray[i].buf_addr =
 			cpu_to_le32((unsigned long)tpc->RxBufferRing[i]);
+		flush_cache((unsigned long)tpc->RxBufferRing[i], RX_BUF_SIZE);
 	}

 #ifdef DEBUG_RTL8169
-- 
1.5.5

[U-Boot] [PATCH 1/2] rtl8169: fix cache coherency problem

[Wolfgang Denk]

Dear Ben,

In message <49A4D6BC.3010608@renesas.com> Yoshihiro Shimoda wrote:
> Fix the problem that cannot access actual data when CPU data cache enabled.
> 
> Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
> ---
>  drivers/net/rtl8169.c |   11 ++++++++++-
>  1 files changed, 10 insertions(+), 1 deletions(-)

I did not see any comments on this?

Ditto for the other patch:

http://article.gmane.org/gmane.comp.boot-loaders.u-boot/55286

?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Do not follow where the path may lead....go instead where there is no
path and leave a trail.

[U-Boot] [PATCH 1/2] rtl8169: fix cache coherency problem

[Nobuhiro Iwamatsu]

Wolfgang Denk wrote:
> Dear Ben,
> 
> In message <49A4D6BC.3010608@renesas.com> Yoshihiro Shimoda wrote:
>> Fix the problem that cannot access actual data when CPU data cache enabled.
>>
>> Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
>> ---
>>  drivers/net/rtl8169.c |   11 ++++++++++-
>>  1 files changed, 10 insertions(+), 1 deletions(-)
> 
> I did not see any comments on this?
> 
> Ditto for the other patch:
> 
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/55286
> 

Tested-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>

I checked and tested these. Work file.

Best regards,
  Nobuhiro

[U-Boot] [PATCH 1/2] rtl8169: fix cache coherency problem

[Wolfgang Denk]

Dear Wolfgang Denk,

In message <20090403215440.D212983797DC@gemini.denx.de> I wrote:
> Dear Ben,
> 
> In message <49A4D6BC.3010608@renesas.com> Yoshihiro Shimoda wrote:
> > Fix the problem that cannot access actual data when CPU data cache enabled.
> > 
> > Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
> > ---
> >  drivers/net/rtl8169.c |   11 ++++++++++-
> >  1 files changed, 10 insertions(+), 1 deletions(-)
> 
> I did not see any comments on this?
> 
> Ditto for the other patch:
> 
> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/55286
> 
> ?

Any comments?

If you don't have time, I can apply this directly.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Well, the way I see it, logic is only a way of being ignorant by num-
bers.                                 - Terry Pratchett, _Small Gods_

[U-Boot] [PATCH 1/2] rtl8169: fix cache coherency problem

[Ben Warren]

Hi Wolfgang,

Wolfgang Denk wrote:
> Dear Wolfgang Denk,
>
> In message <20090403215440.D212983797DC@gemini.denx.de> I wrote:
>   
>> Dear Ben,
>>
>> In message <49A4D6BC.3010608@renesas.com> Yoshihiro Shimoda wrote:
>>     
>>> Fix the problem that cannot access actual data when CPU data cache enabled.
>>>
>>> Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
>>> ---
>>>  drivers/net/rtl8169.c |   11 ++++++++++-
>>>  1 files changed, 10 insertions(+), 1 deletions(-)
>>>       
>> I did not see any comments on this?
>>
>> Ditto for the other patch:
>>
>> http://article.gmane.org/gmane.comp.boot-loaders.u-boot/55286
>>
>> ?
>>     
>
> Any comments?
>
> If you don't have time, I can apply this directly.
>
> Best regards,
>
> Wolfgang Denk
>
>   
This one also looks fine.  Please apply directly.

thanks,
Ben

[U-Boot] [PATCH 1/2] rtl8169: fix cache coherency problem

[Wolfgang Denk]

Dear Yoshihiro Shimoda,

In message <49A4D6BC.3010608@renesas.com> you wrote:
> Fix the problem that cannot access actual data when CPU data cache enabled.
> 
> Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
> ---
>  drivers/net/rtl8169.c |   11 ++++++++++-
>  1 files changed, 10 insertions(+), 1 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I express preference for a chronological  sequence  of  events  which
precludes a violence.   - Terry Pratchett, _The Dark Side of the Sun_