From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerry Van Baren Date: Thu, 30 Apr 2009 13:06:41 -0400 Subject: [U-Boot] [PATCH] include/ns16550.h: Unify structure declaration for registers In-Reply-To: References: <1238769946-30370-1-git-send-email-dzu@denx.de> <49F2657D.5080706@ruby.dti.ne.jp> <49F5C0AA.2000401@ruby.dti.ne.jp> <49F8A196.60202@pobox.com> <49F99F2A.1070603@ge.com> Message-ID: <49F9DAA1.6070400@ge.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Detlev Zundel wrote: > Hi Jerry, > >> Detlev Zundel wrote: >>> Hello Shinya, >>> >>>> Detlev Zundel wrote: >>>>> As I said, I understand now why there were different data-types involved >>>>> although this was kind of non-obvious. So I take it, you had a working >>>>> configuration with REG_SIZE = 4, correct? >>>> I might be unclear. I used to use REG_SIZE = -16, as 16550 registers >>>> are located at 0, +0x10, +0x20, ..., . >> 16 byte stride. That is seriously odd. > > Isn't this "natural" for a 64-bitter? Yes. I wasn't thinking of the processor as 64 bits. [snip] >> >> It sounds like Shinya has some pretty odd (read "broken") hardware >> that is decoding the registers with a 16 byte stride, although his >> example above shows a 4 byte stride (less broken). > > It's a 16-byte stride, although the register shows up neither at the > top, nor at the low end, but "slightly to the left", i.e. at offset 0x3 > ;) That is the big piece I didn't understand. Thanks and sorry for the noise. [snip] Best regards gvb