From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michael Roth Date: Mon, 04 May 2009 14:41:06 +0200 Subject: [U-Boot] [PATCH V2] arm: timer and interrupt init rework In-Reply-To: <20090502212624.AD01183420E8@gemini.denx.de> References: <1240047101-6787-1-git-send-email-plagnioj@jcrosoft.com> <1241216732-13765-1-git-send-email-plagnioj@jcrosoft.com> <49FB7F1A.6090101@googlemail.com> <20090501232305.GI3291@game.jcrosoft.org> <20090502125019.CD06F83420E8@gemini.denx.de> <20090502200026.GL25959@game.jcrosoft.org> <20090502212624.AD01183420E8@gemini.denx.de> Message-ID: <49FEE262.8030401@nessie.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Wolfgang Denk schrieb: > What is "slow clock"? On (some) ARM SoC there are two oscillators: A "slow" free running oscillator typically with a dedicated 32 kHz crystal and the "main" oscillator with a dedicated crystal in the MHz range. The processor starts with the slow slock enabled and init code needs to set up PLLs and muxes etc. to enable the main oscillator and switch to derived clocks like master clock, cpu clock, IO clock and so on.