[U-Boot] [PATCH 3/7] fec_imx27: driver for FEC ethernet controller on i.MX27

[Ben Warren <biggerbadderben@gmail.com>]

Hi Ilya,

Thanks for making all the improvements:

Ilya Yanok wrote:
> Signed-off-by: Ilya Yanok <yanok@emcraft.com>
> ---
>  cpu/arm926ejs/mx27/generic.c |   10 +
>  drivers/net/Makefile         |    1 +
>  drivers/net/fec_imx27.c      |  705 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/net/fec_imx27.h      |  302 ++++++++++++++++++
>  include/netdev.h             |    1 +
>  5 files changed, 1019 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/net/fec_imx27.c
>  create mode 100644 drivers/net/fec_imx27.h
>
>   
Naive question: Is this FEC truly unique to the iMX27?  If not you 
should pick a more generic name.

<snip>
> diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
> index 850d5e6..e820d94 100644
> --- a/cpu/arm926ejs/mx27/generic.c
> +++ b/cpu/arm926ejs/mx27/generic.c
> @@ -20,6 +20,7 @@
>  
>  #include <common.h>
>  #include <div64.h>
> +#include <netdev.h>
>  #include <asm/io.h>
>  #include <asm/arch/imx-regs.h>
>  
> @@ -159,6 +160,15 @@ int print_cpuinfo (void)
>  }
>  #endif
>  
> +int cpu_eth_init(bd_t *bis)
> +{
> +#if defined(CONFIG_FEC_IMX27)
> +	return fecimx27_initialize(bis);
> +#else
> +	return 0;
> +#endif
> +}
> +
>  void imx_gpio_mode(int gpio_mode)
>  {
>  	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index a360a50..ac68beb 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -34,6 +34,7 @@ COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
>  COBJS-$(CONFIG_TULIP) += dc2114x.o
>  COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
>  COBJS-$(CONFIG_DNET) += dnet.o
> +COBJS-$(CONFIG_FEC_IMX27) += fec_imx27.o
>   
Please keep this sorted alphabetically.
>  COBJS-$(CONFIG_E1000) += e1000.o
>  COBJS-$(CONFIG_EEPRO100) += eepro100.o
>  COBJS-$(CONFIG_ENC28J60) += enc28j60.o
> diff --git a/drivers/net/fec_imx27.c b/drivers/net/fec_imx27.c
> new file mode 100644
> index 0000000..4ade348
> --- /dev/null
> +++ b/drivers/net/fec_imx27.c
> @@ -0,0 +1,705 @@
> +/*
> + * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
> + * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
> + * (C) Copyright 2008 Armadeus Systems nc
> + * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
> + * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <net.h>
> +#include <miiphy.h>
> +#include "fec_imx27.h"
> +
> +#include <asm/arch/clock.h>
> +#include <asm/arch/imx-regs.h>
> +#include <asm/io.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifndef CONFIG_MII
> +#error "CONFIG_MII has to be defined!"
> +#endif
> +
> +#undef DEBUG
> +
> +struct nbuf {
> +	uint8_t data[1500];	/**< actual data */
>   
I think 'u8' and friends are more commonly used in U-boot, but am not 
too fussy about this.
> +	int length;		/**< actual length */
> +	int used;		/**< buffer in use or not */
> +	uint8_t head[16];	/**< MAC header(6 + 6 + 2) + 2(aligned) */
> +};
> +
> +struct fec_priv gfec = {
> +	.eth       = (struct ethernet_regs *)IMX_FEC_BASE,
> +	.xcv_type  = MII100,
> +	.rbd_base  = NULL,
> +	.rbd_index = 0,
> +	.tbd_base  = NULL,
> +	.tbd_index = 0,
> +	.bd        = NULL,
> +};
> +
> +/*
> + * MII-interface related functions
> + */
> +static int fec_miiphy_read(char *dev, uint8_t phyAddr, uint8_t regAddr,
> +		uint16_t *retVal)
> +{
> +	struct eth_device *edev = eth_get_dev_by_name(dev);
> +	struct fec_priv *fec = (struct fec_priv *)edev->priv;
> +
> +	uint32_t reg;		/* convenient holder for the PHY register */
> +	uint32_t phy;		/* convenient holder for the PHY */
> +	uint32_t start;
> +
> +	/*
> +	 * reading from any PHY's register is done by properly
> +	 * programming the FEC's MII data register.
> +	 */
> +	writel(FEC_IEVENT_MII, &fec->eth->ievent);
> +	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
> +	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
> +
> +	writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
> +			phy | reg, &fec->eth->mii_data);
> +
> +	/*
> +	 * wait for the related interrupt
> +	 */
> +	start = get_timer_masked();
> +	while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
> +		if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
> +			printf("Read MDIO failed...\n");
> +			return -1;
> +		}
> +	}
> +
> +	/*
> +	 * clear mii interrupt bit
> +	 */
> +	writel(FEC_IEVENT_MII, &fec->eth->ievent);
> +
> +	/*
> +	 * it's now safe to read the PHY's register
> +	 */
> +	*retVal = readl(&fec->eth->mii_data);
> +	debug("fec_miiphy_read: phy: %02x reg:%02x val:%#x\n", phyAddr,
> +			regAddr, *retVal);
> +	return 0;
> +}
> +
> +static int fec_miiphy_write(char *dev, uint8_t phyAddr, uint8_t regAddr,
> +		uint16_t data)
> +{
> +	struct eth_device *edev = eth_get_dev_by_name(dev);
> +	struct fec_priv *fec = (struct fec_priv *)edev->priv;
> +
> +	uint32_t reg;		/* convenient holder for the PHY register */
> +	uint32_t phy;		/* convenient holder for the PHY */
> +	uint32_t start;
> +
> +	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
> +	phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
> +
> +	writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
> +		FEC_MII_DATA_TA | phy | reg | data, &fec->eth->mii_data);
> +
> +	/*
> +	 * wait for the MII interrupt
> +	 */
> +	start = get_timer_masked();
> +	while (!(readl(&fec->eth->ievent) & FEC_IEVENT_MII)) {
> +		if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
> +			printf("Write MDIO failed...\n");
> +			return -1;
> +		}
> +	}
> +
> +	/*
> +	 * clear MII interrupt bit
> +	 */
> +	writel(FEC_IEVENT_MII, &fec->eth->ievent);
> +	debug("fec_miiphy_write: phy: %02x reg:%02x val:%#x\n", phyAddr,
> +			regAddr, data);
> +
> +	return 0;
> +}
> +
> +static int miiphy_restart_aneg(struct eth_device *dev)
> +{
> +	/*
> +	 * Wake up from sleep if necessary
> +	 * Reset PHY, then delay 300ns
> +	 */
> +	miiphy_write(dev->name, 0, PHY_MIPGSR, 0x00FF);
> +	miiphy_write(dev->name, 0, PHY_BMCR, PHY_BMCR_RESET);
> +	udelay(1000);
> +
> +	/*
> +	 * Set the auto-negotiation advertisement register bits
> +	 */
> +	miiphy_write(dev->name, 0, PHY_ANAR, 0x1e0);
> +	miiphy_write(dev->name, 0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
> +
> +	return 0;
> +}
> +
> +static int miiphy_wait_aneg(struct eth_device *dev)
> +{
> +	uint32_t start;
> +	uint16_t status;
> +
> +	/*
> +	 * Wait for AN completion
> +	 */
> +	start = get_timer_masked(); /* get_time_ns(); */
> +	do {
> +		if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
> +			printf("%s: Autonegotiation timeout\n", dev->name);
> +			return -1;
> +		}
> +
> +		if (miiphy_read(dev->name, 0, PHY_BMSR, &status)) {
> +			printf("%s: Autonegotiation failed. status: 0x%04x\n",
> +					dev->name, status);
> +			return -1;
> +		}
> +	} while (!(status & PHY_BMSR_LS));
> +
> +	return 0;
> +}
> +static int fec_rx_task_enable(struct fec_priv *fec)
> +{
> +	writel(1 << 24, &fec->eth->r_des_active);
> +	return 0;
> +}
> +
> +static int fec_rx_task_disable(struct fec_priv *fec)
> +{
> +	return 0;
> +}
> +
> +static int fec_tx_task_enable(struct fec_priv *fec)
> +{
> +	writel(1 << 24, &fec->eth->x_des_active);
> +	return 0;
> +}
> +
> +static int fec_tx_task_disable(struct fec_priv *fec)
> +{
> +	return 0;
> +}
> +
> +/**
> + * Initialize receive task's buffer descriptors
> + * @param[in] fec all we know about the device yet
> + * @param[in] count receive buffer count to be allocated
> + * @param[in] size size of each receive buffer
> + * @return 0 on success
> + *
> + * For this task we need additional memory for the data buffers. And each
> + * data buffer requires some alignment. Thy must be aligned to a specific
> + * boundary each (DB_DATA_ALIGNMENT).
> + */
> +static int fec_rbd_init(struct fec_priv *fec, int count, int size, int once)
> +{
> +	int ix;
> +	uint32_t p = 0;
> +
> +	if (!once) {
> +		/* reserve data memory and consider alignment */
> +		p = (uint32_t)malloc(size * count + DB_DATA_ALIGNMENT);
> +		memset((void *)p, 0, size * count + DB_DATA_ALIGNMENT);
> +		p += DB_DATA_ALIGNMENT-1;
> +		p &= ~(DB_DATA_ALIGNMENT-1);
> +	}
> +
> +	for (ix = 0; ix < count; ix++) {
> +		if (!once) {
> +			writel(p, &fec->rbd_base[ix].data_pointer);
> +			p += size;
> +		}
> +		writew(FEC_RBD_EMPTY, &fec->rbd_base[ix].status);
> +		writew(0, &fec->rbd_base[ix].data_length);
> +	}
> +	/*
> +	 * mark the last RBD to close the ring
> +	 */
> +	writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &fec->rbd_base[ix - 1].status);
> +	fec->rbd_index = 0;
> +
> +	return 0;
> +}
> +
> +/**
> + * Initialize transmit task's buffer descriptors
> + * @param[in] fec all we know about the device yet
> + *
> + * Transmit buffers are created externally. We only have to init the BDs here.\n
> + * Note: There is a race condition in the hardware. When only one BD is in
> + * use it must be marked with the WRAP bit to use it for every transmitt.
> + * This bit in combination with the READY bit results into double transmit
> + * of each data buffer. It seems the state machine checks READY earlier then
> + * resetting it after the first transfer.
> + * Using two BDs solves this issue.
> + */
> +static void fec_tbd_init(struct fec_priv *fec)
> +{
> +	writew(0x0000, &fec->tbd_base[0].status);
> +	writew(FEC_TBD_WRAP, &fec->tbd_base[1].status);
> +	fec->tbd_index = 0;
> +}
> +
> +/**
> + * Mark the given read buffer descriptor as free
> + * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
> + * @param[in] pRbd buffer descriptor to mark free again
> + */
> +static void fec_rbd_clean(int last, struct fec_bd *pRbd)
> +{
> +	/*
> +	 * Reset buffer descriptor as empty
> +	 */
> +	if (last)
> +		writew(FEC_RBD_WRAP | FEC_RBD_EMPTY, &pRbd->status);
> +	else
> +		writew(FEC_RBD_EMPTY, &pRbd->status);
> +	/*
> +	 * no data in it
> +	 */
> +	writew(0, &pRbd->data_length);
> +}
> +
> +static int fec_get_hwaddr(struct eth_device *dev, unsigned char *mac)
> +{
> +	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
> +	int i;
> +
> +	for (i = 0; i < 6; i++)
> +		mac[6-1-i] = readl(&iim->IIM_BANK_AREA0[IIM0_MAC + i]);
> +
> +	return is_valid_ether_addr(mac);
> +}
> +
> +static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
> +{
> +	struct fec_priv *fec = (struct fec_priv *)dev->priv;
> +
> +	writel(0, &fec->eth->iaddr1);
> +	writel(0, &fec->eth->iaddr2);
> +	writel(0, &fec->eth->gaddr1);
> +	writel(0, &fec->eth->gaddr2);
> +
> +	/*
> +	 * Set physical address
> +	 */
> +	writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
> +			&fec->eth->paddr1);
> +	writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
> +
> +	return 0;
> +}
> +
> +/**
> + * Start the FEC engine
> + * @param[in] dev Our device to handle
> + */
> +static int fec_open(struct eth_device *edev)
> +{
> +	struct fec_priv *fec = (struct fec_priv *)edev->priv;
> +
> +	debug("fec_open: fec_open(dev)\n");
> +	/* full-duplex, heartbeat disabled */
> +	writel(1 << 2, &fec->eth->x_cntrl);
> +	fec->rbd_index = 0;
> +
> +	/*
> +	 * Enable FEC-Lite controller
> +	 */
> +	writel(FEC_ECNTRL_ETHER_EN, &fec->eth->ecntrl);
> +
> +	miiphy_wait_aneg(edev);
> +	miiphy_speed(edev->name, 0);
> +	miiphy_duplex(edev->name, 0);
> +
> +	/*
> +	 * Enable SmartDMA receive task
> +	 */
> +	fec_rx_task_enable(fec);
> +
> +	udelay(100000);
> +	return 0;
> +}
> +
> +static int fec_init(struct eth_device *dev, bd_t* bd)
> +{
> +	static int once;
> +	uint32_t base;
> +	struct fec_priv *fec = (struct fec_priv *)dev->priv;
> +
> +	if (!once) {
> +		/*
> +		 * reserve memory for both buffer descriptor chains at once
> +		 * Datasheet forces the startaddress of each chain is 16 byte
> +		 * aligned
> +		 */
> +		base = (uint32_t)malloc((2 + FEC_RBD_NUM) *
> +				sizeof(struct fec_bd) + DB_ALIGNMENT);
> +		memset((void *)base, 0, (2 + FEC_RBD_NUM) *
> +				sizeof(struct fec_bd) + DB_ALIGNMENT);
> +		base += (DB_ALIGNMENT-1);
> +		base &= ~(DB_ALIGNMENT-1);
> +
> +		fec->rbd_base = (struct fec_bd *)base;
> +
> +		base += FEC_RBD_NUM * sizeof(struct fec_bd);
> +
> +		fec->tbd_base = (struct fec_bd *)base;
> +	}
>   
If it's possible that an SOC will someday exist with more than one 
controller this singleton stuff will have to go.  Do you really need it 
here?  Your 'halt' function should free the memory so that it's safe to 
call init() more than once.
<snip>
> sprintf(edev->name, "FEC ETHERNET");
>   
You have a very specific driver name.  Why make it generic here?
> +
> +	miiphy_register(edev->name, fec_miiphy_read, fec_miiphy_write);
> +
> +	eth_register(edev);
> +
> +	if ((NULL != tmp) && (12 <= strlen(tmp))) {
> +		int i;
> +		/* convert MAC from string to int */
> +		for (i = 0; i < 6; i++) {
> +			ethaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
> +			if (tmp)
> +				tmp = (*end) ? end + 1 : end;
> +		}
> +	} else if (fec_get_hwaddr(edev, ethaddr) == 0) {
> +		printf("got MAC address from EEPROM: %pM\n", ethaddr);
> +		setenv("ethaddr", (char *)ethaddr_str);
> +	}
> +	memcpy(edev->enetaddr, ethaddr, 6);
> +	fec_set_hwaddr(edev, ethaddr);
> +
> +	return 0;
> +}
> +
> +int fecimx27_initialize(bd_t *bd)
> +{
> +	int lout = 1;
> +	static int once;
> +
> +	if (!once) {
> +		debug("eth_init: fec_probe(bd)\n");
> +		lout = fec_probe(bd);
> +		once = 1;
> +	}
> +	return lout;
> +}
>   
I don't like this singleton stuff.  You're artificially limiting this 
driver to a single instance.
<snip>

hanks for your submission!
Ben