From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dirk Behme Date: Thu, 28 May 2009 17:01:44 +0200 Subject: [U-Boot] [PATCH] The cache flush using coprocessor must be in lib_arm/cache-cp15.c In-Reply-To: References: Message-ID: <4A1EA758.4050403@googlemail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Kim, Heung Jun wrote: > Hi? I'm about to suggest one more thing related to "change cpu.c under > cpu/arm_cortexa8 dir to common code.". > > asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); > > It's the common feature all over the arm core, not only arm cortex A8. > The common cache function is defined in the lib_arm/cache-cp15.c as you > know. So, It's seems the better method that cache_flush() is moved to > lib_arm/cache-cp15.c > > Signed-off-by: HeungJun, Kim Yes, this is fine. Thanks. Do you like to update http://lists.denx.de/pipermail/u-boot/2009-May/053386.html regarding this and rename the functions there to e.g. cortexa8_l2cache_enable()/disable() (or soc_* or cpu_*)? Best regards Dirk > --- > cpu/arm_cortexa8/cpu.c | 4 ---- > lib_arm/cache-cp15.c | 5 +++++ > 2 files changed, 5 insertions(+), 4 deletions(-) > > diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c > index 3e1780b..329febb 100644 > --- a/cpu/arm_cortexa8/cpu.c > +++ b/cpu/arm_cortexa8/cpu.c > @@ -154,7 +154,3 @@ void l2cache_disable() > } > } > > -static void cache_flush(void) > -{ > - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); > -} > diff --git a/lib_arm/cache-cp15.c b/lib_arm/cache-cp15.c > index 62ed54f..face9b2 100644 > --- a/lib_arm/cache-cp15.c > +++ b/lib_arm/cache-cp15.c > @@ -53,6 +53,11 @@ static void cache_disable(uint32_t cache_bit) > cp_delay(); > set_cr(reg & ~cache_bit); > } > + > +static void cache_flush(void) > +{ > + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); > +} > #endif > > #ifdef CONFIG_SYS_NO_ICACHE