[U-Boot] [PATCH] ppc4xx/net: Fix MDIO clock setup

[U-Boot] [PATCH] ppc4xx/net: Fix MDIO clock setup

[Felix Radensky]

This patch fixes MDIO clock setup in case when OPB frequency is 100MHz.
Current code assumes that the value of sysinfo.freqOPB is 100000000
when OPB frequency is 100MHz. In reality it is 100000001. As a result 
MDIO clock is set to incorrect value, larger than 2.5MHz, thus violating
the standard. This in not a problem on boards equipped with Marvell PHYs
(e.g. Canyonlands), since those PHYs support MDIO clocks up to 8.3MHz, 
but can be a problem for other PHYs (e.g. Realtek ones).

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
---
 drivers/net/4xx_enet.c |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c
index 918373b..7bf3e0a 100644
--- a/drivers/net/4xx_enet.c
+++ b/drivers/net/4xx_enet.c
@@ -871,6 +871,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
     defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_405EX)
+	u32 opbfreq;
 	sys_info_t sysinfo;
 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
@@ -997,12 +998,13 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
 	/* Whack the M1 register */
 	mode_reg = 0x0;
 	mode_reg &= ~0x00000038;
-	if (sysinfo.freqOPB <= 50000000);
-	else if (sysinfo.freqOPB <= 66666667)
+	opbfreq = sysinfo.freqOPB / 1000000;
+	if (opbfreq <= 50);
+	else if (opbfreq <= 66)
 		mode_reg |= EMAC_M1_OBCI_66;
-	else if (sysinfo.freqOPB <= 83333333)
+	else if (opbfreq <= 83)
 		mode_reg |= EMAC_M1_OBCI_83;
-	else if (sysinfo.freqOPB <= 100000000)
+	else if (opbfreq <= 100)
 		mode_reg |= EMAC_M1_OBCI_100;
 	else
 		mode_reg |= EMAC_M1_OBCI_GT100;
-- 
1.5.4.3

[U-Boot] [PATCH] ppc4xx/net: Fix MDIO clock setup

[Ben Warren]

Hi Felix,

Felix Radensky wrote:
> This patch fixes MDIO clock setup in case when OPB frequency is 100MHz.
> Current code assumes that the value of sysinfo.freqOPB is 100000000
> when OPB frequency is 100MHz. In reality it is 100000001. As a result 
> MDIO clock is set to incorrect value, larger than 2.5MHz, thus violating
> the standard. This in not a problem on boards equipped with Marvell PHYs
> (e.g. Canyonlands), since those PHYs support MDIO clocks up to 8.3MHz, 
> but can be a problem for other PHYs (e.g. Realtek ones).
>
> Signed-off-by: Felix Radensky <felix@embedded-sol.com>
>   
Applied to net/next

thanks,
Ben