From: xiangfu <xiangfu.z@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [U-BOOT] nand merge problem
Date: Tue, 02 Jun 2009 10:42:45 +0800 [thread overview]
Message-ID: <4A2491A5.4090707@gmail.com> (raw)
In-Reply-To: <20090601165428.GA9536@b07421-ec1.am.freescale.net>
Thanks Scott,
it's work. :-)
Scott Wood wrote:
> Try something like this instead:
>
> static void jz_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
> {
> struct nand_chip *this = mtd->priv;
> unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
>
> if (ctrl & NAND_CTRL_CHANGE) {
> /* Change this to use I/O accessors. */
> if (ctrl & NAND_NCE) {
> REG_EMC_NFCSR |= EMC_NFCSR_NFCE1;
> } else {
> /*
> * Why set only one bit when NCE is high, but clear
> * four when low? Why clear separate bits in the same
> * register one at a time?
> */
my mistake. I copy those code form the device's kernel source code.
> REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
> REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE2;
> REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE3;
> REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE4;
> }
> }
>
> if (cmd == NAND_CMD_NONE)
> return;
>
> if (ctrl & NAND_CLE)
> nandaddr |= 0x00008000;
> else /* must be ALE */
> nandaddr |= 0x00010000;
>
> writeb(cmd, (uint8_t *)nandaddr);
> }
>
> -Scott
--
Best Regards
Xiangfu Liu
jabber : xiangfu.z at gmail.com
skype : xiangfu.z
next prev parent reply other threads:[~2009-06-02 2:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-26 7:46 [U-Boot] [U-BOOT] nand merge problem xiangfu_gmail
2009-05-26 9:12 ` xiangfu_gmail
2009-05-26 21:17 ` Scott Wood
2009-05-27 0:41 ` xiangfu_gmail
2009-05-27 14:34 ` Scott Wood
[not found] ` <00ab01c9e19b$b2488f50$3e03a8c0@st.jz.com>
2009-05-31 8:09 ` xiangfu
2009-06-01 16:54 ` Scott Wood
2009-06-02 2:42 ` xiangfu [this message]
2009-06-06 14:46 ` [U-Boot] console_init_r problem with ingenic jz4740 cpu xiangfu
2009-06-10 9:14 ` [U-Boot] lcd logo color not correct xiangfu
2009-06-10 14:26 ` xiangfu
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