From mboxrd@z Thu Jan  1 00:00:00 1970
From: xiangfu <xiangfu.z@gmail.com>
Date: Tue, 02 Jun 2009 10:42:45 +0800
Subject: [U-Boot] [U-BOOT] nand merge problem
In-Reply-To: <20090601165428.GA9536@b07421-ec1.am.freescale.net>
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	<00ab01c9e19b$b2488f50$3e03a8c0@st.jz.com>
	<4A223B3F.3030900@gmail.com>
	<20090601165428.GA9536@b07421-ec1.am.freescale.net>
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To: u-boot@lists.denx.de

Thanks Scott,
it's work. :-)

Scott Wood wrote:
> Try something like this instead:
> 
> static void jz_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
> {
> 	struct nand_chip *this = mtd->priv;
> 	unsigned long nandaddr = (unsigned long)this->IO_ADDR_W;
> 
> 	if (ctrl & NAND_CTRL_CHANGE) {
> 		/* Change this to use I/O accessors. */
> 		if (ctrl & NAND_NCE) {
> 			REG_EMC_NFCSR |= EMC_NFCSR_NFCE1; 
> 		} else {
> 			/*
> 			 * Why set only one bit when NCE is high, but clear
> 			 * four when low?  Why clear separate bits in the same
> 			 * register one at a time?
> 			 */
my mistake. I copy those code form the device's kernel source code.
> 			REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE1;
> 			REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE2;
> 			REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE3;
> 			REG_EMC_NFCSR &= ~EMC_NFCSR_NFCE4;
> 		}
> 	}
> 
> 	if (cmd == NAND_CMD_NONE)
> 		return;
> 
> 	if (ctrl & NAND_CLE)
> 		nandaddr |= 0x00008000;
> 	else /* must be ALE */
> 		nandaddr |= 0x00010000;
> 
> 	writeb(cmd, (uint8_t *)nandaddr);
> }
> 
> -Scott


-- 
Best Regards
Xiangfu Liu

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