[U-Boot] TSEC ethernet controller problems (crc errors / corruption)

[David Hawkins <dwh@ovro.caltech.edu>]

Hi Peter,

>>> I am unable to reproduce the corruption on my MPC8349EMDS eval board,
>>> but I'm running out of ideas to try and find the source of this problem.
>> One more piece of info: the MPC8349E-MDS board contains the
>> MPC8349E processor, whereas our board contains the MPC8349EA
>> (silicon v 3.1) processor. We did have a couple of MPC8349EA-MDS
>> boards, however, the Xilinx CPLD on both boards spontaneously
>> destructed (the CPLD sticky labels melted!).
>>
>> We can try putting the MPC8349EA processor from one of the
>> dead boards into the MPC8349E-MDS board socket - I believe
>> this is ok - feel free to warn us that its not :)
> 
> What interface are you using between the MAC and PHY?  I saw somewhat
> similar weirdness at gigabit on a board when using RGMII and the clock
> delays in the PHY and PCB didn't match up correctly (Section 5.12.2 from
> the 88e1111 manual).  If you aren't using RGMII, this wouldn't be your
> issue though...

The default is to use GMII. Ira reconfigured the interface
to RGMII after boot, and saw similar errors to those he was
getting in GMII mode.

Probing the PHY-to-MAC path shows the data we expect,
so the error seems to be internal to the processor ...

The signal integrity on the board is good, we compared
the timing between our board and the Freescale MDS board,
and it all looks very similar.

Cheers,
Dave