[U-Boot] TSEC ethernet controller problems (crc errors / corruption)

[David Hawkins <dwh@ovro.caltech.edu>]

Hi Wolfgang,

>> I've been working on a custom board, based heavily on the Freescale
>> MPC8349EMDS board. The only major difference is that the board has some
>> FPGAs connected to the local bus.
>>
>> I've found that the TSEC / gianfar ethernet does not work for me in
>> 1000mbit mode. I constantly get "got error 4" from U-Boot, which means
>> that a CRC error was detected by the TSEC controller.
>>
>> I have tried running the TSEC in 100mbit mode, without any problems. I
>> can tftp as much data as I want in U-Boot, and I've transferred many,
>> many gigabytes without issue in Linux. The problem is only with 1000mbit
>> mode.
> 
> I read that the same problem happens in Linux when running at
> 1000mbit. Is this understanding correct?
> 
> Does running with root file system mounted over NFS work on this
> board? Does it work at 1000mbit, too?

I'll let Ira answer those questions.

> Did you try and re-check the memory controller initialization?

The memory is DDR1 (2.5V) configured with ECC enabled.
The DDR control clock was moved to various settings to see how
much timing margin there was, and the central setting was
selected (there appears to be good margin).

I'm not sure that a TSEC induced memory burst would be any different
than a DMA induced memory, so if we were going to see errors, I
would have expected to see them during DMA testing.

The strange thing about the patterns Ira is seeing is that the
erroneous data sometimes matches data that occurred much earlier
in a packet, not the last data on the DDR bus. This has a
symptom like a FIFO address wrap-around where the FIFO
erroneously indicates it has valid data, so the FIFO reader
reads the stale data, and writes it to DDR.

Ira will play with some of the TSEC settings and see if he
can change the symptom.

Thanks for the suggestions!

Cheers,
Dave