[U-Boot] TSEC ethernet controller problems (crc errors/ corruption)

[David Hawkins <dwh@ovro.caltech.edu>]

Hi Dave,

> Good news, Good summary!

Thanks!

>> This testing revealed some interesting observations;
>>
>> 1) The Marvell 88E1111 PHY generates a 125MHz output
>>     clock that is used as the PowerPC EC_GTX_CLK125MHZ
>>     clock source on the MDS board.
>>
>>     The MDS board has to use the PHY output as the 125MHz
>>     clock source to the PowerPC, as the PHY is clocked
>>     using a 25MHz oscillator, so there is no alternative
>>     source of 125MHz on the board.
>>
>>     However, the PHY 125MHz output has a *huge* amount
>>     of duty cycle variation depending on whether the
>>     PHY has negotiated as a *master* (clock looks good),
>>     or as a *slave* (horrible looking clock).
>>
>>     When the PHY on the MDS board, or our board,
>>     negotiates the 1Gbit link as a *slave*, observing
>>     the 125MHz output clock with an oscilloscope
>>     triggered on the rising edge of the clock, there
>>     is about 1ns of variation in the timing of the
>>     falling edge.
> 
> IIRC, The FPGA of MPC8349EA-MDS can control if we use the PHY
> as master. We were aware of this.

Ok at least someone else has seen it!

Of course if Freescale had seen this, its a shame they
did not put a warning in the MDS documentation.
However, its really the Marvell data sheet that
should have information on this feature!

Our board layout is such that it'll be a fairly easy fix
to add both a 3.3V buffer and the option to use a 125MHz
oscillator directly, or the PHY 125MHz output.

I'm just glad to figure out what was happening.

Cheers,
Dave