From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Hawkins Date: Tue, 09 Jun 2009 16:35:30 -0700 Subject: [U-Boot] TSEC ethernet controller problems (crc errors/ corruption) In-Reply-To: References: <20090602194659.GA5471@ovro.caltech.edu> <20090602212503.GA16327@ovro.caltech.edu> <20090602221918.GB16327@ovro.caltech.edu> <20090602180817.079aa37f.kim.phillips@freescale.com> <20090603175025.GB7292@ovro.caltech.edu> <20090603151905.b191e4b0.kim.phillips@freescale.com> <4A26EE1D.9020405@windriver.com> <4A2967D2.1020808@windriver.com> <20090605193829.aac47d61.kim.phillips@freescale.com> <1977.173.58.138.219.1244255466.squirrel@webmail.ovro.caltech.edu> <20090608105026.572b00c8.kim.phillips@freescale.com> <4A2D404C.5050103@ovro.caltech.edu> <4A2DA08E.10500@ovro.caltech.edu> <4A2ED83F.1020304@ovro.caltech.edu> Message-ID: <4A2EF1C2.4070103@ovro.caltech.edu> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Dave, > Good news, Good summary! Thanks! >> This testing revealed some interesting observations; >> >> 1) The Marvell 88E1111 PHY generates a 125MHz output >> clock that is used as the PowerPC EC_GTX_CLK125MHZ >> clock source on the MDS board. >> >> The MDS board has to use the PHY output as the 125MHz >> clock source to the PowerPC, as the PHY is clocked >> using a 25MHz oscillator, so there is no alternative >> source of 125MHz on the board. >> >> However, the PHY 125MHz output has a *huge* amount >> of duty cycle variation depending on whether the >> PHY has negotiated as a *master* (clock looks good), >> or as a *slave* (horrible looking clock). >> >> When the PHY on the MDS board, or our board, >> negotiates the 1Gbit link as a *slave*, observing >> the 125MHz output clock with an oscilloscope >> triggered on the rising edge of the clock, there >> is about 1ns of variation in the timing of the >> falling edge. > > IIRC, The FPGA of MPC8349EA-MDS can control if we use the PHY > as master. We were aware of this. Ok at least someone else has seen it! Of course if Freescale had seen this, its a shame they did not put a warning in the MDS documentation. However, its really the Marvell data sheet that should have information on this feature! Our board layout is such that it'll be a fairly easy fix to add both a 3.3V buffer and the option to use a 125MHz oscillator directly, or the PHY 125MHz output. I'm just glad to figure out what was happening. Cheers, Dave