[U-Boot] Uboot and ARM SMP support

[U-Boot] Uboot and ARM SMP support

[Sudeep K N]

Hi,

I have seen the latest Uboot code there is no support for Cortex A9.
What I would like to know is that can we reuse ARM Cortex A8 code
for ARM Cortex A9 SMP system as bootloader must run in single core.

Reference:
http://www.linux-arm.org/LinuxBootLoader/SMPBoot

-- 
Regards,
Sudeep

[U-Boot] Uboot and ARM SMP support

[Jean-Christophe PLAGNIOL-VILLARD]

On 09:33 Thu 25 Jun     , Sudeep K N wrote:
> Hi,
> 
> I have seen the latest Uboot code there is no support for Cortex A9.
> What I would like to know is that can we reuse ARM Cortex A8 code
> for ARM Cortex A9 SMP system as bootloader must run in single core.
Yes you can re-use the A8 code but you will need to update the cache
management to boot you soc in smp mode

In U-Boot you will use and active only one core, the others will be active in
the kernel

Best Regards,
J.

[U-Boot] Uboot and ARM SMP support

[Sudeep K N]

>> I have seen the latest Uboot code there is no support for Cortex A9.
>> What I would like to know is that can we reuse ARM Cortex A8 code
>> for ARM Cortex A9 SMP system as bootloader must run in single core.
> Yes you can re-use the A8 code but you will need to update the cache
> management to boot you soc in smp mode
Do we need this if the bootmonitor/prebootloader is putting second
core to WFE state?

-- 
Regards,
Sudeep

[U-Boot] Uboot and ARM SMP support

[Jean-Christophe PLAGNIOL-VILLARD]

On 13:08 Thu 25 Jun     , Sudeep K N wrote:
> >> I have seen the latest Uboot code there is no support for Cortex A9.
> >> What I would like to know is that can we reuse ARM Cortex A8 code
> >> for ARM Cortex A9 SMP system as bootloader must run in single core.
> > Yes you can re-use the A8 code but you will need to update the cache
> > management to boot you soc in smp mode
> Do we need this if the bootmonitor/prebootloader is putting second
> core to WFE state?
I do not known what do other preloader and always try avoid it
but in u-boot we will use only one core
we can boot amp on some soc but no arm for now

Best Regards,
J.

[U-Boot] Uboot and ARM SMP support

[Sudeep K N]

Sorry, may be I confused you.
I indent to use only one core for u-boot.
I wanted to ask whether we need to update the cache
management to boot for ARM Cortex A9 SMP if we take
ARM Cortex A8 code as base.
I have tried and did not require any change on top of A8 code
to run u-boot on A9 SMP.
Is that right approach?

-- 
Regards,
Sudeep

[U-Boot] Uboot and ARM SMP support

[Nishanth Menon]

Sudeep K N said the following on 06/25/2009 12:11 PM:
> Sorry, may be I confused you.
> I indent to use only one core for u-boot.
> I wanted to ask whether we need to update the cache
> management to boot for ARM Cortex A9 SMP if we take
> ARM Cortex A8 code as base.
> I have tried and did not require any change on top of A8 code
> to run u-boot on A9 SMP.
> Is that right approach?
>
>   
you may want to see [1] how this was done for OMAP4 (which has a SMP
cortex A9)-> we can discuss how to setup cortex_a9 in mainline u-boot.

My thought would be: cpu/arm_cortexa9 - considering that a9 cores could
be from 1 to 4 or so if my memory serves right -> btw, I wonder how SMP
handling is done in u-boot today..

Regards,
Nishanth Menon
Ref:
[1]
http://git.omapzoom.org/?p=repo/u-boot.git;a=tree;h=refs/heads/omap4_dev;hb=refs/heads/omap4_dev

[U-Boot] Uboot and ARM SMP support

[Jean-Christophe PLAGNIOL-VILLARD]

On 12:47 Thu 25 Jun     , Nishanth Menon wrote:
> Sudeep K N said the following on 06/25/2009 12:11 PM:
> > Sorry, may be I confused you.
> > I indent to use only one core for u-boot.
> > I wanted to ask whether we need to update the cache
> > management to boot for ARM Cortex A9 SMP if we take
> > ARM Cortex A8 code as base.
> > I have tried and did not require any change on top of A8 code
> > to run u-boot on A9 SMP.
> > Is that right approach?
> >
> >   
> you may want to see [1] how this was done for OMAP4 (which has a SMP
> cortex A9)-> we can discuss how to setup cortex_a9 in mainline u-boot.
> 
> My thought would be: cpu/arm_cortexa9 - considering that a9 cores could
> be from 1 to 4 or so if my memory serves right -> btw, I wonder how SMP
> handling is done in u-boot today..
for arm I've only a theorical design as I've no SMP board for now
but I want to see SMP boot & AMP boot supported in Mainline

Best Regards,
J.

[U-Boot] Uboot and ARM SMP support

[Pandita, Vikram]

Adding Santosh to loop who has pushed the OMAP4 SMP support into Kernel.org


>-----Original Message-----
>From: Jean-Christophe PLAGNIOL-VILLARD [mailto:plagnioj at jcrosoft.com]
>Sent: Thursday, June 25, 2009 7:44 AM
>To: Nishanth Menon
>Cc: Sudeep K N; u-boot at lists.denx.de; Pandita, Vikram; Tom
>Subject: Re: [U-Boot] Uboot and ARM SMP support
>
>On 12:47 Thu 25 Jun     , Nishanth Menon wrote:
>> Sudeep K N said the following on 06/25/2009 12:11 PM:
>> > Sorry, may be I confused you.
>> > I indent to use only one core for u-boot.
>> > I wanted to ask whether we need to update the cache
>> > management to boot for ARM Cortex A9 SMP if we take
>> > ARM Cortex A8 code as base.
>> > I have tried and did not require any change on top of A8 code
>> > to run u-boot on A9 SMP.
>> > Is that right approach?
>> >
>> >
>> you may want to see [1] how this was done for OMAP4 (which has a SMP
>> cortex A9)-> we can discuss how to setup cortex_a9 in mainline u-boot.
>>
>> My thought would be: cpu/arm_cortexa9 - considering that a9 cores could
>> be from 1 to 4 or so if my memory serves right -> btw, I wonder how SMP
>> handling is done in u-boot today..
>for arm I've only a theorical design as I've no SMP board for now
>but I want to see SMP boot & AMP boot supported in Mainline
>
>Best Regards,
>J.

[U-Boot] Uboot and ARM SMP support

[Sudeep K N]

>for arm I've only a theorical design as I've no SMP board for now
>but I want to see SMP boot & AMP boot supported in Mainline
Could you please provide your idea/theorical design so that we can
try out on the real hardware?

Regards,
Sudeep

[U-Boot] Uboot and ARM SMP support

[Shilimkar, Santosh]

> -----Original Message-----
> From: Pandita, Vikram 
> Sent: Thursday, June 25, 2009 6:32 PM
> To: Jean-Christophe PLAGNIOL-VILLARD; Nishanth Menon; 
> Shilimkar, Santosh
> Cc: Sudeep K N; u-boot at lists.denx.de; Tom
> Subject: RE: [U-Boot] Uboot and ARM SMP support
> 
> Adding Santosh to loop who has pushed the OMAP4 SMP support 
> into Kernel.org
> 
> 
> >-----Original Message-----
> >From: Jean-Christophe PLAGNIOL-VILLARD [mailto:plagnioj at jcrosoft.com]
> >Sent: Thursday, June 25, 2009 7:44 AM
> >To: Nishanth Menon
> >Cc: Sudeep K N; u-boot at lists.denx.de; Pandita, Vikram; Tom
> >Subject: Re: [U-Boot] Uboot and ARM SMP support
> >
> >On 12:47 Thu 25 Jun     , Nishanth Menon wrote:
> >> Sudeep K N said the following on 06/25/2009 12:11 PM:
> >> > Sorry, may be I confused you.
> >> > I indent to use only one core for u-boot.
> >> > I wanted to ask whether we need to update the cache
> >> > management to boot for ARM Cortex A9 SMP if we take
> >> > ARM Cortex A8 code as base.
> >> > I have tried and did not require any change on top of A8 code
> >> > to run u-boot on A9 SMP.
> >> > Is that right approach?
> >> >
> >> >
> >> you may want to see [1] how this was done for OMAP4 (which 
> has a SMP
> >> cortex A9)-> we can discuss how to setup cortex_a9 in 
> mainline u-boot.
> >>
> >> My thought would be: cpu/arm_cortexa9 - considering that 
> a9 cores could
> >> be from 1 to 4 or so if my memory serves right -> btw, I 
> wonder how SMP
> >> handling is done in u-boot today..
> >for arm I've only a theorical design as I've no SMP board for now
> >but I want to see SMP boot & AMP boot supported in Mainline
> >

The approach is perfect and that's what is most of the SMP systems are doing..
If one look at the linux framework, U-boot need not know about the secondary cores.

As far as caches goes, the SCU is not enabled at u-boot level so there is no coherency
between L1 caches.L2 is external and not enabled at u-boot level for time being.
At the point when u-boot transfer control to kernel, the caches are flushed in the 
clean-up path so you need not do any explicit stuff.

In case you want to enable L2 cache ( if preset ), then you need to add support for 
that in the u-boot. 

So essentially u-boot would be almost same as Cortex-A8 except you should avoid programming AuxControl
register because the bit definitions are different.

Hope this helps

Regards,
Santosh
 

[U-Boot] Uboot and ARM SMP support

[Nishanth Menon]

Shilimkar, Santosh said the following on 06/25/2009 04:51 PM:
>> -----Original Message-----
>> From: Pandita, Vikram 
>> Sent: Thursday, June 25, 2009 6:32 PM
>> To: Jean-Christophe PLAGNIOL-VILLARD; Nishanth Menon; 
>> Shilimkar, Santosh
>> Cc: Sudeep K N; u-boot at lists.denx.de; Tom
>> Subject: RE: [U-Boot] Uboot and ARM SMP support
>>
>> Adding Santosh to loop who has pushed the OMAP4 SMP support 
>> into Kernel.org
>>
>>
>>     
>>> -----Original Message-----
>>> From: Jean-Christophe PLAGNIOL-VILLARD [mailto:plagnioj at jcrosoft.com]
>>> Sent: Thursday, June 25, 2009 7:44 AM
>>> To: Nishanth Menon
>>> Cc: Sudeep K N; u-boot at lists.denx.de; Pandita, Vikram; Tom
>>> Subject: Re: [U-Boot] Uboot and ARM SMP support
>>>
>>> On 12:47 Thu 25 Jun     , Nishanth Menon wrote:
>>>       
>>>> Sudeep K N said the following on 06/25/2009 12:11 PM:
>>>>         
>>>>> Sorry, may be I confused you.
>>>>> I indent to use only one core for u-boot.
>>>>> I wanted to ask whether we need to update the cache
>>>>> management to boot for ARM Cortex A9 SMP if we take
>>>>> ARM Cortex A8 code as base.
>>>>> I have tried and did not require any change on top of A8 code
>>>>> to run u-boot on A9 SMP.
>>>>> Is that right approach?
>>>>>
>>>>>
>>>>>           
>>>> you may want to see [1] how this was done for OMAP4 (which 
>>>>         
>> has a SMP
>>     
>>>> cortex A9)-> we can discuss how to setup cortex_a9 in 
>>>>         
>> mainline u-boot.
>>     
>>>> My thought would be: cpu/arm_cortexa9 - considering that 
>>>>         
>> a9 cores could
>>     
>>>> be from 1 to 4 or so if my memory serves right -> btw, I 
>>>>         
>> wonder how SMP
>>     
>>>> handling is done in u-boot today..
>>>>         
>>> for arm I've only a theorical design as I've no SMP board for now
>>> but I want to see SMP boot & AMP boot supported in Mainline
>>>
>>>       
>
> The approach is perfect and that's what is most of the SMP systems are doing..
> If one look at the linux framework, U-boot need not know about the secondary cores.
>
> As far as caches goes, the SCU is not enabled at u-boot level so there is no coherency
> between L1 caches.L2 is external and not enabled at u-boot level for time being.
> At the point when u-boot transfer control to kernel, the caches are flushed in the 
> clean-up path so you need not do any explicit stuff.
>
> In case you want to enable L2 cache ( if preset ), then you need to add support for 
> that in the u-boot. 
>
> So essentially u-boot would be almost same as Cortex-A8 except you should avoid programming AuxControl
> register because the bit definitions are different.
>
> Hope this helps
>   
so how would the new arch look like? do we do:
cpu/arm_cortexa8_9 and common code there?
Regards,
Nishanth Menon

[U-Boot] Uboot and ARM SMP support

[Tom]

Nishanth Menon wrote:
> Shilimkar, Santosh said the following on 06/25/2009 04:51 PM:
>   
<snip>
>>
>> So essentially u-boot would be almost same as Cortex-A8 except you should avoid programming AuxControl
>> register because the bit definitions are different.
>>
>> Hope this helps
>>   
>>     
> so how would the new arch look like? do we do:
> cpu/arm_cortexa8_9 and common code there?
>   
Given my recent experience with common code for i2c on omp24xx and omap3,
I would prefer if they were separate and had no common code.

cpu/arm_cortexa8
cpu/arm_cortexa9

So A8 can be more easily maintained.
As A9 matures, it will diverge more from A8.

Tom

> Regards,
> Nishanth Menon
>   

[U-Boot] Uboot and ARM SMP support

[Dirk Behme]

Shilimkar, Santosh wrote:
>> -----Original Message-----
>> From: Pandita, Vikram 
>> Sent: Thursday, June 25, 2009 6:32 PM
>> To: Jean-Christophe PLAGNIOL-VILLARD; Nishanth Menon; 
>> Shilimkar, Santosh
>> Cc: Sudeep K N; u-boot at lists.denx.de; Tom
>> Subject: RE: [U-Boot] Uboot and ARM SMP support
>>
>> Adding Santosh to loop who has pushed the OMAP4 SMP support 
>> into Kernel.org
>>
>>
>>> -----Original Message-----
>>> From: Jean-Christophe PLAGNIOL-VILLARD [mailto:plagnioj at jcrosoft.com]
>>> Sent: Thursday, June 25, 2009 7:44 AM
>>> To: Nishanth Menon
>>> Cc: Sudeep K N; u-boot at lists.denx.de; Pandita, Vikram; Tom
>>> Subject: Re: [U-Boot] Uboot and ARM SMP support
>>>
>>> On 12:47 Thu 25 Jun     , Nishanth Menon wrote:
>>>> Sudeep K N said the following on 06/25/2009 12:11 PM:
>>>>> Sorry, may be I confused you.
>>>>> I indent to use only one core for u-boot.
>>>>> I wanted to ask whether we need to update the cache
>>>>> management to boot for ARM Cortex A9 SMP if we take
>>>>> ARM Cortex A8 code as base.
>>>>> I have tried and did not require any change on top of A8 code
>>>>> to run u-boot on A9 SMP.
>>>>> Is that right approach?
>>>>>
>>>>>
>>>> you may want to see [1] how this was done for OMAP4 (which 
>> has a SMP
>>>> cortex A9)-> we can discuss how to setup cortex_a9 in 
>> mainline u-boot.
>>>> My thought would be: cpu/arm_cortexa9 - considering that 
>> a9 cores could
>>>> be from 1 to 4 or so if my memory serves right -> btw, I 
>> wonder how SMP
>>>> handling is done in u-boot today..
>>> for arm I've only a theorical design as I've no SMP board for now
>>> but I want to see SMP boot & AMP boot supported in Mainline
>>>
> 
> The approach is perfect and that's what is most of the SMP systems are doing..
> If one look at the linux framework, U-boot need not know about the secondary cores.
> 
> As far as caches goes, the SCU is not enabled at u-boot level so there is no coherency
> between L1 caches.L2 is external and not enabled at u-boot level for time being.
> At the point when u-boot transfer control to kernel, the caches are flushed in the 
> clean-up path so you need not do any explicit stuff.
> 
> In case you want to enable L2 cache ( if preset ), then you need to add support for 
> that in the u-boot. 
> 
> So essentially u-boot would be almost same as Cortex-A8 except you should avoid programming AuxControl
> register because the bit definitions are different.

Yes.

What I think what I (hopefully correctly) understood looking at 
Peter's (looping him in, btw) U-Boot branch

http://www.linux-arm.org/git?p=u-boot-armdev.git;a=summary

is:

* Regarding U-Boot (ARM) SMP support:

There isn't any need for U-Boot (cpu directory) to deal with it. 
Concept seems to be "handle ARM11 MPcore as ARM11 single core and 
Cortex A9 SMP as Cortex A8" at U-Boot level. I.e. boot only the master 
processor and cover it with existing single processor code in cpu 
directory. Then use board specific low_levelinit.S to put other 
(slave) processors into WFI mode. That's all.

* Regarding cpu/cortex_a9 directory:

No need for it. I don't know A9, but looking e.g. at

http://www.linux-arm.org/git?p=u-boot-armdev.git;a=blobdiff;f=MAKEALL;h=84f4bf8862cd49f109174de62777e4bd3499ab03;hp=67030a7355d56d751fdc4499e3c82d8fdb615d6e;hb=eb72ea08d09b7e7ac96d7dc3f428a63f53d266e1;hpb=2e6979454a2ea76c6b2889e40cde2e0ee9ad5e50
http://www.linux-arm.org/git?p=u-boot-armdev.git;a=blobdiff;f=MAKEALL;h=67030a7355d56d751fdc4499e3c82d8fdb615d6e;hp=72cc4ee0d90b5feb90ffe1fc48ddb6c3a0850907;hb=2e6979454a2ea76c6b2889e40cde2e0ee9ad5e50;hpb=ecad37d06857bb4f57bb95e0e0246a68b4d58161

and above idea of re-using single processor core cpu/arm* code, I 
would propose to rename cpu/cortex_a8 to cpu/cortex_ax. And cover A9 
with this, too.

As I don't have an A9 nor know the details, I'm not sure if this would 
work in real life, but the basic idea sounds good for.

Maybe Peter can share his ideas or experience?

Best regards

Dirk

[U-Boot] Uboot and ARM SMP support

[Peter Pearse]

Those interested in SMP booting on ARM may be interested in

http://www.linux-arm.org/LinuxBootLoader/SMPBoot


	On ARM supplied development boards we rely on the pre-installed 

ARM Boot Monitor to provide the necessary setup to allow U-Boot to run uni-core.


	I am about to look at a patch for the ARM Fast Model A9 multicore

in order to boot it without an ARM Boot Monitor. I'll cc this list

once it is added to git://linux-arm.org/u-boot-armdev


Apologies for the disclaimer - our sys admins seemd to have decided to close my open-source account.......


Regards

Peter

> -----Original Message-----
> From: u-boot-bounces at lists.denx.de 
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Nishanth Menon
> Sent: 25 June 2009 10:48
> To: Sudeep K N
> Cc: u-boot at lists.denx.de; Pandita, Vikram; Tom
> Subject: Re: [U-Boot] Uboot and ARM SMP support
> 
> Sudeep K N said the following on 06/25/2009 12:11 PM:
> > Sorry, may be I confused you.
> > I indent to use only one core for u-boot.
> > I wanted to ask whether we need to update the cache 
> management to boot 
> > for ARM Cortex A9 SMP if we take ARM Cortex A8 code as base.
> > I have tried and did not require any change on top of A8 
> code to run 
> > u-boot on A9 SMP.
> > Is that right approach?
> >
> >   
> you may want to see [1] how this was done for OMAP4 (which 
> has a SMP cortex A9)-> we can discuss how to setup cortex_a9 
> in mainline u-boot.
> 
> My thought would be: cpu/arm_cortexa9 - considering that a9 
> cores could be from 1 to 4 or so if my memory serves right -> 
> btw, I wonder how SMP handling is done in u-boot today..
> 
> Regards,
> Nishanth Menon
> Ref:
> [1]
> http://git.omapzoom.org/?p=repo/u-boot.git;a=tree;h=refs/heads
> /omap4_dev;hb=refs/heads/omap4_dev
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
> 
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[U-Boot] Uboot and ARM SMP support

[Nishanth Menon]

Peter Pearse said the following on 06/25/2009 06:55 PM:
> Those interested in SMP booting on ARM may be interested in
>
> http://www.linux-arm.org/LinuxBootLoader/SMPBoot
>
>
> 	On ARM supplied development boards we rely on the pre-installed 
>
> ARM Boot Monitor to provide the necessary setup to allow U-Boot to run uni-core.
>
>
> 	I am about to look at a patch for the ARM Fast Model A9 multicore
>
> in order to boot it without an ARM Boot Monitor. I'll cc this list
>
> once it is added to git://linux-arm.org/u-boot-armdev
>
>
> Apologies for the disclaimer - our sys admins seemd to have decided to close my open-source account.......
>
>   
It might be exciting to look at boot and peripheral support planned:
a) unicore Vs multicore support at u-boot level?
b) single thread scheduling?
c)  interrrupt handling?
d) peripheral and flash handling could be concurrent?
e) anything else which could affect common systems?
f) any kernel/"other OS" specific features?

Regards,
Nishanth Menon

[U-Boot] Uboot and ARM SMP support

[Jean-Christophe PLAGNIOL-VILLARD]

On 10:18 Thu 25 Jun     , Tom wrote:
> Nishanth Menon wrote:
> >Shilimkar, Santosh said the following on 06/25/2009 04:51 PM:
> <snip>
> >>
> >>So essentially u-boot would be almost same as Cortex-A8 except you should avoid programming AuxControl
> >>register because the bit definitions are different.
> >>
> >>Hope this helps
> >so how would the new arch look like? do we do:
> >cpu/arm_cortexa8_9 and common code there?
> Given my recent experience with common code for i2c on omp24xx and omap3,
> I would prefer if they were separate and had no common code.
no sorry I'm bored to copy & paster of code everywhere specialy on arm
> 
> cpu/arm_cortexa8
> cpu/arm_cortexa9
I do not want to see this anymore
> 
> So A8 can be more easily maintained.
it will be a mess on start.S for 2 or 3 specific code line so no
> As A9 matures, it will diverge more from A8.
for now I think merge them make more sense
if it will require in the futur to separte them we will see but for now no

Best Regards,
J.

[U-Boot] Uboot and ARM SMP support

[Shilimkar, Santosh]

> -----Original Message-----
> From: Dirk Behme [mailto:dirk.behme at googlemail.com] 
> Sent: Thursday, June 25, 2009 9:19 PM
> To: Shilimkar, Santosh
> Cc: Pandita, Vikram; Jean-Christophe PLAGNIOL-VILLARD; 
> Nishanth Menon; u-boot at lists.denx.de; Tom; Peter Pearse
> Subject: Re: [U-Boot] Uboot and ARM SMP support
> 
> Shilimkar, Santosh wrote:
> >> -----Original Message-----
> >> From: Pandita, Vikram 
> >> Sent: Thursday, June 25, 2009 6:32 PM
> >> To: Jean-Christophe PLAGNIOL-VILLARD; Nishanth Menon; 
> >> Shilimkar, Santosh
> >> Cc: Sudeep K N; u-boot at lists.denx.de; Tom
> >> Subject: RE: [U-Boot] Uboot and ARM SMP support
> >>
> >> Adding Santosh to loop who has pushed the OMAP4 SMP support 
> >> into Kernel.org
> >>
> >>
> >>> -----Original Message-----
> >>> From: Jean-Christophe PLAGNIOL-VILLARD 
> [mailto:plagnioj at jcrosoft.com]
> >>> Sent: Thursday, June 25, 2009 7:44 AM
> >>> To: Nishanth Menon
> >>> Cc: Sudeep K N; u-boot at lists.denx.de; Pandita, Vikram; Tom
> >>> Subject: Re: [U-Boot] Uboot and ARM SMP support
> >>>
> >>> On 12:47 Thu 25 Jun     , Nishanth Menon wrote:
> >>>> Sudeep K N said the following on 06/25/2009 12:11 PM:
> >>>>> Sorry, may be I confused you.
> >>>>> I indent to use only one core for u-boot.
> >>>>> I wanted to ask whether we need to update the cache
> >>>>> management to boot for ARM Cortex A9 SMP if we take
> >>>>> ARM Cortex A8 code as base.
> >>>>> I have tried and did not require any change on top of A8 code
> >>>>> to run u-boot on A9 SMP.
> >>>>> Is that right approach?
> >>>>>
> >>>>>
> >>>> you may want to see [1] how this was done for OMAP4 (which 
> >> has a SMP
> >>>> cortex A9)-> we can discuss how to setup cortex_a9 in 
> >> mainline u-boot.
> >>>> My thought would be: cpu/arm_cortexa9 - considering that 
> >> a9 cores could
> >>>> be from 1 to 4 or so if my memory serves right -> btw, I 
> >> wonder how SMP
> >>>> handling is done in u-boot today..
> >>> for arm I've only a theorical design as I've no SMP board for now
> >>> but I want to see SMP boot & AMP boot supported in Mainline
> >>>
> > 
> > The approach is perfect and that's what is most of the SMP 
> systems are doing..
> > If one look at the linux framework, U-boot need not know 
> about the secondary cores.
> > 
> > As far as caches goes, the SCU is not enabled at u-boot 
> level so there is no coherency
> > between L1 caches.L2 is external and not enabled at u-boot 
> level for time being.
> > At the point when u-boot transfer control to kernel, the 
> caches are flushed in the 
> > clean-up path so you need not do any explicit stuff.
> > 
> > In case you want to enable L2 cache ( if preset ), then you 
> need to add support for 
> > that in the u-boot. 
> > 
> > So essentially u-boot would be almost same as Cortex-A8 
> except you should avoid programming AuxControl
> > register because the bit definitions are different.
> 
> Yes.
> 
> What I think what I (hopefully correctly) understood looking at 
> Peter's (looping him in, btw) U-Boot branch
> 
> http://www.linux-arm.org/git?p=u-boot-armdev.git;a=summary
> 
> is:
> 
> * Regarding U-Boot (ARM) SMP support:
> 
> There isn't any need for U-Boot (cpu directory) to deal with it. 
> Concept seems to be "handle ARM11 MPcore as ARM11 single core and 
> Cortex A9 SMP as Cortex A8" at U-Boot level. I.e. boot only 
> the master 
> processor and cover it with existing single processor code in cpu 
> directory. Then use board specific low_levelinit.S to put other 
> (slave) processors into WFI mode. That's all.
This perfectly summarises that we don't need to have A9 specific
Directory. Regarding doing something on secondary core, it can be handled
In boot monitor(ROM code) or as suggested in u-boot itself.

> * Regarding cpu/cortex_a9 directory:
> 
> No need for it. I don't know A9, but looking e.g. at
> 
> http://www.linux-arm.org/git?p=u-boot-armdev.git;a=blobdiff;f=
> MAKEALL;h=84f4bf8862cd49f109174de62777e4bd3499ab03;hp=67030a73
55d56d751fdc4499e3c82d8fdb615d6e;hb=eb72ea08d09b7e7ac96d7dc3f428a63f53d266e1;hpb=> 2e6979454a2ea76c6b2889e40cde2e0ee9ad5e50
> http://www.linux-arm.org/git?p=u-boot-armdev.git;a=blobdiff;f=
> MAKEALL;h=67030a7355d56d751fdc4499e3c82d8fdb615d6e;hp=72cc4ee0
d90b5feb90ffe1fc48ddb6c3a0850907;hb=> 2e6979454a2ea76c6b2889e40cde2e0ee9ad5e50;hpb=ecad37d06857bb4f5
> 7bb95e0e0246a68b4d58161
> 
> and above idea of re-using single processor core cpu/arm* code, I 
> would propose to rename cpu/cortex_a8 to cpu/cortex_ax. And cover A9 
> with this, too.
This looks good to me. We just need to handle AuxControl reg bits and L2 cache
Bit differntly for A9.
> As I don't have an A9 nor know the details, I'm not sure if 
> this would 
> work in real life, but the basic idea sounds good for.
> 
> Maybe Peter can share his ideas or experience?
Regards,
Santosh