[U-Boot] V2 remove omap3 compiler warning wrt v7_flush_dcache_all

[U-Boot] V2 remove omap3 compiler warning wrt v7_flush_dcache_all

[Tom Rix]

This is against the arm/next branch. 

This fixes a problem with compile warnings for all OMAP3 targets. 

As per feedback, v7_flush_dcache_all was renamed to the generic
flush_dcache and moved to the omap3 level in the new file cache_flush.S. 

The original fix of using sys_proto.h is still used to fix the warning
for for get_device_type.

compile tested on MAKEALL arm. 
run tested on zoom1.

[U-Boot] [PATCH 1/2] ARM Cortex8 Rename and move v7_flush_dcache_all to flush_dcache

[Tom Rix]

Since there is only one version of flushing the dcache for
arm_cortex8, rename v7_flush_dcache_all to the the generic
name flush_dcache.  Because the function is intended for
only omap3 boards, move the function to the new file
cache_flush.S.

This change fixes the compiler warning all OMAP3 targets have

cpu.c: In function 'cleanup_before_linux':
cpu.c:64: warning: implicit declaration of function 'v7_flush_dcache_all'

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
---
 cpu/arm_cortexa8/cpu.c                 |    2 +-
 cpu/arm_cortexa8/omap3/Makefile        |    1 +
 cpu/arm_cortexa8/omap3/board.c         |    2 +-
 cpu/arm_cortexa8/omap3/cache_flush.S   |  118 ++++++++++++++++++++++++++++++++
 cpu/arm_cortexa8/start.S               |   87 -----------------------
 include/asm-arm/arch-omap3/sys_proto.h |    1 -
 include/asm-arm/cache.h                |    1 +
 7 files changed, 122 insertions(+), 90 deletions(-)
 create mode 100644 cpu/arm_cortexa8/omap3/cache_flush.S

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index fcb5775..7f57ee9 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -61,7 +61,7 @@ int cleanup_before_linux(void)
 	/* turn off L2 cache */
 	l2_cache_disable();
 	/* invalidate L2 cache also */
-	v7_flush_dcache_all(get_device_type());
+	flush_dcache(get_device_type());
 #endif
 	i = 0;
 	/* mem barrier to sync up things */
diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index 1fbd0dc..ea7a1cf 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	=  $(obj)lib$(SOC).a
 
 SOBJS	:= lowlevel_init.o
+SOBJS	+= cache_flush.o
 
 COBJS	+= board.o
 COBJS	+= cache.o
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 439ea6a..c082d8f 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -201,7 +201,7 @@ void s_init(void)
 	 * Right now flushing at low MPU speed.
 	 * Need to move after clock init
 	 */
-	v7_flush_dcache_all(get_device_type());
+	flush_dcache(get_device_type());
 #ifndef CONFIG_ICACHE_OFF
 	icache_enable();
 #endif
diff --git a/cpu/arm_cortexa8/omap3/cache_flush.S b/cpu/arm_cortexa8/omap3/cache_flush.S
new file mode 100644
index 0000000..0b5afc3
--- /dev/null
+++ b/cpu/arm_cortexa8/omap3/cache_flush.S
@@ -0,0 +1,118 @@
+/*
+ * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
+ *
+ * Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
+ *
+ * Copyright (c) 2001	Marius Gr??ger <mag@sysgo.de>
+ * Copyright (c) 2002	Alex Z??pke <azu@sysgo.de>
+ * Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
+ * Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003	Kshitij <kshitij@ti.com>
+ * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ *	flush_dcache()
+ *
+ *	Flush the whole D-cache.
+ *
+ *	Corrupted registers: r0-r5, r7, r9-r11
+ *
+ *	- mm	- mm_struct describing address space
+ */
+	.align 5
+.global flush_dcache
+flush_dcache:
+	stmfd	r13!, {r0 - r5, r7, r9 - r12, r14}
+
+	mov	r7, r0				@ take a backup of device type
+	cmp	r0, #0x3			@ check if the device type is
+						@ GP
+	moveq r12, #0x1				@ set up to invalide L2
+smi:	.word 0x01600070			@ Call SMI monitor (smieq)
+	cmp	r7, #0x3			@ compare again in case its
+						@ lost
+	beq	finished_inval			@ if GP device, inval done
+						@ above
+
+	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
+	ands	r3, r0, #0x7000000		@ extract loc from clidr
+	mov	r3, r3, lsr #23			@ left align loc bit field
+	beq	finished_inval			@ if loc is 0, then no need to
+						@ clean
+	mov	r10, #0				@ start clean at cache level 0
+inval_loop1:
+	add	r2, r10, r10, lsr #1		@ work out 3x current cache
+						@ level
+	mov	r1, r0, lsr r2			@ extract cache type bits from
+						@ clidr
+	and	r1, r1, #7			@ mask of the bits for current
+						@ cache only
+	cmp	r1, #2				@ see what cache we have at
+						@ this level
+	blt	skip_inval			@ skip if no cache, or just
+						@ i-cache
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
+						@ in cssr
+	mov	r2, #0				@ operand for mcr SBZ
+	mcr	p15, 0, r2, c7, c5, 4		@ flush prefetch buffer to
+						@ sych the new cssr&csidr,
+						@ with armv7 this is 'isb',
+						@ but we compile with armv5
+	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
+	and	r2, r1, #7			@ extract the length of the
+						@ cache lines
+	add	r2, r2, #4			@ add 4 (line length offset)
+	ldr	r4, =0x3ff
+	ands	r4, r4, r1, lsr #3		@ find maximum number on the
+						@ way size
+	clz	r5, r4				@ find bit position of way
+						@ size increment
+	ldr	r7, =0x7fff
+	ands	r7, r7, r1, lsr #13		@ extract max number of the
+						@ index size
+inval_loop2:
+	mov	r9, r4				@ create working copy of max
+						@ way size
+inval_loop3:
+	orr	r11, r10, r9, lsl r5		@ factor way and cache number
+						@ into r11
+	orr	r11, r11, r7, lsl r2		@ factor index number into r11
+	mcr	p15, 0, r11, c7, c6, 2		@ invalidate by set/way
+	subs	r9, r9, #1			@ decrement the way
+	bge	inval_loop3
+	subs	r7, r7, #1			@ decrement the index
+	bge	inval_loop2
+skip_inval:
+	add	r10, r10, #2			@ increment cache number
+	cmp	r3, r10
+	bgt	inval_loop1
+finished_inval:
+	mov	r10, #0				@ swith back to cache level 0
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
+						@ in cssr
+	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
+						@ with armv7 this is 'isb',
+						@ but we compile with armv5
+
+	ldmfd	r13!, {r0 - r5, r7, r9 - r12, pc}
+
+
diff --git a/cpu/arm_cortexa8/start.S b/cpu/arm_cortexa8/start.S
index 66b4820..c597d80 100644
--- a/cpu/arm_cortexa8/start.S
+++ b/cpu/arm_cortexa8/start.S
@@ -415,93 +415,6 @@ fiq:
 
 #endif
 
-/*
- *	v7_flush_dcache_all()
- *
- *	Flush the whole D-cache.
- *
- *	Corrupted registers: r0-r5, r7, r9-r11
- *
- *	- mm	- mm_struct describing address space
- */
-	.align 5
-.global v7_flush_dcache_all
-v7_flush_dcache_all:
-	stmfd	r13!, {r0 - r5, r7, r9 - r12, r14}
-
-	mov	r7, r0				@ take a backup of device type
-	cmp	r0, #0x3			@ check if the device type is
-						@ GP
-	moveq r12, #0x1				@ set up to invalide L2
-smi:	.word 0x01600070			@ Call SMI monitor (smieq)
-	cmp	r7, #0x3			@ compare again in case its
-						@ lost
-	beq	finished_inval			@ if GP device, inval done
-						@ above
-
-	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
-	ands	r3, r0, #0x7000000		@ extract loc from clidr
-	mov	r3, r3, lsr #23			@ left align loc bit field
-	beq	finished_inval			@ if loc is 0, then no need to
-						@ clean
-	mov	r10, #0				@ start clean at cache level 0
-inval_loop1:
-	add	r2, r10, r10, lsr #1		@ work out 3x current cache
-						@ level
-	mov	r1, r0, lsr r2			@ extract cache type bits from
-						@ clidr
-	and	r1, r1, #7			@ mask of the bits for current
-						@ cache only
-	cmp	r1, #2				@ see what cache we have at
-						@ this level
-	blt	skip_inval			@ skip if no cache, or just
-						@ i-cache
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
-						@ in cssr
-	mov	r2, #0				@ operand for mcr SBZ
-	mcr	p15, 0, r2, c7, c5, 4		@ flush prefetch buffer to
-						@ sych the new cssr&csidr,
-						@ with armv7 this is 'isb',
-						@ but we compile with armv5
-	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
-	and	r2, r1, #7			@ extract the length of the
-						@ cache lines
-	add	r2, r2, #4			@ add 4 (line length offset)
-	ldr	r4, =0x3ff
-	ands	r4, r4, r1, lsr #3		@ find maximum number on the
-						@ way size
-	clz	r5, r4				@ find bit position of way
-						@ size increment
-	ldr	r7, =0x7fff
-	ands	r7, r7, r1, lsr #13		@ extract max number of the
-						@ index size
-inval_loop2:
-	mov	r9, r4				@ create working copy of max
-						@ way size
-inval_loop3:
-	orr	r11, r10, r9, lsl r5		@ factor way and cache number
-						@ into r11
-	orr	r11, r11, r7, lsl r2		@ factor index number into r11
-	mcr	p15, 0, r11, c7, c6, 2		@ invalidate by set/way
-	subs	r9, r9, #1			@ decrement the way
-	bge	inval_loop3
-	subs	r7, r7, #1			@ decrement the index
-	bge	inval_loop2
-skip_inval:
-	add	r10, r10, #2			@ increment cache number
-	cmp	r3, r10
-	bgt	inval_loop1
-finished_inval:
-	mov	r10, #0				@ swith back to cache level 0
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
-						@ in cssr
-	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
-						@ with armv7 this is 'isb',
-						@ but we compile with armv5
-
-	ldmfd	r13!, {r0 - r5, r7, r9 - r12, pc}
-
-
 	.align	5
 .global reset_cpu
 reset_cpu:
diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h
index 7361d08..2881287 100644
--- a/include/asm-arm/arch-omap3/sys_proto.h
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -55,7 +55,6 @@ void secureworld_exit(void);
 void setup_auxcr(void);
 void try_unlock_memory(void);
 u32 get_boot_type(void);
-void v7_flush_dcache_all(u32);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h
index d0518be..853e2d1 100644
--- a/include/asm-arm/cache.h
+++ b/include/asm-arm/cache.h
@@ -41,5 +41,6 @@ static inline void invalidate_l2_cache(void)
 
 void l2_cache_enable(void);
 void l2_cache_disable(void);
+void flush_dcache(u32 device_type);
 
 #endif /* _ASM_CACHE_H */
-- 
1.6.0.5

[U-Boot] [PATCH 2/2] OMAP3 Fix compiler warning for get_device_type

[Tom Rix]

When MAKEALL arm is run, the omap3 board *.ERR files contains this
warning

cpu.c: In function 'cleanup_before_linux':
cpu.c:64: warning: implicit declaration of function 'get_device_type'

To fix this warning, use the declaration of get_device_type
in sys_proto.h

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
---
 cpu/arm_cortexa8/cpu.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 7f57ee9..ab59ab0 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -35,6 +35,9 @@
 #include <command.h>
 #include <asm/system.h>
 #include <asm/cache.h>
+#ifndef CONFIG_L2_OFF
+#include <asm/arch/sys_proto.h>
+#endif
 
 static void cache_flush(void);
 
-- 
1.6.0.5

[U-Boot] [PATCH 1/2] ARM Cortex8 Rename and move v7_flush_dcache_all to flush_dcache

[Woodruff, Richard]

> From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de] On
> Behalf Of Tom Rix
> Sent: Monday, July 06, 2009 11:48 AM

> Since there is only one version of flushing the dcache for
> arm_cortex8, rename v7_flush_dcache_all to the the generic
> name flush_dcache.  Because the function is intended for
> only omap3 boards, move the function to the new file
> cache_flush.S.

Minor point is file name or function name might change to be more reflective of what it does (cache_ops.S, and invalidate_dcache()).  As there is not really any 'flush' (cleaning out dirty entries to main memory).

Today the dcache is not even enabled in ARM ports.  To do so requires MMU to be enabled to properly map IO regions as non-cached.

As such all we ever need to do is possibly invalidate icache at run time (say you use Kermit to download something and try to execute it).

The dcache invalidate today is only there to setup cache in clean state before calling the kernel.

Later on a dcache-flush/icache-invalidate might need to be added if Dcache is actually enabled.

Regards,
Richard W.

[U-Boot] [PATCH 1/2] ARM Cortex8 Rename and move v7_flush_dcache_all to flush_dcache

[Tom]

Woodruff, Richard wrote:
>> From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de] On
>> Behalf Of Tom Rix
>> Sent: Monday, July 06, 2009 11:48 AM
>>     
>
>   
>> Since there is only one version of flushing the dcache for
>> arm_cortex8, rename v7_flush_dcache_all to the the generic
>> name flush_dcache.  Because the function is intended for
>> only omap3 boards, move the function to the new file
>> cache_flush.S.
>>     
>
> Minor point is file name or function name might change to be more reflective of what it does (cache_ops.S, and invalidate_dcache()).  As there is not really any 'flush' (cleaning out dirty entries to main memory).
>
>   
I will change the name to cache_ops.S
flush_dcache was chosen to match other boards/cpu's and one of the main 
reasons for this change.  If Jean is ok changing flush_dcache to 
invalidate_dcache,  I will make that change too.
Tom
 
> Today the dcache is not even enabled in ARM ports.  To do so requires MMU to be enabled to properly map IO regions as non-cached.
>
> As such all we ever need to do is possibly invalidate icache at run time (say you use Kermit to download something and try to execute it).
>
> The dcache invalidate today is only there to setup cache in clean state before calling the kernel.
>
> Later on a dcache-flush/icache-invalidate might need to be added if Dcache is actually enabled.
>
> Regards,
> Richard W.
>
>   

[U-Boot] [PATCH 1/2] ARM Cortex8 Rename and move v7_flush_dcache_all to flush_dcache

[Jean-Christophe PLAGNIOL-VILLARD]

On 21:57 Mon 06 Jul     , Tom wrote:
> Woodruff, Richard wrote:
> >>From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de] On
> >>Behalf Of Tom Rix
> >>Sent: Monday, July 06, 2009 11:48 AM
> >
> >>Since there is only one version of flushing the dcache for
> >>arm_cortex8, rename v7_flush_dcache_all to the the generic
> >>name flush_dcache.  Because the function is intended for
> >>only omap3 boards, move the function to the new file
> >>cache_flush.S.
> >
> >Minor point is file name or function name might change to be more reflective of what it does (cache_ops.S, and invalidate_dcache()).  As there is not really any 'flush' (cleaning out dirty entries to main memory).
> >
> I will change the name to cache_ops.S
I prefer cache.S
> flush_dcache was chosen to match other boards/cpu's and one of the
> main reasons for this change.  If Jean is ok changing flush_dcache
> to invalidate_dcache,  I will make that change too.
invalidate_dcache is fine for me

Best Regards,
J.

[U-Boot] [PATCH 1/2] ARM Cortex8 Rename and move v7_flush_dcache_all to flush_dcache

[Tom]

Jean-Christophe PLAGNIOL-VILLARD wrote:
>>
>> I will change the name to cache_ops.S
>>     
> I prefer cache.S
>   
cache.c is already taken.
Tom

[U-Boot] [PATCH 1/2] ARM Cortex8 Rename and move v7_flush_dcache_all to flush_dcache

[Jean-Christophe PLAGNIOL-VILLARD]

On 15:44 Tue 07 Jul     , Tom wrote:
> Jean-Christophe PLAGNIOL-VILLARD wrote:
> >>
> >>I will change the name to cache_ops.S
> >I prefer cache.S
> cache.c is already taken.
and contain nearly only assembly
so join everythink in cache.S will make more sense

Best Regards,
J.

[U-Boot] [PATCH 1/2] ARM Cortex8 Rename and move v7_flush_dcache_all to flush_dcache

[Wolfgang Denk]

Dear Tom Rix,

In message <1246898879-6567-2-git-send-email-Tom.Rix@windriver.com> you wrote:
> --===============0808050101==
> 
> Since there is only one version of flushing the dcache for
> arm_cortex8, rename v7_flush_dcache_all to the the generic
> name flush_dcache.  Because the function is intended for
> only omap3 boards, move the function to the new file
> cache_flush.S.
> 
> This change fixes the compiler warning all OMAP3 targets have
> 
> cpu.c: In function 'cleanup_before_linux':
> cpu.c:64: warning: implicit declaration of function 'v7_flush_dcache_all'
> 
> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
> ---
>  cpu/arm_cortexa8/cpu.c                 |    2 +-
>  cpu/arm_cortexa8/omap3/Makefile        |    1 +
>  cpu/arm_cortexa8/omap3/board.c         |    2 +-
>  cpu/arm_cortexa8/omap3/cache_flush.S   |  118 ++++++++++++++++++++++++++++++++
>  cpu/arm_cortexa8/start.S               |   87 -----------------------
>  include/asm-arm/arch-omap3/sys_proto.h |    1 -
>  include/asm-arm/cache.h                |    1 +
>  7 files changed, 122 insertions(+), 90 deletions(-)
>  create mode 100644 cpu/arm_cortexa8/omap3/cache_flush.S

Sorry, this patch does not apply any more:

Applying: ARM Cortex8 Rename and move v7_flush_dcache_all to flush_dcache
error: patch failed: cpu/arm_cortexa8/omap3/Makefile:26
error: cpu/arm_cortexa8/omap3/Makefile: patch does not apply
error: patch failed: cpu/arm_cortexa8/start.S:415
error: cpu/arm_cortexa8/start.S: patch does not apply
fatal: sha1 information is lacking or useless (cpu/arm_cortexa8/omap3/board.c).
Repository lacks necessary blobs to fall back on 3-way merge.
Cannot fall back to three-way merge.
Patch failed at 0001.

Please rebase and resubmit (also patch 2/2).

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Another megabytes the dust.

[U-Boot] [PATCH 1/2] ARM Cortex8 Rename and move v7_flush_dcache_all to flush_dcache

[Tom]

Yes.
Sorry about that. 
I will get something to you this week.
Tom

Wolfgang Denk wrote:
> Dear Tom Rix,
>
> In message <1246898879-6567-2-git-send-email-Tom.Rix@windriver.com> you wrote:
>   
>> --===============0808050101==
>>
>> Since there is only one version of flushing the dcache for
>> arm_cortex8, rename v7_flush_dcache_all to the the generic
>> name flush_dcache.  Because the function is intended for
>> only omap3 boards, move the function to the new file
>> cache_flush.S.
>>
>> This change fixes the compiler warning all OMAP3 targets have
>>
>> cpu.c: In function 'cleanup_before_linux':
>> cpu.c:64: warning: implicit declaration of function 'v7_flush_dcache_all'
>>
>> Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
>> ---
>>  cpu/arm_cortexa8/cpu.c                 |    2 +-
>>  cpu/arm_cortexa8/omap3/Makefile        |    1 +
>>  cpu/arm_cortexa8/omap3/board.c         |    2 +-
>>  cpu/arm_cortexa8/omap3/cache_flush.S   |  118 ++++++++++++++++++++++++++++++++
>>  cpu/arm_cortexa8/start.S               |   87 -----------------------
>>  include/asm-arm/arch-omap3/sys_proto.h |    1 -
>>  include/asm-arm/cache.h                |    1 +
>>  7 files changed, 122 insertions(+), 90 deletions(-)
>>  create mode 100644 cpu/arm_cortexa8/omap3/cache_flush.S
>>     
>
> Sorry, this patch does not apply any more:
>
> Applying: ARM Cortex8 Rename and move v7_flush_dcache_all to flush_dcache
> error: patch failed: cpu/arm_cortexa8/omap3/Makefile:26
> error: cpu/arm_cortexa8/omap3/Makefile: patch does not apply
> error: patch failed: cpu/arm_cortexa8/start.S:415
> error: cpu/arm_cortexa8/start.S: patch does not apply
> fatal: sha1 information is lacking or useless (cpu/arm_cortexa8/omap3/board.c).
> Repository lacks necessary blobs to fall back on 3-way merge.
> Cannot fall back to three-way merge.
> Patch failed at 0001.
>
> Please rebase and resubmit (also patch 2/2).
>
> Best regards,
>
> Wolfgang Denk
>
>