From mboxrd@z Thu Jan  1 00:00:00 1970
From: Dirk Behme <dirk.behme@googlemail.com>
Date: Sun, 16 Aug 2009 20:53:21 +0200
Subject: [U-Boot] D-Cache support for ARM?
Message-ID: <4A8855A1.50602@googlemail.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

Hi,

does anybody have some D-Cache enable code for ARM he likes to share?

I'm thinking about some generic code which takes MMU configuration 
from board config and sets up a 16k first level page table (1MB only 
pages). With this, D-Cache can be enabled for the specified memory 
regions and is flushed/disabled again before U-Boot exit.

MMU config entries in board config could look like

CONFIG_ARM_MMU_FIRST_LEVEL_ENTRY( \
<physical/virtual base address>, // 1:1 mapping \
<size in MB>, \
<cacheable/noncachable>, \
<bufferable/nonbufferable> )

E.g.

CONFIG_ARM_MMU_FIRST_LEVEL_ENTRY(0x000, 16, NONCACHEABLE, 
NONBUFFERABLE) // 16MB NOR
CONFIG_ARM_MMU_FIRST_LEVEL_ENTRY(0x100, 128,  CACHEABLE, BUFFERABLE) 
// 128 MB RAM
CONFIG_ARM_MMU_FIRST_LEVEL_ENTRY(0xF00, 1, NONCACHEABLE, 
NONBUFFERABLE) // 1MB register window

Having only a 1:1 mapping (physical/virtual) would be sufficient in a 
first step, as we are only interested in D-Cache support here (using 
the same memory map as currently done without MMU).

Opinions?

Best regards

Dirk