[U-Boot] 83xx and LCRR setting

Kim Phillips
2009-08-20T00:31:28Z

On Tue, 18 Aug 2009 15:23:47 +0200
Heiko Schocher <hs@denx.de> wrote:

> Hello Kim,

Hello Heiko, sorry for the late reply,

> I actually work on an u-boot mpc8321 port (mostly identical with the kmeter1
> port already in mainline), and I have to set the LCRR (Clock Ratio Register
> Reference Manual 10.3.1.14). As I see in
>
> cpu/mpc83xx/cpu_init.c cpu_init_f()
>
> this is done while running from flash. Hmm... the Reference manual
> says in chapter 10.3.1.14 page 474:
>
> NOTE
> For proper operation of the system, this register setting must not be altered
> while local bus memories or devices are being accessed. Special care needs
> to be taken when running instructions from an local bus controller memory.
>
> Hmm...
>
> On my board (and for example on the MPC832XEMDS) the flash is connected
> to the localbus ... and this register setting is done, while
> running from flash ... Hmm.. is this safe?

yeah, I'm not quite sure how that works myself!

> I only can set the LCRR register succesfully on my board port, if
> I set the LCRR_DBYP bit in the CONFIG_SYS_LCRR define, without it
> I couldn;t run u-boot (with it, it works fine)
>
> Unfortunately this LCRR_DBYP bit (0x80000000) is not documented in
> the MPC8323ERM ... there, it is just marked as reserved (and set
> to 1 on reset)
>
> So, it is ok, just to set this LCRR_DBYP bit? Or should the LCRR
> register only changed, if u-boot runs from ram? Or ...?

I'd say set the bit - my guess it the bit always existed, but it just
got documented in later parts' docs. E.g, this is from the mpc8315
documentation:

0 PBYP PLL bypass. This bit should be set when using low bus clock frequencies (66 MHz or lower).
When in PLL bypass mode, incoming data is captured in the middle of the bus clock cycle.
0 The PLL is enabled.
1 The PLL is bypassed.

hth,

Kim