[U-Boot] [PATCH 00/17] i386 Updates (touches some common drivers)

[U-Boot] [PATCH 00/17] i386 Updates (touches some common drivers)

[Graeme Russ]

Hi all,

I've been working at cleaning up some lingering loose ends on the i386
architecture. This patch series cleans up the bulk of them. This series
in itself is really a number of smaller incemental steps needed to get to
where I wanted to be.

Patches 1 though 6 only effect i386 specific code (cpu/i386, lib_i386 etc)
these patches are needed to get my development platform (eNET board) up
and running again (mainline has drifted away a little since I last worked
on this board and a new gcc caused some compile issues as well)

Patches 7 through 9 effect drivers outside the i386 build tree, however
as far as I can tell, these drivers are only used by the sc520_cdp and
sc520_spunk boards

Patches 10 and 11 fix up the sc520_cdp and sc520_spunk boards. I did not
include these fixes in the above patches because:
  a) The boards were already broken, and;
  b) It made more sense to me for this patch series to be a series of
     little steps towards the end fix rather than one big jumbled jump

As of patch 11, all i386 boards build clean. sc520_cdp and sc520_spunk
could probably work now, but without either board available to test, I
cannot confirm.

Patches 12 and 13 bring a couple of i386 components inline with u-boot
design philosophy

Patch 14 adds PCI support to the eNET board in preparation for getting
networking up and running

At this point, I noticed that my board would sometimes hang during Flash
initialisation - looked like probing the Boot Flash was conflicting with
the execute in place. I don't really know why it started to happen, but
I decided it was about time to move u-boot into RAM which is what patches
15 through 17 do. I have not implemented proper relocation. Sorry
Wolfgang, I know you'll hate what I have done, but it is the next step
towards what will hopefully one day be real relocation.

[U-Boot] [PATCH 01/17] Add errno.h to i386

[Graeme Russ]

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 include/asm-i386/errno.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)
 create mode 100644 include/asm-i386/errno.h

diff --git a/include/asm-i386/errno.h b/include/asm-i386/errno.h
new file mode 100644
index 0000000..4c82b50
--- /dev/null
+++ b/include/asm-i386/errno.h
@@ -0,0 +1 @@
+#include <asm-generic/errno.h>
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 02/17] Change inline asm global symbols to local

[Graeme Russ]

gcc 4.3.2 optimiser creates multiple copies of inline asm (who knows why)
Remove use of global names for labels to prevent 'symbol already defined'
errors

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 board/eNET/eNET.c      |    4 ++--
 cpu/i386/sc520/sc520.c |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 57dd635..27dabaa 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -51,9 +51,9 @@ void init_sc520_enet (void)
 
 	/* wait at least one millisecond */
 	asm("movl	$0x2000,%%ecx\n"
-	    "wait_loop:	pushl %%ecx\n"
+	    "0:	pushl %%ecx\n"
 	    "popl	%%ecx\n"
-	    "loop wait_loop\n": : : "ecx");
+	    "loop 0b\n": : : "ecx");
 
 	/* turn on the SDRAM write buffer */
 	write_mmcr_byte(SC520_DBCTL, 0x11);
diff --git a/cpu/i386/sc520/sc520.c b/cpu/i386/sc520/sc520.c
index ae3b500..1d79210 100644
--- a/cpu/i386/sc520/sc520.c
+++ b/cpu/i386/sc520/sc520.c
@@ -109,9 +109,9 @@ void init_sc520(void)
 
 	/* wait at least one millisecond */
 	asm("movl	$0x2000,%%ecx\n"
-	    "wait_loop:	pushl %%ecx\n"
+	    "0:		pushl %%ecx\n"
 	    "popl	%%ecx\n"
-	    "loop wait_loop\n": : : "ecx");
+	    "loop 0b\n": : : "ecx");
 
 	/* turn on the SDRAM write buffer */
 	write_mmcr_byte(SC520_DBCTL, 0x11);
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 03/17] Fix regression introduced by commit 8c63d47651f7

[Graeme Russ]

A local variable was deleted that should not have been

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 lib_i386/pcat_timer.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/lib_i386/pcat_timer.c b/lib_i386/pcat_timer.c
index e282f64..c351b23 100644
--- a/lib_i386/pcat_timer.c
+++ b/lib_i386/pcat_timer.c
@@ -25,10 +25,13 @@
 #include <asm/io.h>
 #include <asm/i8254.h>
 #include <asm/ibmpc.h>
+#include <asm/interrupt.h>
 
 #define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */
 #define TIMER2_VALUE 0x0a8e /* 440Hz */
 
+static int timer_init_done = 0;
+
 int timer_init(void)
 {
 	/* initialize timer 0 and 2
@@ -52,6 +55,8 @@ int timer_init(void)
 	irq_install_handler (0, timer_isr, NULL);
 	unmask_irq (0);
 
+	timer_init_done = 1;
+
 	return 0;
 }
 
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 04/17] Fix environment configuration for eNET board

[Graeme Russ]

The current configuration of the Environment has the redundant copy of the
environment in the Boot Flash - This was never the intent. The Environment
should instead be in the first two sectors of the first Strata Flash

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 include/configs/eNET.h |   11 +++++------
 1 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index dde4c83..4356714 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -188,14 +188,13 @@
   * Environment configuration
   */
 #define CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_OFFSET		0x20000 /*   Offset   of Environment Sector */
-#define CONFIG_ENV_SIZE			0x08000 /* Total Size of Environment Sector */
 #define CONFIG_ENV_SECT_SIZE		0x20000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE_1 + \
-					 CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR			CONFIG_SYS_FLASH_BASE_1
+/* Redundant Copy */
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_SYS_FLASH_BASE_1 + \
 					 CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SECT_SIZE
 
 
  /*-----------------------------------------------------------------------
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 05/17] Fix sc520 timer interrupt generation

[Graeme Russ]

The current implementation has the timer being started before the interrupt
handler is installed. It the interrupt occurs before the handler is
installed, the timer interrupt is never reset and the timer stops

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 cpu/i386/sc520/sc520_timer.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/cpu/i386/sc520/sc520_timer.c b/cpu/i386/sc520/sc520_timer.c
index 2cb8656..2a3425b 100644
--- a/cpu/i386/sc520/sc520_timer.c
+++ b/cpu/i386/sc520/sc520_timer.c
@@ -54,9 +54,6 @@ int timer_init(void)
 	write_mmcr_word (SC520_GPTMR1MAXCMPA, 100);
 	write_mmcr_word (SC520_GPTMR1CTL, 0xe009);
 
-	/* Clear the GP Timers status register */
-	write_mmcr_byte (SC520_GPTMRSTA, 0x07);
-
 	/* Register the SC520 specific timer interrupt handler */
 	register_timer_isr (sc520_timer_isr);
 
@@ -64,6 +61,9 @@ int timer_init(void)
 	irq_install_handler (0, timer_isr, NULL);
 	unmask_irq (0);
 
+	/* Clear the GP Timer 1 status register to get the show rolling*/
+	write_mmcr_byte (SC520_GPTMRSTA, 0x02);
+
 	return 0;
 }
 
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 06/17] Misc i386 PCI fixups

[Graeme Russ]

Change PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY (Originally done in
commit ff4e66e93c1a, regressed by commit 6d7f610b09f8)

Cast PCI_ROM_ADDRESS_MASK to u32

Wrap probe_pci_video() call inside #ifdef CONFIG_VIDEO

Change call to pci_find_class() to pci_find_devices(). This is based on a
patch submitted on 1st March 2007 (Patch that fixes the compilation errors
for sc520_cdp board) by mushtaq_k

This patch requires that PCI_VIDEO_VENDOR_ID and PCI_VIDEO_DEVICE_ID be
specified in the board config file.  Dummy values have been added for the
SC520 CDP board to enable compilation, but since I do not have one of these,
I do know what the values should be

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 board/sc520_cdp/sc520_cdp.c |    1 +
 cpu/i386/sc520/sc520_pci.c  |    2 +-
 include/configs/sc520_cdp.h |    2 ++
 lib_i386/pci.c              |    2 +-
 lib_i386/video_bios.c       |   18 +++++++++---------
 5 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c
index 830ec37..9cbe63e 100644
--- a/board/sc520_cdp/sc520_cdp.c
+++ b/board/sc520_cdp/sc520_cdp.c
@@ -27,6 +27,7 @@
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/ic/sc520.h>
+#include <asm/ic/pci.h>
 #include <ali512x.h>
 #include <spi.h>
 #include <netdev.h>
diff --git a/cpu/i386/sc520/sc520_pci.c b/cpu/i386/sc520/sc520_pci.c
index 38b837e..871ad0a 100644
--- a/cpu/i386/sc520/sc520_pci.c
+++ b/cpu/i386/sc520/sc520_pci.c
@@ -124,7 +124,7 @@ void pci_sc520_init(struct pci_controller *hose)
 		       SC520_PCI_MEMORY_BUS,
 		       SC520_PCI_MEMORY_PHYS,
 		       SC520_PCI_MEMORY_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,
diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index 3e2bb02..36e1224 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -206,6 +206,8 @@
  ************************************************************/
 #ifndef GRUSS_TESTING
 #define CONFIG_VIDEO			/* To enable video controller support */
+#define PCI_VIDEO_VENDOR_ID 0		/*Use the appropriate vendor ID*/
+#define PCI_VIDEO_DEVICE_ID 0		/*Use the appropriate Device ID*/
 #else
 #undef CONFIG_VIDEO
 #endif
diff --git a/lib_i386/pci.c b/lib_i386/pci.c
index 4331b04..f366bdc 100644
--- a/lib_i386/pci.c
+++ b/lib_i386/pci.c
@@ -60,7 +60,7 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
 	       vendor, device, class_code);
 #endif
 	/* Enable the rom addess decoder */
-	pci_write_config_dword(dev, PCI_ROM_ADDRESS, PCI_ROM_ADDRESS_MASK);
+	pci_write_config_dword(dev, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
 	pci_read_config_dword(dev, PCI_ROM_ADDRESS, &addr_reg);
 
 	if (!addr_reg) {
diff --git a/lib_i386/video_bios.c b/lib_i386/video_bios.c
index ce96a3e..c8060e6 100644
--- a/lib_i386/video_bios.c
+++ b/lib_i386/video_bios.c
@@ -76,18 +76,22 @@ void print_bios_bios_stat(void)
 }
 #endif
 
+#ifdef CONFIG_VIDEO
+
 #define PCI_CLASS_VIDEO             3
 #define PCI_CLASS_VIDEO_STD         0
 #define PCI_CLASS_VIDEO_PROG_IF_VGA 0
 
+static struct pci_device_id supported[] = {
+	{PCI_VIDEO_VENDOR_ID, PCI_VIDEO_DEVICE_ID},
+	{}
+};
 
 static u32 probe_pci_video(void)
 {
 	pci_dev_t devbusfn;
 
-	if ((devbusfn = pci_find_class(PCI_CLASS_VIDEO,
-				       PCI_CLASS_VIDEO_STD,
-				       PCI_CLASS_VIDEO_PROG_IF_VGA, 0)) != -1) {
+	if ((devbusfn = pci_find_devices(supported, 0) != -1)) {
 		u32 old;
 		u32 addr;
 
@@ -103,7 +107,7 @@ static u32 probe_pci_video(void)
 
 		/* Test the ROM decoder, do the device support a rom? */
 		pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old);
-		pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, PCI_ROM_ADDRESS_MASK);
+		pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
 		pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr);
 		pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old);
 
@@ -133,11 +137,6 @@ static u32 probe_pci_video(void)
 	return 0;
 }
 
-
-#endif
-
-#ifdef CONFIG_VIDEO
-
 static int probe_isa_video(void)
 {
 	u32 ptr;
@@ -220,3 +219,4 @@ int video_bios_init(void)
 
 }
 #endif
+#endif
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 07/17] Misc SATA fixups

[Graeme Russ]

Cast first parameter to sata_cpy()

In /drivers/block/ata_piix.h, ata_id_has_lba48(), ata_id_has_lba(),
ata_id_has_dma(), ata_id_u32(), ata_id_u64() are all defined in
include/libata.h which is included in ata.h which is included by all files
which include ata_piix.h (only ata_piix.c) so these definitions are
supurflous to (and conlict with) this in libata.h. Interestingly, my
compiler complains about ata_id_u64 already being defined, but not
ata_id_u32

ata_dump_id() is defined in include/libata.h and should not be static
(maybe should even use ata_dump_id() in libata.c

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 drivers/block/ata_piix.c |   10 +++++-----
 drivers/block/ata_piix.h |   15 +--------------
 2 files changed, 6 insertions(+), 19 deletions(-)

diff --git a/drivers/block/ata_piix.c b/drivers/block/ata_piix.c
index 549de31..c81d11a 100644
--- a/drivers/block/ata_piix.c
+++ b/drivers/block/ata_piix.c
@@ -310,7 +310,7 @@ sata_bus_softreset (int num)
 	}
 
 	if (status & ATA_BUSY)
-		printf ("ata%u is slow to respond,plz be patient\n", port);
+		printf ("ata%u is slow to respond,plz be patient\n", num);
 
 	while ((status & ATA_BUSY)) {
 		msleep (100);
@@ -318,7 +318,7 @@ sata_bus_softreset (int num)
 	}
 
 	if (status & ATA_BUSY) {
-		printf ("ata%u failed to respond : ", port);
+		printf ("ata%u failed to respond : ", num);
 		printf ("bus reset failed\n");
 		return 1;
 	}
@@ -389,11 +389,11 @@ sata_identify (int num, int dev)
 		return;
 	}
 
-	sata_cpy (sata_dev_desc[devno].revision, iop->fw_rev,
+	sata_cpy ((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
 		  sizeof (sata_dev_desc[devno].revision));
-	sata_cpy (sata_dev_desc[devno].vendor, iop->model,
+	sata_cpy ((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
 		  sizeof (sata_dev_desc[devno].vendor));
-	sata_cpy (sata_dev_desc[devno].product, iop->serial_no,
+	sata_cpy ((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
 		  sizeof (sata_dev_desc[devno].product));
 	strswab (sata_dev_desc[devno].revision);
 	strswab (sata_dev_desc[devno].vendor);
diff --git a/drivers/block/ata_piix.h b/drivers/block/ata_piix.h
index 11885af..9157cf8 100644
--- a/drivers/block/ata_piix.h
+++ b/drivers/block/ata_piix.h
@@ -37,20 +37,7 @@ struct sata_port {
 
 /***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/
 #ifdef SATA_DECL		/*SATA library specific declarations */
-#define ata_id_has_lba48(id)    ((id)[83] & (1 << 10))
-#define ata_id_has_lba(id)      ((id)[49] & (1 << 9))
-#define ata_id_has_dma(id)      ((id)[49] & (1 << 8))
-#define ata_id_u32(id,n)        \
-	(((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
-#define ata_id_u64(id,n)        \
-	(((u64) (id)[(n) + 3] << 48) | \
-	((u64) (id)[(n) + 2] << 32) | \
-	((u64) (id)[(n) + 1] << 16) | \
-	((u64) (id)[(n) + 0]) )
-#endif
-
-#ifdef SATA_DECL		/*SATA library specific declarations */
-static inline void
+inline void
 ata_dump_id (u16 * id)
 {
 	PRINTF ("49 = 0x%04x  "
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 08/17] Misc ti_pci1410a fixups

[Graeme Russ]

Removed do_pinit() - now declared in cmd_pcmcia.c

Added #define CONFIG_CMD_PCMCIA around pcmcia_off() in line with other
PCMCIA drivers

signed/unsigned type fixups

Added semi-colon after default: label as required by newer gcc

The only board that appears to use this driver is the sc520_spunk which
is very old and very likely very broken anyway. I do not have one to test
whether this patch breaks anything functionaly, I have can only check
that it compiles without warning or error

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 drivers/pcmcia/ti_pci1410a.c |   62 ++++++++++++-----------------------------
 1 files changed, 18 insertions(+), 44 deletions(-)

diff --git a/drivers/pcmcia/ti_pci1410a.c b/drivers/pcmcia/ti_pci1410a.c
index 6ab9759..4ac2e0f 100644
--- a/drivers/pcmcia/ti_pci1410a.c
+++ b/drivers/pcmcia/ti_pci1410a.c
@@ -68,13 +68,12 @@
 
 int pcmcia_on(int ide_base_bus);
 
-static int  pcmcia_off(void);
 static int  hardware_disable(int slot);
 static int  hardware_enable(int slot);
 static int  voltage_set(int slot, int vcc, int vpp);
 static void print_funcid(int func);
-static void print_fixed(volatile uchar *p);
-static int  identify(volatile uchar *p);
+static void print_fixed(volatile char *p);
+static int  identify(volatile char *p);
 static int  check_ide_device(int slot, int ide_base_bus);
 
 
@@ -86,33 +85,6 @@ const char *indent = "\t   ";
 /* ------------------------------------------------------------------------- */
 
 
-int do_pinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-#ifndef CONFIG_SYS_FIRST_PCMCIA_BUS
-# define CONFIG_SYS_FIRST_PCMCIA_BUS 0
-#endif
-
-	int rcode = 0;
-
-	if (argc != 2) {
-		printf ("Usage: pinit {on | off}\n");
-		return 1;
-	}
-	if (strcmp(argv[1],"on") == 0) {
-		rcode = pcmcia_on(CONFIG_SYS_FIRST_PCMCIA_BUS);
-	} else if (strcmp(argv[1],"off") == 0) {
-		rcode = pcmcia_off();
-	} else {
-		printf ("Usage: pinit {on | off}\n");
-		return 1;
-	}
-
-	return rcode;
-}
-
-/* ------------------------------------------------------------------------- */
-
-
 static struct pci_device_id supported[] = {
 	{ PCI_VENDOR_ID_TI, 0xac50 }, /* Ti PCI1410A */
 	{ PCI_VENDOR_ID_TI, 0xac56 }, /* Ti PCI1510 */
@@ -245,7 +217,8 @@ int pcmcia_on(int ide_base_bus)
 /* ------------------------------------------------------------------------- */
 
 
-static int pcmcia_off (void)
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_off (void)
 {
 	int slot = 0;
 
@@ -285,6 +258,7 @@ static int pcmcia_off (void)
 	return 0;
 }
 
+#endif
 
 /* ------------------------------------------------------------------------- */
 
@@ -294,9 +268,9 @@ static int pcmcia_off (void)
 int ide_devices_found;
 static int check_ide_device(int slot, int ide_base_bus)
 {
-	volatile uchar *ident = NULL;
-	volatile uchar *feature_p[MAX_FEATURES];
-	volatile uchar *p, *start;
+	volatile char *ident = NULL;
+	volatile char *feature_p[MAX_FEATURES];
+	volatile char *p, *start;
 	int n_features = 0;
 	uchar func_id = ~0;
 	uchar code, len;
@@ -314,7 +288,7 @@ static int check_ide_device(int slot, int ide_base_bus)
 		return 1;
 	}
 
-	start = p = (volatile uchar *) pcmcia_cis_ptr;
+	start = p = (volatile char *) pcmcia_cis_ptr;
 
 	while ((p - start) < MAX_TUPEL_SZ) {
 
@@ -417,7 +391,7 @@ static int voltage_set(int slot, int vcc, int vpp)
 		socket_control |= 0x30;
 		break;
 	case 0:
-	default:
+	default: ;
 	}
 
 	switch (vpp) {
@@ -431,7 +405,7 @@ static int voltage_set(int slot, int vcc, int vpp)
 		socket_control |= 0x3;
 		break;
 	case 0:
-	default:
+	default: ;
 	}
 
 	writel(socket_control, reg);
@@ -537,7 +511,7 @@ static void print_funcid(int func)
 
 /* ------------------------------------------------------------------------- */
 
-static void print_fixed(volatile uchar *p)
+static void print_fixed(volatile char *p)
 {
 	if (p == NULL)
 		return;
@@ -605,17 +579,17 @@ static void print_fixed(volatile uchar *p)
 #define MAX_IDENT_CHARS		64
 #define	MAX_IDENT_FIELDS	4
 
-static uchar *known_cards[] = {
+static char *known_cards[] = {
 	"ARGOSY PnPIDE D5",
 	NULL
 };
 
-static int identify(volatile uchar *p)
+static int identify(volatile char *p)
 {
-	uchar id_str[MAX_IDENT_CHARS];
-	uchar data;
-	uchar *t;
-	uchar **card;
+	char id_str[MAX_IDENT_CHARS];
+	char data;
+	char *t;
+	char **card;
 	int i, done;
 
 	if (p == NULL)
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 09/17] Misc ds1722 fixups

[Graeme Russ]

This patch is based on a patch submitted by Jean-Christophe PLAGNIOL-VILLARD
on 18th May 2008 as part of a general i386 / sc520 fixup which was never
applied

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 drivers/hwmon/ds1722.c |    3 ++-
 include/ds1722.h       |   32 ++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+), 1 deletions(-)
 create mode 100644 include/ds1722.h

diff --git a/drivers/hwmon/ds1722.c b/drivers/hwmon/ds1722.c
index 7e2f1ed..a46cd4d 100644
--- a/drivers/hwmon/ds1722.c
+++ b/drivers/hwmon/ds1722.c
@@ -1,6 +1,7 @@
 
 #include <common.h>
-#include <ssi.h>
+#include <asm/ic/ssi.h>
+#include <ds1722.h>
 
 static void ds1722_select(int dev)
 {
diff --git a/include/ds1722.h b/include/ds1722.h
new file mode 100644
index 0000000..44f0830
--- /dev/null
+++ b/include/ds1722.h
@@ -0,0 +1,32 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DS1722_H_
+#define _DS1722_H_
+
+#define DS1722_RESOLUTION_8BIT	0x0
+#define DS1722_RESOLUTION_9BIT	0x1
+#define DS1722_RESOLUTION_10BIT	0x2
+#define DS1722_RESOLUTION_11BIT	0x3
+#define DS1722_RESOLUTION_12BIT	0x4
+
+int ds1722_probe(int dev);
+
+#endif /* _DS1722_H_ */
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 10/17] Fixup sc520_spunk board

[Graeme Russ]

Primary intent is to resolve build errors for this board which has been
neglected for a very long time. I do not have one of these boards, so I
cannot test functionality

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 board/sc520_spunk/sc520_spunk.c |   33 +++++++++++++++++++++++++++++++--
 include/configs/sc520_spunk.h   |    2 ++
 2 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c
index d3bd869..36a0a8e 100644
--- a/board/sc520_spunk/sc520_spunk.c
+++ b/board/sc520_spunk/sc520_spunk.c
@@ -24,11 +24,13 @@
 
 #include <common.h>
 #include <pci.h>
-#include <ssi.h>
 #include <netdev.h>
+#include <ds1722.h>
 #include <asm/io.h>
 #include <asm/pci.h>
 #include <asm/ic/sc520.h>
+#include <asm/ic/pci.h>
+#include <asm/ic/ssi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -112,7 +114,7 @@ static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev
 	};
 	static int next_irq_index=0;
 
-	char tmp_pin;
+	uchar tmp_pin;
 	int pin;
 
 	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
@@ -637,6 +639,33 @@ void ssi_chip_select(int dev)
 	}
 }
 
+void spi_eeprom_probe(int x)
+{
+}
+
+int spi_eeprom_read(int x, int offset, uchar *buffer, int len)
+{
+       return 0;
+}
+
+int spi_eeprom_write(int x, int offset, uchar *buffer, int len)
+{
+       return 0;
+}
+
+void mw_eeprom_probe(int x)
+{
+}
+
+int mw_eeprom_read(int x, int offset, uchar *buffer, int len)
+{
+       return 0;
+}
+
+int mw_eeprom_write(int x, int offset, uchar *buffer, int len)
+{
+       return 0;
+}
 
 void spi_init_f(void)
 {
diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
index d42ef84..f3fc960 100644
--- a/include/configs/sc520_spunk.h
+++ b/include/configs/sc520_spunk.h
@@ -37,6 +37,7 @@
 
 #define CONFIG_X86		1	/* This is a X86 CPU		*/
 #define CONFIG_SYS_SC520	1	/* Include support for AMD SC520 */
+#define CONFIG_SYS_SC520_SSI
 
 #define CONFIG_SYS_SDRAM_PRECHARGE_DELAY 6     /* 6T */
 #define CONFIG_SYS_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
@@ -218,6 +219,7 @@
 #define CONFIG_SYS_PCMCIA_CIS_WIN_SIZE     0x00100000
 #define CONFIG_SYS_PCMCIA_IO_WIN           0xe000
 #define CONFIG_SYS_PCMCIA_IO_WIN_SIZE      16
+#define CONFIG_PCMCIA_SLOT_A /* TODO: Check this */
 
 /************************************************************
  * DISK Partition support
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 11/17] Misc sc520 cdp fixups

[Graeme Russ]

Now that the PCI, SATA et al compile problems have been resolved, the
cludge that was applied to avoid them can be removed

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 include/configs/sc520_cdp.h |   22 ----------------------
 1 files changed, 0 insertions(+), 22 deletions(-)

diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index 36e1224..214a9af 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h
@@ -30,7 +30,6 @@
 
 #define CONFIG_SKIP_RELOCATE_UBOOT
 
-#define GRUSS_TESTING
 /*
  * High Level Configuration Options
  * (easy to change)
@@ -85,11 +84,7 @@
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_PCI
-#ifndef GRUSS_TESTING
 #define CONFIG_CMD_SATA
-#else
-#undef CONFIG_CMD_SATA
-#endif
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_EEPROM
@@ -181,17 +176,10 @@
 /************************************************************
 *SATA/Native Stuff
 ************************************************************/
-#ifndef GRUSS_TESTING
 #define CONFIG_SYS_SATA_MAXBUS         2       /*Max Sata buses supported */
 #define CONFIG_SYS_SATA_DEVS_PER_BUS   2      /*Max no. of devices per bus/port */
 #define CONFIG_SYS_SATA_MAX_DEVICE     (CONFIG_SYS_SATA_MAXBUS* CONFIG_SYS_SATA_DEVS_PER_BUS)
 #define CONFIG_ATA_PIIX		1       /*Supports ata_piix driver */
-#else
-#undef CONFIG_SYS_SATA_MAXBUS
-#undef CONFIG_SYS_SATA_DEVS_PER_BUS
-#undef CONFIG_SYS_SATA_MAX_DEVICE
-#undef CONFIG_ATA_PIIX
-#endif
 
 
 /************************************************************
@@ -204,13 +192,9 @@
 /************************************************************
  * Video/Keyboard support
  ************************************************************/
-#ifndef GRUSS_TESTING
 #define CONFIG_VIDEO			/* To enable video controller support */
 #define PCI_VIDEO_VENDOR_ID 0		/*Use the appropriate vendor ID*/
 #define PCI_VIDEO_DEVICE_ID 0		/*Use the appropriate Device ID*/
-#else
-#undef CONFIG_VIDEO
-#endif
 #define CONFIG_I8042_KBD
 #define CONFIG_SYS_ISA_IO 0
 
@@ -223,7 +207,6 @@
 /*
  * PCI stuff
  */
-#ifndef GRUSS_TESTING
 #define CONFIG_PCI                                /* include pci support */
 #define CONFIG_PCI_PNP                            /* pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW
@@ -232,11 +215,6 @@
 #define	CONFIG_SYS_SECOND_PCI_IRQ  9
 #define CONFIG_SYS_THIRD_PCI_IRQ   11
 #define	CONFIG_SYS_FORTH_PCI_IRQ   15
-#else
-#undef CONFIG_PCI
-#undef CONFIG_PCI_PNP
-#undef CONFIG_PCI_SCAN_SHOW
-#endif
 
 
 #endif	/* __CONFIG_H */
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 12/17] Replace [read, write]_mmcr_[byte, word, long] with memory mapped structure

[Graeme Russ]

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 board/eNET/eNET.c               |   86 ++++----
 board/sc520_cdp/flash.c         |   14 +-
 board/sc520_cdp/sc520_cdp.c     |  171 ++++++++--------
 board/sc520_spunk/sc520_spunk.c |  211 ++++++++++----------
 cpu/i386/sc520/sc520.c          |   71 ++------
 cpu/i386/sc520/sc520_pci.c      |   66 +++---
 cpu/i386/sc520/sc520_ssi.c      |   28 ++--
 cpu/i386/sc520/sc520_timer.c    |   31 ++--
 include/asm-i386/ic/sc520.h     |  417 ++++++++++++++++++++++-----------------
 9 files changed, 550 insertions(+), 545 deletions(-)

diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 27dabaa..29cf295 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -46,7 +46,7 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
 void init_sc520_enet (void)
 {
 	/* Set CPU Speed to 100MHz */
-	write_mmcr_byte(SC520_CPUCTL, 1);
+	sc520_mmcr->cpuctl = 0x01;
 	gd->cpu_clk = 100000000;
 
 	/* wait at least one millisecond */
@@ -56,7 +56,7 @@ void init_sc520_enet (void)
 	    "loop 0b\n": : : "ecx");
 
 	/* turn on the SDRAM write buffer */
-	write_mmcr_byte(SC520_DBCTL, 0x11);
+	sc520_mmcr->dbctl = 0x11;
 
 	/* turn on the cache and disable write through */
 	asm("movl	%%cr0, %%eax\n"
@@ -71,51 +71,51 @@ int board_init(void)
 {
 	init_sc520_enet();
 
-	write_mmcr_byte(SC520_GPCSRT, 0x01);		/* GP Chip Select Recovery Time */
-	write_mmcr_byte(SC520_GPCSPW, 0x07);		/* GP Chip Select Pulse Width */
-	write_mmcr_byte(SC520_GPCSOFF, 0x00);		/* GP Chip Select Offset */
-	write_mmcr_byte(SC520_GPRDW, 0x05);		/* GP Read pulse width */
-	write_mmcr_byte(SC520_GPRDOFF, 0x01);		/* GP Read offset */
-	write_mmcr_byte(SC520_GPWRW, 0x05);		/* GP Write pulse width */
-	write_mmcr_byte(SC520_GPWROFF, 0x01);		/* GP Write offset */
-
-	write_mmcr_word(SC520_PIODATA15_0, 0x0630);	/* PIO15_PIO0 Data */
-	write_mmcr_word(SC520_PIODATA31_16, 0x2000);	/* PIO31_PIO16 Data */
-	write_mmcr_word(SC520_PIODIR31_16, 0x2000);	/* GPIO Direction */
-	write_mmcr_word(SC520_PIODIR15_0, 0x87b5);	/* GPIO Direction */
-	write_mmcr_word(SC520_PIOPFS31_16, 0x0dfe);	/* GPIO pin function 31-16 reg */
-	write_mmcr_word(SC520_PIOPFS15_0, 0x200a);	/* GPIO pin function 15-0 reg */
-	write_mmcr_byte(SC520_CSPFS, 0x00f8);		/* Chip Select Pin Function Select */
-
-	write_mmcr_long(SC520_PAR2, 0x200713f8);	/* Uart A (GPCS0, 0x013f8, 8 Bytes) */
-	write_mmcr_long(SC520_PAR3, 0x2c0712f8);	/* Uart B (GPCS3, 0x012f8, 8 Bytes) */
-	write_mmcr_long(SC520_PAR4, 0x300711f8);	/* Uart C (GPCS4, 0x011f8, 8 Bytes) */
-	write_mmcr_long(SC520_PAR5, 0x340710f8);	/* Uart D (GPCS5, 0x010f8, 8 Bytes) */
-	write_mmcr_long(SC520_PAR6, 0xe3ffc000);	/* SDRAM (0x00000000, 128MB) */
-	write_mmcr_long(SC520_PAR7, 0xaa3fd000);	/* StrataFlash (ROMCS1, 0x10000000, 16MB) */
-	write_mmcr_long(SC520_PAR8, 0xca3fd100);	/* StrataFlash (ROMCS2, 0x11000000, 16MB) */
-	write_mmcr_long(SC520_PAR9, 0x4203d900);	/* SRAM (GPCS0, 0x19000000, 1MB) */
-	write_mmcr_long(SC520_PAR10, 0x4e03d910);	/* SRAM (GPCS3, 0x19100000, 1MB) */
-	write_mmcr_long(SC520_PAR11, 0x50018100);	/* DP-RAM (GPCS4, 0x18100000, 4kB) */
-	write_mmcr_long(SC520_PAR12, 0x54020000);	/* CFLASH1 (0x200000000, 4kB) */
-	write_mmcr_long(SC520_PAR13, 0x5c020001);	/* CFLASH2 (0x200010000, 4kB) */
-/*	write_mmcr_long(SC520_PAR14, 0x8bfff800); */	/* BOOTCS at  0x18000000 */
-/*	write_mmcr_long(SC520_PAR15, 0x38201000); */	/* LEDs etc (GPCS6, 0x1000, 20 Bytes */
+	sc520_mmcr->gpcsrt = 0x01;		/* GP Chip Select Recovery Time */
+	sc520_mmcr->gpcspw = 0x07;		/* GP Chip Select Pulse Width */
+	sc520_mmcr->gpcsoff = 0x00;		/* GP Chip Select Offset */
+	sc520_mmcr->gprdw = 0x05;		/* GP Read pulse width */
+	sc520_mmcr->gprdoff = 0x01;		/* GP Read offset */
+	sc520_mmcr->gpwrw = 0x05;		/* GP Write pulse width */
+	sc520_mmcr->gpwroff = 0x01;		/* GP Write offset */
+
+	sc520_mmcr->piodata15_0 = 0x0630;	/* PIO15_PIO0 Data */
+	sc520_mmcr->piodata31_16 = 0x2000;	/* PIO31_PIO16 Data */
+	sc520_mmcr->piodir31_16 = 0x2000;	/* GPIO Direction */
+	sc520_mmcr->piodir15_0 = 0x87b5;	/* GPIO Direction */
+	sc520_mmcr->piopfs31_16 = 0x0dfe;	/* GPIO pin function 31-16 reg */
+	sc520_mmcr->piopfs15_0 = 0x200a;	/* GPIO pin function 15-0 reg */
+	sc520_mmcr->cspfs = 0x00f8;		/* Chip Select Pin Function Select */
+
+	sc520_mmcr->par[2] = 0x200713f8;	/* Uart A (GPCS0, 0x013f8, 8 Bytes) */
+	sc520_mmcr->par[3] = 0x2c0712f8;	/* Uart B (GPCS3, 0x012f8, 8 Bytes) */
+	sc520_mmcr->par[4] = 0x300711f8;	/* Uart C (GPCS4, 0x011f8, 8 Bytes) */
+	sc520_mmcr->par[5] = 0x340710f8;	/* Uart D (GPCS5, 0x010f8, 8 Bytes) */
+	sc520_mmcr->par[6] =  0xe3ffc000;	/* SDRAM (0x00000000, 128MB) */
+	sc520_mmcr->par[7] = 0xaa3fd000;	/* StrataFlash (ROMCS1, 0x10000000, 16MB) */
+	sc520_mmcr->par[8] = 0xca3fd100;	/* StrataFlash (ROMCS2, 0x11000000, 16MB) */
+	sc520_mmcr->par[9] = 0x4203d900;	/* SRAM (GPCS0, 0x19000000, 1MB) */
+	sc520_mmcr->par[10] = 0x4e03d910;	/* SRAM (GPCS3, 0x19100000, 1MB) */
+	sc520_mmcr->par[11] = 0x50018100;	/* DP-RAM (GPCS4, 0x18100000, 4kB) */
+	sc520_mmcr->par[12] = 0x54020000;	/* CFLASH1 (0x200000000, 4kB) */
+	sc520_mmcr->par[13] = 0x5c020001;	/* CFLASH2 (0x200010000, 4kB) */
+/*	sc520_mmcr->par14 = 0x8bfff800; */	/* BOOTCS at  0x18000000 */
+/*	sc520_mmcr->par15 = 0x38201000; */	/* LEDs etc (GPCS6, 0x1000, 20 Bytes */
 
 	/* Disable Watchdog */
-	write_mmcr_word(0x0cb0, 0x3333);
-	write_mmcr_word(0x0cb0, 0xcccc);
-	write_mmcr_word(0x0cb0, 0x0000);
+	sc520_mmcr->wdtmrctl = 0x3333;
+	sc520_mmcr->wdtmrctl = 0xcccc;
+	sc520_mmcr->wdtmrctl = 0x0000;
 
 	/* Chip Select Configuration */
-	write_mmcr_word(SC520_BOOTCSCTL, 0x0033);
-	write_mmcr_word(SC520_ROMCS1CTL, 0x0615);
-	write_mmcr_word(SC520_ROMCS2CTL, 0x0615);
-
-	write_mmcr_byte(SC520_ADDDECCTL, 0x02);
-	write_mmcr_byte(SC520_UART1CTL, 0x07);
-	write_mmcr_byte(SC520_SYSARBCTL,0x06);
-	write_mmcr_word(SC520_SYSARBMENB, 0x0003);
+	sc520_mmcr->bootcsctl = 0x0033;
+	sc520_mmcr->romcs1ctl = 0x0615;
+	sc520_mmcr->romcs2ctl = 0x0615;
+
+	sc520_mmcr->adddecctl = 0x02;
+	sc520_mmcr->uart1ctl = 0x07;
+	sc520_mmcr->sysarbctl = 0x06;
+	sc520_mmcr->sysarbmenb = 0x0003;
 
 	/* Crystal is 33.000MHz */
 	gd->bus_clk = 33000000;
diff --git a/board/sc520_cdp/flash.c b/board/sc520_cdp/flash.c
index dcb8c57..64831b7 100644
--- a/board/sc520_cdp/flash.c
+++ b/board/sc520_cdp/flash.c
@@ -337,12 +337,12 @@ done:	;
 	unsigned micro; \
 	unsigned milli=0; \
 	\
-	micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+	micro = sc520_mmcr->swtmrmilli; \
 	 \
 	for (;;) { \
 		\
-		milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
-		micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \
+		milli += sc520_mmcr->swtmrmilli; \
+		micro = sc520_mmcr->swtmrmicro; \
 		\
 		if ((delay) <= (micro + (milli * 1000))) { \
 			break; \
@@ -364,12 +364,12 @@ static u32 _amd_erase_flash(u32 addr, u32 sector)
 	/* Sector erase command comes last */
 	*(volatile u32*)(addr + sector) = 0x30303030;
 
-	elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+	elapsed = sc520_mmcr->swtmrmilli; /* dummy read */
 	elapsed = 0;
 	__udelay(50);
 	while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) {
 
-		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		elapsed += sc520_mmcr->swtmrmilli;
 		if (elapsed > ((CONFIG_SYS_FLASH_ERASE_TOUT/CONFIG_SYS_HZ) * 1000)) {
 			*(volatile u32*)(addr) = 0xf0f0f0f0;
 			return 1;
@@ -487,12 +487,12 @@ static int _amd_write_word(unsigned start, unsigned dest, unsigned data)
 
 	dest2[0] = data;
 
-	elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+	elapsed = sc520_mmcr->swtmrmilli; /* dummy read */
 	elapsed = 0;
 
 	/* data polling for D7 */
 	while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) {
-		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		elapsed += sc520_mmcr->swtmrmilli;
 		if (elapsed > ((CONFIG_SYS_FLASH_WRITE_TOUT/CONFIG_SYS_HZ) * 1000)) {
 			addr2[0] = 0xf0f0f0f0;
 			return 1;
diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c
index 9cbe63e..9312f4f 100644
--- a/board/sc520_cdp/sc520_cdp.c
+++ b/board/sc520_cdp/sc520_cdp.c
@@ -58,61 +58,60 @@ DECLARE_GLOBAL_DATA_PTR;
 static void irq_init(void)
 {
 	/* disable global interrupt mode */
-	write_mmcr_byte(SC520_PICICR, 0x40);
+	sc520_mmcr->picicr = 0x40;
 
 	/* set all irqs to edge */
-	write_mmcr_byte(SC520_MPICMODE, 0x00);
-	write_mmcr_byte(SC520_SL1PICMODE, 0x00);
-	write_mmcr_byte(SC520_SL2PICMODE, 0x00);
+	sc520_mmcr->pic_mode[0] = 0x00;
+	sc520_mmcr->pic_mode[1] = 0x00;
+	sc520_mmcr->pic_mode[2] = 0x00;
 
 	/* active low polarity on PIC interrupt pins,
 	 *  active high polarity on all other irq pins */
-	write_mmcr_word(SC520_INTPINPOL, 0x0000);
+	sc520_mmcr->intpinpol = 0x0000;
 
 	/* set irq number mapping */
-	write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */
-	write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
-	write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
-	write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */
-	write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
-	write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
-	write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
-	write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
-	write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
-	write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
-	write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
-	write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED);      /* disable Synchronius serial INT */
-	write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
-	write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
-	write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
-	write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
-	write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
+	sc520_mmcr->gp_tmr_int_map[0] = SC520_IRQ_DISABLED;	/* disable GP timer 0 INT */
+	sc520_mmcr->gp_tmr_int_map[1] = SC520_IRQ_DISABLED;	/* disable GP timer 1 INT */
+	sc520_mmcr->gp_tmr_int_map[2] = SC520_IRQ_DISABLED;	/* disable GP timer 2 INT */
+	sc520_mmcr->pit_int_map[0] = SC520_IRQ0;		/* Set PIT timer 0 INT to IRQ0 */
+	sc520_mmcr->pit_int_map[1] = SC520_IRQ_DISABLED;	/* disable PIT timer 1 INT */
+	sc520_mmcr->pit_int_map[2] = SC520_IRQ_DISABLED;	/* disable PIT timer 2 INT */
+	sc520_mmcr->pci_int_map[0] = SC520_IRQ_DISABLED;	/* disable PCI INT A */
+	sc520_mmcr->pci_int_map[1] = SC520_IRQ_DISABLED;	/* disable PCI INT B */
+	sc520_mmcr->pci_int_map[2] = SC520_IRQ_DISABLED;	/* disable PCI INT C */
+	sc520_mmcr->pci_int_map[3] = SC520_IRQ_DISABLED;	/* disable PCI INT D */
+	sc520_mmcr->dmabcintmap = SC520_IRQ_DISABLED;		/* disable DMA INT */
+	sc520_mmcr->ssimap = SC520_IRQ_DISABLED;		/* disable Synchronius serial INT */
+	sc520_mmcr->wdtmap = SC520_IRQ_DISABLED;		/* disable Watchdog INT */
+	sc520_mmcr->rtcmap = SC520_IRQ8;			/* Set RTC int to 8 */
+	sc520_mmcr->wpvmap = SC520_IRQ_DISABLED;		/* disable write protect INT */
+	sc520_mmcr->icemap = SC520_IRQ1;			/* Set ICE Debug Serielport INT to IRQ1 */
+	sc520_mmcr->ferrmap = SC520_IRQ13; 			/* Set FP error INT to IRQ13 */
 
 	if (CONFIG_SYS_USE_SIO_UART) {
-		write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
-		write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
-		write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3);          /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
-		write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4);          /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
+		sc520_mmcr->uart_int_map[0] = SC520_IRQ_DISABLED;	/* disable internal UART1 INT */
+		sc520_mmcr->uart_int_map[1] = SC520_IRQ_DISABLED;	/* disable internal UART2 INT */
+		sc520_mmcr->gp_int_map[3] = SC520_IRQ3;		/* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
+		sc520_mmcr->gp_int_map[4] = SC520_IRQ4;		/* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
 	} else {
-		write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);         /* Set internal UART2 INT to IRQ4 */
-		write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);         /* Set internal UART2 INT to IRQ3 */
-		write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ3 (ISA IRQ3) */
-		write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ4 (ISA IRQ4) */
+		sc520_mmcr->uart_int_map[0] = SC520_IRQ4;		/* Set internal UART2 INT to IRQ4 */
+		sc520_mmcr->uart_int_map[1] = SC520_IRQ3;		/* Set internal UART2 INT to IRQ3 */
+		sc520_mmcr->gp_int_map[3] = SC520_IRQ_DISABLED;	/* disable GPIRQ3 (ISA IRQ3) */
+		sc520_mmcr->gp_int_map[4] = SC520_IRQ_DISABLED;	/* disable GPIRQ4 (ISA IRQ4) */
 	}
 
-	write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1);             /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
-	write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5);             /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
-	write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6);             /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
-	write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7);             /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
-	write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8);             /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
-	write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9);             /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
-	write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11);            /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
-	write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12);            /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
-	write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14);            /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
-
-	write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);                /* Map PCI hostbridge INT to NMI */
-	write_mmcr_word(SC520_ECCMAP, 0x100);                    /* Map SDRAM ECC failure INT to NMI */
-
+	sc520_mmcr->gp_int_map[1] = SC520_IRQ1;			/* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
+	sc520_mmcr->gp_int_map[5] = SC520_IRQ5;			/* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
+	sc520_mmcr->gp_int_map[6] = SC520_IRQ6;			/* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
+	sc520_mmcr->gp_int_map[7] = SC520_IRQ7;			/* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
+	sc520_mmcr->gp_int_map[8] = SC520_IRQ8;			/* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
+	sc520_mmcr->gp_int_map[9] = SC520_IRQ9;			/* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
+	sc520_mmcr->gp_int_map[0] = SC520_IRQ11;		/* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
+	sc520_mmcr->gp_int_map[2] = SC520_IRQ12;		/* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
+	sc520_mmcr->gp_int_map[10] = SC520_IRQ14;		/* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
+
+	sc520_mmcr->pcihostmap = 0x11f;				/* Map PCI hostbridge INT to NMI */
+	sc520_mmcr->eccmap = 0x100;				/* Map SDRAM ECC failure INT to NMI */
 }
 
 #ifdef CONFIG_PCI
@@ -235,23 +234,22 @@ static void bus_init(void)
 {
 
 	/* set up the GP IO pins */
-	write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff);	/* set the GPIO pin function 31-16 reg */
-	write_mmcr_word(SC520_PIOPFS15_0, 0xffff);	/* set the GPIO pin function 15-0 reg */
-	write_mmcr_byte(SC520_CSPFS, 0xf8);		/* set the CS pin function  reg */
-	write_mmcr_byte(SC520_CLKSEL, 0x70);
-
-
-	write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */
-	write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
-	write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
-	write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
-	write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
-	write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
-	write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
-
-	write_mmcr_word(SC520_BOOTCSCTL, 0x1823);		/* set up timing of BOOTCS */
-	write_mmcr_word(SC520_ROMCS1CTL, 0x1823);		/* set up timing of ROMCS1 */
-	write_mmcr_word(SC520_ROMCS2CTL, 0x1823);		/* set up timing of ROMCS2 */
+	sc520_mmcr->piopfs31_16 = 0xf7ff;	/* set the GPIO pin function 31-16 reg */
+	sc520_mmcr->piopfs15_0 = 0xffff;	/* set the GPIO pin function 15-0 reg */
+	sc520_mmcr->cspfs = 0xf8;		/* set the CS pin function  reg */
+	sc520_mmcr->clksel = 0x70;
+
+	sc520_mmcr->gpcsrt = 1;   		/* set the GP CS offset */
+	sc520_mmcr->gpcspw = 3;   		/* set the GP CS pulse width */
+	sc520_mmcr->gpcsoff = 1;  		/* set the GP CS offset */
+	sc520_mmcr->gprdw = 3;    		/* set the RD pulse width */
+	sc520_mmcr->gprdoff = 1;  		/* set the GP RD offset */
+	sc520_mmcr->gpwrw = 3;   		 /* set the GP WR pulse width */
+	sc520_mmcr->gpwroff = 1; 		 /* set the GP WR offset */
+
+	sc520_mmcr->bootcsctl = 0x1823;		/* set up timing of BOOTCS */
+	sc520_mmcr->romcs1ctl = 0x1823;		/* set up timing of ROMCS1 */
+	sc520_mmcr->romcs2ctl = 0x1823;		/* set up timing of ROMCS2 */
 
 	/* adjust the memory map:
 	 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
@@ -260,31 +258,31 @@ static void bus_init(void)
 
 
 	/* SRAM = GPCS3 128k @ d0000-effff*/
-	write_mmcr_long(SC520_PAR2,  0x4e00400d);
+	sc520_mmcr->par[2] = 0x4e00400d;
 
 	/* IDE0 = GPCS6 1f0-1f7 */
-	write_mmcr_long(SC520_PAR3,  0x380801f0);
+	sc520_mmcr->par[3] = 0x380801f0;
 
 	/* IDE1 = GPCS7 3f6 */
-	write_mmcr_long(SC520_PAR4,  0x3c0003f6);
+	sc520_mmcr->par[4] = 0x3c0003f6;
 	/* bootcs */
-	write_mmcr_long(SC520_PAR12, 0x8bffe800);
+	sc520_mmcr->par[12] = 0x8bffe800;
 	/* romcs2 */
-	write_mmcr_long(SC520_PAR13, 0xcbfff000);
+	sc520_mmcr->par[13] = 0xcbfff000;
 	/* romcs1 */
-	write_mmcr_long(SC520_PAR14, 0xabfff800);
+	sc520_mmcr->par[14] = 0xabfff800;
 	/* 680 LEDS */
-	write_mmcr_long(SC520_PAR15, 0x30000640);
+	sc520_mmcr->par[15] = 0x30000640;
 
-	write_mmcr_byte(SC520_ADDDECCTL, 0);
+	sc520_mmcr->adddecctl = 0;
 
 	asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
 
 	if (CONFIG_SYS_USE_SIO_UART) {
-		write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
+		sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | UART2_DIS | UART1_DIS;
 		setup_ali_sio(1);
 	} else {
-		write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
+		sc520_mmcr->adddecctl = sc520_mmcr->adddecctl & ~(UART2_DIS|UART1_DIS);
 		setup_ali_sio(0);
 		silence_uart(0x3e8);
 		silence_uart(0x2e8);
@@ -352,7 +350,7 @@ u32 isa_map_rom(u32 bus_addr, int size)
 	PRINTF ("setting PAR11 to %x\n", par);
 
 	/* Map rom 0x10000 with PAR1 */
-	write_mmcr_long(SC520_PAR11,  par);
+	sc520_mmcr->par[11] = par;
 
 	return bus_addr;
 }
@@ -364,8 +362,8 @@ u32 isa_map_rom(u32 bus_addr, int size)
 void isa_unmap_rom(u32 addr)
 {
 	PRINTF("isa_unmap_rom asked to unmap %x", addr);
-	if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
-		write_mmcr_long(SC520_PAR11, 0);
+	if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
+		sc520_mmcr->par[11] = 0;
 		PRINTF(" done\n");
 		return;
 	}
@@ -401,7 +399,7 @@ u32 pci_get_rom_window(struct pci_controller *hose, int size)
 	PRINTF ("setting PAR1 to %x\n", par);
 
 	/* Map rom 0x10000 with PAR1 */
-	write_mmcr_long(SC520_PAR1,  par);
+	sc520_mmcr->par[1] = par;
 
 	return PCI_ROM_TEMP_SPACE;
 }
@@ -414,7 +412,7 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
 {
 	PRINTF("pci_remove_rom_window: %x", addr);
 	if (addr == PCI_ROM_TEMP_SPACE) {
-		write_mmcr_long(SC520_PAR1, 0);
+		sc520_mmcr->par[1] = 0;
 		PRINTF(" done\n");
 		return;
 	}
@@ -432,11 +430,10 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
 int pci_enable_legacy_video_ports(struct pci_controller *hose)
 {
 	/* Map video memory to 0xa0000*/
-	write_mmcr_long(SC520_PAR0,  0x7200400a);
+	sc520_mmcr->par[0] = 0x7200400a;
 
 	/* forward all I/O accesses to PCI */
-	write_mmcr_byte(SC520_ADDDECCTL,
-			read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
+	sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
 
 
 	/* so we map away all io ports to pci (only way to access pci io
@@ -446,32 +443,32 @@ int pci_enable_legacy_video_ports(struct pci_controller *hose)
 	 */
 
 	/* bring 0x100 - 0x1ef back to ISA using PAR5 */
-	write_mmcr_long(SC520_PAR5, 0x30ef0100);
+	sc520_mmcr->par[5] = 0x30ef0100;
 
 	/* IDE use 1f0-1f7 */
 
 	/* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
-	write_mmcr_long(SC520_PAR6, 0x30ff01f8);
+	sc520_mmcr->par[6] = 0x30ff01f8;
 
 	/* com2 use 2f8-2ff */
 
 	/* bring 0x300 - 0x3af back to ISA using PAR7 */
-	write_mmcr_long(SC520_PAR7, 0x30af0300);
+	sc520_mmcr->par[7] = 0x30af0300;
 
 	/* vga use 3b0-3bb */
 
 	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
-	write_mmcr_long(SC520_PAR8, 0x300303bc);
+	sc520_mmcr->par[8] = 0x300303bc;
 
 	/* vga use 3c0-3df */
 
 	/* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
-	write_mmcr_long(SC520_PAR9, 0x301503e0);
+	sc520_mmcr->par[9] = 0x301503e0;
 
 	/* ide use 3f6 */
 
 	/* bring 0x3f7  back to ISA using PAR10 */
-	write_mmcr_long(SC520_PAR10, 0x300003f7);
+	sc520_mmcr->par[10] = 0x300003f7;
 
 	/* com1 use 3f8-3ff */
 
@@ -490,12 +487,12 @@ int board_init(void)
 	irq_init();
 
 	/* max drive current on SDRAM */
-	write_mmcr_word(SC520_DSCTL, 0x0100);
+	sc520_mmcr->dsctl = 0x0100;
 
 	/* enter debug mode after next reset (only if jumper is also set) */
-	write_mmcr_byte(SC520_RESCFG, 0x08);
+	sc520_mmcr->rescfg = 0x08;
 	/* configure the software timer to 33.333MHz */
-	write_mmcr_byte(SC520_SWTMRCFG, 0);
+	sc520_mmcr->swtmrcfg = 0;
 	gd->bus_clk = 33333000;
 
 	return 0;
diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c
index 36a0a8e..dbb5c48 100644
--- a/board/sc520_spunk/sc520_spunk.c
+++ b/board/sc520_spunk/sc520_spunk.c
@@ -47,53 +47,54 @@ DECLARE_GLOBAL_DATA_PTR;
 static void irq_init(void)
 {
 	/* disable global interrupt mode */
-	write_mmcr_byte(SC520_PICICR, 0x40);
+	sc520_mmcr->picicr = 0x40;
 
 	/* set all irqs to edge */
-	write_mmcr_byte(SC520_MPICMODE, 0x00);
-	write_mmcr_byte(SC520_SL1PICMODE, 0x00);
-	write_mmcr_byte(SC520_SL2PICMODE, 0x00);
+	sc520_mmcr->pic_mode[0] = 0x00;
+	sc520_mmcr->pic_mode[1] = 0x00;
+	sc520_mmcr->pic_mode[2] = 0x00;
 
 	/* active low polarity on PIC interrupt pins,
 	 *  active high polarity on all other irq pins */
-	write_mmcr_word(SC520_INTPINPOL, 0x0000);
+	sc520_mmcr->intpinpol = 0x0000;
 
 	/* set irq number mapping */
-	write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */
-	write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
-	write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
-	write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */
-	write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
-	write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
-	write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
-	write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
-	write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
-	write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
-	write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
-	write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6);              /* Set Synchronius serial INT to IRQ6*/
-	write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
-	write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
-	write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
-	write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
-	write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
-
-	write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);            /* Set internal UART2 INT to IRQ4 */
-	write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);            /* Set internal UART2 INT to IRQ3 */
-
-	write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7);             /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
-	write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14);            /* Set GPIRQ1 (CF IRQ) to IRQ14 */
-	write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5);             /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
-	write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);     /* disbale GIRQ4 ( IRR IRQ ) */
-	write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ5 */
-	write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ6 */
-	write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ7 */
-	write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ8 */
-	write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ9 */
-	write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ2 */
-	write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED);     /* disable GPIRQ10 */
-
-	write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);               /* Map PCI hostbridge INT to NMI */
-	write_mmcr_word(SC520_ECCMAP, 0x100);                   /* Map SDRAM ECC failure INT to NMI */
+	sc520_mmcr->gp_tmr_int_map[0] = SC520_IRQ_DISABLED;	/* disable GP timer 0 INT */
+	sc520_mmcr->gp_tmr_int_map[1] = SC520_IRQ_DISABLED;	/* disable GP timer 1 INT */
+	sc520_mmcr->gp_tmr_int_map[2] = SC520_IRQ_DISABLED;	/* disable GP timer 2 INT */
+	sc520_mmcr->pit_int_map[0] = SC520_IRQ0;		/* Set PIT timer 0 INT to IRQ0 */
+	sc520_mmcr->pit_int_map[1] = SC520_IRQ_DISABLED;	/* disable PIT timer 1 INT */
+	sc520_mmcr->pit_int_map[2] = SC520_IRQ_DISABLED;	/* disable PIT timer 2 INT */
+	sc520_mmcr->pci_int_map[0] = SC520_IRQ_DISABLED;	/* disable PCI INT A */
+	sc520_mmcr->pci_int_map[1] = SC520_IRQ_DISABLED;	/* disable PCI INT B */
+	sc520_mmcr->pci_int_map[2] = SC520_IRQ_DISABLED;	/* disable PCI INT C */
+	sc520_mmcr->pci_int_map[3] = SC520_IRQ_DISABLED;	/* disable PCI INT D */
+	sc520_mmcr->dmabcintmap = SC520_IRQ_DISABLED;		/* disable DMA INT */
+	sc520_mmcr->ssimap = SC520_IRQ6;			/* Set Synchronius serial INT to IRQ6*/
+	sc520_mmcr->wdtmap = SC520_IRQ_DISABLED;		/* disable Watchdog INT */
+	sc520_mmcr->rtcmap = SC520_IRQ8;			/* Set RTC int to 8 */
+	sc520_mmcr->wpvmap = SC520_IRQ_DISABLED;		/* disable write protect INT */
+	sc520_mmcr->icemap = SC520_IRQ1;			/* Set ICE Debug Serielport INT to IRQ1 */
+	sc520_mmcr->ferrmap = SC520_IRQ13; 			/* Set FP error INT to IRQ13 */
+
+
+	sc520_mmcr->uart_int_map[0] = SC520_IRQ4;		/* Set internal UART1 INT to IRQ4 */
+	sc520_mmcr->uart_int_map[1] = SC520_IRQ3;		/* Set internal UART2 INT to IRQ3 */
+
+	sc520_mmcr->gp_int_map[0] = SC520_IRQ7;			/* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
+	sc520_mmcr->gp_int_map[1] = SC520_IRQ14;		/* Set GPIRQ1 (CF IRQ) to IRQ14 */
+	sc520_mmcr->gp_int_map[3] = SC520_IRQ5;			/* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
+	sc520_mmcr->gp_int_map[4] = SC520_IRQ_DISABLED;		/* disbale GIRQ4 ( IRR IRQ ) */
+	sc520_mmcr->gp_int_map[5] = SC520_IRQ_DISABLED;		/* disable GPIRQ5 */
+	sc520_mmcr->gp_int_map[6] = SC520_IRQ_DISABLED;		/* disable GPIRQ6 */
+	sc520_mmcr->gp_int_map[7] = SC520_IRQ_DISABLED;		/* disable GPIRQ7 */
+	sc520_mmcr->gp_int_map[8] = SC520_IRQ_DISABLED;		/* disable GPIRQ8 */
+	sc520_mmcr->gp_int_map[9] = SC520_IRQ_DISABLED;		/* disable GPIRQ9 */
+	sc520_mmcr->gp_int_map[2] = SC520_IRQ_DISABLED;		/* disable GPIRQ2 */
+	sc520_mmcr->gp_int_map[10] = SC520_IRQ_DISABLED;	/* disable GPIRQ10 */
+
+	sc520_mmcr->pcihostmap = 0x11f;				/* Map PCI hostbridge INT to NMI */
+	sc520_mmcr->eccmap = 0x100;				/* Map SDRAM ECC failure INT to NMI */
 
 }
 
@@ -101,7 +102,7 @@ static void irq_init(void)
 /* PCI stuff */
 static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 {
-	int version = read_mmcr_byte(SC520_SYSINFO);
+	int version = sc520_mmcr->sysinfo;
 
 	/* a configurable lists of irqs to steal
 	 * when we need one (a board with more pci interrupt pins
@@ -255,41 +256,41 @@ static void bus_init(void)
 	 * ??  Hyglo version 0.97 (small board)
 	 * 10  Spunk board
 	 */
-	int version = read_mmcr_byte(SC520_SYSINFO);
+	int version = sc520_mmcr->sysinfo;
 
 	if (version) {
 		/* set up the GP IO pins (for the Spunk board) */
-		write_mmcr_word(SC520_PIOPFS31_16, 0xfff0);	/* set the GPIO pin function 31-16 reg */
-		write_mmcr_word(SC520_PIOPFS15_0,  0x000f);	/* set the GPIO pin function 15-0 reg */
-		write_mmcr_word(SC520_PIODIR31_16, 0x000f);	/* set the GPIO direction 31-16 reg */
-		write_mmcr_word(SC520_PIODIR15_0,  0x1ff0);	/* set the GPIO direction 15-0 reg */
-		write_mmcr_byte(SC520_CSPFS, 0xc0);		/* set the CS pin function reg */
-		write_mmcr_byte(SC520_CLKSEL, 0x70);
+		sc520_mmcr->piopfs31_16 = 0xfff0;	/* set the GPIO pin function 31-16 reg */
+		sc520_mmcr->piopfs15_0 = 0x000f;	/* set the GPIO pin function 15-0 reg */
+		sc520_mmcr->piodir31_16 = 0x000f;	/* set the GPIO direction 31-16 reg */
+		sc520_mmcr->piodir15_0 = 0x1ff0;	/* set the GPIO direction 15-0 reg */
+		sc520_mmcr->cspfs = 0xc0;		/* set the CS pin function reg */
+		sc520_mmcr->clksel = 0x70;
 
-		write_mmcr_word(SC520_PIOCLR31_16, 0x0003);     /* reset SSI chip-selects */
-		write_mmcr_word(SC520_PIOSET31_16, 0x000c);
+		sc520_mmcr->pioclr31_16 = 0x0003;	/* reset SSI chip-selects */
+		sc520_mmcr->pioset31_16 = 0x000c;
 
 	} else {
 		/* set up the GP IO pins (for the Hyglo board) */
-		write_mmcr_word(SC520_PIOPFS31_16, 0xffc0);	/* set the GPIO pin function 31-16 reg */
-		write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f);	/* set the GPIO pin function 15-0 reg */
-		write_mmcr_word(SC520_PIODIR31_16, 0x003f);	/* set the GPIO direction 31-16 reg */
-		write_mmcr_word(SC520_PIODIR15_0, 0xe180);	/* set the GPIO direction 15-0 reg */
-		write_mmcr_byte(SC520_CSPFS, 0x00);		/* set the CS pin function reg */
-		write_mmcr_byte(SC520_CLKSEL, 0x70);
-
-		write_mmcr_word(SC520_PIOCLR15_0, 0x0180);      /* reset SSI chip-selects */
+		sc520_mmcr->piopfs31_16 = 0xffc0;	/* set the GPIO pin function 31-16 reg */
+		sc520_mmcr->piopfs15_0 = 0x1e7f;	/* set the GPIO pin function 15-0 reg */
+		sc520_mmcr->piodir31_16 = 0x003f;	/* set the GPIO direction 31-16 reg */
+		sc520_mmcr->piodir15_0 = 0xe180;	/* set the GPIO direction 15-0 reg */
+		sc520_mmcr->cspfs = 0x00;		/* set the CS pin function reg */
+		sc520_mmcr->clksel = 0x70;
+
+		sc520_mmcr->pioclr15_0 = 0x0180;	/* reset SSI chip-selects */
 	}
 
-	write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */
-	write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
-	write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
-	write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
-	write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
-	write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
-	write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
+	sc520_mmcr->gpcsrt = 1;		/* set the GP CS offset */
+	sc520_mmcr->gpcspw = 3;		/* set the GP CS pulse width */
+	sc520_mmcr->gpcsoff = 1;	/* set the GP CS offset */
+	sc520_mmcr->gprdw = 3;		/* set the RD pulse width */
+	sc520_mmcr->gprdoff = 1;	/* set the GP RD offset */
+	sc520_mmcr->gpwrw = 3;		/* set the GP WR pulse width */
+	sc520_mmcr->gpwroff = 1;	/* set the GP WR offset */
 
-	write_mmcr_word(SC520_BOOTCSCTL, 0x0407);		/* set up timing of BOOTCS */
+	sc520_mmcr->bootcsctl = 0x0407;	/* set up timing of BOOTCS */
 
 	/* adjust the memory map:
 	 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
@@ -298,17 +299,17 @@ static void bus_init(void)
 
 
 	/* bootcs */
-	write_mmcr_long(SC520_PAR12, 0x8bffe800);
+	sc520_mmcr->par[12] = 0x8bffe800;
 
 	/* IDE0 = GPCS6 1f0-1f7 */
-	write_mmcr_long(SC520_PAR3,  0x380801f0);
+	sc520_mmcr->par[3] = 0x380801f0;
 
 	/* IDE1 = GPCS7 3f6 */
-	write_mmcr_long(SC520_PAR4,  0x3c0003f6);
+	sc520_mmcr->par[4] = 0x3c0003f6;
 
 	asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
 
-	write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
+	sc520_mmcr->adddecctl = sc520_mmcr->adddecctl & ~(UART2_DIS|UART1_DIS);
 
 }
 
@@ -361,7 +362,7 @@ u32 isa_map_rom(u32 bus_addr, int size)
 	printf ("setting PAR11 to %x\n", par);
 
 	/* Map rom 0x10000 with PAR1 */
-	write_mmcr_long(SC520_PAR11,  par);
+	sc520_mmcr->par[11] = par;
 
 	return bus_addr;
 }
@@ -373,8 +374,8 @@ u32 isa_map_rom(u32 bus_addr, int size)
 void isa_unmap_rom(u32 addr)
 {
 	printf("isa_unmap_rom asked to unmap %x", addr);
-	if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
-		write_mmcr_long(SC520_PAR11, 0);
+	if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
+		sc520_mmcr->par[11] = 0;
 		printf(" done\n");
 		return;
 	}
@@ -410,7 +411,7 @@ u32 pci_get_rom_window(struct pci_controller *hose, int size)
 	printf ("setting PAR1 to %x\n", par);
 
 	/* Map rom 0x10000 with PAR1 */
-	write_mmcr_long(SC520_PAR1,  par);
+	sc520_mmcr->par[1] = par;
 
 	return PCI_ROM_TEMP_SPACE;
 }
@@ -423,7 +424,7 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
 {
 	printf("pci_remove_rom_window: %x", addr);
 	if (addr == PCI_ROM_TEMP_SPACE) {
-		write_mmcr_long(SC520_PAR1, 0);
+		sc520_mmcr->par[1] = 0;
 		printf(" done\n");
 		return;
 	}
@@ -441,11 +442,10 @@ void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
 int pci_enable_legacy_video_ports(struct pci_controller *hose)
 {
 	/* Map video memory to 0xa0000*/
-	write_mmcr_long(SC520_PAR0,  0x7200400a);
+	sc520_mmcr->par[0] = 0x7200400a;
 
 	/* forward all I/O accesses to PCI */
-	write_mmcr_byte(SC520_ADDDECCTL,
-			read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
+	sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
 
 
 	/* so we map away all io ports to pci (only way to access pci io
@@ -455,22 +455,22 @@ int pci_enable_legacy_video_ports(struct pci_controller *hose)
 	 */
 
 	/* bring 0x100 - 0x2f7 back to ISA using PAR5 */
-	write_mmcr_long(SC520_PAR5, 0x31f70100);
+	sc520_mmcr->par[5] = 0x31f70100;
 
 	/* com2 use 2f8-2ff */
 
 	/* bring 0x300 - 0x3af back to ISA using PAR7 */
-	write_mmcr_long(SC520_PAR7, 0x30af0300);
+	sc520_mmcr->par[7] = 0x30af0300;
 
 	/* vga use 3b0-3bb */
 
 	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
-	write_mmcr_long(SC520_PAR8, 0x300303bc);
+	sc520_mmcr->par[8] = 0x300303bc;
 
 	/* vga use 3c0-3df */
 
 	/* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
-	write_mmcr_long(SC520_PAR9, 0x301703e0);
+	sc520_mmcr->par[9] = 0x301703e0;
 
 	/* com1 use 3f8-3ff */
 
@@ -489,12 +489,12 @@ int board_init(void)
 	irq_init();
 
 	/* max drive current on SDRAM */
-	write_mmcr_word(SC520_DSCTL, 0x0100);
+	sc520_mmcr->dsctl = 0x0100;
 
 	/* enter debug mode after next reset (only if jumper is also set) */
-	write_mmcr_byte(SC520_RESCFG, 0x08);
+	sc520_mmcr->rescfg = 0x08;
 	/* configure the software timer to 33.000MHz */
-	write_mmcr_byte(SC520_SWTMRCFG, 1);
+	sc520_mmcr->swtmrcfg = 1;
 	gd->bus_clk = 33000000;
 
 	return 0;
@@ -508,17 +508,15 @@ int dram_init(void)
 
 void show_boot_progress(int val)
 {
-	int version = read_mmcr_byte(SC520_SYSINFO);
+	int version = sc520_mmcr->sysinfo;
 
 	if (val < -32) val = -1;  /* let things compatible */
 	if (version == 0) {
 		/* PIO31-PIO16 Data */
-		write_mmcr_word(SC520_PIODATA31_16,
-				(read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */
+		sc520_mmcr->piodata31_16 = (sc520_mmcr->piodata31_16 & 0xffc0) | ((val&0x7e)>>1); /* 0x1f8 >> 3 */
 
 		/* PIO0-PIO15 Data */
-		write_mmcr_word(SC520_PIODATA15_0,
-				(read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13));
+		sc520_mmcr->piodata15_0 = (sc520_mmcr->piodata15_0 & 0x1fff)| ((val&0x7)<<13);
 	} else {
 		/* newer boards use PIO4-PIO12 */
 		/* PIO0-PIO15 Data */
@@ -527,8 +525,7 @@ void show_boot_progress(int val)
 #else
 		val = (val & 0x007) | ((val & 0x07e) << 2);
 #endif
-		write_mmcr_word(SC520_PIODATA15_0,
-				(read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4));
+		sc520_mmcr->piodata15_0 = (sc520_mmcr->piodata15_0 & 0xe00f) | ((val&0x01ff)<<4);
 	}
 }
 
@@ -536,7 +533,7 @@ void show_boot_progress(int val)
 int last_stage_init(void)
 {
 
-	int version = read_mmcr_byte(SC520_SYSINFO);
+	int version = sc520_mmcr->sysinfo;
 
 	printf("Omicron Ceti SC520 Spunk revision %x\n", version);
 
@@ -587,30 +584,30 @@ int last_stage_init(void)
 
 void ssi_chip_select(int dev)
 {
-	int version = read_mmcr_byte(SC520_SYSINFO);
+	int version = sc520_mmcr->sysinfo;
 
 	if (version) {
 		/* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */
 		switch (dev) {
 		case 1: /* EEPROM */
-			write_mmcr_word(SC520_PIOCLR31_16, 0x0004);
+			sc520_mmcr->pioclr31_16 = 0x0004;
 			break;
 
 		case 2: /* Temp Probe */
-			write_mmcr_word(SC520_PIOSET31_16, 0x0002);
+			sc520_mmcr->pioset31_16 = 0x0002;
 			break;
 
 		case 3: /* CAN */
-			write_mmcr_word(SC520_PIOCLR31_16, 0x0008);
+			sc520_mmcr->pioclr31_16 = 0x0008;
 			break;
 
 		case 4: /* AUX */
-			write_mmcr_word(SC520_PIOSET31_16, 0x0001);
+			sc520_mmcr->pioset31_16 = 0x0001;
 			break;
 
 		case 0:
-			write_mmcr_word(SC520_PIOCLR31_16, 0x0003);
-			write_mmcr_word(SC520_PIOSET31_16, 0x000c);
+			sc520_mmcr->pioclr31_16 = 0x0003;
+			sc520_mmcr->pioset31_16 = 0x000c;
 			break;
 
 		default:
@@ -622,15 +619,15 @@ void ssi_chip_select(int dev)
 
 		switch (dev) {
 		case 1: /* EEPROM */
-			write_mmcr_word(SC520_PIOSET15_0, 0x0100);
+			sc520_mmcr->pioset15_0 = 0x0100;
 			break;
 
 		case 2: /* Temp Probe */
-			write_mmcr_word(SC520_PIOSET15_0, 0x0080);
+			sc520_mmcr->pioset15_0 = 0x0080;
 			break;
 
 		case 0:
-			write_mmcr_word(SC520_PIOCLR15_0, 0x0180);
+			sc520_mmcr->pioclr15_0 = 0x0180;
 			break;
 
 		default:
@@ -669,9 +666,7 @@ int mw_eeprom_write(int x, int offset, uchar *buffer, int len)
 
 void spi_init_f(void)
 {
-	read_mmcr_byte(SC520_SYSINFO) ?
-		spi_eeprom_probe(1) :
-	mw_eeprom_probe(1);
+	sc520_mmcr->sysinfo ? spi_eeprom_probe(1) : mw_eeprom_probe(1);
 
 }
 
@@ -686,7 +681,7 @@ ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
 		offset |= addr[i];
 	}
 
-	return	read_mmcr_byte(SC520_SYSINFO) ?
+	return	sc520_mmcr->sysinfo ?
 		spi_eeprom_read(1, offset, buffer, len) :
 	mw_eeprom_read(1, offset, buffer, len);
 }
@@ -702,7 +697,7 @@ ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
 		offset |= addr[i];
 	}
 
-	return	read_mmcr_byte(SC520_SYSINFO) ?
+	return	sc520_mmcr->sysinfo ?
 		spi_eeprom_write(1, offset, buffer, len) :
 	mw_eeprom_write(1, offset, buffer, len);
 }
diff --git a/cpu/i386/sc520/sc520.c b/cpu/i386/sc520/sc520.c
index 1d79210..4b566a7 100644
--- a/cpu/i386/sc520/sc520.c
+++ b/cpu/i386/sc520/sc520.c
@@ -33,75 +33,35 @@ DECLARE_GLOBAL_DATA_PTR;
 /*
  * utility functions for boards based on the AMD sc520
  *
- * void write_mmcr_byte(u16 mmcr, u8 data)
- * void write_mmcr_word(u16 mmcr, u16 data)
- * void write_mmcr_long(u16 mmcr, u32 data)
- *
- * u8   read_mmcr_byte(u16 mmcr)
- * u16  read_mmcr_word(u16 mmcr)
- * u32  read_mmcr_long(u16 mmcr)
- *
  * void init_sc520(void)
  * unsigned long init_sc520_dram(void)
  */
 
-static u32 mmcr_base= 0xfffef000;
-
-void write_mmcr_byte(u16 mmcr, u8 data)
-{
-	writeb(data, mmcr+mmcr_base);
-}
-
-void write_mmcr_word(u16 mmcr, u16 data)
-{
-	writew(data, mmcr+mmcr_base);
-}
-
-void write_mmcr_long(u16 mmcr, u32 data)
-{
-	writel(data, mmcr+mmcr_base);
-}
-
-u8 read_mmcr_byte(u16 mmcr)
-{
-	return readb(mmcr+mmcr_base);
-}
-
-u16 read_mmcr_word(u16 mmcr)
-{
-	return readw(mmcr+mmcr_base);
-}
-
-u32 read_mmcr_long(u16 mmcr)
-{
-	return readl(mmcr+mmcr_base);
-}
-
+volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
 
 void init_sc520(void)
 {
 	/* Set the UARTxCTL register at it's slower,
 	 * baud clock giving us a 1.8432 MHz reference
 	 */
-	write_mmcr_byte(SC520_UART1CTL, 7);
-	write_mmcr_byte(SC520_UART2CTL, 7);
+	sc520_mmcr->uart1ctl = 0x07;
+	sc520_mmcr->uart2ctl = 0x07;
 
 	/* first set the timer pin mapping */
-	write_mmcr_byte(SC520_CLKSEL, 0x72);	/* no clock frequency selected, use 1.1892MHz */
+	sc520_mmcr->clksel = 0x72;	/* no clock frequency selected, use 1.1892MHz */
 
 	/* enable PCI bus arbitrer */
-	write_mmcr_byte(SC520_SYSARBCTL,0x02);  /* enable concurrent mode */
-
-	write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
-	write_mmcr_word(SC520_HBCTL,0x04);      /* enable posted-writes */
+	sc520_mmcr->sysarbctl = 0x02;	/* enable concurrent mode */
 
+	sc520_mmcr->sysarbmenb = 0x1f;	/* enable external grants */
+	sc520_mmcr->hbctl = 0x04;	/* enable posted-writes */
 
 	if (CONFIG_SYS_SC520_HIGH_SPEED) {
-		write_mmcr_byte(SC520_CPUCTL, 0x2);	/* set it to 133 MHz and write back */
+		sc520_mmcr->cpuctl = 0x02;	/* set it to 133 MHz and write back */
 		gd->cpu_clk = 133000000;
 		printf("## CPU Speed set to 133MHz\n");
 	} else {
-		write_mmcr_byte(SC520_CPUCTL, 1);	/* set CPU to 100 MHz and write back cache */
+		sc520_mmcr->cpuctl = 0x01;	/* set it to 100 MHz and write back */
 		printf("## CPU Speed set to 100MHz\n");
 		gd->cpu_clk = 100000000;
 	}
@@ -114,7 +74,7 @@ void init_sc520(void)
 	    "loop 0b\n": : : "ecx");
 
 	/* turn on the SDRAM write buffer */
-	write_mmcr_byte(SC520_DBCTL, 0x11);
+	sc520_mmcr->dbctl = 0x11;
 
 	/* turn on the cache and disable write through */
 	asm("movl	%%cr0, %%eax\n"
@@ -156,10 +116,9 @@ unsigned long init_sc520_dram(void)
 		val = 3;  /* 62.4us */
 	}
 
-	write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
+	sc520_mmcr->drcctl = (sc520_mmcr->drcctl & 0xcf) | (val<<4);
 
-	val = read_mmcr_byte(SC520_DRCTMCTL);
-	val &= 0xf0;
+	val = sc520_mmcr->drctmctl & 0xf0;
 
 	if (cas_precharge_delay==3) {
 		val |= 0x04;   /* 3T */
@@ -174,12 +133,12 @@ unsigned long init_sc520_dram(void)
 	} else {
 		val |= 1;
 	}
-	write_mmcr_byte(SC520_DRCTMCTL, val);
+	sc520_mmcr->drctmctl = val;
 #endif
 
 	/* We read-back the configuration of the dram
 	 * controller that the assembly code wrote */
-	dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
+	dram_ctrl = sc520_mmcr->drcbendadr;
 
 	bd->bi_dram[0].start = 0;
 	if (dram_ctrl & 0x80) {
@@ -232,7 +191,7 @@ void reset_cpu(ulong addr)
 {
 	printf("Resetting using SC520 MMCR\n");
 	/* Write a '1' to the SYS_RST of the RESCFG MMCR */
-	write_mmcr_word(SC520_RESCFG, 0x0001);
+	sc520_mmcr->rescfg = 0x01;
 
 	/* NOTREACHED */
 }
diff --git a/cpu/i386/sc520/sc520_pci.c b/cpu/i386/sc520/sc520_pci.c
index 871ad0a..f446c6d 100644
--- a/cpu/i386/sc520/sc520_pci.c
+++ b/cpu/i386/sc520/sc520_pci.c
@@ -33,23 +33,23 @@ static struct {
 	u16 level_reg;
 	u8 level_bit;
 } sc520_irq[] = {
-	{ SC520_IRQ0,  SC520_MPICMODE,  0x01 },
-	{ SC520_IRQ1,  SC520_MPICMODE,  0x02 },
-	{ SC520_IRQ2,  SC520_SL1PICMODE, 0x02 },
-	{ SC520_IRQ3,  SC520_MPICMODE,  0x08 },
-	{ SC520_IRQ4,  SC520_MPICMODE,  0x10 },
-	{ SC520_IRQ5,  SC520_MPICMODE,  0x20 },
-	{ SC520_IRQ6,  SC520_MPICMODE,  0x40 },
-	{ SC520_IRQ7,  SC520_MPICMODE,  0x80 },
-
-	{ SC520_IRQ8,  SC520_SL1PICMODE, 0x01 },
-	{ SC520_IRQ9,  SC520_SL1PICMODE, 0x02 },
-	{ SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
-	{ SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
-	{ SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
-	{ SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
-	{ SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
-	{ SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
+	{ SC520_IRQ0,  0, 0x01 },
+	{ SC520_IRQ1,  0, 0x02 },
+	{ SC520_IRQ2,  1, 0x02 },
+	{ SC520_IRQ3,  0, 0x08 },
+	{ SC520_IRQ4,  0, 0x10 },
+	{ SC520_IRQ5,  0, 0x20 },
+	{ SC520_IRQ6,  0, 0x40 },
+	{ SC520_IRQ7,  0, 0x80 },
+
+	{ SC520_IRQ8,  1, 0x01 },
+	{ SC520_IRQ9,  1, 0x02 },
+	{ SC520_IRQ10, 1, 0x04 },
+	{ SC520_IRQ11, 1, 0x08 },
+	{ SC520_IRQ12, 1, 0x10 },
+	{ SC520_IRQ13, 1, 0x20 },
+	{ SC520_IRQ14, 1, 0x40 },
+	{ SC520_IRQ15, 1, 0x80 }
 };
 
 
@@ -77,34 +77,34 @@ int pci_sc520_set_irq(int pci_pin, int irq)
 
 	/* first disable any non-pci interrupt source that use
 	 * this level */
-	for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
-		if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
-			continue;
-		}
-		if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
-			write_mmcr_byte(i, SC520_IRQ_DISABLED);
-		}
+
+	/* PCI interrupt mapping (A through D)*/
+	for (i=0; i<=3 ;i++) {
+		if (sc520_mmcr->pci_int_map[i] == sc520_irq[irq].priority)
+			sc520_mmcr->pci_int_map[i] = SC520_IRQ_DISABLED;
+	}
+
+	/* GP IRQ interrupt mapping */
+	for (i=0; i<=10 ;i++) {
+		if (sc520_mmcr->gp_int_map[i] == sc520_irq[irq].priority)
+			sc520_mmcr->gp_int_map[i] = SC520_IRQ_DISABLED;
 	}
 
 	/* Set the trigger to level */
-	write_mmcr_byte(sc520_irq[irq].level_reg,
-			read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
+	sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] =
+		sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] | sc520_irq[irq].level_bit;
 
 
 	if (pci_pin < 4) {
 		/* PCI INTA-INTD */
 		/* route the interrupt */
-		write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
-
-
+		sc520_mmcr->pci_int_map[pci_pin] = sc520_irq[irq].priority;
 	} else {
 		/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
-		write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
+		sc520_mmcr->gp_int_map[pci_pin - 4] = sc520_irq[irq].priority;
 
 		/* also set the polarity in this case */
-		write_mmcr_word(SC520_INTPINPOL,
-				read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
-
+		sc520_mmcr->intpinpol = sc520_mmcr->intpinpol | (1 << (pci_pin-4));
 	}
 
 	/* register the pin */
diff --git a/cpu/i386/sc520/sc520_ssi.c b/cpu/i386/sc520/sc520_ssi.c
index dd667ca..8dbe17a 100644
--- a/cpu/i386/sc520/sc520_ssi.c
+++ b/cpu/i386/sc520/sc520_ssi.c
@@ -61,32 +61,34 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
 		temp |= PHS_INV_ENB;
 	}
 
-	write_mmcr_byte(SC520_SSICTL, temp);
+	sc520_mmcr->ssictl = temp;
 
 	return 0;
 }
 
 u8 ssi_txrx_byte(u8 data)
 {
-	write_mmcr_byte(SC520_SSIXMIT, data);
-	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
-	write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
-	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
-	return read_mmcr_byte(SC520_SSIRCV);
+	sc520_mmcr->ssixmit = data;
+	while (sc520_mmcr->ssista & SSISTA_BSY);
+	sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMITRCV;
+	while (sc520_mmcr->ssista & SSISTA_BSY);
+
+	return sc520_mmcr->ssircv;
 }
 
 
 void ssi_tx_byte(u8 data)
 {
-	write_mmcr_byte(SC520_SSIXMIT, data);
-	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
-	write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
+	sc520_mmcr->ssixmit = data;
+	while (sc520_mmcr->ssista & SSISTA_BSY);
+	sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMIT;
 }
 
 u8 ssi_rx_byte(void)
 {
-	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
-	write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
-	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
-	return read_mmcr_byte(SC520_SSIRCV);
+	while (sc520_mmcr->ssista & SSISTA_BSY);
+	sc520_mmcr->ssicmd = SSICMD_CMD_SEL_RCV;
+	while (sc520_mmcr->ssista & SSISTA_BSY);
+
+	return sc520_mmcr->ssircv;
 }
diff --git a/cpu/i386/sc520/sc520_timer.c b/cpu/i386/sc520/sc520_timer.c
index 2a3425b..23de14b 100644
--- a/cpu/i386/sc520/sc520_timer.c
+++ b/cpu/i386/sc520/sc520_timer.c
@@ -30,29 +30,29 @@
 void sc520_timer_isr(void)
 {
 	/* Ack the GP Timer Interrupt */
-	write_mmcr_byte (SC520_GPTMRSTA, 0x02);
+	sc520_mmcr->gptmrsta = 0x02;
 }
 
 int timer_init(void)
 {
 	/* Map GP Timer 1 to Master PIC IR0  */
-	write_mmcr_byte (SC520_GPTMR1MAP, 0x01);
+	sc520_mmcr->gp_tmr_int_map[1] = 0x01;
 
 	/* Disable GP Timers 1 & 2 - Allow configuration writes */
-	write_mmcr_word (SC520_GPTMR1CTL, 0x4000);
-	write_mmcr_word (SC520_GPTMR2CTL, 0x4000);
+	sc520_mmcr->gptmr1ctl = 0x4000;
+	sc520_mmcr->gptmr2ctl = 0x4000;
 
 	/* Reset GP Timers 1 & 2 */
-	write_mmcr_word (SC520_GPTMR1CNT, 0x0000);
-	write_mmcr_word (SC520_GPTMR2CNT, 0x0000);
+	sc520_mmcr->gptmr1cnt = 0x0000;
+	sc520_mmcr->gptmr2cnt = 0x0000;
 
 	/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
-	write_mmcr_word (SC520_GPTMR2MAXCMPA, 83);
-	write_mmcr_word (SC520_GPTMR2CTL, 0xc001);
+	sc520_mmcr->gptmr2maxcmpa = 83;
+	sc520_mmcr->gptmr2ctl = 0xc001;
 
 	/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
-	write_mmcr_word (SC520_GPTMR1MAXCMPA, 100);
-	write_mmcr_word (SC520_GPTMR1CTL, 0xe009);
+	sc520_mmcr->gptmr1maxcmpa = 100;
+	sc520_mmcr->gptmr1ctl = 0xe009;
 
 	/* Register the SC520 specific timer interrupt handler */
 	register_timer_isr (sc520_timer_isr);
@@ -62,7 +62,7 @@ int timer_init(void)
 	unmask_irq (0);
 
 	/* Clear the GP Timer 1 status register to get the show rolling*/
-	write_mmcr_byte (SC520_GPTMRSTA, 0x02);
+	sc520_mmcr->gptmrsta = 0x02;
 
 	return 0;
 }
@@ -71,12 +71,13 @@ void udelay(unsigned long usec)
 {
 	int m = 0;
 	long u;
+	long temp;
 
-	read_mmcr_word (SC520_SWTMRMILLI);
-	read_mmcr_word (SC520_SWTMRMICRO);
+	temp = sc520_mmcr->swtmrmilli;
+	temp = sc520_mmcr->swtmrmicro;
 
 	do {
-		m += read_mmcr_word (SC520_SWTMRMILLI);
-		u = read_mmcr_word (SC520_SWTMRMICRO) + (m * 1000);
+		m += sc520_mmcr->swtmrmilli;
+		u = sc520_mmcr->swtmrmicro + (m * 1000);
 	} while (u < usec);
 }
diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h
index bf39516..57c9904 100644
--- a/include/asm-i386/ic/sc520.h
+++ b/include/asm-i386/ic/sc520.h
@@ -24,179 +24,243 @@
 #ifndef _ASM_IC_SC520_H_
 #define _ASM_IC_SC520_H_ 1
 
-/* Memory mapped configuration registers, MMCR */
-#define SC520_REVID		0x0000	/* ElanSC520 Microcontroller Revision ID Register */
-#define SC520_CPUCTL		0x0002	/* Am5x86 CPU Control Register */
-#define SC520_DRCCTL		0x0010	/* SDRAM Control Register */
-#define SC520_DRCTMCTL		0x0012	/* SDRAM Timing Control Register */
-#define SC520_DRCCFG		0x0014	/* SDRAM Bank Configuration Register*/
-#define SC520_DRCBENDADR	0x0018	/* SDRAM Bank 0-3 Ending Address Register*/
-#define SC520_ECCCTL		0x0020	/* ECC Control Register */
-#define SC520_ECCSTA		0x0021	/* ECC Status Register */
-#define SC520_ECCCKBPOS		0x0022	/* ECC Check Bit Position Register */
-#define SC520_ECCSBADD		0x0024	/* ECC Single-Bit Error Address Register */
+#ifndef __ASSEMBLY__
+
+void init_sc520(void);
+unsigned long init_sc520_dram(void);
+
+/* Memory mapped configuration registers */
+typedef struct sc520_mmcr {
+	u16 revid;	/* ElanSC520 microcontroller revision id */
+	u8  cpuctl;	/* am5x86 CPU control  */
+
+	u8  pad_0x003[0x0d];
+
+	u8  drcctl;		/* SDRAM control */
+	u8  pad_0x011[0x01];
+	u8  drctmctl;		/* SDRAM timing control */
+	u8  pad_0x013[0x01];
+	u16 drccfg;		/* SDRAM bank configuration*/
+	u8  pad_0x016[0x02];
+	u32 drcbendadr;		/* SDRAM bank 0-3 ending address*/
+	u8  pad_0x01c[0x04];
+	u8  eccctl;		/* ECC control */
+	u8  eccsta;		/* ECC status */
+	u8  eccckbpos;		/* ECC check bit position */
+	u8  ecccktest;		/* ECC Check Code Test */
+	u32 eccsbadd;		/* ECC single-bit error address */
+	u32 eccmbadd;		/* ECC multi-bit error address */
+
+	u8  pad_0x02c[0x14];
+
+	u8  dbctl;		/* SDRAM buffer control */
+
+	u8  pad_0x041[0x0f];
+
+	u16 bootcsctl;		/* /BOOTCS control */
+	u8  pad_0x052[0x02];
+	u16 romcs1ctl;		/* /ROMCS1 control */
+	u16 romcs2ctl;		/* /ROMCS2 control */
+
+	u8  pad_0x058[0x08];
+
+	u16 hbctl;		/* host bridge control */
+	u16 hbtgtirqctl;	/* host bridge target interrupt control */
+	u16 hbtgtirqsta;	/* host bridge target interrupt status */
+	u16 hbmstirqctl;	/* host bridge target interrupt control */
+	u16 hbmstirqsta;	/* host bridge master interrupt status */
+	u8  pad_0x06a[0x02];
+	u32 mstintadd;		/* host bridge master interrupt address */
+
+	u8  sysarbctl;		/* system arbiter control */
+	u8  pciarbsta;		/* PCI bus arbiter status */
+	u16 sysarbmenb;		/* system arbiter master enable */
+	u32 arbprictl;		/* arbiter priority control */
+
+	u8  pad_0x078[0x08];
+
+	u8  adddecctl;		/* address decode control */
+	u8  pad_0x081[0x01];
+	u16 wpvsta;		/* write-protect violation status */
+	u8  pad_0x084[0x04];
+	u32 par[16];		/* programmable address regions */
+
+	u8  pad_0x0c8[0x0b38];
+
+	u8  gpecho;		/* GP echo mode */
+	u8  gpcsdw;		/* GP chip select data width */
+	u16 gpcsqual;		/* GP chip select qualification */
+	u8  pad_0xc04[0x4];
+	u8  gpcsrt;		/* GP chip select recovery time */
+	u8  gpcspw;		/* GP chip select pulse width */
+	u8  gpcsoff;		/* GP chip select offset */
+	u8  gprdw;		/* GP read pulse width */
+	u8  gprdoff;		/* GP read offset */
+	u8  gpwrw;		/* GP write pulse width */
+	u8  gpwroff;		/* GP write offset */
+	u8  gpalew;		/* GP ale pulse width */
+	u8  gpaleoff;		/* GP ale offset */
+
+	u8  pad_0xc11[0x0f];
+
+	u16 piopfs15_0;		/* PIO15-PIO0 pin function select */
+	u16 piopfs31_16;	/* PIO31-PIO16 pin function select */
+	u8  cspfs;		/* chip select pin function select */
+	u8  pad_0xc25[0x01];
+	u8  clksel;		/* clock select */
+	u8  pad_0xc27[0x01];
+	u16 dsctl;		/* drive strength control */
+	u16 piodir15_0;		/* PIO15-PIO0 direction */
+	u16 piodir31_16;	/* PIO31-PIO16 direction */
+	u8  pad_0xc2e[0x02];
+	u16 piodata15_0	;	/* PIO15-PIO0 data */
+	u16 piodata31_16;	/* PIO31-PIO16 data */
+	u16 pioset15_0;		/* PIO15-PIO0 set */
+	u16 pioset31_16;	/* PIO31-PIO16 set */
+	u16 pioclr15_0;		/* PIO15-PIO0 clear */
+	u16 pioclr31_16;	/* PIO31-PIO16 clear */
+
+	u8  pad_0xc3c[0x24];
+
+	u16 swtmrmilli;		/* software timer millisecond count */
+	u16 swtmrmicro;		/* software timer microsecond count */
+	u8  swtmrcfg;		/* software timer configuration */
+
+	u8  pad_0xc65[0x0b];
+
+	u8  gptmrsta;		/* GP timers status register */
+	u8  pad_0xc71;
+	u16 gptmr0ctl;		/* GP timer 0 mode/control */
+	u16 gptmr0cnt;		/* GP timer 0 count */
+	u16 gptmr0maxcmpa;	/* GP timer 0 maxcount compare A */
+	u16 gptmr0maxcmpb;	/* GP timer 0 maxcount compare B */
+	u16 gptmr1ctl;		/* GP timer 1 mode/control */
+	u16 gptmr1cnt;		/* GP timer 1 count */
+	u16 gptmr1maxcmpa;	/* GP timer 1 maxcount compare A */
+	u16 gptmr1maxcmpb;	/* GP timer 1 maxcount compare B*/
+	u16 gptmr2ctl;		/* GP timer 2 mode/control */
+	u16 gptmr2cnt;		/* GP timer 2 count */
+	u8  pad_0xc86[0x08];
+	u16 gptmr2maxcmpa;	/* GP timer 2 maxcount compare A */
+
+	u8  pad_0xc90[0x20];
+
+	u16 wdtmrctl;		/* watchdog timer control */
+	u16 wdtmrcntl;		/* watchdog timer count low */
+	u16 wdtmrcnth;		/* watchdog timer count high */
+
+	u8  pad_0xcb6[0x0a];
+
+	u8  uart1ctl;		/* UART 1 general control */
+	u8  uart1sta;		/* UART 1 general status */
+	u8  uart1fcrshad;	/* UART 1 FIFO control shadow */
+	u8  pad_0xcc3[0x01];
+	u8  uart2ctl;		/* UART 2 general control */
+	u8  uart2sta;		/* UART 2 general status */
+	u8  uart2fcrshad;	/* UART 2 FIFO control shadow */
+
+	u8  pad_0xcc7[0x09];
+
+	u8  ssictl;		/* SSI control */
+	u8  ssixmit;		/* SSI transmit */
+	u8  ssicmd;		/* SSI command */
+	u8  ssista;		/* SSI status */
+	u8  ssircv;		/* SSI receive */
+
+	u8  pad_0xcd5[0x2b];
+
+	u8  picicr;		/* interrupt control */
+	u8  pad_0xd01[0x01];
+	u8  pic_mode[3];	/* PIC interrupt mode */
+	u8  pad_0xd05[0x03];
+	u16 swint16_1;		/* software interrupt 16-1 control */
+	u8  swint22_17;		/* software interrupt 22-17/NMI control */
+	u8  pad_0xd0b[0x05];
+	u16 intpinpol;		/* interrupt pin polarity */
+	u8  pad_0xd12[0x02];
+	u16 pcihostmap;		/* PCI host bridge interrupt mapping */
+	u8  pad_0xd16[0x02];
+	u16 eccmap;		/* ECC interrupt mapping */
+	u8  gp_tmr_int_map[3];	/* GP timer interrupt mapping */
+	u8  pad_0xd1d[0x03];
+	u8  pit_int_map[3];	/* PIT interrupt mapping */
+	u8  pad_0xd23[0x05];
+	u8  uart_int_map[2];	/* UART interrupt mapping */
+	u8  pad_0xd2a[0x06];
+	u8  pci_int_map[4];	/* PCI interrupt mapping (A through D)*/
+	u8  pad_0xd34[0x0c];
+	u8  dmabcintmap;	/* DMA buffer chaining interrupt mapping */
+	u8  ssimap;		/* SSI interrupt mapping register */
+	u8  wdtmap;		/* watchdog timer interrupt mapping */
+	u8  rtcmap;		/* RTC interrupt mapping register */
+	u8  wpvmap;		/* write-protect interrupt mapping */
+	u8  icemap;		/* AMDebug JTAG Rx/Tx interrupt mapping */
+	u8  ferrmap;		/* floating point error interrupt mapping */
+	u8  pad_0xd47[0x09];
+	u8  gp_int_map[11];	/* GP IRQ interrupt mapping */
+
+	u8  pad_0xd5b[0x15];
+
+	u8  sysinfo;		/* system board information */
+	u8  pad_0xd71[0x01];
+	u8  rescfg;		/* reset configuration */
+	u8  pad_0xd73[0x01];
+	u8  ressta;		/* reset status */
+
+	u8  pad_0xd75[0x0b];
+
+	u8  gpdmactl;		/* GP-DMA Control */
+	u8  gpdmammio;		/* GP-DMA memory-mapped I/O */
+	u16 gpdmaextchmapa;	/* GP-DMA resource channel map a */
+	u16 gpdmaextchmapb;	/* GP-DMA resource channel map b */
+	u8  gp_dma_ext_pg_0;	/* GP-DMA channel extended page 0 */
+	u8  gp_dma_ext_pg_1;	/* GP-DMA channel extended page 0 */
+	u8  gp_dma_ext_pg_2;	/* GP-DMA channel extended page 0 */
+	u8  gp_dma_ext_pg_3;	/* GP-DMA channel extended page 0 */
+	u8  gp_dma_ext_pg_5;	/* GP-DMA channel extended page 0 */
+	u8  gp_dma_ext_pg_6;	/* GP-DMA channel extended page 0 */
+	u8  gp_dma_ext_pg_7;	/* GP-DMA channel extended page 0 */
+	u8  pad_0xd8d[0x03];
+	u8  gpdmaexttc3;	/* GP-DMA channel 3 extender transfer count */
+	u8  gpdmaexttc5;	/* GP-DMA channel 5 extender transfer count */
+	u8  gpdmaexttc6;	/* GP-DMA channel 6 extender transfer count */
+	u8  gpdmaexttc7;	/* GP-DMA channel 7 extender transfer count */
+	u8  pad_0xd94[0x4];
+	u8  gpdmabcctl;		/* buffer chaining control */
+	u8  gpdmabcsta;		/* buffer chaining status */
+	u8  gpdmabsintenb;	/* buffer chaining interrupt enable */
+	u8  gpdmabcval;		/* buffer chaining valid */
+	u8  pad_0xd9c[0x04];
+	u16 gpdmanxtaddl3;	/* GP-DMA channel 3 next address low */
+	u16 gpdmanxtaddh3;	/* GP-DMA channel 3 next address high */
+	u16 gpdmanxtaddl5;	/* GP-DMA channel 5 next address low */
+	u16 gpdmanxtaddh5;	/* GP-DMA channel 5 next address high */
+	u16 gpdmanxtaddl6;	/* GP-DMA channel 6 next address low */
+	u16 gpdmanxtaddh6;	/* GP-DMA channel 6 next address high */
+	u16 gpdmanxtaddl7;	/* GP-DMA channel 7 next address low */
+	u16 gpdmanxtaddh7;	/* GP-DMA channel 7 next address high */
+	u16 gpdmanxttcl3;	/* GP-DMA channel 3 next transfer count low */
+	u16 gpdmanxttch3;	/* GP-DMA channel 3 next transfer count high */
+	u16 gpdmanxttcl5;	/* GP-DMA channel 5 next transfer count low */
+	u16 gpdmanxttch5;	/* GP-DMA channel 5 next transfer count high */
+	u16 gpdmanxttcl6;	/* GP-DMA channel 6 next transfer count low */
+	u16 gpdmanxttch6;	/* GP-DMA channel 6 next transfer count high */
+	u16 gpdmanxttcl7;	/* GP-DMA channel 7 next transfer count low */
+	u16 gpdmanxttch7;	/* GP-DMA channel 7 next transfer count high */
+
+	u8  pad_0xdc0[0x0240];
+} sc520_mmcr_t;
+
+extern volatile sc520_mmcr_t *sc520_mmcr;
+
+#endif
+
+/* MMCR Offsets (required for assembler code */
 #define SC520_DBCTL		0x0040	/* SDRAM Buffer Control Register */
-#define SC520_BOOTCSCTL		0x0050	/* /BOOTCS Control Register */
-#define SC520_ROMCS1CTL		0x0054	/* /ROMCS1 Control Register */
-#define SC520_ROMCS2CTL		0x0056	/* /ROMCS2 Control Register */
-#define SC520_HBCTL		0x0060	/* Host Bridge Control Register */
-#define SC520_HBTGTIRQCTL	0x0062	/* Host Bridge Target Interrupt Control Register */
-#define SC520_HBTGTIRQSTA	0x0064	/* Host Bridge Target Interrupt Status Register */
-#define SC520_HBMSTIRQCTL	0x0066	/* Host Bridge Target Interrupt Control Register */
-#define SC520_HBMSTIRQSTA	0x0068	/* Host Bridge Master Interrupt Status Register */
-#define SC520_MSTINTADD		0x006c	/* Host Bridge Master Interrupt Address Register */
-#define SC520_SYSARBCTL		0x0070	/* System Arbiter Control Register */
-#define SC520_PCIARBSTA		0x0071	/* PCI Bus Arbiter Status Register */
-#define SC520_SYSARBMENB	0x0072	/* System Arbiter Master Enable Register */
-#define SC520_ARBPRICTL		0x0074	/* Arbiter Priority Control Register */
-#define SC520_ADDDECCTL		0x0080	/* Address Decode Control Register */
-#define SC520_WPVSTA		0x0082	/* Write-Protect Violation Status Register */
-#define SC520_PAR0		0x0088	/* Programmable Address Region 0 Register */
-#define SC520_PAR1		0x008c	/* Programmable Address Region 1 Register */
-#define SC520_PAR2		0x0090	/* Programmable Address Region 2 Register */
-#define SC520_PAR3		0x0094	/* Programmable Address Region 3 Register */
-#define SC520_PAR4		0x0098	/* Programmable Address Region 4 Register */
-#define SC520_PAR5		0x009c	/* Programmable Address Region 5 Register */
-#define SC520_PAR6		0x00a0	/* Programmable Address Region 6 Register */
-#define SC520_PAR7		0x00a4	/* Programmable Address Region 7 Register */
-#define SC520_PAR8		0x00a8	/* Programmable Address Region 8 Register */
-#define SC520_PAR9		0x00ac	/* Programmable Address Region 9 Register */
-#define SC520_PAR10		0x00b0	/* Programmable Address Region 10 Register */
-#define SC520_PAR11		0x00b4	/* Programmable Address Region 11 Register */
-#define SC520_PAR12		0x00b8	/* Programmable Address Region 12 Register */
-#define SC520_PAR13		0x00bc	/* Programmable Address Region 13 Register */
 #define SC520_PAR14		0x00c0	/* Programmable Address Region 14 Register */
 #define SC520_PAR15		0x00c4	/* Programmable Address Region 15 Register */
-#define SC520_GPECHO		0x0c00	/* GP Echo Mode Register */
-#define SC520_GPCSDW		0x0c01	/* GP Chip Select Data Width Register */
-#define SC520_GPCSQUAL		0x0c02	/* GP Chip Select Qualification Register */
-#define SC520_GPCSRT		0x0c08	/* GP Chip Select Recovery Time Register */
-#define SC520_GPCSPW		0x0c09	/* GP Chip Select Pulse Width Register */
-#define SC520_GPCSOFF		0x0c0a	/* GP Chip Select Offset Register */
-#define SC520_GPRDW		0x0c0b	/* GP Read Pulse Width Register */
-#define SC520_GPRDOFF		0x0c0c	/* GP Read Offset Register */
-#define SC520_GPWRW		0x0c0d	/* GP Write Pulse Width Register */
-#define SC520_GPWROFF		0x0c0e	/* GP Write Offset Register */
-#define SC520_GPALEW		0x0c0f	/* GP ALE Pulse Width Register */
-#define SC520_GPALEOFF		0x0c10	/* GP ALE Offset Register */
-#define SC520_PIOPFS15_0	0x0c20	/* PIO15-PIO0 Pin Function Select */
-#define SC520_PIOPFS31_16	0x0c22	/* PIO31-PIO16 Pin Function Select */
-#define SC520_CSPFS		0x0c24	/* Chip Select Pin Function Select */
-#define SC520_CLKSEL		0x0c26	/* Clock Select */
-#define SC520_DSCTL		0x0c28	/* Drive Strength Control */
-#define SC520_PIODIR15_0	0x0c2a	/* PIO15-PIO0 Direction */
-#define SC520_PIODIR31_16	0x0c2c	/* PIO31-PIO16 Direction */
-#define SC520_PIODATA15_0	0x0c30	/* PIO15-PIO0 Data */
-#define SC520_PIODATA31_16	0x0c32	/* PIO31-PIO16 Data */
-#define SC520_PIOSET15_0	0x0c34	/* PIO15-PIO0 Set */
-#define SC520_PIOSET31_16	0x0c36	/* PIO31-PIO16 Set */
-#define SC520_PIOCLR15_0	0x0c38	/* PIO15-PIO0 Clear */
-#define SC520_PIOCLR31_16	0x0c3a	/* PIO31-PIO16 Clear */
-#define SC520_SWTMRMILLI	0x0c60	/* Software Timer Millisecond Count */
-#define SC520_SWTMRMICRO	0x0c62	/* Software Timer Microsecond Count */
-#define SC520_SWTMRCFG		0x0c64	/* Software Timer Configuration */
-#define SC520_GPTMRSTA		0x0c70	/* GP Timers Status Register */
-#define SC520_GPTMR0CTL		0x0c72	/* GP Timer 0 Mode/Control Register */
-#define SC520_GPTMR0CNT		0x0c74	/* GP Timer 0 Count Register */
-#define SC520_GPTMR0MAXCMPA	0x0c76	/* GP Timer 0 Maxcount Compare A Register */
-#define SC520_GPTMR0MAXCMPB	0x0c78	/* GP Timer 0 Maxcount Compare B Register */
-#define SC520_GPTMR1CTL		0x0c7a	/* GP Timer 1 Mode/Control Register */
-#define SC520_GPTMR1CNT		0x0c7c	/* GP Timer 1 Count Register */
-#define SC520_GPTMR1MAXCMPA	0x0c7e	/* GP Timer 1 Maxcount Compare Register A */
-#define SC520_GPTMR1MAXCMPB	0x0c80	/* GP Timer 1 Maxcount Compare B Register */
-#define SC520_GPTMR2CTL		0x0c82	/* GP Timer 2 Mode/Control Register */
-#define SC520_GPTMR2CNT		0x0c84	/* GP Timer 2 Count Register */
-#define SC520_GPTMR2MAXCMPA	0x0c8e	/* GP Timer 2 Maxcount Compare A Register */
-#define SC520_WDTMRCTL		0x0cb0	/* Watchdog Timer Control Register */
-#define SC520_WDTMRCNTL		0x0cb2	/* Watchdog Timer Count Low Register */
-#define SC520_WDTMRCNTH		0x0cb4	/* Watchdog Timer Count High Register */
-#define SC520_UART1CTL		0x0cc0	/* UART 1 General Control Register */
-#define SC520_UART1STA		0x0cc1	/* UART 1 General Status Register */
-#define SC520_UART1FCRSHAD	0x0cc2	/* UART 1 FIFO Control Shadow Register */
-#define SC520_UART2CTL		0x0cc4	/* UART 2 General Control Register */
-#define SC520_UART2STA		0x0cc5	/* UART 2 General Status Register */
-#define SC520_UART2FCRSHAD	0x0cc6	/* UART 2 FIFO Control Shadow Register */
-#define SC520_SSICTL		0x0cd0	/* SSI Control */
-#define SC520_SSIXMIT		0x0cd1	/* SSI Transmit */
-#define SC520_SSICMD		0x0cd2	/* SSI Command */
-#define SC520_SSISTA		0x0cd3	/* SSI Status */
-#define SC520_SSIRCV		0x0cd4	/* SSI Receive */
-#define SC520_PICICR		0x0d00	/* Interrupt Control Register */
-#define SC520_MPICMODE		0x0d02	/* Master PIC Interrupt Mode Register */
-#define SC520_SL1PICMODE	0x0d03	/* Slave 1 PIC Interrupt Mode Register */
-#define SC520_SL2PICMODE	0x0d04	/* Slave 2 PIC Interrupt Mode Register */
-#define SC520_SWINT16_1		0x0d08	/* Software Interrupt 16-1 Control Register */
-#define SC520_SWINT22_17	0x0d0a	/* Software Interrupt 22-17/NMI Control Register */
-#define SC520_INTPINPOL		0x0d10	/* Interrupt Pin Polarity Register */
-#define SC520_PCIHOSTMAP	0x0d14	/* PCI Host Bridge Interrupt Mappin Register */
-#define SC520_ECCMAP		0x0d18	/* ECC Interrupt Mapping Register */
-#define SC520_GPTMR0MAP		0x0d1a	/* GP Timer 0 Interrupt Mapping Register */
-#define SC520_GPTMR1MAP		0x0d1b	/* GP Timer 1 Interrupt Mapping Register */
-#define SC520_GPTMR2MAP		0x0d1c	/* GP Timer 2 Interrupt Mapping Register */
-#define SC520_PIT0MAP		0x0d20	/* PIT0 Interrupt Mapping Register */
-#define SC520_PIT1MAP		0x0d21	/* PIT1 Interrupt Mapping Register */
-#define SC520_PIT2MAP		0x0d22	/* PIT2 Interrupt Mapping Register */
-#define SC520_UART1MAP		0x0d28	/* UART 1 Interrupt Mapping Register */
-#define SC520_UART2MAP		0x0d29	/* UART 2 Interrupt Mapping Register */
-#define SC520_PCIINTAMAP	0x0d30	/* PCI Interrupt A Mapping Register */
-#define SC520_PCIINTBMAP	0x0d31	/* PCI Interrupt B Mapping Register */
-#define SC520_PCIINTCMAP	0x0d32	/* PCI Interrupt C Mapping Register */
-#define SC520_PCIINTDMAP	0x0d33	/* PCI Interrupt D Mapping Register */
-#define SC520_DMABCINTMAP	0x0d40	/* DMA Buffer Chaining Interrupt Mapping Register */
-#define SC520_SSIMAP		0x0d41	/* SSI Interrupt Mapping Register */
-#define SC520_WDTMAP		0x0d42	/* Watchdog Timer Interrupt Mapping Register */
-#define SC520_RTCMAP		0x0d43	/* RTC Interrupt Mapping Register */
-#define SC520_WPVMAP		0x0d44	/* Write-Protect Interrupt Mapping Register */
-#define SC520_ICEMAP		0x0d45	/* AMDebug JTAG RX/TX Interrupt Mapping Register */
-#define SC520_FERRMAP		0x0d46	/* Floating Point Error Interrupt Mapping Register */
-#define SC520_GP0IMAP		0x0d50	/* GPIRQ0 Interrupt Mapping Register */
-#define SC520_GP1IMAP		0x0d51	/* GPIRQ1 Interrupt Mapping Register */
-#define SC520_GP2IMAP		0x0d52	/* GPIRQ2 Interrupt Mapping Register */
-#define SC520_GP3IMAP		0x0d53	/* GPIRQ3 Interrupt Mapping Register */
-#define SC520_GP4IMAP		0x0d54	/* GPIRQ4 Interrupt Mapping Register */
-#define SC520_GP5IMAP		0x0d55	/* GPIRQ5 Interrupt Mapping Register */
-#define SC520_GP6IMAP		0x0d56	/* GPIRQ6 Interrupt Mapping Register */
-#define SC520_GP7IMAP		0x0d57	/* GPIRQ7 Interrupt Mapping Register */
-#define SC520_GP8IMAP		0x0d58	/* GPIRQ8 Interrupt Mapping Register */
-#define SC520_GP9IMAP		0x0d59	/* GPIRQ9 Interrupt Mapping Register */
-#define SC520_GP10IMAP		0x0d5a	/* GPIRQ10 Interrupt Mapping Register */
-#define SC520_SYSINFO		0x0d70	/* System Board Information Register */
-#define SC520_RESCFG		0x0d72	/* Reset Configuration Register */
-#define SC520_RESSTA		0x0d74	/* Reset Status Register */
-#define SC520_GPDMAMMIO		0x0d81	/* GP-DMA Memory-Mapped I/O Register */
-#define SC520_GPDMAEXTCHMAPA	0x0d82	/* GP-DMA Resource Channel Map A */
-#define SC520_GPDMAEXTCHMAPB	0x0d84	/* GP-DMA Resource Channel Map B */
-#define SC520_GPDMAEXTPG0	0x0d86	/* GP-DMA Channel 0 Extended Page */
-#define SC520_GPDMAEXTPG1	0x0d87	/* GP-DMA Channel 1 Extended Page */
-#define SC520_GPDMAEXTPG2	0x0d88	/* GP-DMA Channel 2 Extended Page */
-#define SC520_GPDMAEXTPG3	0x0d89	/* GP-DMA Channel 3 Extended Page */
-#define SC520_GPDMAEXTPG5	0x0d8a	/* GP-DMA Channel 5 Extended Page */
-#define SC520_GPDMAEXTPG6	0x0d8b	/* GP-DMA Channel 6 Extended Page */
-#define SC520_GPDMAEXTPG7	0x0d8c	/* GP-DMA Channel 7 Extended Page */
-#define SC520_GPDMAEXTTC3	0x0d90	/* GP-DMA Channel 3 Extender Transfer count */
-#define SC520_GPDMAEXTTC5	0x0d91	/* GP-DMA Channel 5 Extender Transfer count */
-#define SC520_GPDMAEXTTC6	0x0d92	/* GP-DMA Channel 6 Extender Transfer count */
-#define SC520_GPDMAEXTTC7	0x0d93	/* GP-DMA Channel 7 Extender Transfer count */
-#define SC520_GPDMABCCTL	0x0d98	/* Buffer Chaining Control */
-#define SC520_GPDMABCSTA	0x0d99	/* Buffer Chaining Status */
-#define SC520_GPDMABSINTENB	0x0d9a	/* Buffer Chaining Interrupt Enable */
-#define SC520_GPDMABCVAL	0x0d9b	/* Buffer Chaining Valid */
-#define SC520_GPDMANXTADDL3	0x0da0	/* GP-DMA Channel 3 Next Address Low */
-#define SC520_GPDMANXTADDH3	0x0da2	/* GP-DMA Channel 3 Next Address High */
-#define SC520_GPDMANXTADDL5	0x0da4	/* GP-DMA Channel 5 Next Address Low */
-#define SC520_GPDMANXTADDH5	0x0da6	/* GP-DMA Channel 5 Next Address High */
-#define SC520_GPDMANXTADDL6	0x0da8	/* GP-DMA Channel 6 Next Address Low */
-#define SC520_GPDMANXTADDH6	0x0daa	/* GP-DMA Channel 6 Next Address High */
-#define SC520_GPDMANXTADDL7	0x0dac	/* GP-DMA Channel 7 Next Address Low */
-#define SC520_GPDMANXTADDH7	0x0dae	/* GP-DMA Channel 7 Next Address High */
-#define SC520_GPDMANXTTCL3	0x0db0	/* GP-DMA Channel 3 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH3	0x0db2	/* GP-DMA Channel 3 Next Transfer Count High */
-#define SC520_GPDMANXTTCL5	0x0db4	/* GP-DMA Channel 5 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH5	0x0db6	/* GP-DMA Channel 5 Next Transfer Count High */
-#define SC520_GPDMANXTTCL6	0x0db8	/* GP-DMA Channel 6 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH6	0x0dba	/* GP-DMA Channel 6 Next Transfer Count High */
-#define SC520_GPDMANXTTCL7	0x0dbc	/* GP-DMA Channel 7 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH7	0x0dbe	/* GP-DMA Channel 7 Next Transfer Count High */
+#define SC520_SWTMRMILLI	0x0c60  /* Software Timer Millisecond Count */
+#define SC520_SWTMRMICRO	0x0c62  /* Software Timer Microsecond Count */
 
 /* MMCR Register bits (not all of them :) ) */
 
@@ -221,7 +285,6 @@
 #define SSISTA_BSY		0x02	/* SSI Busy */
 #define SSISTA_TC_INT		0x01	/* SSI Transaction Complete Interrupt */
 
-
 /* BITS for SC520_ADDDECCTL: */
 #define WPV_INT_ENB		0x80	/* Write-Protect Violation Interrupt Enable */
 #define IO_HOLE_DEST_PCI	0x10	/* I/O Hole Access Destination */
@@ -233,7 +296,6 @@
 #define SC520_REG_ADDR		0x00000cf8
 #define SC520_REG_DATA		0x00000cfc
 
-
 #define SC520_ISA_MEM_PHYS	0x00000000
 #define SC520_ISA_MEM_BUS	0x00000000
 #define SC520_ISA_MEM_SIZE	0x01000000
@@ -282,15 +344,4 @@
 #define SC520_IRQ14 9
 #define SC520_IRQ15 10
 
-/* utility functions */
-void write_mmcr_byte(u16 mmcr, u8 data);
-void write_mmcr_word(u16 mmcr, u16 data);
-void write_mmcr_long(u16 mmcr, u32 data);
-u8 read_mmcr_byte(u16 mmcr);
-u16 read_mmcr_word(u16 mmcr);
-u32 read_mmcr_long(u16 mmcr);
-
-void init_sc520(void);
-unsigned long init_sc520_dram(void);
-
 #endif
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 13/17] Moved PCI from #ifdef to conditional compile for sc520 boards

[Graeme Russ]

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 board/eNET/Makefile                 |   10 +-
 board/sc520_cdp/Makefile            |   14 +-
 board/sc520_cdp/sc520_cdp.c         |  239 --------------------------
 board/sc520_cdp/sc520_cdp_pci.c     |  271 +++++++++++++++++++++++++++++
 board/sc520_spunk/Makefile          |   14 +-
 board/sc520_spunk/sc520_spunk.c     |  298 --------------------------------
 board/sc520_spunk/sc520_spunk_pci.c |  323 +++++++++++++++++++++++++++++++++++
 lib_i386/Makefile                   |    4 +-
 lib_i386/pci.c                      |    3 -
 lib_i386/pci_type1.c                |    5 -
 10 files changed, 617 insertions(+), 564 deletions(-)
 create mode 100644 board/sc520_cdp/sc520_cdp_pci.c
 create mode 100644 board/sc520_spunk/sc520_spunk_pci.c

diff --git a/board/eNET/Makefile b/board/eNET/Makefile
index 4813b4b..bf5736a 100644
--- a/board/eNET/Makefile
+++ b/board/eNET/Makefile
@@ -31,12 +31,12 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= eNET.o
-SOBJS	:= eNET_start16.o eNET_start.o
+COBJS-y	+= eNET.o
+SOBJS-y	+= eNET_start16.o
+SOBJS-y	+= eNET_start.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
diff --git a/board/sc520_cdp/Makefile b/board/sc520_cdp/Makefile
index 0d2800d..7944a01 100644
--- a/board/sc520_cdp/Makefile
+++ b/board/sc520_cdp/Makefile
@@ -28,12 +28,14 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= sc520_cdp.o flash.o
-SOBJS	:= sc520_cdp_asm.o sc520_cdp_asm16.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+COBJS-y	+= sc520_cdp.o
+COBJS-y	+= flash.o
+COBJS-$(CONFIG_PCI) += sc520_cdp_pci.o
+SOBJS-y	+= sc520_cdp_asm.o
+SOBJS-y	+= sc520_cdp_asm16.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c
index 9312f4f..4c44b24 100644
--- a/board/sc520_cdp/sc520_cdp.c
+++ b/board/sc520_cdp/sc520_cdp.c
@@ -23,11 +23,8 @@
  */
 
 #include <common.h>
-#include <pci.h>
 #include <asm/io.h>
-#include <asm/pci.h>
 #include <asm/ic/sc520.h>
-#include <asm/ic/pci.h>
 #include <ali512x.h>
 #include <spi.h>
 #include <netdev.h>
@@ -114,87 +111,6 @@ static void irq_init(void)
 	sc520_mmcr->eccmap = 0x100;				/* Map SDRAM ECC failure INT to NMI */
 }
 
-#ifdef CONFIG_PCI
-/* PCI stuff */
-static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	/* a configurable lists of irqs to steal
-	 * when we need one (a board with more pci interrupt pins
-	 * would use a larger table */
-	static int irq_list[] = {
-		CONFIG_SYS_FIRST_PCI_IRQ,
-		CONFIG_SYS_SECOND_PCI_IRQ,
-		CONFIG_SYS_THIRD_PCI_IRQ,
-		CONFIG_SYS_FORTH_PCI_IRQ
-	};
-	static int next_irq_index=0;
-
-	uchar tmp_pin;
-	int pin;
-
-	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
-	pin = tmp_pin;
-
-	pin-=1; /* pci config space use 1-based numbering */
-	if (-1 == pin) {
-		return; /* device use no irq */
-	}
-
-
-	/* map device number +  pin to a pin on the sc520 */
-	switch (PCI_DEV(dev)) {
-	case 20:
-		pin+=SC520_PCI_INTA;
-		break;
-
-	case 19:
-		pin+=SC520_PCI_INTB;
-		break;
-
-	case 18:
-		pin+=SC520_PCI_INTC;
-		break;
-
-	case 17:
-		pin+=SC520_PCI_INTD;
-		break;
-
-	default:
-		return;
-	}
-
-	pin&=3; /* wrap around */
-
-	if (sc520_pci_ints[pin] == -1) {
-		/* re-route one interrupt for us */
-		if (next_irq_index > 3) {
-			return;
-		}
-		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
-			return;
-		}
-		next_irq_index++;
-	}
-
-
-	if (-1 != sc520_pci_ints[pin]) {
-		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
-					   sc520_pci_ints[pin]);
-	}
-	PRINTF("fixup_irq: device %d pin %c irq %d\n",
-	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
-}
-
-static struct pci_controller sc520_cdp_hose = {
-	fixup_irq: pci_sc520_cdp_fixup_irq,
-};
-
-void pci_init_board(void)
-{
-	pci_sc520_init(&sc520_cdp_hose);
-}
-#endif
-
 static void silence_uart(int port)
 {
 	outb(0, port+1);
@@ -322,161 +238,6 @@ static void bus_init(void)
  */
 
 /*
- * This function should map a chunk of size bytes
- * of the system address space to the ISA bus
- *
- * The function will return the memory address
- * as seen by the host (which may very will be the
- * same as the bus address)
- */
-u32 isa_map_rom(u32 bus_addr, int size)
-{
-	u32 par;
-
-	PRINTF("isa_map_rom asked to map %d bytes at %x\n",
-	       size, bus_addr);
-
-	par = size;
-	if (par < 0x80000) {
-		par = 0x80000;
-	}
-	par >>= 12;
-	par--;
-	par&=0x7f;
-	par <<= 18;
-	par |= (bus_addr>>12);
-	par |= 0x50000000;
-
-	PRINTF ("setting PAR11 to %x\n", par);
-
-	/* Map rom 0x10000 with PAR1 */
-	sc520_mmcr->par[11] = par;
-
-	return bus_addr;
-}
-
-/*
- * this function removed any mapping created
- * with pci_get_rom_window()
- */
-void isa_unmap_rom(u32 addr)
-{
-	PRINTF("isa_unmap_rom asked to unmap %x", addr);
-	if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
-		sc520_mmcr->par[11] = 0;
-		PRINTF(" done\n");
-		return;
-	}
-	PRINTF(" not ours\n");
-}
-
-#ifdef CONFIG_PCI
-#define PCI_ROM_TEMP_SPACE 0x10000
-/*
- * This function should map a chunk of size bytes
- * of the system address space to the PCI bus,
- * suitable to map PCI ROMS (bus address < 16M)
- * the function will return the host memory address
- * which should be converted into a bus address
- * before used to configure the PCI rom address
- * decoder
- */
-u32 pci_get_rom_window(struct pci_controller *hose, int size)
-{
-	u32 par;
-
-	par = size;
-	if (par < 0x80000) {
-		par = 0x80000;
-	}
-	par >>= 16;
-	par--;
-	par&=0x7ff;
-	par <<= 14;
-	par |= (PCI_ROM_TEMP_SPACE>>16);
-	par |= 0x72000000;
-
-	PRINTF ("setting PAR1 to %x\n", par);
-
-	/* Map rom 0x10000 with PAR1 */
-	sc520_mmcr->par[1] = par;
-
-	return PCI_ROM_TEMP_SPACE;
-}
-
-/*
- * this function removed any mapping created
- * with pci_get_rom_window()
- */
-void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
-{
-	PRINTF("pci_remove_rom_window: %x", addr);
-	if (addr == PCI_ROM_TEMP_SPACE) {
-		sc520_mmcr->par[1] = 0;
-		PRINTF(" done\n");
-		return;
-	}
-	PRINTF(" not ours\n");
-
-}
-
-/*
- * This function is called in order to provide acces to the
- * legacy video I/O ports on the PCI bus.
- * After this function accesses to I/O ports 0x3b0-0x3bb and
- * 0x3c0-0x3df shuld result in transactions on the PCI bus.
- *
- */
-int pci_enable_legacy_video_ports(struct pci_controller *hose)
-{
-	/* Map video memory to 0xa0000*/
-	sc520_mmcr->par[0] = 0x7200400a;
-
-	/* forward all I/O accesses to PCI */
-	sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
-
-
-	/* so we map away all io ports to pci (only way to access pci io
-	 * below 0x400. But then we have to map back the portions that we dont
-	 * use so that the generate cycles on the GPIO bus where the sio and
-	 * ISA slots are connected, this requre the use of several PAR registers
-	 */
-
-	/* bring 0x100 - 0x1ef back to ISA using PAR5 */
-	sc520_mmcr->par[5] = 0x30ef0100;
-
-	/* IDE use 1f0-1f7 */
-
-	/* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
-	sc520_mmcr->par[6] = 0x30ff01f8;
-
-	/* com2 use 2f8-2ff */
-
-	/* bring 0x300 - 0x3af back to ISA using PAR7 */
-	sc520_mmcr->par[7] = 0x30af0300;
-
-	/* vga use 3b0-3bb */
-
-	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
-	sc520_mmcr->par[8] = 0x300303bc;
-
-	/* vga use 3c0-3df */
-
-	/* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
-	sc520_mmcr->par[9] = 0x301503e0;
-
-	/* ide use 3f6 */
-
-	/* bring 0x3f7  back to ISA using PAR10 */
-	sc520_mmcr->par[10] = 0x300003f7;
-
-	/* com1 use 3f8-3ff */
-
-	return 0;
-}
-#endif
-
-/*
  * Miscelaneous platform dependent initialisations
  */
 
diff --git a/board/sc520_cdp/sc520_cdp_pci.c b/board/sc520_cdp/sc520_cdp_pci.c
new file mode 100644
index 0000000..ccb7988
--- /dev/null
+++ b/board/sc520_cdp/sc520_cdp_pci.c
@@ -0,0 +1,271 @@
+/*
+ *
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+#include <asm/ic/pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef SC520_CDP_DEBUG
+
+#ifdef	SC520_CDP_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	/* a configurable lists of irqs to steal
+	 * when we need one (a board with more pci interrupt pins
+	 * would use a larger table */
+	static int irq_list[] = {
+		CONFIG_SYS_FIRST_PCI_IRQ,
+		CONFIG_SYS_SECOND_PCI_IRQ,
+		CONFIG_SYS_THIRD_PCI_IRQ,
+		CONFIG_SYS_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+
+	uchar tmp_pin;
+	int pin;
+
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+
+	pin-=1; /* pci config space use 1-based numbering */
+	if (-1 == pin) {
+		return; /* device use no irq */
+	}
+
+
+	/* map device number +  pin to a pin on the sc520 */
+	switch (PCI_DEV(dev)) {
+	case 20:
+		pin+=SC520_PCI_INTA;
+		break;
+
+	case 19:
+		pin+=SC520_PCI_INTB;
+		break;
+
+	case 18:
+		pin+=SC520_PCI_INTC;
+		break;
+
+	case 17:
+		pin+=SC520_PCI_INTD;
+		break;
+
+	default:
+		return;
+	}
+
+	pin&=3; /* wrap around */
+
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+			return;
+		}
+		next_irq_index++;
+	}
+
+
+	if (-1 != sc520_pci_ints[pin]) {
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+					   sc520_pci_ints[pin]);
+	}
+	PRINTF("fixup_irq: device %d pin %c irq %d\n",
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+}
+
+static struct pci_controller sc520_cdp_hose = {
+	fixup_irq: pci_sc520_cdp_fixup_irq,
+};
+
+void pci_init_board(void)
+{
+	pci_sc520_init(&sc520_cdp_hose);
+}
+
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ *
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size)
+{
+	u32 par;
+
+	PRINTF("isa_map_rom asked to map %d bytes at %x\n",
+	       size, bus_addr);
+
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 12;
+	par--;
+	par&=0x7f;
+	par <<= 18;
+	par |= (bus_addr>>12);
+	par |= 0x50000000;
+
+	PRINTF ("setting PAR11 to %x\n", par);
+
+	/* Map rom 0x10000 with PAR1 */
+	sc520_mmcr->par[11] = par;
+
+	return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+	PRINTF("isa_unmap_rom asked to unmap %x", addr);
+	if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
+		sc520_mmcr->par[11] = 0;
+		PRINTF(" done\n");
+		return;
+	}
+	PRINTF(" not ours\n");
+}
+
+#define PCI_ROM_TEMP_SPACE 0x10000
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size)
+{
+	u32 par;
+
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 16;
+	par--;
+	par&=0x7ff;
+	par <<= 14;
+	par |= (PCI_ROM_TEMP_SPACE>>16);
+	par |= 0x72000000;
+
+	PRINTF ("setting PAR1 to %x\n", par);
+
+	/* Map rom 0x10000 with PAR1 */
+	sc520_mmcr->par[1] = par;
+
+	return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+	PRINTF("pci_remove_rom_window: %x", addr);
+	if (addr == PCI_ROM_TEMP_SPACE) {
+		sc520_mmcr->par[1] = 0;
+		PRINTF(" done\n");
+		return;
+	}
+	PRINTF(" not ours\n");
+
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus.
+ * After this function accesses to I/O ports 0x3b0-0x3bb and
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ *
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+	/* Map video memory to 0xa0000*/
+	sc520_mmcr->par[0] = 0x7200400a;
+
+	/* forward all I/O accesses to PCI */
+	sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
+
+
+	/* so we map away all io ports to pci (only way to access pci io
+	 * below 0x400. But then we have to map back the portions that we dont
+	 * use so that the generate cycles on the GPIO bus where the sio and
+	 * ISA slots are connected, this requre the use of several PAR registers
+	 */
+
+	/* bring 0x100 - 0x1ef back to ISA using PAR5 */
+	sc520_mmcr->par[5] = 0x30ef0100;
+
+	/* IDE use 1f0-1f7 */
+
+	/* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
+	sc520_mmcr->par[6] = 0x30ff01f8;
+
+	/* com2 use 2f8-2ff */
+
+	/* bring 0x300 - 0x3af back to ISA using PAR7 */
+	sc520_mmcr->par[7] = 0x30af0300;
+
+	/* vga use 3b0-3bb */
+
+	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+	sc520_mmcr->par[8] = 0x300303bc;
+
+	/* vga use 3c0-3df */
+
+	/* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
+	sc520_mmcr->par[9] = 0x301503e0;
+
+	/* ide use 3f6 */
+
+	/* bring 0x3f7  back to ISA using PAR10 */
+	sc520_mmcr->par[10] = 0x300003f7;
+
+	/* com1 use 3f8-3ff */
+
+	return 0;
+}
diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile
index e04172e..06fa2f3 100644
--- a/board/sc520_spunk/Makefile
+++ b/board/sc520_spunk/Makefile
@@ -28,12 +28,14 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= sc520_spunk.o flash.o
-SOBJS	:= sc520_spunk_asm.o sc520_spunk_asm16.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+COBJS-y	+= sc520_spunk.o
+COBJS-y	+= flash.o
+COBJS-$(CONFIG_PCI) += sc520_spunk_pci.o
+SOBJS-y	+= sc520_spunk_asm.o
+SOBJS-y	+= sc520_spunk_asm16.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c
index dbb5c48..09f11bb 100644
--- a/board/sc520_spunk/sc520_spunk.c
+++ b/board/sc520_spunk/sc520_spunk.c
@@ -23,13 +23,10 @@
  */
 
 #include <common.h>
-#include <pci.h>
 #include <netdev.h>
 #include <ds1722.h>
 #include <asm/io.h>
-#include <asm/pci.h>
 #include <asm/ic/sc520.h>
-#include <asm/ic/pci.h>
 #include <asm/ic/ssi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -98,156 +95,6 @@ static void irq_init(void)
 
 }
 
-
-/* PCI stuff */
-static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	int version = sc520_mmcr->sysinfo;
-
-	/* a configurable lists of irqs to steal
-	 * when we need one (a board with more pci interrupt pins
-	 * would use a larger table */
-	static int irq_list[] = {
-		CONFIG_SYS_FIRST_PCI_IRQ,
-		CONFIG_SYS_SECOND_PCI_IRQ,
-		CONFIG_SYS_THIRD_PCI_IRQ,
-		CONFIG_SYS_FORTH_PCI_IRQ
-	};
-	static int next_irq_index=0;
-
-	uchar tmp_pin;
-	int pin;
-
-	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
-	pin = tmp_pin;
-
-	pin-=1; /* pci config space use 1-based numbering */
-	if (-1 == pin) {
-		return; /* device use no irq */
-	}
-
-
-	/* map device number +  pin to a pin on the sc520 */
-	switch (PCI_DEV(dev)) {
-	case 6:  /* ETH0 */
-		pin+=SC520_PCI_INTA;
-		break;
-
-	case 7:  /* ETH1 */
-		pin+=SC520_PCI_INTB;
-		break;
-
-	case 8:  /* Crypto */
-		pin+=SC520_PCI_INTC;
-		break;
-
-	case 9: /* PMC slot */
-		pin+=SC520_PCI_INTD;
-		break;
-
-	case 10: /* PC-Card */
-
-		if (version < 10) {
-			pin+=SC520_PCI_INTD;
-		} else {
-			pin+=SC520_PCI_INTC;
-		}
-		break;
-
-	default:
-		return;
-	}
-
-	pin&=3; /* wrap around */
-
-	if (sc520_pci_ints[pin] == -1) {
-		/* re-route one interrupt for us */
-		if (next_irq_index > 3) {
-			return;
-		}
-		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
-			return;
-		}
-		next_irq_index++;
-	}
-
-
-	if (-1 != sc520_pci_ints[pin]) {
-		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
-					   sc520_pci_ints[pin]);
-	}
-#if 0
-	printf("fixup_irq: device %d pin %c irq %d\n",
-	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
-#endif
-}
-
-
-static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose,
-					      pci_dev_t dev, struct pci_config_table *te)
-{
-	u32 io_base;
-	u32 temp;
-
-	pciauto_config_device(hose, dev);
-
-	pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07);  /* enable device */
-	pci_hose_write_config_byte(hose, dev, 0x0c, 0x10);         /* cacheline size */
-	pci_hose_write_config_byte(hose, dev, 0x0d, 0x40);         /* latency timer */
-	pci_hose_write_config_byte(hose, dev, 0x1b, 0x40);         /* cardbus latency timer */
-	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040);  /* reset cardbus */
-	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080);  /* route interrupts though ExCA */
-	pci_hose_write_config_word(hose, dev,  0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
-
-	pci_hose_read_config_dword(hose, dev,  0x80, &temp); /* System control */
-	pci_hose_write_config_dword(hose, dev,  0x80, temp | 0x60); /* System control: disable clockrun */
-	/* route MF0 to ~INT and MF3 to IRQ7
-	 * reserve all others */
-	pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002);
-	pci_hose_write_config_byte(hose, dev, 0x91, 0x00);    /* card control */
-	pci_hose_write_config_byte(hose, dev, 0x92, 0x62);    /* device control */
-
-	if (te->device != 0xac56) {
-		pci_hose_write_config_byte(hose, dev, 0x93, 0x21);    /* async interrupt enable */
-		pci_hose_write_config_word(hose, dev, 0xa8, 0x0000);  /* reset GPIO */
-		pci_hose_write_config_word(hose, dev, 0xac, 0x0000);  /* reset GPIO */
-		pci_hose_write_config_word(hose, dev, 0xaa, 0x0000);  /* reset GPIO */
-		pci_hose_write_config_word(hose, dev, 0xae, 0x0000);  /* reset GPIO */
-	} else {
-		pci_hose_write_config_byte(hose, dev, 0x93, 0x20);    /*  */
-	}
-	pci_hose_write_config_word(hose, dev, 0xa4, 0x8000);  /* reset power management */
-
-
-	pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
-	io_base &= ~0xfL;
-
-	writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
-	writel(0, io_base+0x10);     /* CLKRUN default */
-	writel(0, io_base+0x20);     /* CLKRUN default */
-
-}
-
-
-static struct pci_config_table pci_sc520_spunk_config_table[] = {
-	{ 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
-	{ 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
-	{ 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
-};
-
-static struct pci_controller sc520_spunk_hose = {
-	fixup_irq: pci_sc520_spunk_fixup_irq,
-	config_table: pci_sc520_spunk_config_table,
-	first_busno: 0x00,
-	last_busno: 0xff,
-};
-
-void pci_init_board(void)
-{
-	pci_sc520_init(&sc520_spunk_hose);
-}
-
-
 /* set up the ISA bus timing and system address mappings */
 static void bus_init(void)
 {
@@ -334,151 +181,6 @@ static void bus_init(void)
  */
 
 /*
- * This function should map a chunk of size bytes
- * of the system address space to the ISA bus
- *
- * The function will return the memory address
- * as seen by the host (which may very will be the
- * same as the bus address)
- */
-u32 isa_map_rom(u32 bus_addr, int size)
-{
-	u32 par;
-
-	printf("isa_map_rom asked to map %d bytes at %x\n",
-	       size, bus_addr);
-
-	par = size;
-	if (par < 0x80000) {
-		par = 0x80000;
-	}
-	par >>= 12;
-	par--;
-	par&=0x7f;
-	par <<= 18;
-	par |= (bus_addr>>12);
-	par |= 0x50000000;
-
-	printf ("setting PAR11 to %x\n", par);
-
-	/* Map rom 0x10000 with PAR1 */
-	sc520_mmcr->par[11] = par;
-
-	return bus_addr;
-}
-
-/*
- * this function removed any mapping created
- * with pci_get_rom_window()
- */
-void isa_unmap_rom(u32 addr)
-{
-	printf("isa_unmap_rom asked to unmap %x", addr);
-	if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
-		sc520_mmcr->par[11] = 0;
-		printf(" done\n");
-		return;
-	}
-	printf(" not ours\n");
-}
-
-#ifdef CONFIG_PCI
-#define PCI_ROM_TEMP_SPACE 0x10000
-/*
- * This function should map a chunk of size bytes
- * of the system address space to the PCI bus,
- * suitable to map PCI ROMS (bus address < 16M)
- * the function will return the host memory address
- * which should be converted into a bus address
- * before used to configure the PCI rom address
- * decoder
- */
-u32 pci_get_rom_window(struct pci_controller *hose, int size)
-{
-	u32 par;
-
-	par = size;
-	if (par < 0x80000) {
-		par = 0x80000;
-	}
-	par >>= 16;
-	par--;
-	par&=0x7ff;
-	par <<= 14;
-	par |= (PCI_ROM_TEMP_SPACE>>16);
-	par |= 0x72000000;
-
-	printf ("setting PAR1 to %x\n", par);
-
-	/* Map rom 0x10000 with PAR1 */
-	sc520_mmcr->par[1] = par;
-
-	return PCI_ROM_TEMP_SPACE;
-}
-
-/*
- * this function removed any mapping created
- * with pci_get_rom_window()
- */
-void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
-{
-	printf("pci_remove_rom_window: %x", addr);
-	if (addr == PCI_ROM_TEMP_SPACE) {
-		sc520_mmcr->par[1] = 0;
-		printf(" done\n");
-		return;
-	}
-	printf(" not ours\n");
-
-}
-
-/*
- * This function is called in order to provide acces to the
- * legacy video I/O ports on the PCI bus.
- * After this function accesses to I/O ports 0x3b0-0x3bb and
- * 0x3c0-0x3df shuld result in transactions on the PCI bus.
- *
- */
-int pci_enable_legacy_video_ports(struct pci_controller *hose)
-{
-	/* Map video memory to 0xa0000*/
-	sc520_mmcr->par[0] = 0x7200400a;
-
-	/* forward all I/O accesses to PCI */
-	sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
-
-
-	/* so we map away all io ports to pci (only way to access pci io
-	 * below 0x400. But then we have to map back the portions that we dont
-	 * use so that the generate cycles on the GPIO bus where the sio and
-	 * ISA slots are connected, this requre the use of several PAR registers
-	 */
-
-	/* bring 0x100 - 0x2f7 back to ISA using PAR5 */
-	sc520_mmcr->par[5] = 0x31f70100;
-
-	/* com2 use 2f8-2ff */
-
-	/* bring 0x300 - 0x3af back to ISA using PAR7 */
-	sc520_mmcr->par[7] = 0x30af0300;
-
-	/* vga use 3b0-3bb */
-
-	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
-	sc520_mmcr->par[8] = 0x300303bc;
-
-	/* vga use 3c0-3df */
-
-	/* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
-	sc520_mmcr->par[9] = 0x301703e0;
-
-	/* com1 use 3f8-3ff */
-
-	return 0;
-}
-#endif
-
-/*
  * Miscelaneous platform dependent initialisations
  */
 
diff --git a/board/sc520_spunk/sc520_spunk_pci.c b/board/sc520_spunk/sc520_spunk_pci.c
new file mode 100644
index 0000000..1b5d0f1
--- /dev/null
+++ b/board/sc520_spunk/sc520_spunk_pci.c
@@ -0,0 +1,323 @@
+/*
+ *
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <ds1722.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+#include <asm/ic/pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	int version = sc520_mmcr->sysinfo;
+
+	/* a configurable lists of irqs to steal
+	 * when we need one (a board with more pci interrupt pins
+	 * would use a larger table */
+	static int irq_list[] = {
+		CONFIG_SYS_FIRST_PCI_IRQ,
+		CONFIG_SYS_SECOND_PCI_IRQ,
+		CONFIG_SYS_THIRD_PCI_IRQ,
+		CONFIG_SYS_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+
+	uchar tmp_pin;
+	int pin;
+
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+
+	pin-=1; /* pci config space use 1-based numbering */
+	if (-1 == pin) {
+		return; /* device use no irq */
+	}
+
+
+	/* map device number +  pin to a pin on the sc520 */
+	switch (PCI_DEV(dev)) {
+	case 6:  /* ETH0 */
+		pin+=SC520_PCI_INTA;
+		break;
+
+	case 7:  /* ETH1 */
+		pin+=SC520_PCI_INTB;
+		break;
+
+	case 8:  /* Crypto */
+		pin+=SC520_PCI_INTC;
+		break;
+
+	case 9: /* PMC slot */
+		pin+=SC520_PCI_INTD;
+		break;
+
+	case 10: /* PC-Card */
+
+		if (version < 10) {
+			pin+=SC520_PCI_INTD;
+		} else {
+			pin+=SC520_PCI_INTC;
+		}
+		break;
+
+	default:
+		return;
+	}
+
+	pin&=3; /* wrap around */
+
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+			return;
+		}
+		next_irq_index++;
+	}
+
+
+	if (-1 != sc520_pci_ints[pin]) {
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+					   sc520_pci_ints[pin]);
+	}
+#if 0
+	printf("fixup_irq: device %d pin %c irq %d\n",
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+#endif
+}
+
+
+static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose,
+					      pci_dev_t dev, struct pci_config_table *te)
+{
+	u32 io_base;
+	u32 temp;
+
+	pciauto_config_device(hose, dev);
+
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07);  /* enable device */
+	pci_hose_write_config_byte(hose, dev, 0x0c, 0x10);         /* cacheline size */
+	pci_hose_write_config_byte(hose, dev, 0x0d, 0x40);         /* latency timer */
+	pci_hose_write_config_byte(hose, dev, 0x1b, 0x40);         /* cardbus latency timer */
+	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040);  /* reset cardbus */
+	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080);  /* route interrupts though ExCA */
+	pci_hose_write_config_word(hose, dev,  0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
+
+	pci_hose_read_config_dword(hose, dev,  0x80, &temp); /* System control */
+	pci_hose_write_config_dword(hose, dev,  0x80, temp | 0x60); /* System control: disable clockrun */
+	/* route MF0 to ~INT and MF3 to IRQ7
+	 * reserve all others */
+	pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002);
+	pci_hose_write_config_byte(hose, dev, 0x91, 0x00);    /* card control */
+	pci_hose_write_config_byte(hose, dev, 0x92, 0x62);    /* device control */
+
+	if (te->device != 0xac56) {
+		pci_hose_write_config_byte(hose, dev, 0x93, 0x21);    /* async interrupt enable */
+		pci_hose_write_config_word(hose, dev, 0xa8, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xac, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xaa, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xae, 0x0000);  /* reset GPIO */
+	} else {
+		pci_hose_write_config_byte(hose, dev, 0x93, 0x20);    /*  */
+	}
+	pci_hose_write_config_word(hose, dev, 0xa4, 0x8000);  /* reset power management */
+
+
+	pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
+	io_base &= ~0xfL;
+
+	writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
+	writel(0, io_base+0x10);     /* CLKRUN default */
+	writel(0, io_base+0x20);     /* CLKRUN default */
+
+}
+
+
+static struct pci_config_table pci_sc520_spunk_config_table[] = {
+	{ 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
+	{ 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
+	{ 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
+};
+
+static struct pci_controller sc520_spunk_hose = {
+	fixup_irq: pci_sc520_spunk_fixup_irq,
+	config_table: pci_sc520_spunk_config_table,
+	first_busno: 0x00,
+	last_busno: 0xff,
+};
+
+void pci_init_board(void)
+{
+	pci_sc520_init(&sc520_spunk_hose);
+}
+
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ *
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size)
+{
+	u32 par;
+
+	printf("isa_map_rom asked to map %d bytes at %x\n",
+	       size, bus_addr);
+
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 12;
+	par--;
+	par&=0x7f;
+	par <<= 18;
+	par |= (bus_addr>>12);
+	par |= 0x50000000;
+
+	printf ("setting PAR11 to %x\n", par);
+
+	/* Map rom 0x10000 with PAR1 */
+	sc520_mmcr->par[11] = par;
+
+	return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+	printf("isa_unmap_rom asked to unmap %x", addr);
+	if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
+		sc520_mmcr->par[11] = 0;
+		printf(" done\n");
+		return;
+	}
+	printf(" not ours\n");
+}
+
+#define PCI_ROM_TEMP_SPACE 0x10000
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size)
+{
+	u32 par;
+
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 16;
+	par--;
+	par&=0x7ff;
+	par <<= 14;
+	par |= (PCI_ROM_TEMP_SPACE>>16);
+	par |= 0x72000000;
+
+	printf ("setting PAR1 to %x\n", par);
+
+	/* Map rom 0x10000 with PAR1 */
+	sc520_mmcr->par[1] = par;
+
+	return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+	printf("pci_remove_rom_window: %x", addr);
+	if (addr == PCI_ROM_TEMP_SPACE) {
+		sc520_mmcr->par[1] = 0;
+		printf(" done\n");
+		return;
+	}
+	printf(" not ours\n");
+
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus.
+ * After this function accesses to I/O ports 0x3b0-0x3bb and
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ *
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+	/* Map video memory to 0xa0000*/
+	sc520_mmcr->par[0] = 0x7200400a;
+
+	/* forward all I/O accesses to PCI */
+	sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
+
+
+	/* so we map away all io ports to pci (only way to access pci io
+	 * below 0x400. But then we have to map back the portions that we dont
+	 * use so that the generate cycles on the GPIO bus where the sio and
+	 * ISA slots are connected, this requre the use of several PAR registers
+	 */
+
+	/* bring 0x100 - 0x2f7 back to ISA using PAR5 */
+	sc520_mmcr->par[5] = 0x31f70100;
+
+	/* com2 use 2f8-2ff */
+
+	/* bring 0x300 - 0x3af back to ISA using PAR7 */
+	sc520_mmcr->par[7] = 0x30af0300;
+
+	/* vga use 3b0-3bb */
+
+	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+	sc520_mmcr->par[8] = 0x300303bc;
+
+	/* vga use 3c0-3df */
+
+	/* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
+	sc520_mmcr->par[9] = 0x301703e0;
+
+	/* com1 use 3f8-3ff */
+
+	return 0;
+}
diff --git a/lib_i386/Makefile b/lib_i386/Makefile
index ec6f236..bb9b330 100644
--- a/lib_i386/Makefile
+++ b/lib_i386/Makefile
@@ -32,8 +32,8 @@ SOBJS-y	+= realmode_switch.o
 COBJS-y	+= bios_setup.o
 COBJS-y	+= board.o
 COBJS-y	+= bootm.o
-COBJS-y	+= pci.o
-COBJS-y	+= pci_type1.o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS-$(CONFIG_PCI) += pci_type1.o
 COBJS-y	+= realmode.o
 COBJS-y	+= video_bios.o
 COBJS-y	+= video.o
diff --git a/lib_i386/pci.c b/lib_i386/pci.c
index f366bdc..9020e7c 100644
--- a/lib_i386/pci.c
+++ b/lib_i386/pci.c
@@ -26,7 +26,6 @@
 #include <asm/io.h>
 #include <asm/pci.h>
 
-#ifdef CONFIG_PCI
 #undef PCI_ROM_SCAN_VERBOSE
 
 int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
@@ -151,5 +150,3 @@ int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
 
 	return res;
 }
-
-#endif
diff --git a/lib_i386/pci_type1.c b/lib_i386/pci_type1.c
index 8da8c1c..225ae4a 100644
--- a/lib_i386/pci_type1.c
+++ b/lib_i386/pci_type1.c
@@ -11,9 +11,6 @@
  */
 
 #include <common.h>
-
-#ifdef CONFIG_PCI
-
 #include <asm/io.h>
 #include <pci.h>
 
@@ -52,5 +49,3 @@ void pci_setup_type1(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
 	hose->cfg_addr = (unsigned int *) cfg_addr;
 	hose->cfg_data = (unsigned char *) cfg_data;
 }
-
-#endif
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 14/17] Add PCI support to eNET board

[Graeme Russ]

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 board/eNET/Makefile    |    1 +
 board/eNET/eNET_pci.c  |   95 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/configs/eNET.h |   14 ++++----
 3 files changed, 103 insertions(+), 7 deletions(-)
 create mode 100644 board/eNET/eNET_pci.c

diff --git a/board/eNET/Makefile b/board/eNET/Makefile
index bf5736a..588d21d 100644
--- a/board/eNET/Makefile
+++ b/board/eNET/Makefile
@@ -32,6 +32,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS-y	+= eNET.o
+COBJS-$(CONFIG_PCI) += eNET_pci.o
 SOBJS-y	+= eNET_start16.o
 SOBJS-y	+= eNET_start.o
 
diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c
new file mode 100644
index 0000000..e80a8fe
--- /dev/null
+++ b/board/eNET/eNET_pci.c
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ at gmail.com.
+ *
+ * (C) Copyright 2002
+ * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/ic/pci.h>
+
+static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	/* a configurable lists of IRQs to steal when we need one */
+	static int irq_list[] = {
+		CONFIG_SYS_FIRST_PCI_IRQ,
+		CONFIG_SYS_SECOND_PCI_IRQ,
+		CONFIG_SYS_THIRD_PCI_IRQ,
+		CONFIG_SYS_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+
+	uchar tmp_pin;
+	int pin;
+
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+
+	pin -= 1; /* PCI config space use 1-based numbering */
+	if (pin == -1) {
+		return; /* device use no irq */
+	}
+
+	/* map device number +  pin to a pin on the sc520 */
+	switch (PCI_DEV(dev)) {
+	case 12:	/* First Ethernet Chip */
+		pin += SC520_PCI_INTA;
+		break;
+
+	case 13:	/* Second Ethernet Chip */
+		pin += SC520_PCI_INTB;
+		break;
+
+	default:
+		return;
+	}
+
+	pin &= 3; /* wrap around */
+
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+			return;
+		}
+		next_irq_index++;
+	}
+
+	if (-1 != sc520_pci_ints[pin]) {
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+					   sc520_pci_ints[pin]);
+	}
+	printf("fixup_irq: device %d pin %c irq %d\n",
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+}
+
+static struct pci_controller enet_hose = {
+	fixup_irq: pci_enet_fixup_irq,
+};
+
+void pci_init_board(void)
+{
+	pci_sc520_init(&enet_hose);
+}
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index 4356714..243a554 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -86,6 +86,7 @@
 #define CONFIG_CMD_MISC		/* Misc functions like sleep etc*/
 #undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
 #undef CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_PCI		/* PCI support			*/
 #define CONFIG_CMD_RUN		/* run command in env variable	*/
 #define CONFIG_CMD_SAVEENV	/* saveenv			*/
 #define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
@@ -200,13 +201,12 @@
  /*-----------------------------------------------------------------------
   * PCI configuration
   */
-#undef CONFIG_PCI                                /* include pci support */
-#undef CONFIG_PCI_PNP                            /* pci plug-and-play */
-#undef CONFIG_PCI_SCAN_SHOW
-#undef CONFIG_SYS_FIRST_PCI_IRQ
-#undef CONFIG_SYS_SECOND_PCI_IRQ
-#undef CONFIG_SYS_THIRD_PCI_IRQ
-#undef CONFIG_SYS_FORTH_PCI_IRQ
+#define CONFIG_PCI                                /* include pci support */
+#define CONFIG_PCI_PNP                            /* pci plug-and-play */
+#define CONFIG_SYS_FIRST_PCI_IRQ   10
+#define CONFIG_SYS_SECOND_PCI_IRQ  9
+#define CONFIG_SYS_THIRD_PCI_IRQ   11
+#define CONFIG_SYS_FORTH_PCI_IRQ   15
 
 /*-----------------------------------------------------------------------
  * Hardware watchdog configuration
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 15/17] Move eNET low-level initialisation into asm

[Graeme Russ]

Allows earlier indication of boot progress by initialising the LEDs and
Serial Port while the CPU is still in 16-bit (Real) mode

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 board/eNET/eNET.c           |   24 --------
 board/eNET/eNET_start.S     |    7 ++-
 board/eNET/eNET_start16.S   |  130 ++++++++++++++++++++++++++++++++++++++++++-
 board/eNET/hardware.h       |   16 +++++
 include/asm-i386/ic/sc520.h |   20 ++++++-
 5 files changed, 167 insertions(+), 30 deletions(-)

diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 29cf295..3dc63a8 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -46,14 +46,6 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
 void init_sc520_enet (void)
 {
 	/* Set CPU Speed to 100MHz */
-	sc520_mmcr->cpuctl = 0x01;
-	gd->cpu_clk = 100000000;
-
-	/* wait at least one millisecond */
-	asm("movl	$0x2000,%%ecx\n"
-	    "0:	pushl %%ecx\n"
-	    "popl	%%ecx\n"
-	    "loop 0b\n": : : "ecx");
 
 	/* turn on the SDRAM write buffer */
 	sc520_mmcr->dbctl = 0x11;
@@ -79,14 +71,6 @@ int board_init(void)
 	sc520_mmcr->gpwrw = 0x05;		/* GP Write pulse width */
 	sc520_mmcr->gpwroff = 0x01;		/* GP Write offset */
 
-	sc520_mmcr->piodata15_0 = 0x0630;	/* PIO15_PIO0 Data */
-	sc520_mmcr->piodata31_16 = 0x2000;	/* PIO31_PIO16 Data */
-	sc520_mmcr->piodir31_16 = 0x2000;	/* GPIO Direction */
-	sc520_mmcr->piodir15_0 = 0x87b5;	/* GPIO Direction */
-	sc520_mmcr->piopfs31_16 = 0x0dfe;	/* GPIO pin function 31-16 reg */
-	sc520_mmcr->piopfs15_0 = 0x200a;	/* GPIO pin function 15-0 reg */
-	sc520_mmcr->cspfs = 0x00f8;		/* Chip Select Pin Function Select */
-
 	sc520_mmcr->par[2] = 0x200713f8;	/* Uart A (GPCS0, 0x013f8, 8 Bytes) */
 	sc520_mmcr->par[3] = 0x2c0712f8;	/* Uart B (GPCS3, 0x012f8, 8 Bytes) */
 	sc520_mmcr->par[4] = 0x300711f8;	/* Uart C (GPCS4, 0x011f8, 8 Bytes) */
@@ -102,18 +86,10 @@ int board_init(void)
 /*	sc520_mmcr->par14 = 0x8bfff800; */	/* BOOTCS at  0x18000000 */
 /*	sc520_mmcr->par15 = 0x38201000; */	/* LEDs etc (GPCS6, 0x1000, 20 Bytes */
 
-	/* Disable Watchdog */
-	sc520_mmcr->wdtmrctl = 0x3333;
-	sc520_mmcr->wdtmrctl = 0xcccc;
-	sc520_mmcr->wdtmrctl = 0x0000;
-
 	/* Chip Select Configuration */
-	sc520_mmcr->bootcsctl = 0x0033;
 	sc520_mmcr->romcs1ctl = 0x0615;
 	sc520_mmcr->romcs2ctl = 0x0615;
 
-	sc520_mmcr->adddecctl = 0x02;
-	sc520_mmcr->uart1ctl = 0x07;
 	sc520_mmcr->sysarbctl = 0x06;
 	sc520_mmcr->sysarbmenb = 0x0003;
 
diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S
index 1b07d62..9052935 100644
--- a/board/eNET/eNET_start.S
+++ b/board/eNET/eNET_start.S
@@ -21,12 +21,17 @@
  * MA 02111-1307 USA
  */
 
+#include <asm/ic/sc520.h>
 #include "hardware.h"
 
 /* board early intialization */
 .globl early_board_init
 early_board_init:
-	/* No 32-bit board specific initialisation */
+	/* Light up the LEDs */
+	movw	$LED_LATCH_ADDRESS, %dx
+	movb	$LED_1_BITMASK | LED_2_BITMASK, %al
+	outb	%al, %dx
+
 	jmp	*%ebp		/* return to caller */
 
 .globl show_boot_progress_asm
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
index 48e4d83..31b33ec 100644
--- a/board/eNET/eNET_start16.S
+++ b/board/eNET/eNET_start16.S
@@ -27,8 +27,7 @@
  * that is used by U-boot to its final destination.
  */
 
-/* #include <asm/ic/sc520_defs.h> */
-
+#include <asm/ic/sc520.h>
 #include "hardware.h"
 
 .text
@@ -45,6 +44,65 @@ board_init16:
 	movw	$0xdf00, %ax
 	movw	%ax, %ds
 
+	/* Disable Watchdog */
+	movl    $SC520_WDTMRCTL, %edi
+	movw	$0x3333, %ax
+	movw	%ax, (%di)
+	movw	$0xcccc, %ax
+	movw	%ax, (%di)
+	movw	$0x3333, %ax
+	movw	%ax, (%di)
+
+	/* Set CPU to 100MHz Speed */
+	movb	$0x01, %al
+	movl    $SC520_CPUCTL, %edi
+	movb	%al, (%di)
+
+	/* wait at least one millisecond */
+	movl	$0x1000,%ecx
+cpuspddelay:
+	loop 	cpuspddelay
+
+	/* PIO15_PIO0 Data */
+	movl    $SC520_PIODATA15_0, %edi
+	movw	$0x0630, %ax
+	movw	%ax, (%di)
+
+	/* PIO31_PIO16 Data */
+	movl    $SC520_PIODATA31_16, %edi
+	movw	$0x2000, %ax
+	movw	%ax, (%di)
+
+	/* PIO Direction */
+	movl    $SC520_PIODIR31_16, %edi
+	movw	$0x2000, %ax
+	movw	%ax, (%di)
+
+	/* PIO Direction */
+	movl    $SC520_PIODIR15_0, %edi
+	movw	$0x87b5, %ax
+	movw	%ax, (%di)
+
+	/* PIO pin function 31-16 reg */
+	movl    $SC520_PIOPFS31_16, %edi
+	movw	$0x0dfe, %ax
+	movw	%ax, (%di)
+
+	/* PIO pin function 15-0 reg */
+	movl    $SC520_PIOPFS15_0, %edi
+	movw	$0x200a, %ax
+	movw	%ax, (%di)
+
+	/* Chip Select Pin Function Select */
+	movl    $SC520_CSPFS, %edi
+	movw	$0x00f8, %ax
+	movw	%ax, (%di)
+
+	/* Setup Chip Select for Boot Flash */
+	movl    $SC520_BOOTCSCTL, %edi
+	movw	$0x0033, %ax
+	movl	%eax, (%di)
+
 	/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
 	movl    $0x00c0, %edi		/* SC520_PAR14 */
 	movl	$0x8bfff800, %eax	/* TODO: Check this */
@@ -60,6 +118,74 @@ board_init16:
 	xorw    %ax, %ax
 	movb    %al, (%di)
 
+	/* Enable UART 1 */
+	movl    $SC520_ADDDECCTL, %edi
+	movb	$0x02, %al
+	movb	%al, (%di)
+
+	/* Configure UART 1 - 9600 Baud 8N1 */
+	movl    $SC520_UART1CTL, %edi
+	movb	$0x07, %al
+	movb	%al, (%di)
+
+	/* Set DLAB bit */
+	movw	$(UART0_BASE + UART_LCR), %dx
+	movb	$0x80, %al
+	outb	%al, %dx
+
+	/* Set baudrate divisor (LSB) */
+	movw	$(UART0_BASE + UART_DLL), %dx
+	movb	$0x0c, %al
+	outb	%al, %dx
+
+	/* Set baudrate divisor (MSB) */
+	movw	$(UART0_BASE + UART_DLM), %dx
+	movb	$0x00, %al
+	outb	%al, %dx
+
+	/* clear DLAB; set 8 bits, no parity */
+	movw	$(UART0_BASE + UART_LCR), %dx
+	movb	$0x03, %al
+	outb	%al, %dx
+
+	/* enable FIFO */
+	movw	$(UART0_BASE + UART_FCR), %dx
+	movb	$0x01, %al
+	outb	%al, %dx
+
+	/* Set DTR and RTS active */
+	movw	$(UART0_BASE + UART_MCR), %dx
+	movb	$0x0b, %al
+	outb	%al, %dx
+
+	/* clear line status */
+	movw	$(UART0_BASE + UART_LSR), %dx
+	inb	%dx, %al
+
+	/* read receive buffer */
+	movw	$(UART0_BASE + UART_RBR), %dx
+	inb	%dx, %al
+
+	/* set scratchpad */
+	movw	$(UART0_BASE + UART_SCR), %dx
+	movb	$0x00, %al
+	outb	%al, %dx
+
+	/* Disable Interrupts */
+	movw	$(UART0_BASE + UART_IER), %dx
+	movb	$0x00, %al
+	outb	%al, %dx
+
+	/* wait for the UART clock to settle */
+	movl	$0x10000,%ecx
+uartdelay:
+	loop 	uartdelay
+
+	/* Light up the LEDs */
+	movw	$LED_LATCH_ADDRESS, %dx
+	movb	$LED_1_BITMASK, %al
+	outb	%al, %dx
+
 	/* Disabe MMCR alias */
 	movw	$0xfffc, %dx
 	movl	$0x000000cb, %eax
diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h
index 42474a6..5a8ae40 100644
--- a/board/eNET/hardware.h
+++ b/board/eNET/hardware.h
@@ -32,4 +32,20 @@
 #define LED_TX_BITMASK		0x10
 #define LED_ERR_BITMASK		0x20
 
+/* Serial Port Definitions */
+#define UART0_BASE 		0x3f8
+
+#define UART_RBR   		0x00
+#define UART_THR   		0x00
+#define UART_IER  		0x01
+#define UART_IIR  		0x02
+#define UART_FCR  		0x02
+#define UART_LCR   		0x03
+#define UART_MCR   		0x04
+#define UART_LSR  		0x05
+#define UART_MSR   		0x06
+#define UART_SCR   		0x07
+#define UART_DLL   		0x00
+#define UART_DLM   		0x01
+
 #endif /* HARDWARE_H_ */
diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h
index 57c9904..723e38f 100644
--- a/include/asm-i386/ic/sc520.h
+++ b/include/asm-i386/ic/sc520.h
@@ -1,6 +1,6 @@
 /*
  * (C) Copyright 2002
- * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
+ * Daniel Engstr???m, Omicron Ceti AB <daniel@omicron.se>.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -134,7 +134,8 @@ typedef struct sc520_mmcr {
 	u16 gptmr0cnt;		/* GP timer 0 count */
 	u16 gptmr0maxcmpa;	/* GP timer 0 maxcount compare A */
 	u16 gptmr0maxcmpb;	/* GP timer 0 maxcount compare B */
-	u16 gptmr1ctl;		/* GP timer 1 mode/control */
+	u16 gptmr1ctl;		/*#define SC520_SWTMRMILLI	0x
+	 GP timer 1 mode/control */
 	u16 gptmr1cnt;		/* GP timer 1 count */
 	u16 gptmr1maxcmpa;	/* GP timer 1 maxcount compare A */
 	u16 gptmr1maxcmpb;	/* GP timer 1 maxcount compare B*/
@@ -223,7 +224,8 @@ typedef struct sc520_mmcr {
 	u8  pad_0xd8d[0x03];
 	u8  gpdmaexttc3;	/* GP-DMA channel 3 extender transfer count */
 	u8  gpdmaexttc5;	/* GP-DMA channel 5 extender transfer count */
-	u8  gpdmaexttc6;	/* GP-DMA channel 6 extender transfer count */
+	u8  gpdmaexttc6;	/* GP-DMA ch+#define SC520_CPUCTL		0x0001
+	annel 6 extender transfer count */
 	u8  gpdmaexttc7;	/* GP-DMA channel 7 extender transfer count */
 	u8  pad_0xd94[0x4];
 	u8  gpdmabcctl;		/* buffer chaining control */
@@ -256,11 +258,23 @@ extern volatile sc520_mmcr_t *sc520_mmcr;
 #endif
 
 /* MMCR Offsets (required for assembler code */
+#define SC520_CPUCTL		0x0001	/* CPU Control */
 #define SC520_DBCTL		0x0040	/* SDRAM Buffer Control Register */
+#define SC520_BOOTCSCTL		0x0050	/* BOOT Flaash Chip Select Control */
+#define SC520_ADDDECCTL		0x0080	/* Address Decode Control */
 #define SC520_PAR14		0x00c0	/* Programmable Address Region 14 Register */
 #define SC520_PAR15		0x00c4	/* Programmable Address Region 15 Register */
+#define SC520_PIOPFS15_0	0x0c20	/* GPIO pin function 15-0 reg */
+#define SC520_PIOPFS31_16	0x0c22	/* GPIO pin function 31-16 reg */
+#define SC520_CSPFS		0x0c24	/* Chip Select Pin Function Select */
+#define SC520_PIODIR15_0	0x0c2a	/* GPIO Direction */
+#define SC520_PIODIR31_16	0x0c2c	/* GPIO Direction */
+#define SC520_PIODATA15_0	0x0c30	/* PIO15_PIO0 Data */
+#define SC520_PIODATA31_16	0x0c32	/* PIO31_PIO16 Data */
 #define SC520_SWTMRMILLI	0x0c60  /* Software Timer Millisecond Count */
 #define SC520_SWTMRMICRO	0x0c62  /* Software Timer Microsecond Count */
+#define SC520_WDTMRCTL		0x0cb0	/* Watchdog Timer Control */
+#define SC520_UART1CTL		0x0cc0	/* UART 1 Control */
 
 /* MMCR Register bits (not all of them :) ) */
 
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 16/17] Move low level eNET board init into dedicated sections

[Graeme Russ]

This patch is in readiness for moving all u-boot code + data from Flash to
RAM. Low level init code is not needed after bootstrap and therefore does
not need to be copied. Moving this code into dedicated sections makes it
easier

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 board/eNET/eNET_start.S             |    3 +++
 board/eNET/u-boot.lds               |    4 ++--
 board/sc520_cdp/sc520_cdp_asm.S     |    1 +
 board/sc520_cdp/u-boot.lds          |    4 ++--
 board/sc520_spunk/sc520_spunk_asm.S |    1 +
 board/sc520_spunk/u-boot.lds        |    4 ++--
 cpu/i386/sc520/sc520_asm.S          |    2 +-
 cpu/i386/start.S                    |    2 +-
 8 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S
index 9052935..54675c0 100644
--- a/board/eNET/eNET_start.S
+++ b/board/eNET/eNET_start.S
@@ -24,6 +24,9 @@
 #include <asm/ic/sc520.h>
 #include "hardware.h"
 
+.section .start32, "ax"
+
+
 /* board early intialization */
 .globl early_board_init
 early_board_init:
diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds
index 4ea424d..284d2bd 100644
--- a/board/eNET/u-boot.lds
+++ b/board/eNET/u-boot.lds
@@ -78,8 +78,8 @@ SECTIONS
 	 * The fff0 offset of resetvec is important, however.
 	 */
 
-	. = 0xfffffe00;
-	.start32 : AT (0x3807fe00) { *(.start32); }
+	. = 0xffffee00;
+	.start32 : AT (0x3807ee00) { *(.start32); }
 
 	. = 0xf800;
 	.start16 : AT (0x3807f800) { *(.start16); }
diff --git a/board/sc520_cdp/sc520_cdp_asm.S b/board/sc520_cdp/sc520_cdp_asm.S
index 3a8a03f..904cfb9 100644
--- a/board/sc520_cdp/sc520_cdp_asm.S
+++ b/board/sc520_cdp/sc520_cdp_asm.S
@@ -25,6 +25,7 @@
  * We can then use the leds to display status information.
  */
 
+.section .start32, "ax"
 sc520_cdp_registers:
 /* size    offset        value */
 .word 1 ; .word 0x040 ; .long 0x00       /* SDRAM buffer control */
diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds
index df437c7..d232dc1 100644
--- a/board/sc520_cdp/u-boot.lds
+++ b/board/sc520_cdp/u-boot.lds
@@ -79,8 +79,8 @@ SECTIONS
 	 */
 
 
-	. = 0xfffffe00;
-	.start32 : AT (0x387ffe00) { *(.start32); }
+	. = 0xffffee00;
+	.start32 : AT (0x3807ee00) { *(.start32); }
 
 	. = 0xff00;
 	.start16 : AT (0x387fff00) { *(.start16); }
diff --git a/board/sc520_spunk/sc520_spunk_asm.S b/board/sc520_spunk/sc520_spunk_asm.S
index eda7e91..020bd02 100644
--- a/board/sc520_spunk/sc520_spunk_asm.S
+++ b/board/sc520_spunk/sc520_spunk_asm.S
@@ -25,6 +25,7 @@
  * We can then use the leds to display status information.
  */
 
+.section .start32, "ax"
 sc520_cdp_registers:
 /* size    offset        value */
 .word 1 ; .word 0x040 ; .long 0x00       /* SDRAM buffer control */
diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds
index efb570b..f6d1abf 100644
--- a/board/sc520_spunk/u-boot.lds
+++ b/board/sc520_spunk/u-boot.lds
@@ -80,8 +80,8 @@ SECTIONS
 	 */
 
 
-	. = 0xfffffe00;
-	.start32 : AT (0x387ffe00) { *(.start32); }
+	. = 0xffffee00;
+	.start32 : AT (0x3807ee00) { *(.start32); }
 
 	. = 0xff00;
 	.start16 : AT (0x387fff00) { *(.start16); }
diff --git a/cpu/i386/sc520/sc520_asm.S b/cpu/i386/sc520/sc520_asm.S
index 2042d9b..07e2acd 100644
--- a/cpu/i386/sc520/sc520_asm.S
+++ b/cpu/i386/sc520/sc520_asm.S
@@ -106,7 +106,7 @@
 
 #include <config.h>
 
-.section .text
+.section .start32, "ax"
 .equ            DRCCTL,     0x0fffef010   /* DRAM control register */
 .equ            DRCTMCTL,   0x0fffef012   /* DRAM timing control register */
 .equ            DRCCFG,     0x0fffef014   /* DRAM bank configuration register */
diff --git a/cpu/i386/start.S b/cpu/i386/start.S
index 59089ef..bb4a5cf 100644
--- a/cpu/i386/start.S
+++ b/cpu/i386/start.S
@@ -27,7 +27,7 @@
 #include <version.h>
 
 
-.section .text
+.section .start32, "ax"
 .code32
 .globl _start
 .type _start, @function
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 17/17] Change entire eNET code + data to run from RAM

[Graeme Russ]

Flash probing can cause the Boot Flash to lock up - Entire contents of
Flash (minus the low level asm init which is not needed post-bootstrap)
is copied to RAM

This is not an ideal relocation mechanism. This change sets TEXT_BASE
to an area just below the guaranteed 64MB RAM which exists on all eNET
boards. At some stage in the future, I hope to implement a proper
relocation mechanism

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
 board/eNET/config.mk   |    2 +-
 board/eNET/u-boot.lds  |   65 ++++++++++++++++++++++++++++-------------------
 cpu/i386/start.S       |    8 ++++++
 include/configs/eNET.h |    6 ++--
 4 files changed, 51 insertions(+), 30 deletions(-)

diff --git a/board/eNET/config.mk b/board/eNET/config.mk
index a763841..833c66e 100644
--- a/board/eNET/config.mk
+++ b/board/eNET/config.mk
@@ -21,4 +21,4 @@
 # MA 02111-1307 USA
 #
 
-TEXT_BASE = 0x38040000
+TEXT_BASE = 0x03FC0000
diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds
index 284d2bd..7311e8b 100644
--- a/board/eNET/u-boot.lds
+++ b/board/eNET/u-boot.lds
@@ -27,47 +27,42 @@ ENTRY(_start)
 
 SECTIONS
 {
-	. = 0x38040000;		/* Location of bootcode in flash */
+	/*
+	 * All eNET boards have at least 64MB memory on board. The Boot Flash
+	 * is 512kB, but only 256kB of this is used for U-Boot. start.S will
+	 * copy the 256kB U-Boot executable from Flash into RAM starting at
+	 * the address 256kB below 64MB (i.e. 0x03FC0000)
+	 */
+	. = 0x03FC0000;
+ 
+	_i386boot_rom_copy_start = .;
+	/* ---  Begin data copied from Flash --- */
 	.text  : { *(.text); }
-
 	. = ALIGN(4);
-	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
 
-	_i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+	. = ALIGN(4);
 
-	. = 0x03FF0000;		/* Ram data segment to use */
-	_i386boot_romdata_dest = ABSOLUTE(.);
-	.data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
-	_i386boot_romdata_start = LOADADDR(.data);
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	. = ALIGN(4);
 
+	.data : { *(.data) }
 	. = ALIGN(4);
-	.got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
 
+	.got : { *(.got) }
 	. = ALIGN(4);
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
-	_i386boot_cmd_start = LOADADDR(.u_boot_cmd);
 
-	_i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got) + SIZEOF(.u_boot_cmd);
+	/* ---  End data copied from Flash --- */
+	_i386boot_rom_copy_end = .;
 
-	. = ALIGN(4);
-	_i386boot_bss_start = ABSOLUTE(.);
 	.bss (NOLOAD) : { *(.bss) }
-	_i386boot_bss_size = SIZEOF(.bss);
 
 	/* 16bit realmode trampoline code */
 	.realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) + SIZEOF(.u_boot_cmd)) { *(.realmode) }
 
-	_i386boot_realmode = LOADADDR(.realmode);
-	_i386boot_realmode_size = SIZEOF(.realmode);
-
 	/* 16bit BIOS emulation code (just enough to boot Linux) */
 	.bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
 
-	_i386boot_bios = LOADADDR(.bios);
-	_i386boot_bios_size = SIZEOF(.bios);
-
 	/* The load addresses below assumes that the flash
 	 * will be mapped so that 0x387f0000 == 0xffff0000
 	 * at reset time
@@ -79,12 +74,30 @@ SECTIONS
 	 */
 
 	. = 0xffffee00;
-	.start32 : AT (0x3807ee00) { *(.start32); }
+	.start32 : AT (0x03ffee00) { *(.start32); }
 
 	. = 0xf800;
-	.start16 : AT (0x3807f800) { *(.start16); }
+	.start16 : AT (0x03fff800) { *(.start16); }
 
 	. = 0xfff0;
-	.resetvec : AT (0x3807fff0) { *(.resetvec); }
+	.resetvec : AT (0x03fffff0) { *(.resetvec); }
 	_i386boot_end = (LOADADDR(.resetvec) + SIZEOF(.resetvec) );
+
+	/* Export section information */
+	_i386boot_bss_start = ADDR(.bss);
+	_i386boot_bss_size  = SIZEOF(.bss);
+	_i386boot_realmode = LOADADDR(.realmode);
+	_i386boot_realmode_size = SIZEOF(.realmode);
+	_i386boot_bios = LOADADDR(.bios);
+	_i386boot_bios_size = SIZEOF(.bios);
+
+	_i386boot_romdata_start = LOADADDR(.rodata);
+
+	_i386boot_romdata_dest = LOADADDR(.data);
+	_i386boot_cmd_start = LOADADDR(.u_boot_cmd);
+	_i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got) + SIZEOF(.u_boot_cmd);
+
+	__u_boot_cmd_start = ADDR(.u_boot_cmd);
+	__u_boot_cmd_end = ADDR(.u_boot_cmd) + SIZEOF(.u_boot_cmd);
+
 }
diff --git a/cpu/i386/start.S b/cpu/i386/start.S
index bb4a5cf..cb2633f 100644
--- a/cpu/i386/start.S
+++ b/cpu/i386/start.S
@@ -116,10 +116,18 @@ stack_ok:
 	jmp	show_boot_progress_asm
 .progress2:
 
+#ifdef CONFIG_SYS_FULL_CODE_COPY
+	/* copy text, rodata, u_boot_cmd, data, and got sections from Flash */
+	movl	$TEXT_BASE, %edi		/* destination address */
+	movl	$CONFIG_SYS_MONITOR_BASE, %esi	/* source address */
+	movl	$_i386boot_rom_copy_end, %ecx
+	subl	$_i386boot_rom_copy_start, %ecx
+#else
 	/* copy data section to ram, size must be 4-byte aligned */
 	movl	$_i386boot_romdata_dest, %edi	  /* destination address */
 	movl	$_i386boot_romdata_start, %esi	  /* source address */
 	movl	$_i386boot_romdata_size, %ecx     /* number of bytes to copy */
+#endif
 	movl	%ecx, %eax
 	andl	$3, %eax
 	jnz	data_fail
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index 243a554..cfcd909 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -28,6 +28,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SYS_FULL_CODE_COPY
 /*
  * Stuff still to be dealt with -
  */
@@ -154,9 +156,7 @@
  * Memory organization
  */
 #define CONFIG_SYS_STACK_SIZE		0x8000  	/* Size of bootloader stack */
-#define CONFIG_SYS_BL_START_FLASH	0x38040000	/* Address of relocated code */
-#define CONFIG_SYS_BL_START_RAM		0x03fd0000	/* Address of relocated code */
-#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE         0x38040000	/* Address of code in Boot Flash */
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon	*/
 #define CONFIG_SYS_FLASH_BASE		0x38000000	/* Boot Flash */
 #define CONFIG_SYS_FLASH_BASE_1		0x10000000	/* StrataFlash 1 */
-- 
1.6.0.2.GIT

[U-Boot] [PATCH 00/17] i386 Updates (touches some common drivers)

[Mike Frysinger]

please set sendemail.chainreplyto to false in your git settings.  patch series 
should be like:
[summary 0/xx]
|- [patch 1/xx]
|- [patch 2/xx]
....

not:
[summary 0/xx]
`- [patch 1/xx]
  `- [patch 2/xx]
    `- ....

the latter makes things a lot more painful for people to parse with their e-
mail clients.

you might have to update your git if it doesnt support this option (i see 
you're using 1.6.0 where as latest release is 1.6.4) ...
-mike
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[U-Boot] [PATCH 00/17] i386 Updates (touches some common drivers)

[Wolfgang Denk]

Dear Mike Frysinger,

In message <200908230001.46558.vapier@gentoo.org> you wrote:
>
> please set sendemail.chainreplyto to false in your git settings.  patch series 

Why that?

> should be like:
> [summary 0/xx]
> |- [patch 1/xx]
> |- [patch 2/xx]
> ....
>
> not:
> [summary 0/xx]
> `- [patch 1/xx]
>   `- [patch 2/xx]
>     `- ....

On contrary. The second form is much more useful as it also indicates
the order in which patches should be applied - too often people forget
the -n.

> the latter makes things a lot more painful for people to parse with their e-
> mail clients.

Huh? To me that makes no difference. Actually, I like the second form
better.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Every little picofarad has a nanohenry all its own.      - Don Vonada

[U-Boot] [PATCH 00/17] i386 Updates (touches some common drivers)

[Mike Frysinger]

On Sunday 23 August 2009 01:36:55 Wolfgang Denk wrote:
> Mike Frysinger wrote:
> > please set sendemail.chainreplyto to false in your git settings.  patch
> > series
>
> Why that?
>
> > should be like:
> > [summary 0/xx]
> >
> > |- [patch 1/xx]
> > |- [patch 2/xx]
> >
> > ....
> >
> > not:
> > [summary 0/xx]
> > `- [patch 1/xx]
> >   `- [patch 2/xx]
> >     `- ....
>
> On contrary. The second form is much more useful as it also indicates
> the order in which patches should be applied - too often people forget
> the -n.

the numbering indicates the proper order and that is what -n controls.  it's 
not directly related to threading as that is an independent option --chain-
reply-to.

> > the latter makes things a lot more painful for people to parse with their
> > e- mail clients.
>
> Huh? To me that makes no difference. Actually, I like the second form
> better.

you must either not thread your e-mails properly, or your monitor is insanely 
wide and/or you use insanely small fonts.  as soon as you hit 10+ depth on 
threads, subjects easily start getting truncated in the display.  seeing a few 
to no characters in the e-mail reader for a subject is a pita.  if it's all 
the same thread, that's one thing as the subject doesnt really change, but in 
this case they arent.

sane example:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/66481

insane example:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/66597
-mike
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[U-Boot] [PATCH 15/17] Move eNET low-level initialisation into asm

[Graeme Russ]

On Sun, Aug 23, 2009 at 12:59 PM, Graeme Russ<graeme.russ@gmail.com> wrote:
> Allows earlier indication of boot progress by initialising the LEDs and
> Serial Port while the CPU is still in 16-bit (Real) mode
>

Just noticed a couple of quibbles in this patch - Nothing major

> diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h
> index 57c9904..723e38f 100644
> --- a/include/asm-i386/ic/sc520.h
> +++ b/include/asm-i386/ic/sc520.h
> @@ -1,6 +1,6 @@
>  /*
>  * (C) Copyright 2002
> - * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
> + * Daniel Engstr???m, Omicron Ceti AB <daniel@omicron.se>.
>  *
>  * See file CREDITS for list of people who contributed to this
>  * project.
> @@ -134,7 +134,8 @@ typedef struct sc520_mmcr {
>        u16 gptmr0cnt;          /* GP timer 0 count */
>        u16 gptmr0maxcmpa;      /* GP timer 0 maxcount compare A */
>        u16 gptmr0maxcmpb;      /* GP timer 0 maxcount compare B */
> -       u16 gptmr1ctl;          /* GP timer 1 mode/control */
> +       u16 gptmr1ctl;          /*#define SC520_SWTMRMILLI      0x
> +        GP timer 1 mode/control */
>        u16 gptmr1cnt;          /* GP timer 1 count */
>        u16 gptmr1maxcmpa;      /* GP timer 1 maxcount compare A */
>        u16 gptmr1maxcmpb;      /* GP timer 1 maxcount compare B*/
> @@ -223,7 +224,8 @@ typedef struct sc520_mmcr {
>        u8  pad_0xd8d[0x03];
>        u8  gpdmaexttc3;        /* GP-DMA channel 3 extender transfer count */
>        u8  gpdmaexttc5;        /* GP-DMA channel 5 extender transfer count */
> -       u8  gpdmaexttc6;        /* GP-DMA channel 6 extender transfer count */
> +       u8  gpdmaexttc6;        /* GP-DMA ch+#define SC520_CPUCTL               0x0001
> +       annel 6 extender transfer count */
>        u8  gpdmaexttc7;        /* GP-DMA channel 7 extender transfer count */
>        u8  pad_0xd94[0x4];
>        u8  gpdmabcctl;         /* buffer chaining control */

None of these should be in the patch. Should I resubmit now or wait until
discussion on the other parts has been finalised?

Regards

G

[U-Boot] [PATCH 00/17] i386 Updates (touches some common drivers)

[Graeme Russ]

On Sun, Aug 23, 2009 at 4:14 PM, Mike Frysinger<vapier@gentoo.org> wrote:
> On Sunday 23 August 2009 01:36:55 Wolfgang Denk wrote:
>> Mike Frysinger wrote:
>> > please set sendemail.chainreplyto to false in your git settings.  patch
>> > series
>>
>> Why that?
>>

>
> sane example:
> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/66481
>
> insane example:
> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/66597
> -mike

I must say, I agree with Mike - It just looks 'odd' and adds nothing that
[Patch x/y] does not already add

[U-Boot] [PATCH 15/17] Move eNET low-level initialisation into asm

[Mike Frysinger]

On Monday 24 August 2009 03:17:26 Graeme Russ wrote:
> None of these should be in the patch. Should I resubmit now or wait until
> discussion on the other parts has been finalised?

if you need to fix only one or two patches in a series, it's generally 
preferred you fix those one or two patches rather than reposting the whole 
series.  sending a v2 with the reply header set to this patch and a small 
explanation of the change is easy to do and for people to monitor.

if there's something fundamentally wrong with the series, or you made a 
mistake in just about every one, then you should respin and resubmit as a new 
thread.

posting a new series to fix only one or two things makes reviewing much harder 
as it's often unclear what has changed (and thus what exactly needs double 
checking)
-mike
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[U-Boot] [PATCH 15/17] Move eNET low-level initialisation into asm

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-16-git-send-email-graeme.russ@gmail.com> you wrote:
>
> --- a/board/eNET/hardware.h
> +++ b/board/eNET/hardware.h
> @@ -32,4 +32,20 @@
>  #define LED_TX_BITMASK		0x10
>  #define LED_ERR_BITMASK		0x20
>  
> +/* Serial Port Definitions */
> +#define UART0_BASE 		0x3f8
> +
> +#define UART_RBR   		0x00
> +#define UART_THR   		0x00
> +#define UART_IER  		0x01
> +#define UART_IIR  		0x02
> +#define UART_FCR  		0x02
> +#define UART_LCR   		0x03
> +#define UART_MCR   		0x04
> +#define UART_LSR  		0x05
> +#define UART_MSR   		0x06
> +#define UART_SCR   		0x07
> +#define UART_DLL   		0x00
> +#define UART_DLM   		0x01

Please remove all SPACE characters that preceed TAB characters
(s/  *\t/\t/g)

> --- a/include/asm-i386/ic/sc520.h
> +++ b/include/asm-i386/ic/sc520.h
> @@ -1,6 +1,6 @@
>  /*
>   * (C) Copyright 2002
> - * Daniel Engstr?m, Omicron Ceti AB <daniel@omicron.se>.
> + * Daniel Engstr???m, Omicron Ceti AB <daniel@omicron.se>.

Please do not mess umlauts.

>   * See file CREDITS for list of people who contributed to this
>   * project.
> @@ -134,7 +134,8 @@ typedef struct sc520_mmcr {
>  	u16 gptmr0cnt;		/* GP timer 0 count */
>  	u16 gptmr0maxcmpa;	/* GP timer 0 maxcount compare A */
>  	u16 gptmr0maxcmpb;	/* GP timer 0 maxcount compare B */
> -	u16 gptmr1ctl;		/* GP timer 1 mode/control */
> +	u16 gptmr1ctl;		/*#define SC520_SWTMRMILLI	0x
> +	 GP timer 1 mode/control */

Your patch is line wrapped or otherwise corrupted.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
One friend in a lifetime is much; two  are  many;  three  are  hardly
possible. Friendship needs a certain parallelism of life, a community
of thought, a rivalry of aim.                     - Henry Brook Adams

[U-Boot] [PATCH v2 15/17] Move eNET low-level initialisation into asm

[Graeme Russ]

Allows earlier indication of boot progress by initialising the LEDs and
Serial Port while the CPU is still in 16-bit (Real) mode

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
Version 2
 - Fixed comments corrupted by accidental middle-mouse button press while
   scrolling through code with mouse wheel
 - Fixed mangled umlaut
 - Fixed space before tab highlighted by Wolfgang Denk
 - Restored removed setting of gd->cpu_clk

 board/eNET/eNET.c           |   23 --------
 board/eNET/eNET_start.S     |    7 ++-
 board/eNET/eNET_start16.S   |  130 ++++++++++++++++++++++++++++++++++++++++++-
 board/eNET/hardware.h       |   16 +++++
 include/asm-i386/ic/sc520.h |   12 ++++
 5 files changed, 162 insertions(+), 26 deletions(-)

diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 29cf295..26a9e9d 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -46,15 +46,8 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
 void init_sc520_enet (void)
 {
 	/* Set CPU Speed to 100MHz */
-	sc520_mmcr->cpuctl = 0x01;
 	gd->cpu_clk = 100000000;
 
-	/* wait at least one millisecond */
-	asm("movl	$0x2000,%%ecx\n"
-	    "0:	pushl %%ecx\n"
-	    "popl	%%ecx\n"
-	    "loop 0b\n": : : "ecx");
-
 	/* turn on the SDRAM write buffer */
 	sc520_mmcr->dbctl = 0x11;
 
@@ -79,14 +72,6 @@ int board_init(void)
 	sc520_mmcr->gpwrw = 0x05;		/* GP Write pulse width */
 	sc520_mmcr->gpwroff = 0x01;		/* GP Write offset */
 
-	sc520_mmcr->piodata15_0 = 0x0630;	/* PIO15_PIO0 Data */
-	sc520_mmcr->piodata31_16 = 0x2000;	/* PIO31_PIO16 Data */
-	sc520_mmcr->piodir31_16 = 0x2000;	/* GPIO Direction */
-	sc520_mmcr->piodir15_0 = 0x87b5;	/* GPIO Direction */
-	sc520_mmcr->piopfs31_16 = 0x0dfe;	/* GPIO pin function 31-16 reg */
-	sc520_mmcr->piopfs15_0 = 0x200a;	/* GPIO pin function 15-0 reg */
-	sc520_mmcr->cspfs = 0x00f8;		/* Chip Select Pin Function Select */
-
 	sc520_mmcr->par[2] = 0x200713f8;	/* Uart A (GPCS0, 0x013f8, 8 Bytes) */
 	sc520_mmcr->par[3] = 0x2c0712f8;	/* Uart B (GPCS3, 0x012f8, 8 Bytes) */
 	sc520_mmcr->par[4] = 0x300711f8;	/* Uart C (GPCS4, 0x011f8, 8 Bytes) */
@@ -102,18 +87,10 @@ int board_init(void)
 /*	sc520_mmcr->par14 = 0x8bfff800; */	/* BOOTCS at  0x18000000 */
 /*	sc520_mmcr->par15 = 0x38201000; */	/* LEDs etc (GPCS6, 0x1000, 20 Bytes */
 
-	/* Disable Watchdog */
-	sc520_mmcr->wdtmrctl = 0x3333;
-	sc520_mmcr->wdtmrctl = 0xcccc;
-	sc520_mmcr->wdtmrctl = 0x0000;
-
 	/* Chip Select Configuration */
-	sc520_mmcr->bootcsctl = 0x0033;
 	sc520_mmcr->romcs1ctl = 0x0615;
 	sc520_mmcr->romcs2ctl = 0x0615;
 
-	sc520_mmcr->adddecctl = 0x02;
-	sc520_mmcr->uart1ctl = 0x07;
 	sc520_mmcr->sysarbctl = 0x06;
 	sc520_mmcr->sysarbmenb = 0x0003;
 
diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S
index 1b07d62..9052935 100644
--- a/board/eNET/eNET_start.S
+++ b/board/eNET/eNET_start.S
@@ -21,12 +21,17 @@
  * MA 02111-1307 USA
  */
 
+#include <asm/ic/sc520.h>
 #include "hardware.h"
 
 /* board early intialization */
 .globl early_board_init
 early_board_init:
-	/* No 32-bit board specific initialisation */
+	/* Light up the LEDs */
+	movw	$LED_LATCH_ADDRESS, %dx
+	movb	$LED_1_BITMASK | LED_2_BITMASK, %al
+	outb	%al, %dx
+
 	jmp	*%ebp		/* return to caller */
 
 .globl show_boot_progress_asm
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
index 48e4d83..31b33ec 100644
--- a/board/eNET/eNET_start16.S
+++ b/board/eNET/eNET_start16.S
@@ -27,8 +27,7 @@
  * that is used by U-boot to its final destination.
  */
 
-/* #include <asm/ic/sc520_defs.h> */
-
+#include <asm/ic/sc520.h>
 #include "hardware.h"
 
 .text
@@ -45,6 +44,65 @@ board_init16:
 	movw	$0xdf00, %ax
 	movw	%ax, %ds
 
+	/* Disable Watchdog */
+	movl    $SC520_WDTMRCTL, %edi
+	movw	$0x3333, %ax
+	movw	%ax, (%di)
+	movw	$0xcccc, %ax
+	movw	%ax, (%di)
+	movw	$0x3333, %ax
+	movw	%ax, (%di)
+
+	/* Set CPU to 100MHz Speed */
+	movb	$0x01, %al
+	movl    $SC520_CPUCTL, %edi
+	movb	%al, (%di)
+
+	/* wait at least one millisecond */
+	movl	$0x1000,%ecx
+cpuspddelay:
+	loop 	cpuspddelay
+
+	/* PIO15_PIO0 Data */
+	movl    $SC520_PIODATA15_0, %edi
+	movw	$0x0630, %ax
+	movw	%ax, (%di)
+
+	/* PIO31_PIO16 Data */
+	movl    $SC520_PIODATA31_16, %edi
+	movw	$0x2000, %ax
+	movw	%ax, (%di)
+
+	/* PIO Direction */
+	movl    $SC520_PIODIR31_16, %edi
+	movw	$0x2000, %ax
+	movw	%ax, (%di)
+
+	/* PIO Direction */
+	movl    $SC520_PIODIR15_0, %edi
+	movw	$0x87b5, %ax
+	movw	%ax, (%di)
+
+	/* PIO pin function 31-16 reg */
+	movl    $SC520_PIOPFS31_16, %edi
+	movw	$0x0dfe, %ax
+	movw	%ax, (%di)
+
+	/* PIO pin function 15-0 reg */
+	movl    $SC520_PIOPFS15_0, %edi
+	movw	$0x200a, %ax
+	movw	%ax, (%di)
+
+	/* Chip Select Pin Function Select */
+	movl    $SC520_CSPFS, %edi
+	movw	$0x00f8, %ax
+	movw	%ax, (%di)
+
+	/* Setup Chip Select for Boot Flash */
+	movl    $SC520_BOOTCSCTL, %edi
+	movw	$0x0033, %ax
+	movl	%eax, (%di)
+
 	/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
 	movl    $0x00c0, %edi		/* SC520_PAR14 */
 	movl	$0x8bfff800, %eax	/* TODO: Check this */
@@ -60,6 +118,74 @@ board_init16:
 	xorw    %ax, %ax
 	movb    %al, (%di)
 
+	/* Enable UART 1 */
+	movl    $SC520_ADDDECCTL, %edi
+	movb	$0x02, %al
+	movb	%al, (%di)
+
+	/* Configure UART 1 - 9600 Baud 8N1 */
+	movl    $SC520_UART1CTL, %edi
+	movb	$0x07, %al
+	movb	%al, (%di)
+
+	/* Set DLAB bit */
+	movw	$(UART0_BASE + UART_LCR), %dx
+	movb	$0x80, %al
+	outb	%al, %dx
+
+	/* Set baudrate divisor (LSB) */
+	movw	$(UART0_BASE + UART_DLL), %dx
+	movb	$0x0c, %al
+	outb	%al, %dx
+
+	/* Set baudrate divisor (MSB) */
+	movw	$(UART0_BASE + UART_DLM), %dx
+	movb	$0x00, %al
+	outb	%al, %dx
+
+	/* clear DLAB; set 8 bits, no parity */
+	movw	$(UART0_BASE + UART_LCR), %dx
+	movb	$0x03, %al
+	outb	%al, %dx
+
+	/* enable FIFO */
+	movw	$(UART0_BASE + UART_FCR), %dx
+	movb	$0x01, %al
+	outb	%al, %dx
+
+	/* Set DTR and RTS active */
+	movw	$(UART0_BASE + UART_MCR), %dx
+	movb	$0x0b, %al
+	outb	%al, %dx
+
+	/* clear line status */
+	movw	$(UART0_BASE + UART_LSR), %dx
+	inb	%dx, %al
+
+	/* read receive buffer */
+	movw	$(UART0_BASE + UART_RBR), %dx
+	inb	%dx, %al
+
+	/* set scratchpad */
+	movw	$(UART0_BASE + UART_SCR), %dx
+	movb	$0x00, %al
+	outb	%al, %dx
+
+	/* Disable Interrupts */
+	movw	$(UART0_BASE + UART_IER), %dx
+	movb	$0x00, %al
+	outb	%al, %dx
+
+	/* wait for the UART clock to settle */
+	movl	$0x10000,%ecx
+uartdelay:
+	loop 	uartdelay
+
+	/* Light up the LEDs */
+	movw	$LED_LATCH_ADDRESS, %dx
+	movb	$LED_1_BITMASK, %al
+	outb	%al, %dx
+
 	/* Disabe MMCR alias */
 	movw	$0xfffc, %dx
 	movl	$0x000000cb, %eax
diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h
index 42474a6..cabf8e4 100644
--- a/board/eNET/hardware.h
+++ b/board/eNET/hardware.h
@@ -32,4 +32,20 @@
 #define LED_TX_BITMASK		0x10
 #define LED_ERR_BITMASK		0x20
 
+/* Serial Port Definitions */
+#define UART0_BASE		0x3f8
+
+#define UART_RBR		0x00
+#define UART_THR		0x00
+#define UART_IER		0x01
+#define UART_IIR		0x02
+#define UART_FCR		0x02
+#define UART_LCR		0x03
+#define UART_MCR		0x04
+#define UART_LSR		0x05
+#define UART_MSR		0x06
+#define UART_SCR		0x07
+#define UART_DLL		0x00
+#define UART_DLM		0x01
+
 #endif /* HARDWARE_H_ */
diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h
index 57c9904..56f0fd8 100644
--- a/include/asm-i386/ic/sc520.h
+++ b/include/asm-i386/ic/sc520.h
@@ -256,11 +256,23 @@ extern volatile sc520_mmcr_t *sc520_mmcr;
 #endif
 
 /* MMCR Offsets (required for assembler code */
+#define SC520_CPUCTL		0x0001	/* CPU Control */
 #define SC520_DBCTL		0x0040	/* SDRAM Buffer Control Register */
+#define SC520_BOOTCSCTL		0x0050	/* BOOT Flaash Chip Select Control */
+#define SC520_ADDDECCTL		0x0080	/* Address Decode Control */
 #define SC520_PAR14		0x00c0	/* Programmable Address Region 14 Register */
 #define SC520_PAR15		0x00c4	/* Programmable Address Region 15 Register */
+#define SC520_PIOPFS15_0	0x0c20	/* GPIO pin function 15-0 reg */
+#define SC520_PIOPFS31_16	0x0c22	/* GPIO pin function 31-16 reg */
+#define SC520_CSPFS		0x0c24	/* Chip Select Pin Function Select */
+#define SC520_PIODIR15_0	0x0c2a	/* GPIO Direction */
+#define SC520_PIODIR31_16	0x0c2c	/* GPIO Direction */
+#define SC520_PIODATA15_0	0x0c30	/* PIO15_PIO0 Data */
+#define SC520_PIODATA31_16	0x0c32	/* PIO31_PIO16 Data */
 #define SC520_SWTMRMILLI	0x0c60  /* Software Timer Millisecond Count */
 #define SC520_SWTMRMICRO	0x0c62  /* Software Timer Microsecond Count */
+#define SC520_WDTMRCTL		0x0cb0	/* Watchdog Timer Control */
+#define SC520_UART1CTL		0x0cc0	/* UART 1 Control */
 
 /* MMCR Register bits (not all of them :) ) */
 
-- 
1.6.4.1.174.g32f4c

[U-Boot] [PATCH v2 15/17] Move eNET low-level initialisation into asm

[Wolfgang Denk]

Dear Graeme Russ,

In message <1251111477-15561-1-git-send-email-graeme.russ@gmail.com> you wrote:
> Allows earlier indication of boot progress by initialising the LEDs and
> Serial Port while the CPU is still in 16-bit (Real) mode

I have to admit that I am not a friend of moving C code to assembler.
This contradicts pretty basic principles of U-Boot design.

I can understand that you want diagnosis as early as possible, but 162
insertions versus 26 deletions is a clear indocation that something is
awfully wrong.


Are you absolutely sure this is a good idea?


> Version 2
>  - Fixed comments corrupted by accidental middle-mouse button press while
>    scrolling through code with mouse wheel
>  - Fixed mangled umlaut
>  - Fixed space before tab highlighted by Wolfgang Denk

You did not catch all of these, see below.

> diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
> index 48e4d83..31b33ec 100644
> --- a/board/eNET/eNET_start16.S
> +++ b/board/eNET/eNET_start16.S
...
> @@ -45,6 +44,65 @@ board_init16:
>  	movw	$0xdf00, %ax
>  	movw	%ax, %ds
>  
> +	/* Disable Watchdog */
> +	movl    $SC520_WDTMRCTL, %edi
> +	movw	$0x3333, %ax
> +	movw	%ax, (%di)
> +	movw	$0xcccc, %ax
> +	movw	%ax, (%di)
> +	movw	$0x3333, %ax
> +	movw	%ax, (%di)
> +
> +	/* Set CPU to 100MHz Speed */
> +	movb	$0x01, %al
> +	movl    $SC520_CPUCTL, %edi
> +	movb	%al, (%di)
> +
> +	/* wait at least one millisecond */
> +	movl	$0x1000,%ecx
> +cpuspddelay:
> +	loop 	cpuspddelay

SPACE + TAB ...

...
> +	/* wait for the UART clock to settle */
> +	movl	$0x10000,%ecx
> +uartdelay:
> +	loop 	uartdelay

SPACE + TAB ...


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The so-called "desktop metaphor" of today's workstations  is  instead
an  "airplane-seat"  metaphor.  Anyone who has shuffled a lap full of
papers while seated between two portly passengers will recognize  the
difference -- one can see only a very few things at once.
                                                   - Fred Brooks, Jr.

[U-Boot] [PATCH v2 15/17] Move eNET low-level initialisation into asm

[Graeme Russ]

Wolfgang Denk wrote:
> Dear Graeme Russ,
> 
> In message <1251111477-15561-1-git-send-email-graeme.russ@gmail.com> you wrote:
>> Allows earlier indication of boot progress by initialising the LEDs and
>> Serial Port while the CPU is still in 16-bit (Real) mode
> 
> I have to admit that I am not a friend of moving C code to assembler.
> This contradicts pretty basic principles of U-Boot design.
> 

Normally I would agree

> I can understand that you want diagnosis as early as possible, but 162
> insertions versus 26 deletions is a clear indocation that something is
> awfully wrong.

When it came to relocating the code into RAM, I had an awful time trying
to figure out where it was failing. The LEDs turned out to be not so
useful because the board was resetting, so the LEDs just kept going
through a crazy sequence so I needed serial output.

The other nice thing is it gives serial output to low level init
functions in the C code before init_serial()

> Are you absolutely sure this is a good idea?

Hmm, maybe now that it's working I may not need it. I just stg pop'd
it and the following patches applied cleanly (although it did need to
auto modify patch 16) and the board still works so I guess I can ditch
it - Shortens patch series by one - How would you like the resend (maybe
same length series with Patch 15 being blank?)

>>  - Fixed space before tab highlighted by Wolfgang Denk
> 
> You did not catch all of these, see below.
 
Arghh, only looked at sc520.h - I just did a global search for space
followed by tab - 1000+ hits, but i386 and eNET are clean :)

> Best regards,
> 
> Wolfgang Denk

Regards,

G

[U-Boot] [PATCH v2 15/17] Move eNET low-level initialisation into asm

[Wolfgang Denk]

Dear Graeme Russ,

In message <4A927E3B.8040903@gmail.com> you wrote:
>
> > Are you absolutely sure this is a good idea?
> 
> Hmm, maybe now that it's working I may not need it. I just stg pop'd
> it and the following patches applied cleanly (although it did need to
> auto modify patch 16) and the board still works so I guess I can ditch
> it - Shortens patch series by one - How would you like the resend (maybe
> same length series with Patch 15 being blank?)

I don;t use that code, and don;t even know which debug options you
have on x86. So it's your decision in the end.

> Arghh, only looked at sc520.h - I just did a global search for space
> followed by tab - 1000+ hits, but i386 and eNET are clean :)

So you have 1000+ fixes to do? Thanks in advance.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The Gates in my computer are AND, OR and NOT; they are not Bill.

[U-Boot] [PATCH v2 15/17] Move eNET low-level initialisation into asm

[Graeme Russ]

Wolfgang Denk wrote:
> Dear Graeme Russ,
> 
> In message <4A927E3B.8040903@gmail.com> you wrote:
>>> Are you absolutely sure this is a good idea?
>> Hmm, maybe now that it's working I may not need it. I just stg pop'd
>> it and the following patches applied cleanly (although it did need to
>> auto modify patch 16) and the board still works so I guess I can ditch
>> it - Shortens patch series by one - How would you like the resend (maybe
>> same length series with Patch 15 being blank?)
> 
> I don;t use that code, and don;t even know which debug options you
> have on x86. So it's your decision in the end.

OK, I will ditch - I'll resend a blank 15 and new 16 & 17 tomorrow - It's
getting late

> 
>> Arghh, only looked at sc520.h - I just did a global search for space
>> followed by tab - 1000+ hits, but i386 and eNET are clean :)
> 
> So you have 1000+ fixes to do? Thanks in advance.

LOL - Maybe I'll take that challenge one day

> 
> Best regards,
> 
> Wolfgang Denk
> 

[U-Boot] [PATCH 00/17] i386 Updates (touches some common drivers)

[Scott Wood]

On Sun, Aug 23, 2009 at 07:36:55AM +0200, Wolfgang Denk wrote:
> Dear Mike Frysinger,
> 
> In message <200908230001.46558.vapier@gentoo.org> you wrote:
> >
> > please set sendemail.chainreplyto to false in your git settings.  patch series 
> 
> Why that?
> 
> > should be like:
> > [summary 0/xx]
> > |- [patch 1/xx]
> > |- [patch 2/xx]
> > ....
> >
> > not:
> > [summary 0/xx]
> > `- [patch 1/xx]
> >   `- [patch 2/xx]
> >     `- ....
> 
> On contrary. The second form is much more useful as it also indicates
> the order in which patches should be applied - too often people forget
> the -n.
> 
> > the latter makes things a lot more painful for people to parse with their e-
> > mail clients.
> 
> Huh? To me that makes no difference. Actually, I like the second form
> better.

I much prefer the first form.  Besides being more like just about every
other vertical list in the world, the second form tends to push the
meaningful bit of the subject line off the right edge of the screen.  The
[U-Boot] tag doesn't help in that respect either...

-Scott

[U-Boot] [PATCH v3 15/17] Move low level eNET board init into dedicated sections (Abandoned)

[Graeme Russ]

This patch has been abandoned - It's place in the patch series has been kept
so as not to disrupt the versioning of later patches

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---

[U-Boot] [PATCH v2 16/17] Move low level eNET board init into dedicated sections

[Graeme Russ]

This patch is in readiness for moving all u-boot code + data from Flash to
RAM. Low level init code is not needed after bootstrap and therefore does
not need to be copied. Moving this code into dedicated sections makes it
easier

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
Version 2
 - Modified slightly to account for dropping of patch 15 (no functional
   changes)

 board/eNET/eNET_start.S             |    3 +++
 board/eNET/u-boot.lds               |    4 ++--
 board/sc520_cdp/sc520_cdp_asm.S     |    1 +
 board/sc520_cdp/u-boot.lds          |    4 ++--
 board/sc520_spunk/sc520_spunk_asm.S |    1 +
 board/sc520_spunk/u-boot.lds        |    4 ++--
 cpu/i386/sc520/sc520_asm.S          |    2 +-
 cpu/i386/start.S                    |    2 +-
 8 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S
index 1b07d62..1309ac7 100644
--- a/board/eNET/eNET_start.S
+++ b/board/eNET/eNET_start.S
@@ -23,6 +23,9 @@
 
 #include "hardware.h"
 
+.section .start32, "ax"
+
+
 /* board early intialization */
 .globl early_board_init
 early_board_init:
diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds
index 4ea424d..284d2bd 100644
--- a/board/eNET/u-boot.lds
+++ b/board/eNET/u-boot.lds
@@ -78,8 +78,8 @@ SECTIONS
 	 * The fff0 offset of resetvec is important, however.
 	 */
 
-	. = 0xfffffe00;
-	.start32 : AT (0x3807fe00) { *(.start32); }
+	. = 0xffffee00;
+	.start32 : AT (0x3807ee00) { *(.start32); }
 
 	. = 0xf800;
 	.start16 : AT (0x3807f800) { *(.start16); }
diff --git a/board/sc520_cdp/sc520_cdp_asm.S b/board/sc520_cdp/sc520_cdp_asm.S
index 3a8a03f..904cfb9 100644
--- a/board/sc520_cdp/sc520_cdp_asm.S
+++ b/board/sc520_cdp/sc520_cdp_asm.S
@@ -25,6 +25,7 @@
  * We can then use the leds to display status information.
  */
 
+.section .start32, "ax"
 sc520_cdp_registers:
 /* size    offset        value */
 .word 1 ; .word 0x040 ; .long 0x00       /* SDRAM buffer control */
diff --git a/board/sc520_cdp/u-boot.lds b/board/sc520_cdp/u-boot.lds
index df437c7..d232dc1 100644
--- a/board/sc520_cdp/u-boot.lds
+++ b/board/sc520_cdp/u-boot.lds
@@ -79,8 +79,8 @@ SECTIONS
 	 */
 
 
-	. = 0xfffffe00;
-	.start32 : AT (0x387ffe00) { *(.start32); }
+	. = 0xffffee00;
+	.start32 : AT (0x3807ee00) { *(.start32); }
 
 	. = 0xff00;
 	.start16 : AT (0x387fff00) { *(.start16); }
diff --git a/board/sc520_spunk/sc520_spunk_asm.S b/board/sc520_spunk/sc520_spunk_asm.S
index eda7e91..020bd02 100644
--- a/board/sc520_spunk/sc520_spunk_asm.S
+++ b/board/sc520_spunk/sc520_spunk_asm.S
@@ -25,6 +25,7 @@
  * We can then use the leds to display status information.
  */
 
+.section .start32, "ax"
 sc520_cdp_registers:
 /* size    offset        value */
 .word 1 ; .word 0x040 ; .long 0x00       /* SDRAM buffer control */
diff --git a/board/sc520_spunk/u-boot.lds b/board/sc520_spunk/u-boot.lds
index efb570b..f6d1abf 100644
--- a/board/sc520_spunk/u-boot.lds
+++ b/board/sc520_spunk/u-boot.lds
@@ -80,8 +80,8 @@ SECTIONS
 	 */
 
 
-	. = 0xfffffe00;
-	.start32 : AT (0x387ffe00) { *(.start32); }
+	. = 0xffffee00;
+	.start32 : AT (0x3807ee00) { *(.start32); }
 
 	. = 0xff00;
 	.start16 : AT (0x387fff00) { *(.start16); }
diff --git a/cpu/i386/sc520/sc520_asm.S b/cpu/i386/sc520/sc520_asm.S
index 2042d9b..07e2acd 100644
--- a/cpu/i386/sc520/sc520_asm.S
+++ b/cpu/i386/sc520/sc520_asm.S
@@ -106,7 +106,7 @@
 
 #include <config.h>
 
-.section .text
+.section .start32, "ax"
 .equ            DRCCTL,     0x0fffef010   /* DRAM control register */
 .equ            DRCTMCTL,   0x0fffef012   /* DRAM timing control register */
 .equ            DRCCFG,     0x0fffef014   /* DRAM bank configuration register */
diff --git a/cpu/i386/start.S b/cpu/i386/start.S
index 59089ef..bb4a5cf 100644
--- a/cpu/i386/start.S
+++ b/cpu/i386/start.S
@@ -27,7 +27,7 @@
 #include <version.h>
 
 
-.section .text
+.section .start32, "ax"
 .code32
 .globl _start
 .type _start, @function
-- 
1.6.4.1.174.g32f4c

[U-Boot] [PATCH v2 16/17] Move low level eNET board init into dedicated sections

[Wolfgang Denk]

Dear Graeme Russ,

In message <1251195588-7799-1-git-send-email-graeme.russ@gmail.com> you wrote:
> This patch is in readiness for moving all u-boot code + data from Flash to
> RAM. Low level init code is not needed after bootstrap and therefore does
> not need to be copied. Moving this code into dedicated sections makes it
> easier

But is this worth the effort? It makes the design more complicated.


Best regards,

Wolfgang Denk

--
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
In a business, marketroids, salespukes, and  lawyers  have  different
goals from those who actually do work and produce something. Usually,
is  is the former who triumph over the latter, due to the simple rule
that those who print the money make the rules.
         -- Tom Christiansen in <5jdcls$b04$2@csnews.cs.colorado.edu>

[U-Boot] [PATCH v2 16/17] Move low level eNET board init into dedicated sections

[Graeme Russ]

Wolfgang Denk wrote:
> Dear Graeme Russ,
> 
> In message <1251195588-7799-1-git-send-email-graeme.russ@gmail.com> you wrote:
>> This patch is in readiness for moving all u-boot code + data from Flash to
>> RAM. Low level init code is not needed after bootstrap and therefore does
>> not need to be copied. Moving this code into dedicated sections makes it
>> easier
> 
> But is this worth the effort? It makes the design more complicated.
> 

Actually I think the opposite is true - The low level asm code is all
placed at the bottom (or is it top?) end of the Boot Flash rather than
interleaved in the rest of the .text section. This is critical for the
real mode code as there is a tight limit on the jump lengths. This patch
makes it all the more consistent

> 
> Best regards,
> 
> Wolfgang Denk
> 

Regards,

G

[U-Boot] [PATCH 01/17] Add errno.h to i386

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-2-git-send-email-graeme.russ@gmail.com> you wrote:
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  include/asm-i386/errno.h |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
>  create mode 100644 include/asm-i386/errno.h

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Peace was the way.
	-- Kirk, "The City on the Edge of Forever", stardate unknown

[U-Boot] [PATCH 02/17] Change inline asm global symbols to local

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-3-git-send-email-graeme.russ@gmail.com> you wrote:
> gcc 4.3.2 optimiser creates multiple copies of inline asm (who knows why)
> Remove use of global names for labels to prevent 'symbol already defined'
> errors
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  board/eNET/eNET.c      |    4 ++--
>  cpu/i386/sc520/sc520.c |    4 ++--
>  2 files changed, 4 insertions(+), 4 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Philosophy is a game with objectives and no rules.
Mathematics is a game with rules and no objectives.

[U-Boot] [PATCH 03/17] Fix regression introduced by commit 8c63d47651f7

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-4-git-send-email-graeme.russ@gmail.com> you wrote:
> A local variable was deleted that should not have been
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  lib_i386/pcat_timer.c |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
C++ was an interesting and valuable experiment, but we've learned its
lessons and it's time to move on.
                            - Peter Curran in <DCqM4z.BxB@isgtec.com>

[U-Boot] [PATCH 04/17] Fix environment configuration for eNET board

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-5-git-send-email-graeme.russ@gmail.com> you wrote:
> The current configuration of the Environment has the redundant copy of the
> environment in the Boot Flash - This was never the intent. The Environment
> should instead be in the first two sectors of the first Strata Flash
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  include/configs/eNET.h |   11 +++++------
>  1 files changed, 5 insertions(+), 6 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The easiest way to figure the cost of living is to take  your  income
and add ten percent.

[U-Boot] [PATCH 05/17] Fix sc520 timer interrupt generation

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-6-git-send-email-graeme.russ@gmail.com> you wrote:
> The current implementation has the timer being started before the interrupt
> handler is installed. It the interrupt occurs before the handler is
> installed, the timer interrupt is never reset and the timer stops
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  cpu/i386/sc520/sc520_timer.c |    6 +++---
>  1 files changed, 3 insertions(+), 3 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There's no honorable way to kill, no gentle way to destroy.  There is
nothing good in war.  Except its ending.
	-- Abraham Lincoln, "The Savage Curtain", stardate 5906.5

[U-Boot] [PATCH 06/17] Misc i386 PCI fixups

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-7-git-send-email-graeme.russ@gmail.com> you wrote:
> Change PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY (Originally done in
> commit ff4e66e93c1a, regressed by commit 6d7f610b09f8)
> 
> Cast PCI_ROM_ADDRESS_MASK to u32
> 
> Wrap probe_pci_video() call inside #ifdef CONFIG_VIDEO
> 
> Change call to pci_find_class() to pci_find_devices(). This is based on a
> patch submitted on 1st March 2007 (Patch that fixes the compilation errors
> for sc520_cdp board) by mushtaq_k
> 
> This patch requires that PCI_VIDEO_VENDOR_ID and PCI_VIDEO_DEVICE_ID be
> specified in the board config file.  Dummy values have been added for the
> SC520 CDP board to enable compilation, but since I do not have one of these,
> I do know what the values should be
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  board/sc520_cdp/sc520_cdp.c |    1 +
>  cpu/i386/sc520/sc520_pci.c  |    2 +-
>  include/configs/sc520_cdp.h |    2 ++
>  lib_i386/pci.c              |    2 +-
>  lib_i386/video_bios.c       |   18 +++++++++---------
>  5 files changed, 14 insertions(+), 11 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I was playing poker the other night... with Tarot cards. I got a full
house and 4 people died.                              - Steven Wright

[U-Boot] [PATCH 07/17] Misc SATA fixups

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-8-git-send-email-graeme.russ@gmail.com> you wrote:
> Cast first parameter to sata_cpy()
> 
> In /drivers/block/ata_piix.h, ata_id_has_lba48(), ata_id_has_lba(),
> ata_id_has_dma(), ata_id_u32(), ata_id_u64() are all defined in
> include/libata.h which is included in ata.h which is included by all files
> which include ata_piix.h (only ata_piix.c) so these definitions are
> supurflous to (and conlict with) this in libata.h. Interestingly, my
> compiler complains about ata_id_u64 already being defined, but not
> ata_id_u32
> 
> ata_dump_id() is defined in include/libata.h and should not be static
> (maybe should even use ata_dump_id() in libata.c
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  drivers/block/ata_piix.c |   10 +++++-----
>  drivers/block/ata_piix.h |   15 +--------------
>  2 files changed, 6 insertions(+), 19 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
My play was a complete success.  The audience was a failure.

[U-Boot] [PATCH 08/17] Misc ti_pci1410a fixups

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-9-git-send-email-graeme.russ@gmail.com> you wrote:
> Removed do_pinit() - now declared in cmd_pcmcia.c
> 
> Added #define CONFIG_CMD_PCMCIA around pcmcia_off() in line with other
> PCMCIA drivers
> 
> signed/unsigned type fixups
> 
> Added semi-colon after default: label as required by newer gcc
> 
> The only board that appears to use this driver is the sc520_spunk which
> is very old and very likely very broken anyway. I do not have one to test
> whether this patch breaks anything functionaly, I have can only check
> that it compiles without warning or error
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  drivers/pcmcia/ti_pci1410a.c |   62 ++++++++++++-----------------------------
>  1 files changed, 18 insertions(+), 44 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Don't hit a man when he's down - kick him; it's easier.

[U-Boot] [PATCH 09/17] Misc ds1722 fixups

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-10-git-send-email-graeme.russ@gmail.com> you wrote:
> This patch is based on a patch submitted by Jean-Christophe PLAGNIOL-VILLARD
> on 18th May 2008 as part of a general i386 / sc520 fixup which was never
> applied
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  drivers/hwmon/ds1722.c |    3 ++-
>  include/ds1722.h       |   32 ++++++++++++++++++++++++++++++++
>  2 files changed, 34 insertions(+), 1 deletions(-)
>  create mode 100644 include/ds1722.h

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
On the subject of C program indentation: "In My Egotistical  Opinion,
most  people's  C  programs  should be indented six feet downward and
covered with dirt."                               - Blair P. Houghton

[U-Boot] [PATCH 10/17] Fixup sc520_spunk board

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-11-git-send-email-graeme.russ@gmail.com> you wrote:
> Primary intent is to resolve build errors for this board which has been
> neglected for a very long time. I do not have one of these boards, so I
> cannot test functionality
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  board/sc520_spunk/sc520_spunk.c |   33 +++++++++++++++++++++++++++++++--
>  include/configs/sc520_spunk.h   |    2 ++
>  2 files changed, 33 insertions(+), 2 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I thought my people would grow tired of killing. But you were  right,
they  see it is easier than trading. And it has its pleasures. I feel
it myself. Like the hunt, but with richer rewards.
	-- Apella, "A Private Little War", stardate 4211.8

[U-Boot] [PATCH 11/17] Misc sc520 cdp fixups

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-12-git-send-email-graeme.russ@gmail.com> you wrote:
> Now that the PCI, SATA et al compile problems have been resolved, the
> cludge that was applied to avoid them can be removed
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  include/configs/sc520_cdp.h |   22 ----------------------
>  1 files changed, 0 insertions(+), 22 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There is nothing in this world constant but inconstancy.      - Swift

[U-Boot] [PATCH 12/17] Replace [read, write]_mmcr_[byte, word, long] with memory mapped structure

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-13-git-send-email-graeme.russ@gmail.com> you wrote:
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  board/eNET/eNET.c               |   86 ++++----
>  board/sc520_cdp/flash.c         |   14 +-
>  board/sc520_cdp/sc520_cdp.c     |  171 ++++++++--------
>  board/sc520_spunk/sc520_spunk.c |  211 ++++++++++----------
>  cpu/i386/sc520/sc520.c          |   71 ++------
>  cpu/i386/sc520/sc520_pci.c      |   66 +++---
>  cpu/i386/sc520/sc520_ssi.c      |   28 ++--
>  cpu/i386/sc520/sc520_timer.c    |   31 ++--
>  include/asm-i386/ic/sc520.h     |  417 ++++++++++++++++++++++-----------------
>  9 files changed, 550 insertions(+), 545 deletions(-)

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Nobody trips over mountains. It is the small pebble that  causes  you
to  stumble.  Pass all the pebbles in your path and you will find you
have crossed the mountain.

[U-Boot] [PATCH 13/17] Moved PCI from #ifdef to conditional compile for sc520 boards

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-14-git-send-email-graeme.russ@gmail.com> you wrote:
> --===============2050527354==
> 
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  board/eNET/Makefile                 |   10 +-
>  board/sc520_cdp/Makefile            |   14 +-
>  board/sc520_cdp/sc520_cdp.c         |  239 --------------------------
>  board/sc520_cdp/sc520_cdp_pci.c     |  271 +++++++++++++++++++++++++++++
>  board/sc520_spunk/Makefile          |   14 +-
>  board/sc520_spunk/sc520_spunk.c     |  298 --------------------------------
>  board/sc520_spunk/sc520_spunk_pci.c |  323 +++++++++++++++++++++++++++++++++++
>  lib_i386/Makefile                   |    4 +-
>  lib_i386/pci.c                      |    3 -
>  lib_i386/pci_type1.c                |    5 -
>  10 files changed, 617 insertions(+), 564 deletions(-)
>  create mode 100644 board/sc520_cdp/sc520_cdp_pci.c
>  create mode 100644 board/sc520_spunk/sc520_spunk_pci.c

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Certainly there are things in life that money  can't  buy,  but  it's
very funny - Did you ever try buying them without money? - Ogden Nash

[U-Boot] [PATCH 14/17] Add PCI support to eNET board

[Wolfgang Denk]

Dear Graeme Russ,

In message <1250996401-13642-15-git-send-email-graeme.russ@gmail.com> you wrote:
> --===============0053267559==
> 
> 
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
>  board/eNET/Makefile    |    1 +
>  board/eNET/eNET_pci.c  |   95 ++++++++++++++++++++++++++++++++++++++++++++++++
>  include/configs/eNET.h |   14 ++++----
>  3 files changed, 103 insertions(+), 7 deletions(-)
>  create mode 100644 board/eNET/eNET_pci.c

Applied, thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"IBM uses what I like to call the 'hole-in-the-ground  technique'  to
destroy  the  competition.....  IBM digs a big HOLE in the ground and
covers it with leaves. It then puts a big POT OF GOLD nearby. Then it
gives the call, 'Hey, look at all this gold, get over here fast.'  As
soon  as  the competitor approaches the pot, he falls into the pit"
                                                     - John C. Dvorak