From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerry Van Baren Date: Thu, 27 Aug 2009 07:41:46 -0400 Subject: [U-Boot] [PATCH v3] mpc83xx: update LCRR register handling In-Reply-To: <4A9625B3.7040509@denx.de> References: <4A93A975.40009@denx.de> <4A93CB96.8000701@denx.de> <20090825103925.dc7ec42c.kim.phillips@freescale.com> <4A94D615.1060504@denx.de> <20090826173628.ddb2bdd4.kim.phillips@freescale.com> <4A9625B3.7040509@denx.de> Message-ID: <4A9670FA.4030108@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Heiko, One minor critique, I had problems parsing the comment: Heiko Schocher wrote: > MPC8379E RM says (10-34): > Once LCRR[CLKDIV] is written, the register should be read, and then > an isync should be executed. > So update this in code. > Also define a LCRR mask for processors, which uses not all bits ^^^^^^^^^^^^^^^^^^^^^^^ Suggested change: Also define a LCRR mask for processors to prevent setting any reserved bits in the LCRR register (as, for example, mpc832x did). > in the LCRR register (as for example mpc832x did). > > Signed-off-by: Heiko Schocher Thanks, gvb