[U-Boot] [PATCH] arm_cortexa8: support cache flush to other soc

Kyungmin Park
2009-09-04T09:34:17Z

Hi,

As he goes to home, I reply it instead.

On Fri, Sep 4, 2009 at 5:43 PM, Dirk Behme<dirk.behme@googlemail.com> wrote:
> Dear Minkyu Kang,
>
> Minkyu Kang wrote:
>> Current code is supported only omap3 soc.
>> this patch will support s5pc1xx(s5pc100 and s5pc110) soc also.
>
> Thanks for this patch!
>
> How is this patch related to
>
> http://lists.denx.de/pipermail/u-boot/2009-August/058492.html
>

It's not good idea to move invalidate_cache to omap directory. we need it.

>
>> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
>> ---
>> ?cpu/arm_cortexa8/cpu.c | ? 24 +++++++++++-------------
>> ?1 files changed, 11 insertions(+), 13 deletions(-)
>>
>> diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
>> index 5a5981e..3d430b1 100644
>> --- a/cpu/arm_cortexa8/cpu.c
>> +++ b/cpu/arm_cortexa8/cpu.c
>> @@ -35,9 +35,6 @@
>> ?#include <command.h>
>> ?#include <asm/system.h>
>> ?#include <asm/cache.h>
>> -#ifndef CONFIG_L2_OFF
>> -#include <asm/arch/sys_proto.h>
>> -#endif
>>
>> ?static void cache_flush(void);
>>
>> @@ -61,17 +58,18 @@ int cleanup_before_linux(void)
>> ? ? ? cache_flush();
>>
>> ?#ifndef CONFIG_L2_OFF
>> - ? ? /* turn off L2 cache */
>> - ? ? l2_cache_disable();
>> - ? ? /* invalidate L2 cache also */
>> - ? ? v7_flush_dcache_all(get_device_type());
>> -#endif
>> - ? ? i = 0;
>> - ? ? /* mem barrier to sync up things */
>> - ? ? asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
>> + ? ? if (get_device_type() != 0xC100) {
>
> Hmm, what is this "0xC100" ?

Now we got two cpu, s5pc100 and s5pc110. In case of s5pc100 we don't
need to turn off l2 cache. but s5pc110 needs it.
So first check the device type, actually cpu type. then determine turn
off l2 cache or not.

>
>> + ? ? ? ? ? ? /* turn off L2 cache */
>> + ? ? ? ? ? ? l2_cache_disable();
>> + ? ? ? ? ? ? /* invalidate L2 cache also */
>> + ? ? ? ? ? ? v7_flush_dcache_all(get_device_type());
>>
>> -#ifndef CONFIG_L2_OFF
>> - ? ? l2_cache_enable();
>> + ? ? ? ? ? ? i = 0;
>> + ? ? ? ? ? ? /* mem barrier to sync up things */
>> + ? ? ? ? ? ? asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
>> +
>> + ? ? ? ? ? ? l2_cache_enable();
>> + ? ? }
>> ?#endif
>
> What's about the order of #ifndef CONFIG_L2_OFF?
>
> While we had before
>
>
> #ifndef CONFIG_L2_OFF
> ? ? ? ?/* turn off L2 cache */
> ? ? ? ?l2_cache_disable();
> ? ? ? ?/* invalidate L2 cache also */
> ? ? ? ?v7_flush_dcache_all(get_device_type());
> #endif
> ? ? ? ?i = 0;
> ? ? ? ?/* mem barrier to sync up things */
> ? ? ? ?asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
>
> #ifndef CONFIG_L2_OFF
> ? ? ? ?l2_cache_enable();
> #endif
>
>
> after this patch we would have
>
>
> #ifndef CONFIG_L2_OFF
> ? ? ? ?if (get_device_type() != 0xC100) {
> ? ? ? ? ? ? ? ?/* turn off L2 cache */
> ? ? ? ? ? ? ? ?l2_cache_disable();
> ? ? ? ? ? ? ? ?/* invalidate L2 cache also */
> ? ? ? ? ? ? ? ?v7_flush_dcache_all(get_device_type());
> ? ? ? ? ? ? ? ?i = 0;
> ? ? ? ? ? ? ? ?/* mem barrier to sync up things */
> ? ? ? ? ? ? ? ?asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
>
> ? ? ? ? ? ? ? ?l2_cache_enable();
> ? ? ? ?}
> #endif
>
> Is this intended?

maybe not. now we only tested the smdkc100 but actual use is internal
board for s5pc100 & s5pc110.
He will be modify it.

Thank you,
Kyungmin Park