* [U-Boot] [PATCH] ppc/85xx: Fix LCRR_CLKDIV defines
@ 2009-09-16 3:26 Kumar Gala
2009-09-16 3:32 ` Peter Tyser
0 siblings, 1 reply; 5+ messages in thread
From: Kumar Gala @ 2009-09-16 3:26 UTC (permalink / raw)
To: u-boot
For some reason the CLKDIV field varies between SoC in how it interprets
the bit values.
All 83xx and early (e500v1) PQ3 devices support:
clk/2: CLKDIV = 2
clk/4: CLKDIV = 4
clk/8: CLKDIV = 8
Newer PQ3 (e500v2) and MPC86xx support:
clk/4: CLKDIV = 2
clk/8: CLKDIV = 4
clk/16: CLKDIV = 8
Ensure that the MPC86xx and MPC85xx still get the same behavior and make
the the defines reflect their logical view (not the value of the field).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
include/asm-ppc/fsl_lbc.h | 8 ++++++++
include/configs/XPEDITE5170.h | 2 +-
include/configs/XPEDITE5200.h | 2 +-
include/configs/XPEDITE5370.h | 2 +-
4 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index a28082e..08d31e1 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -311,9 +311,17 @@
*/
#define LCRR_CLKDIV 0x0000001F
#define LCRR_CLKDIV_SHIFT 0
+#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \
+ defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \
+ defined(CONFIG_MPC8560)
#define LCRR_CLKDIV_2 0x00000002
#define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008
+#else
+#define LCRR_CLKDIV_4 0x00000002
+#define LCRR_CLKDIV_8 0x00000004
+#define LCRR_CLKDIV_16 0x00000008
+#endif
/* LTEDR - Transfer Error Check Disable Register
*/
diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index 242466a..30642cd 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -122,7 +122,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
*/
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
/*
* NAND flash configuration
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index deda208..d79231b 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -103,7 +103,7 @@
* 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
*/
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
/*
* NAND flash configuration
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 3c58ebe..65e1afd 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -116,7 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
*/
-#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
+#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
/*
* NAND flash configuration
--
1.6.0.6
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] ppc/85xx: Fix LCRR_CLKDIV defines
2009-09-16 3:26 [U-Boot] [PATCH] ppc/85xx: Fix LCRR_CLKDIV defines Kumar Gala
@ 2009-09-16 3:32 ` Peter Tyser
2009-09-16 4:11 ` Kumar Gala
2009-09-16 4:29 ` Chris Moore
0 siblings, 2 replies; 5+ messages in thread
From: Peter Tyser @ 2009-09-16 3:32 UTC (permalink / raw)
To: u-boot
On Tue, 2009-09-15 at 22:26 -0500, Kumar Gala wrote:
> For some reason the CLKDIV field varies between SoC in how it interprets
> the bit values.
>
> All 83xx and early (e500v1) PQ3 devices support:
> clk/2: CLKDIV = 2
> clk/4: CLKDIV = 4
> clk/8: CLKDIV = 8
>
> Newer PQ3 (e500v2) and MPC86xx support:
> clk/4: CLKDIV = 2
> clk/8: CLKDIV = 4
> clk/16: CLKDIV = 8
>
> Ensure that the MPC86xx and MPC85xx still get the same behavior and make
> the the defines reflect their logical view (not the value of the field).
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Thanks
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] ppc/85xx: Fix LCRR_CLKDIV defines
2009-09-16 3:32 ` Peter Tyser
@ 2009-09-16 4:11 ` Kumar Gala
2009-09-16 4:38 ` Peter Tyser
2009-09-16 4:29 ` Chris Moore
1 sibling, 1 reply; 5+ messages in thread
From: Kumar Gala @ 2009-09-16 4:11 UTC (permalink / raw)
To: u-boot
On Sep 15, 2009, at 10:32 PM, Peter Tyser wrote:
> On Tue, 2009-09-15 at 22:26 -0500, Kumar Gala wrote:
>> For some reason the CLKDIV field varies between SoC in how it
>> interprets
>> the bit values.
>>
>> All 83xx and early (e500v1) PQ3 devices support:
>> clk/2: CLKDIV = 2
>> clk/4: CLKDIV = 4
>> clk/8: CLKDIV = 8
>>
>> Newer PQ3 (e500v2) and MPC86xx support:
>> clk/4: CLKDIV = 2
>> clk/8: CLKDIV = 4
>> clk/16: CLKDIV = 8
>>
>> Ensure that the MPC86xx and MPC85xx still get the same behavior and
>> make
>> the the defines reflect their logical view (not the value of the
>> field).
>>
>> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
>
> Acked-by: Peter Tyser <ptyser@xes-inc.com>
Peter,
I did notice that we dont actually set LCRR anywhere :)
- k
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] ppc/85xx: Fix LCRR_CLKDIV defines
2009-09-16 4:11 ` Kumar Gala
@ 2009-09-16 4:38 ` Peter Tyser
0 siblings, 0 replies; 5+ messages in thread
From: Peter Tyser @ 2009-09-16 4:38 UTC (permalink / raw)
To: u-boot
On Tue, 2009-09-15 at 23:11 -0500, Kumar Gala wrote:
> On Sep 15, 2009, at 10:32 PM, Peter Tyser wrote:
>
> > On Tue, 2009-09-15 at 22:26 -0500, Kumar Gala wrote:
> >> For some reason the CLKDIV field varies between SoC in how it
> >> interprets
> >> the bit values.
> >>
> >> All 83xx and early (e500v1) PQ3 devices support:
> >> clk/2: CLKDIV = 2
> >> clk/4: CLKDIV = 4
> >> clk/8: CLKDIV = 8
> >>
> >> Newer PQ3 (e500v2) and MPC86xx support:
> >> clk/4: CLKDIV = 2
> >> clk/8: CLKDIV = 4
> >> clk/16: CLKDIV = 8
> >>
> >> Ensure that the MPC86xx and MPC85xx still get the same behavior and
> >> make
> >> the the defines reflect their logical view (not the value of the
> >> field).
> >>
> >> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> >
> > Acked-by: Peter Tyser <ptyser@xes-inc.com>
>
> Peter,
>
> I did notice that we dont actually set LCRR anywhere :)
Lol, that's great:) CONFIG_SYS_LBC_LCRR does affect the value of
sysinfo.freqLocalBus and thus gd->lbc_clk. And sysinfo.freqLocalBus is
used to print the LBC frequency on bootup which added to the delusion
that I was speeding it up:)
A few other boards seem to define CONFIG_SYS_LBC_LCRR, but don't
implement a board-specific modification of the LBCC register, so they
should have the same "bug".
I'll take a closer look tomorrow.
Peter
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH] ppc/85xx: Fix LCRR_CLKDIV defines
2009-09-16 3:32 ` Peter Tyser
2009-09-16 4:11 ` Kumar Gala
@ 2009-09-16 4:29 ` Chris Moore
1 sibling, 0 replies; 5+ messages in thread
From: Chris Moore @ 2009-09-16 4:29 UTC (permalink / raw)
To: u-boot
Peter Tyser a ?crit :
> On Tue, 2009-09-15 at 22:26 -0500, Kumar Gala wrote:
>
>> For some reason the CLKDIV field varies between SoC in how it interprets
>> the bit values.
>>
>>
[snip]
>>
>> Ensure that the MPC86xx and MPC85xx still get the same behavior and make
>> the the defines reflect their logical view (not the value of the field).
>>
>>
Nit picking:
I just noticed that there is a duplicate "the" here.
Also I prefer "behaviour" but this is a US/UK issue :-(
<troll>Why can't Americans write English ;-) ?</troll>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2009-09-16 4:38 UTC | newest]
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2009-09-16 3:26 [U-Boot] [PATCH] ppc/85xx: Fix LCRR_CLKDIV defines Kumar Gala
2009-09-16 3:32 ` Peter Tyser
2009-09-16 4:11 ` Kumar Gala
2009-09-16 4:38 ` Peter Tyser
2009-09-16 4:29 ` Chris Moore
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