* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
@ 2009-09-20 17:28 gareatech at gmail.com
2009-09-21 17:55 ` Magnus Lilja
0 siblings, 1 reply; 15+ messages in thread
From: gareatech at gmail.com @ 2009-09-20 17:28 UTC (permalink / raw)
To: u-boot
From: Fred Fan <fanyefeng@gmail.com>
This patch just supports boot into u-boot from mmc or spi-nor flash.
It just implements console, iomux and clock. There are no ethernet,
nor-flash, mmc or other peripheral drivers.
Sign-of-by: Fred.Fan <fanyefeng@gmail.com>
Sign-of-by: Fred.Fan <r01011@freescale.com>
---
MAINTAINERS | 4 +
MAKEALL | 1 +
Makefile | 3 +
board/freescale/imx51/Makefile | 49 +++
board/freescale/imx51/board-imx51.h | 64 ++++
board/freescale/imx51/config.mk | 2 +
| 113 ++++++
board/freescale/imx51/imx51.c | 233 ++++++++++++
board/freescale/imx51/lowlevel_init.S | 281 ++++++++++++++
board/freescale/imx51/u-boot.lds | 72 ++++
cpu/arm_cortexa8/mx51/Makefile | 50 +++
cpu/arm_cortexa8/mx51/clock.c | 229 +++++++++++
cpu/arm_cortexa8/mx51/crm_regs.h | 673 +++++++++++++++++++++++++++++++++
cpu/arm_cortexa8/mx51/interrupts.c | 33 ++
cpu/arm_cortexa8/mx51/iomux.c | 199 ++++++++++
cpu/arm_cortexa8/mx51/serial.c | 223 +++++++++++
cpu/arm_cortexa8/mx51/soc.c | 66 ++++
cpu/arm_cortexa8/mx51/timer.c | 112 ++++++
include/asm-arm/arch-mx51/iomux.h | 240 ++++++++++++
include/asm-arm/arch-mx51/mx51.h | 416 ++++++++++++++++++++
include/asm-arm/arch-mx51/mx51_pins.h | 370 ++++++++++++++++++
include/configs/imx51.h | 177 +++++++++
22 files changed, 3610 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/imx51/Makefile
create mode 100644 board/freescale/imx51/board-imx51.h
create mode 100644 board/freescale/imx51/config.mk
create mode 100644 board/freescale/imx51/flash_header.S
create mode 100644 board/freescale/imx51/imx51.c
create mode 100644 board/freescale/imx51/lowlevel_init.S
create mode 100644 board/freescale/imx51/u-boot.lds
create mode 100644 cpu/arm_cortexa8/mx51/Makefile
create mode 100644 cpu/arm_cortexa8/mx51/clock.c
create mode 100644 cpu/arm_cortexa8/mx51/crm_regs.h
create mode 100644 cpu/arm_cortexa8/mx51/interrupts.c
create mode 100644 cpu/arm_cortexa8/mx51/iomux.c
create mode 100644 cpu/arm_cortexa8/mx51/serial.c
create mode 100644 cpu/arm_cortexa8/mx51/soc.c
create mode 100644 cpu/arm_cortexa8/mx51/timer.c
create mode 100644 include/asm-arm/arch-mx51/iomux.h
create mode 100644 include/asm-arm/arch-mx51/mx51.h
create mode 100644 include/asm-arm/arch-mx51/mx51_pins.h
create mode 100644 include/configs/imx51.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 620604c..5fb1221 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -549,6 +549,10 @@ Fabio Estevam <Fabio.Estevam@freescale.com>
mx31pdk i.MX31
+Fred Fan <fanyefeng@gmail.com>
+
+ imx51 i.MX51
+
Peter Figuli <peposh@etc.sk>
wepep250 xscale
diff --git a/MAKEALL b/MAKEALL
index edebaea..ed8c437 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -581,6 +581,7 @@ LIST_ARM_CORTEX_A8=" \
omap3_pandora \
omap3_zoom1 \
omap3_zoom2 \
+ imx51 \
"
#########################################################################
diff --git a/Makefile b/Makefile
index e4499d7..27a418c 100644
--- a/Makefile
+++ b/Makefile
@@ -3229,6 +3229,9 @@ mx31pdk_nand_config : unconfig
fi
@$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
+imx51_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 imx51 freescale mx51
+
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
diff --git a/board/freescale/imx51/Makefile b/board/freescale/imx51/Makefile
new file mode 100644
index 0000000..fbd40f2
--- /dev/null
+++ b/board/freescale/imx51/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := imx51.o
+SOBJS := lowlevel_init.o flash_header.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/imx51/board-imx51.h b/board/freescale/imx51/board-imx51.h
new file mode 100644
index 0000000..7a2cae0
--- /dev/null
+++ b/board/freescale/imx51/board-imx51.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __BOARD_FREESCALE_BOARD_IMX51_H__
+#define __BOARD_FREESCALE_BOARD_IMX51_H__
+
+/*!
+ * @defgroup BRDCFG_MX51 Board Configuration Options
+ * @ingroup MSL_MX51
+ */
+
+/*!
+ * @file mx51_3stack/board-imx51.h
+ *
+ * @brief This file contains all the board level configuration options.
+ *
+ * It currently hold the options defined for MX51 3Stack Platform.
+ *
+ * @ingroup BRDCFG_IMX51
+ */
+
+/* CPLD offsets */
+#define PBC_LED_CTRL (0x20000)
+#define PBC_SB_STAT (0x20008)
+#define PBC_ID_AAAA (0x20040)
+#define PBC_ID_5555 (0x20048)
+#define PBC_VERSION (0x20050)
+#define PBC_ID_CAFE (0x20058)
+#define PBC_INT_STAT (0x20010)
+#define PBC_INT_MASK (0x20038)
+#define PBC_INT_REST (0x20020)
+#define PBC_SW_RESET (0x20060)
+
+/* LED switchs */
+#define LED_SWITCH_REG 0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG 0x08
+/* status, interrupt */
+#define INTR_STATUS_REG 0x10
+#define INTR_MASK_REG 0x38
+#define INTR_RESET_REG 0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG 0x40
+#define MAGIC_NUMBER2_REG 0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG 0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG 0x58
+/* module reset register*/
+#define MODULE_RESET_REG 0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG 0x68
+
+#endif /* __BOARD_FREESCALE_BOARD_IMX51_H__ */
diff --git a/board/freescale/imx51/config.mk b/board/freescale/imx51/config.mk
new file mode 100644
index 0000000..d8b0f10
--- /dev/null
+++ b/board/freescale/imx51/config.mk
@@ -0,0 +1,2 @@
+LDSCRIPT = board/$(VENDOR)/$(BOARD)/u-boot.lds
+TEXT_BASE = 0x97800000
--git a/board/freescale/imx51/flash_header.S b/board/freescale/imx51/flash_header.S
new file mode 100644
index 0000000..6790679
--- /dev/null
+++ b/board/freescale/imx51/flash_header.S
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx51.h>
+#include "board-imx51.h"
+
+#ifdef CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+#define MXC_DCD_ITEM(i, type, addr, val) \
+dcd_node_##i: \
+ .word type ; \
+ .word addr ; \
+ .word val ; \
+
+.section ".text.flasheader", "x"
+ b _start
+ .org CONFIG_FLASH_HEADER_OFFSET
+app_code_jump_v: .word _start
+app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER
+app_code_csf: .word 0
+dcd_ptr_ptr: .word dcd_ptr
+super_root_key: .word 0
+dcd_ptr: .word dcd_array_start
+app_dest_ptr: .word TEXT_BASE
+dcd_array_start:
+magic: .word 0xB17219E9
+dcd_array_size: .word dcd_data_end - dcd_array_start - 8
+/* DCD */
+/* DDR2 IOMUX configuration */
+MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
+MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
+MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
+MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
+MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
+MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
+MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
+MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
+MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
+MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
+MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
+MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
+MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
+MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
+MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
+MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
+MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
+MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
+/* Set drive strength to MAX */
+MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6)
+MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6)
+MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6)
+MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6)
+/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
+/* CAS=3, BL=4 */
+MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
+MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
+MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
+MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
+MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
+/* Init DRAM on CS0 */
+MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
+MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
+MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
+MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
+MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
+MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
+MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
+MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
+/* Init DRAM on CS1 */
+MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
+MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
+MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
+MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
+MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
+MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
+MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
+MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
+MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
+MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
+MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
+MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
+MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
+dcd_data_end:
+image_len: .word 0x100000
+//image_len: .word _end - _start
+#endif
diff --git a/board/freescale/imx51/imx51.c b/board/freescale/imx51/imx51.c
new file mode 100644
index 0000000..f152c9a
--- /dev/null
+++ b/board/freescale/imx51/imx51.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx51.h>
+#include <asm/arch/mx51_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <i2c.h>
+#include "board-imx51.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+u32 mx51_io_base_addr;
+volatile u32 *esdhc_base_pointer;
+
+u32 get_board_rev(void)
+{
+ return system_rev;
+}
+
+static inline void setup_soc_rev(void)
+{
+ int reg;
+ reg = __raw_readl(ROM_SI_REV);
+ switch (reg) {
+ case 0x02:
+ system_rev = 0x51000 | CHIP_REV_1_1;
+ break;
+ case 0x10:
+ if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) {
+ system_rev = 0x51000 | CHIP_REV_2_5;
+ } else {
+ system_rev = 0x51000 | CHIP_REV_2_0;
+ }
+ break;
+ default:
+ system_rev = 0x51000 | CHIP_REV_1_0;
+ }
+}
+
+static inline void set_board_rev(int rev)
+{
+ system_rev |= (rev & 0xF) << 8;
+}
+
+inline int is_soc_rev(int rev)
+{
+ return (system_rev & 0xFF) - rev;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+static void setup_uart(void)
+{
+ unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
+ mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
+ mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
+}
+
+void setup_nfc(void)
+{
+ /* Enable NFC IOMUX */
+ mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
+}
+
+static void setup_expio(void)
+{
+ u32 reg;
+ /* CS5 setup */
+ mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
+ writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1);
+ writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2);
+ /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
+ writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1);
+ /* APR = 0 */
+ writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2);
+ /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
+ * WCSA=0, WCSN=0
+ */
+ writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1);
+ if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) &&
+ (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) {
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+ reg = (reg & (~0x70000)) | 0x30000;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
+ /* make sure divider effective */
+ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
+ ;
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+ }
+ mx51_io_base_addr = CS5_BASE_ADDR;
+ } else {
+ /* CS1 */
+ writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1);
+ writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2);
+ /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
+ writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1);
+ /* APR=0 */
+ writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2);
+ /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
+ * WEN=0, WCSA=0, WCSN=0
+ */
+ writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1);
+ mx51_io_base_addr = CS1_BASE_ADDR;
+ }
+
+ /* Reset interrupt status reg */
+ writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
+ writew(0x00, mx51_io_base_addr + PBC_INT_REST);
+ writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
+
+ /* Reset the XUART and Ethernet controllers */
+ reg = readw(mx51_io_base_addr + PBC_SW_RESET);
+ reg |= 0x9;
+ writew(reg, mx51_io_base_addr + PBC_SW_RESET);
+ reg &= ~0x9;
+ writew(reg, mx51_io_base_addr + PBC_SW_RESET);
+}
+
+#ifdef CONFIG_NET_MULTI
+
+#if defined(CONFIG_DRIVER_SMC911X)
+extern int smc911x_initialize(bd_t *bis);
+#endif
+int board_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+#if defined(CONFIG_DRIVER_SMC911X)
+ rc = smc911x_initialize(bis);
+#endif
+
+ return rc;
+}
+#endif
+
+int board_init(void)
+{
+ setup_soc_rev();
+
+ gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE; /* board id for linux */
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ setup_uart();
+ setup_nfc();
+ setup_expio();
+ return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+ return 0;
+}
+#endif
+
+int checkboard(void)
+{
+ printf("Board: MX51 BABBAGE ");
+
+ if (system_rev & CHIP_REV_2_5) {
+ printf("2.5 [");
+ } else if (system_rev & CHIP_REV_2_0) {
+ printf("2.0 [");
+ } else if (system_rev & CHIP_REV_1_1) {
+ printf("1.1 [");
+ } else {
+ printf("1.0 [");
+ }
+
+ switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
+ case 0x0001:
+ printf("POR");
+ break;
+ case 0x0009:
+ printf("RST");
+ break;
+ case 0x0010:
+ case 0x0011:
+ printf("WDOG");
+ break;
+ default:
+ printf("unknown");
+ }
+ printf("]\n");
+ return 0;
+}
+
diff --git a/board/freescale/imx51/lowlevel_init.S b/board/freescale/imx51/lowlevel_init.S
new file mode 100644
index 0000000..e1296f8
--- /dev/null
+++ b/board/freescale/imx51/lowlevel_init.S
@@ -0,0 +1,281 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx51.h>
+#include "board-imx51.h"
+
+/*
+ * return soc version
+ * 0x10: TO1
+ * 0x20: TO2
+ * 0x30: TO3
+ */
+.macro check_soc_version ret, tmp
+.endm
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+ /* reconfigure L2 cache aux control reg */
+ ldr r0, =0x03C000C4
+ mcr p15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =0x77777777
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+.endm /* init_aips */
+
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+.endm /* init_max */
+
+/* M4IF setup */
+.macro init_m4if
+ /* VPU and IPU given higher priority (0x4)
+ * IPU accesses with ID=0x1 given highest priority (=0xA)
+ */
+ ldr r0, =M4IF_BASE_ADDR
+
+ ldr r1, =0x00000203
+ str r1, [r0, #0x40]
+
+ ldr r1, =0x0
+ str r1, [r0, #0x44]
+
+ ldr r1, =0x00120125
+ str r1, [r0, #0x9C]
+
+ ldr r1, =0x001901A3
+ str r1, [r0, #0x48]
+
+/*
+ ldr r1, =0x00000a01
+ str r1, [r0, #0x48]
+ ldr r1, =0x00000404
+ str r1, [r0, #0x40]
+*/
+.endm /* init_m4if */
+
+/* To support 133MHz DDR */
+.macro init_drive_strength
+.endm /* init_drive_strength */
+
+/* CPLD on CS5 setup */
+.macro init_debug_board
+.endm /* init_debug_board */
+
+.macro setup_pll pll, freq
+ ldr r2, =\pll
+ ldr r1, =0x00001232
+ str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ mov r1, #0x2
+ str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ str r3, [r2, #PLL_DP_OP]
+ str r3, [r2, #PLL_DP_HFS_OP]
+
+ str r4, [r2, #PLL_DP_MFD]
+ str r4, [r2, #PLL_DP_HFS_MFD]
+
+ str r5, [r2, #PLL_DP_MFN]
+ str r5, [r2, #PLL_DP_HFS_MFN]
+
+ ldr r1, =0x00001232
+ str r1, [r2, #PLL_DP_CTL]
+1: ldr r1, [r2, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+.endm
+
+.macro init_clock
+ ldr r0, =CCM_BASE_ADDR
+ mov r1, #0x00060000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+
+ mov r3, #DP_OP_800
+ mov r4, #DP_MFD_800
+ mov r5, #DP_MFN_800
+ setup_pll PLL1_BASE_ADDR
+ mov r3, #DP_OP_665
+ mov r4, #DP_MFD_665
+ mov r5, #DP_MFN_665
+ setup_pll PLL3_BASE_ADDR
+
+ /* Switch peripheral to PLL 3 */
+ ldr r1, =0x0000D3C0
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, =0x033B9145
+ str r1, [r0, #CLKCTL_CBCDR]
+ mov r3, #DP_OP_665
+ mov r4, #DP_MFD_665
+ mov r5, #DP_MFN_665
+ setup_pll PLL2_BASE_ADDR
+
+ /* Switch peripheral to PLL2 */
+ ldr r1, =0x013B9145
+ str r1, [r0, #CLKCTL_CBCDR]
+ ldr r1, =0x0000E3C0
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ mov r3, #DP_OP_216
+ mov r4, #DP_MFD_216
+ mov r5, #DP_MFN_216
+ setup_pll PLL3_BASE_ADDR
+
+ /* Set the platform clock dividers */
+ ldr r2, =ARM_BASE_ADDR
+ ldr r1, =0x00000725
+ str r1, [r2, #0x14]
+
+ /* Switch ARM back to PLL 1 */
+ mov r1, #0
+ str r1, [r0, #CLKCTL_CCSR]
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Use lp_apm (24MHz) source for perclk */
+ mov r2, #0x48
+ ldr r2, [r0]
+ cmp r2, #0x10
+ ldrhs r1, =0x000020C2
+ ldrlo r1, =0x0000E3C2
+ str r1, [r0, #CLKCTL_CBCMR]
+ /* TO1.x emi = ahb, all perclk dividers are 1 since using 24MHz */
+ /* TO2.x ddr from PLL1, all perclk dividers are 1 since using 24MHz */
+ ldrhs r1, =0x59239100
+ ldrlo r1, =0x013D9100
+ strlo r1, [r0, #CLKCTL_CBCDR]
+
+ /* use PLL2 for UART source, get 66.5MHz */
+ ldr r1, =0xA5A2A020
+ str r1, [r0, #CLKCTL_CSCMR1]
+ ldr r1, =0x00C30321
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ /* make sure divider effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0
+ bne 1b
+
+ mov r1, #0x0
+ str r1, [r0, #CLKCTL_CCDR]
+.endm
+
+.macro setup_wdog
+ ldr r0, =WDOG1_BASE_ADDR
+ mov r1, #0x30
+ strh r1, [r0]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Platform CHIP level init*/
+ ldr r0, =GPIO1_BASE_ADDR
+ ldr r1, [r0, #0x0]
+ orr r1, r1, #(1 << 23)
+ str r1, [r0, #0x0]
+ ldr r1, [r0, #0x4]
+ orr r1, r1, #(1 << 23)
+ str r1, [r0, #0x4]
+
+#ifdef TURN_OFF_IMPRECISE_ABORT
+ mrs r0, cpsr
+ bic r0, r0, #0x100
+ msr cpsr, r0
+#endif
+
+ mrc 15, 0, r1, c1, c0, 0
+
+#ifndef BRANCH_PREDICTION_ENABLE
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #7
+ mcr 15, 0, r0, c1, c0, 1
+#else
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #7
+ mcr 15, 0, r0, c1, c0, 1
+ orr r1, r1, #(1<<11)
+#endif
+
+#ifdef UNALIGNED_ACCESS_ENABLE
+ orr r1, r1, #(1<<22)
+#endif
+
+#ifdef LOW_INT_LATENCY_ENABLE
+ orr r1, r1, #(1<<21)
+#endif
+ mcr 15, 0, r1, c1, c0, 0
+
+ mov r0, #0
+#ifdef BRANCH_PREDICTION_ENABLE
+ mcr 15, 0, r0, c15, c2, 4
+#endif
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
+ init_l2cc
+
+ init_aips
+
+ init_max
+
+ init_m4if
+
+ init_drive_strength
+
+ init_clock
+ init_debug_board
+ /*init_sdram*/
+
+ /* return from mxc_nand_load */
+ /* r12 saved upper lr*/
+ mov pc, lr
+
+/* Board level setting value */
+DDR_PERCHARGE_CMD: .word 0x04008008
+DDR_REFRESH_CMD: .word 0x00008010
+DDR_LMR1_W: .word 0x00338018
+DDR_LMR_CMD: .word 0xB2220000
+DDR_TIMING_W: .word 0xB02567A9
+DDR_MISC_W: .word 0x000A0104
diff --git a/board/freescale/imx51/u-boot.lds b/board/freescale/imx51/u-boot.lds
new file mode 100644
index 0000000..8cf619f
--- /dev/null
+++ b/board/freescale/imx51/u-boot.lds
@@ -0,0 +1,72 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+ board/freescale/imx51/flash_header.o (.text.flasheader)
+ cpu/arm_cortexa8/start.o
+ board/freescale/imx51/libimx51.a (.text)
+ lib_arm/libarm.a (.text)
+ net/libnet.a (.text)
+ drivers/mtd/libmtd.a (.text)
+ drivers/mmc/libmmc.a (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/cpu/arm_cortexa8/mx51/Makefile b/cpu/arm_cortexa8/mx51/Makefile
new file mode 100644
index 0000000..ee241ca
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS-y = soc.o timer.o serial.o clock.o iomux.o
+SOBJS-y =
+
+COBJS-$(CONFIG_USE_IRQ) += interrupts.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm_cortexa8/mx51/clock.c b/cpu/arm_cortexa8/mx51/clock.c
new file mode 100644
index 0000000..64f2c61
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/clock.c
@@ -0,0 +1,229 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx51.h>
+#include <asm/errno.h>
+#include "crm_regs.h"
+
+enum pll_clocks {
+PLL1_CLK = MXC_DPLL1_BASE,
+PLL2_CLK = MXC_DPLL2_BASE,
+PLL3_CLK = MXC_DPLL3_BASE,
+};
+
+enum pll_sw_clocks {
+PLL1_SW_CLK,
+PLL2_SW_CLK,
+PLL3_SW_CLK,
+};
+
+static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
+{
+ u32 mfi, mfn, mfd, pd;
+
+ mfn = __raw_readl(pll + MXC_PLL_DP_MFN);
+ mfd = __raw_readl(pll + MXC_PLL_DP_MFD) + 1;
+ mfi = __raw_readl(pll + MXC_PLL_DP_OP);
+ pd = (mfi & 0xF) + 1;
+ mfi = (mfi >> 4) & 0xF;
+ mfi = (mfi >= 5) ? mfi : 5;
+
+ return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
+}
+
+u32 __get_mcu_main_clk(void)
+{
+ u32 reg, freq;
+ reg = (__raw_readl(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
+ MXC_CCM_CACRR_ARM_PODF_OFFSET;
+ freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
+ return freq / (reg + 1);
+}
+
+static u32 __get_periph_clk(void)
+{
+ u32 reg;
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+ reg = __raw_readl(MXC_CCM_CBCMR);
+ switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
+ MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+ case 0:
+ return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
+ case 1:
+ return __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
+ default:
+ return 0;
+ }
+ }
+ return __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
+}
+
+static u32 __get_ipg_clk(void)
+{
+ u32 ahb_podf, ipg_podf;
+
+ ahb_podf = __raw_readl(MXC_CCM_CBCDR);
+ ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
+ MXC_CCM_CBCDR_IPG_PODF_OFFSET;
+ ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
+ MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+ return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
+}
+
+static u32 __get_ipg_per_clk(void)
+{
+ u32 pred1, pred2, podf;
+ if (__raw_readl(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
+ return __get_ipg_clk();
+ /* Fixme: not handle what about lpm*/
+ podf = __raw_readl(MXC_CCM_CBCDR);
+ pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
+ pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
+ podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
+
+ return __get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
+}
+
+static u32 __get_uart_clk(void)
+{
+ unsigned int freq, reg, pred, podf;
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
+ MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
+ case 0x0:
+ freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
+ break;
+ case 0x1:
+ freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
+ break;
+ case 0x2:
+ freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
+ break;
+ default:
+ return 66500000;
+ }
+
+ reg = __raw_readl(MXC_CCM_CSCDR1);
+
+ pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
+
+ podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+ freq /= (pred + 1) * (podf + 1);
+
+ return freq;
+}
+
+/*!
++ * This function returns the low power audio clock.
++ */
+u32 get_lp_apm(void)
+{
+ u32 ret_val = 0;
+ u32 ccsr = __raw_readl(MXC_CCM_CCSR);
+
+ if (((ccsr >> 9) & 1) == 0)
+ ret_val = CONFIG_MX51_HCLK_FREQ;
+ else
+ ret_val = ((32768 * 1024));
+
+ return ret_val;
+}
+
+static u32 __get_cspi_clk(void)
+{
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+ u32 cscmr1 = __raw_readl(MXC_CCM_CSCMR1);
+ u32 cscdr2 = __raw_readl(MXC_CCM_CSCDR2);
+
+ pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
+ >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
+ pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
+ >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
+ clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
+ >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+
+ switch (clk_sel) {
+ case 0:
+ ret_val = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case 1:
+ ret_val = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case 2:
+ ret_val = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ default:
+ ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ }
+
+ return ret_val;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return __get_mcu_main_clk();
+ case MXC_AHB_CLK:
+ break;
+ case MXC_IPG_CLK:
+ return __get_ipg_clk();
+ case MXC_IPG_PERCLK:
+ return __get_ipg_per_clk();
+ case MXC_UART_CLK:
+ return __get_uart_clk();
+ case MXC_CSPI_CLK:
+ return __get_cspi_clk();
+ case MXC_FEC_CLK:
+ return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
+ default:
+ break;
+ }
+ return -1;
+}
+
+void mxc_show_clocks(void)
+{
+ u32 freq;
+ freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
+ printf("mx51 pll1: %dMHz\n", freq / 1000000);
+ freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
+ printf("mx51 pll2: %dMHz\n", freq / 1000000);
+ freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
+ printf("mx51 pll3: %dMHz\n", freq / 1000000);
+ printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
+ printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
+ printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
+ printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK));
+}
diff --git a/cpu/arm_cortexa8/mx51/crm_regs.h b/cpu/arm_cortexa8/mx51/crm_regs.h
new file mode 100644
index 0000000..6436bed
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/crm_regs.h
@@ -0,0 +1,673 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+
+#define MXC_CCM_BASE CCM_BASE_ADDR
+#define MXC_DPLL1_BASE PLL1_BASE_ADDR
+#define MXC_DPLL2_BASE PLL2_BASE_ADDR
+#define MXC_DPLL3_BASE PLL3_BASE_ADDR
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL 0x00
+#define MXC_PLL_DP_CONFIG 0x04
+#define MXC_PLL_DP_OP 0x08
+#define MXC_PLL_DP_MFD 0x0C
+#define MXC_PLL_DP_MFN 0x10
+#define MXC_PLL_DP_MFNMINUS 0x14
+#define MXC_PLL_DP_MFNPLUS 0x18
+#define MXC_PLL_DP_HFS_OP 0x1C
+#define MXC_PLL_DP_HFS_MFD 0x20
+#define MXC_PLL_DP_HFS_MFN 0x24
+#define MXC_PLL_DP_MFN_TOGC 0x28
+#define MXC_PLL_DP_DESTAT 0x2c
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
+#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
+#define MXC_PLL_DP_CTL_ADE 0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
+#define MXC_PLL_DP_CTL_HFSM 0x80
+#define MXC_PLL_DP_CTL_PRE 0x40
+#define MXC_PLL_DP_CTL_UPEN 0x20
+#define MXC_PLL_DP_CTL_RST 0x10
+#define MXC_PLL_DP_CTL_RCP 0x8
+#define MXC_PLL_DP_CTL_PLM 0x4
+#define MXC_PLL_DP_CTL_BRM0 0x2
+#define MXC_PLL_DP_CTL_LRF 0x1
+
+#define MXC_PLL_DP_CONFIG_BIST 0x8
+#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
+#define MXC_PLL_DP_CONFIG_AREN 0x2
+#define MXC_PLL_DP_CONFIG_LDREQ 0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET 4
+#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
+#define MXC_PLL_DP_OP_PDF_OFFSET 0
+#define MXC_PLL_DP_OP_PDF_MASK 0xF
+
+#define MXC_PLL_DP_MFD_OFFSET 0
+#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET 0x0
+#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
+#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
+#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
+#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
+
+#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
+#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
+
+/* Register addresses of CCM*/
+#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
+#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
+#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
+#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
+#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
+#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
+#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
+#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
+#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
+#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
+#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
+#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
+#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
+#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
+#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
+#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
+#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
+#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
+#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
+#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
+#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
+#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
+#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
+#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
+#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
+#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
+#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
+#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
+#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
+#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
+#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
+#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
+#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
+#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x84)
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN (1 << 12)
+#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
+#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
+#define MXC_CCM_CCR_FPM_EN (1 << 8)
+#define MXC_CCM_CCR_OSCNT_OFFSET (0)
+#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
+#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
+#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
+
+/* Define the bits in register CSR */
+#define MXC_CCM_CSR_COSR_READY (1 << 5)
+#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
+#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
+#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
+#define MXC_CCM_CSR_FPM_READY (1 << 1)
+#define MXC_CCM_CSR_REF_EN_B (1 << 0)
+
+/* Define the bits in register CCSR */
+#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
+#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
+#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
+#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
+#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
+#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
+#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
+#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
+#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
+#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
+#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
+#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
+#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
+#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
+#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
+#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
+
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET (26)
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK (0x7 << 26)
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
+#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
+#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
+#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
+#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
+#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
+
+/* Define the bits in register CS1CDR and CS2CDR */
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
+
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
+
+/* Define the bits in register CDCDR */
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
+
+/* Define the bits in register CHSCCDR */
+#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
+
+/* Define the bits in register CSCDR3 */
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
+
+/* Define the bits in register CSCDR4 */
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
+
+/* Define the bits in register CDHIPR */
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
+#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
+#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
+#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
+#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
+#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
+
+/* Define the bits in register CDCR */
+#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
+#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
+#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
+#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
+#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
+#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
+#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
+#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
+#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
+#define MXC_CCM_CLPCR_LPM_OFFSET (0)
+#define MXC_CCM_CLPCR_LPM_MASK (0x3)
+
+/* Define the bits in register CISR */
+#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
+#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
+#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
+#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
+#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
+#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
+#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
+#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
+#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
+#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
+#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
+#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
+#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
+#define MXC_CCM_CISR_LRF_PLL1 (0x1)
+
+/* Define the bits in register CIMR */
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
+#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
+#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
+#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
+#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
+#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
+#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
+#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
+#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
+#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
+#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
+#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
+#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
+
+/* Define the bits in register CCOSR */
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
+#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
+
+/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
+#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
+
+/* Define the bits in registers CCGRx */
+#define MXC_CCM_CCGR_CG_MASK 0x3
+
+#define MXC_CCM_CCGR0_CG15_OFFSET 30
+#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
+#define MXC_CCM_CCGR0_CG14_OFFSET 28
+#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
+#define MXC_CCM_CCGR0_CG13_OFFSET 26
+#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
+#define MXC_CCM_CCGR0_CG12_OFFSET 24
+#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
+#define MXC_CCM_CCGR0_CG11_OFFSET 22
+#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
+#define MXC_CCM_CCGR0_CG10_OFFSET 20
+#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
+#define MXC_CCM_CCGR0_CG9_OFFSET 18
+#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
+#define MXC_CCM_CCGR0_CG8_OFFSET 16
+#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
+#define MXC_CCM_CCGR0_CG7_OFFSET 14
+#define MXC_CCM_CCGR0_CG6_OFFSET 12
+#define MXC_CCM_CCGR0_CG5_OFFSET 10
+#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
+#define MXC_CCM_CCGR0_CG4_OFFSET 8
+#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
+#define MXC_CCM_CCGR0_CG3_OFFSET 6
+#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
+#define MXC_CCM_CCGR0_CG2_OFFSET 4
+#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
+#define MXC_CCM_CCGR0_CG1_OFFSET 2
+#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
+#define MXC_CCM_CCGR0_CG0_OFFSET 0
+#define MXC_CCM_CCGR0_CG0_MASK 0x3
+
+#define MXC_CCM_CCGR1_CG15_OFFSET 30
+#define MXC_CCM_CCGR1_CG14_OFFSET 28
+#define MXC_CCM_CCGR1_CG13_OFFSET 26
+#define MXC_CCM_CCGR1_CG12_OFFSET 24
+#define MXC_CCM_CCGR1_CG11_OFFSET 22
+#define MXC_CCM_CCGR1_CG10_OFFSET 20
+#define MXC_CCM_CCGR1_CG9_OFFSET 18
+#define MXC_CCM_CCGR1_CG8_OFFSET 16
+#define MXC_CCM_CCGR1_CG7_OFFSET 14
+#define MXC_CCM_CCGR1_CG6_OFFSET 12
+#define MXC_CCM_CCGR1_CG5_OFFSET 10
+#define MXC_CCM_CCGR1_CG4_OFFSET 8
+#define MXC_CCM_CCGR1_CG3_OFFSET 6
+#define MXC_CCM_CCGR1_CG2_OFFSET 4
+#define MXC_CCM_CCGR1_CG1_OFFSET 2
+#define MXC_CCM_CCGR1_CG0_OFFSET 0
+
+#define MXC_CCM_CCGR2_CG15_OFFSET 30
+#define MXC_CCM_CCGR2_CG14_OFFSET 28
+#define MXC_CCM_CCGR2_CG13_OFFSET 26
+#define MXC_CCM_CCGR2_CG12_OFFSET 24
+#define MXC_CCM_CCGR2_CG11_OFFSET 22
+#define MXC_CCM_CCGR2_CG10_OFFSET 20
+#define MXC_CCM_CCGR2_CG9_OFFSET 18
+#define MXC_CCM_CCGR2_CG8_OFFSET 16
+#define MXC_CCM_CCGR2_CG7_OFFSET 14
+#define MXC_CCM_CCGR2_CG6_OFFSET 12
+#define MXC_CCM_CCGR2_CG5_OFFSET 10
+#define MXC_CCM_CCGR2_CG4_OFFSET 8
+#define MXC_CCM_CCGR2_CG3_OFFSET 6
+#define MXC_CCM_CCGR2_CG2_OFFSET 4
+#define MXC_CCM_CCGR2_CG1_OFFSET 2
+#define MXC_CCM_CCGR2_CG0_OFFSET 0
+
+#define MXC_CCM_CCGR3_CG15_OFFSET 30
+#define MXC_CCM_CCGR3_CG14_OFFSET 28
+#define MXC_CCM_CCGR3_CG13_OFFSET 26
+#define MXC_CCM_CCGR3_CG12_OFFSET 24
+#define MXC_CCM_CCGR3_CG11_OFFSET 22
+#define MXC_CCM_CCGR3_CG10_OFFSET 20
+#define MXC_CCM_CCGR3_CG9_OFFSET 18
+#define MXC_CCM_CCGR3_CG8_OFFSET 16
+#define MXC_CCM_CCGR3_CG7_OFFSET 14
+#define MXC_CCM_CCGR3_CG6_OFFSET 12
+#define MXC_CCM_CCGR3_CG5_OFFSET 10
+#define MXC_CCM_CCGR3_CG4_OFFSET 8
+#define MXC_CCM_CCGR3_CG3_OFFSET 6
+#define MXC_CCM_CCGR3_CG2_OFFSET 4
+#define MXC_CCM_CCGR3_CG1_OFFSET 2
+#define MXC_CCM_CCGR3_CG0_OFFSET 0
+
+#define MXC_CCM_CCGR4_CG15_OFFSET 30
+#define MXC_CCM_CCGR4_CG14_OFFSET 28
+#define MXC_CCM_CCGR4_CG13_OFFSET 26
+#define MXC_CCM_CCGR4_CG12_OFFSET 24
+#define MXC_CCM_CCGR4_CG11_OFFSET 22
+#define MXC_CCM_CCGR4_CG10_OFFSET 20
+#define MXC_CCM_CCGR4_CG9_OFFSET 18
+#define MXC_CCM_CCGR4_CG8_OFFSET 16
+#define MXC_CCM_CCGR4_CG7_OFFSET 14
+#define MXC_CCM_CCGR4_CG6_OFFSET 12
+#define MXC_CCM_CCGR4_CG5_OFFSET 10
+#define MXC_CCM_CCGR4_CG4_OFFSET 8
+#define MXC_CCM_CCGR4_CG3_OFFSET 6
+#define MXC_CCM_CCGR4_CG2_OFFSET 4
+#define MXC_CCM_CCGR4_CG1_OFFSET 2
+#define MXC_CCM_CCGR4_CG0_OFFSET 0
+
+#define MXC_CCM_CCGR5_CG15_OFFSET 30
+#define MXC_CCM_CCGR5_CG14_OFFSET 28
+#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
+#define MXC_CCM_CCGR5_CG13_OFFSET 26
+#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
+#define MXC_CCM_CCGR5_CG12_OFFSET 24
+#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
+#define MXC_CCM_CCGR5_CG11_OFFSET 22
+#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
+#define MXC_CCM_CCGR5_CG10_OFFSET 20
+#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
+#define MXC_CCM_CCGR5_CG9_OFFSET 18
+#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
+#define MXC_CCM_CCGR5_CG8_OFFSET 16
+#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
+#define MXC_CCM_CCGR5_CG7_OFFSET 14
+#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
+#define MXC_CCM_CCGR5_CG6_OFFSET 12
+#define MXC_CCM_CCGR5_CG5_OFFSET 10
+#define MXC_CCM_CCGR5_CG4_OFFSET 8
+#define MXC_CCM_CCGR5_CG3_OFFSET 6
+#define MXC_CCM_CCGR5_CG2_OFFSET 4
+#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
+#define MXC_CCM_CCGR5_CG1_OFFSET 2
+#define MXC_CCM_CCGR5_CG0_OFFSET 0
+
+#define MXC_CCM_CCGR6_CG4_OFFSET 8
+#define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8)
+#define MXC_CCM_CCGR6_CG3_OFFSET 6
+#define MXC_CCM_CCGR6_CG2_OFFSET 4
+#define MXC_CCM_CCGR6_CG1_OFFSET 2
+#define MXC_CCM_CCGR6_CG0_OFFSET 0
+
+#define MXC_CORTEXA8_BASE ARM_BASE_ADDR
+#define MXC_GPC_BASE GPC_BASE_ADDR
+#define MXC_DPTC_LP_BASE (GPC_BASE_ADDR + 0x80)
+#define MXC_DPTC_GP_BASE (GPC_BASE_ADDR + 0x100)
+#define MXC_DVFS_CORE_BASE (GPC_BASE_ADDR + 0x180)
+#define MXC_DPTC_PER_BASE (GPC_BASE_ADDR + 0x1C0)
+#define MXC_PGC_IPU_BASE (GPC_BASE_ADDR + 0x220)
+#define MXC_PGC_VPU_BASE (GPC_BASE_ADDR + 0x240)
+#define MXC_PGC_GPU_BASE (GPC_BASE_ADDR + 0x260)
+#define MXC_SRPG_NEON_BASE (GPC_BASE_ADDR + 0x280)
+#define MXC_SRPG_ARM_BASE (GPC_BASE_ADDR + 0x2A0)
+#define MXC_SRPG_EMPGC0_BASE (GPC_BASE_ADDR + 0x2C0)
+#define MXC_SRPG_EMPGC1_BASE (GPC_BASE_ADDR + 0x2D0)
+#define MXC_SRPG_MEGAMIX_BASE (GPC_BASE_ADDR + 0x2E0)
+#define MXC_SRPG_EMI_BASE (GPC_BASE_ADDR + 0x300)
+
+/* CORTEXA8 platform */
+#define MXC_CORTEXA8_PLAT_PVID (MXC_CORTEXA8_BASE + 0x0)
+#define MXC_CORTEXA8_PLAT_GPC (MXC_CORTEXA8_BASE + 0x4)
+#define MXC_CORTEXA8_PLAT_PIC (MXC_CORTEXA8_BASE + 0x8)
+#define MXC_CORTEXA8_PLAT_LPC (MXC_CORTEXA8_BASE + 0xC)
+#define MXC_CORTEXA8_PLAT_NEON_LPC (MXC_CORTEXA8_BASE + 0x10)
+#define MXC_CORTEXA8_PLAT_ICGC (MXC_CORTEXA8_BASE + 0x14)
+#define MXC_CORTEXA8_PLAT_AMC (MXC_CORTEXA8_BASE + 0x18)
+#define MXC_CORTEXA8_PLAT_NMC (MXC_CORTEXA8_BASE + 0x20)
+#define MXC_CORTEXA8_PLAT_NMS (MXC_CORTEXA8_BASE + 0x24)
+
+/* DVFS CORE */
+#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
+#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
+#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
+#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
+#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
+#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
+#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
+#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
+#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
+#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
+#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
+#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
+#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
+#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
+#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
+#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
+#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
+
+/* GPC */
+#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
+#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
+#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
+#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC)
+#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10)
+#define MXC_GPC_PGR_ARMPG_OFFSET 8
+#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
+
+/* PGC */
+#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
+#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
+#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
+#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
+#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
+#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
+
+#define MXC_PGCR_PCR 1
+#define MXC_SRPGCR_PCR 1
+#define MXC_EMPGCR_PCR 1
+#define MXC_PGSR_PSR 1
+
+
+#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
+#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
+
+/* SRPG */
+#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
+#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
+#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
+
+#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
+#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
+#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
+
+#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
+#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
+#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
+
+#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
+#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
+#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
+
+#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
+#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
+#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
+
+#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
+#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
+#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
+
+#ifndef __ASSEMBLE__
+extern unsigned int __get_mcu_main_clk(void);
+extern void mxc_show_clocks(void);
+#endif
+#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/cpu/arm_cortexa8/mx51/interrupts.c b/cpu/arm_cortexa8/mx51/interrupts.c
new file mode 100644
index 0000000..c0d70ac
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/interrupts.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx51.h>
+
+/* nothing really to do with interrupts. */
+int interrupt_init(void)
+{
+ return 0;
+}
diff --git a/cpu/arm_cortexa8/mx51/iomux.c b/cpu/arm_cortexa8/mx51/iomux.c
new file mode 100644
index 0000000..80082aa
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/iomux.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup GPIO_MX51 Board GPIO and Muxing Setup
+ * @ingroup MSL_MX51
+ */
+/*!
+ * @file mach-mx51/iomux.c
+ *
+ * @brief I/O Muxing control functions
+ *
+ * @ingroup GPIO_MX51
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx51.h>
+#include <asm/arch/mx51_pins.h>
+#include <asm/arch/iomux.h>
+
+/*!
+ * IOMUX register (base) addresses
+ */
+enum iomux_reg_addr {
+ IOMUXGPR0 = IOMUXC_BASE_ADDR,
+ IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
+ IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
+ IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
+ IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
+ IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
+};
+
+#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
+
+static inline u32 _get_mux_reg(iomux_pin_name_t pin)
+{
+ u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
+
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
+ if ((pin == MX51_PIN_NANDF_RB5) ||
+ (pin == MX51_PIN_NANDF_RB6) ||
+ (pin == MX51_PIN_NANDF_RB7))
+ ; /* Do nothing */
+ else if (mux_reg >= 0x2FC)
+ mux_reg += 8;
+ else if (mux_reg >= 0x130)
+ mux_reg += 0xC;
+ }
+ mux_reg += IOMUXSW_MUX_CTL;
+ return mux_reg;
+}
+
+static inline u32 _get_pad_reg(iomux_pin_name_t pin)
+{
+ u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
+
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
+ if ((pin == MX51_PIN_NANDF_RB5) ||
+ (pin == MX51_PIN_NANDF_RB6) ||
+ (pin == MX51_PIN_NANDF_RB7))
+ ; /* Do nothing */
+ else if (pad_reg == 0x4D0 - PAD_I_START)
+ pad_reg += 0x4C;
+ else if (pad_reg == 0x860 - PAD_I_START)
+ pad_reg += 0x9C;
+ else if (pad_reg >= 0x804 - PAD_I_START)
+ pad_reg += 0xB0;
+ else if (pad_reg >= 0x7FC - PAD_I_START)
+ pad_reg += 0xB4;
+ else if (pad_reg >= 0x4E4 - PAD_I_START)
+ pad_reg += 0xCC;
+ else
+ pad_reg += 8;
+ }
+ pad_reg += IOMUXSW_PAD_CTL;
+ return pad_reg;
+}
+
+static inline u32 _get_mux_end(void)
+{
+ if (is_soc_rev(CHIP_REV_2_0) < 0)
+ return IOMUXC_BASE_ADDR + (0x3F8 - 4);
+ else
+ return IOMUXC_BASE_ADDR + (0x3F0 - 4);
+}
+
+/*!
+ * This function is used to configure a pin through the IOMUX module.
+ * FIXED ME: for backward compatible. Will be static function!
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param cfg an output function as defined in \b #iomux_pin_cfg_t
+ *
+ * @return 0 if successful; Non-zero otherwise
+ */
+static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+ u32 mux_reg = _get_mux_reg(pin);
+
+ if ((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
+ return -1;
+ if (cfg == IOMUX_CONFIG_GPIO)
+ writel(PIN_TO_ALT_GPIO(pin), mux_reg);
+ else
+ writel(cfg, mux_reg);
+
+ return 0;
+}
+
+/*!
+ * Request ownership for an IO pin. This function has to be the first one
+ * being called before that pin is used. The caller has to check the
+ * return value to make sure it returns 0.
+ *
+ * @param pin a name defined by \b iomux_pin_name_t
+ * @param cfg an input function as defined in \b #iomux_pin_cfg_t
+ *
+ * @return 0 if successful; Non-zero otherwise
+ */
+int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+ int ret = iomux_config_mux(pin, cfg);
+ return ret;
+}
+
+/*!
+ * Release ownership for an IO pin
+ *
+ * @param pin a name defined by \b iomux_pin_name_t
+ * @param cfg an input function as defined in \b #iomux_pin_cfg_t
+ */
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+}
+
+/*!
+ * This function configures the pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param config the ORed value of elements defined in \b #iomux_pad_config_t
+ */
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
+{
+ u32 pad_reg = _get_pad_reg(pin);
+ writel(config, pad_reg);
+}
+
+unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
+{
+ u32 pad_reg = _get_pad_reg(pin);
+ return readl(pad_reg);
+}
+/*!
+ * This function configures input path.
+ *
+ * @param input index of input select register as defined in \b
+ * #iomux_input_select_t
+ * @param config the binary value of elements defined in \b
+ * #iomux_input_config_t
+ */
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
+{
+ u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
+
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
+ if (input == MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT)
+ input -= 4;
+ else if (input ==
+ MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT)
+ input -= 3;
+ else if (input >= MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT)
+ input -= 2;
+ else if (input >=
+ MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT)
+ input -= 5;
+ else if (input >=
+ MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT)
+ input -= 3;
+ else if (input >= MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT)
+ input -= 2;
+ else if (input >= MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT)
+ input -= 1;
+
+ reg += INPUT_CTL_START_TO1;
+ } else {
+ reg += INPUT_CTL_START;
+ }
+
+ writel(config, reg);
+}
diff --git a/cpu/arm_cortexa8/mx51/serial.c b/cpu/arm_cortexa8/mx51/serial.c
new file mode 100644
index 0000000..580ac13
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/serial.c
@@ -0,0 +1,223 @@
+/*
+ * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#ifdef CONFIG_SERIAL
+#define SERIAL_BASE CONFIG_SERIAL
+
+#ifdef CONFIG_SERIAL_MULTI
+#error "CONFIG_SERIAL_MULTI can not exist with CONFIG_SERIAL"
+#endif
+
+#include <asm/arch/mx51.h>
+
+/* Register definitions */
+#define URXD 0x0 /* Receiver Register */
+#define UTXD 0x40 /* Transmitter Register */
+#define UCR1 0x80 /* Control Register 1 */
+#define UCR2 0x84 /* Control Register 2 */
+#define UCR3 0x88 /* Control Register 3 */
+#define UCR4 0x8c /* Control Register 4 */
+#define UFCR 0x90 /* FIFO Control Register */
+#define USR1 0x94 /* Status Register 1 */
+#define USR2 0x98 /* Status Register 2 */
+#define UESC 0x9c /* Escape Character Register */
+#define UTIM 0xa0 /* Escape Timer Register */
+#define UBIR 0xa4 /* BRM Incremental Register */
+#define UBMR 0xa8 /* BRM Modulator Register */
+#define UBRC 0xac /* Baud Rate Count Register */
+#define UTS 0xb4 /* UART Test Register (mx31) */
+
+/* UART Control Register Bit Fields.*/
+#define URXD_CHARRDY (1<<15)
+#define URXD_ERR (1<<14)
+#define URXD_OVRRUN (1<<13)
+#define URXD_FRMERR (1<<12)
+#define URXD_BRK (1<<11)
+#define URXD_PRERR (1<<10)
+#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
+#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
+#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
+#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
+#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
+#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
+#define UCR1_IREN (1<<7) /* Infrared interface enable */
+#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
+#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
+#define UCR1_SNDBRK (1<<4) /* Send break */
+#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
+#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
+#define UCR1_DOZE (1<<1) /* Doze */
+#define UCR1_UARTEN (1<<0) /* UART enabled */
+#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
+#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
+#define UCR2_CTSC (1<<13) /* CTS pin control */
+#define UCR2_CTS (1<<12) /* Clear to send */
+#define UCR2_ESCEN (1<<11) /* Escape enable */
+#define UCR2_PREN (1<<8) /* Parity enable */
+#define UCR2_PROE (1<<7) /* Parity odd/even */
+#define UCR2_STPB (1<<6) /* Stop */
+#define UCR2_WS (1<<5) /* Word size */
+#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
+#define UCR2_TXEN (1<<2) /* Transmitter enabled */
+#define UCR2_RXEN (1<<1) /* Receiver enabled */
+#define UCR2_SRST (1<<0) /* SW reset */
+#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
+#define UCR3_PARERREN (1<<12) /* Parity enable */
+#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
+#define UCR3_DSR (1<<10) /* Data set ready */
+#define UCR3_DCD (1<<9) /* Data carrier detect */
+#define UCR3_RI (1<<8) /* Ring indicator */
+#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
+#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
+#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
+#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
+#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
+#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
+#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
+#define UCR3_BPEN (1<<0) /* Preset registers enable */
+#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
+#define UCR4_INVR (1<<9) /* Inverted infrared reception */
+#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
+#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
+#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
+#define UCR4_IRSC (1<<5) /* IR special case */
+#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
+#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
+#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
+#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
+#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
+#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
+#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
+#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
+#define USR1_RTSS (1<<14) /* RTS pin status */
+#define USR1_TRDY (1<<13)/* Transmitter ready interrupt/dma flag */
+#define USR1_RTSD (1<<12) /* RTS delta */
+#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
+#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
+#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
+#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
+#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
+#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
+#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
+#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
+#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
+#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
+#define USR2_IDLE (1<<12) /* Idle condition */
+#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
+#define USR2_WAKE (1<<7) /* Wake */
+#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
+#define USR2_TXDC (1<<3) /* Transmitter complete */
+#define USR2_BRCD (1<<2) /* Break condition */
+#define USR2_ORE (1<<1) /* Overrun error */
+#define USR2_RDR (1<<0) /* Recv data ready */
+#define UTS_FRCPERR (1<<13) /* Force parity error */
+#define UTS_LOOP (1<<12) /* Loop tx and rx */
+#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
+#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
+#define UTS_TXFULL (1<<4) /* TxFIFO full */
+#define UTS_RXFULL (1<<3) /* RxFIFO full */
+#define UTS_SOFTRST (1<<0) /* Software reset */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void serial_setbrg(void)
+{
+ u32 clk = mxc_get_clock(MXC_UART_CLK);
+
+ if (!gd->baudrate)
+ gd->baudrate = CONFIG_BAUDRATE;
+
+ /* divide input clock by 2 */
+ __raw_writel(0x4 << 7, SERIAL_BASE + UFCR);
+ __raw_writel(0xF, SERIAL_BASE + UBIR);
+ __raw_writel(clk / (2 * gd->baudrate), SERIAL_BASE + UBMR);
+}
+
+int serial_getc(void)
+{
+ while (__raw_readl(SERIAL_BASE + UTS) & UTS_RXEMPTY)
+ ;
+ return __raw_readl(SERIAL_BASE + URXD);
+}
+
+void serial_putc(const char c)
+{
+ __raw_writel(c, SERIAL_BASE + UTXD);
+
+ /* wait for transmitter to be ready */
+ while (!(__raw_readl(SERIAL_BASE + UTS) & UTS_TXEMPTY))
+ ;
+
+ /* If \n, also do \r */
+ if (c == '\n')
+ serial_putc('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+int serial_tstc(void)
+{
+ /* If receive fifo is empty, return false */
+ if (__raw_readl(SERIAL_BASE + UTS) & UTS_RXEMPTY)
+ return 0;
+ return 1;
+}
+
+void serial_puts(const char *s)
+{
+ while (*s)
+ serial_putc(*s++);
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int serial_init(void)
+{
+ __raw_writel(0x0, SERIAL_BASE + UCR1);
+ __raw_writel(0x0, SERIAL_BASE + UCR2);
+
+ while (!(__raw_readl(SERIAL_BASE + UCR2) & UCR2_SRST))
+ ;
+
+ __raw_writel(0x0704, SERIAL_BASE + UCR3);
+ __raw_writel(0x8000, SERIAL_BASE + UCR4);
+ __raw_writel(0x002B, SERIAL_BASE + UESC);
+ __raw_writel(0x0, SERIAL_BASE + UTIM);
+
+ __raw_writel(0x0, SERIAL_BASE + UTS);
+
+ serial_setbrg();
+
+ __raw_writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
+ SERIAL_BASE + UCR2);
+
+ __raw_writel(UCR1_UARTEN, SERIAL_BASE + UCR1);
+
+ return 0;
+}
+
+#endif /* CONFIG_SERIAL */
diff --git a/cpu/arm_cortexa8/mx51/soc.c b/cpu/arm_cortexa8/mx51/soc.c
new file mode 100644
index 0000000..cd8ce9d
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/soc.c
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx51.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include "crm_regs.h"
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ printf("CPU: Freescale i.MX51 family %d.%dV at %d MHz\n",
+ (get_board_rev() & 0xFF) >> 4,
+ (get_board_rev() & 0xF),
+ __get_mcu_main_clk() / 1000000);
+ mxc_show_clocks();
+ return 0;
+}
+#endif
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+#if defined(CONFIG_MXC_FEC)
+extern int mxc_fec_initialize(bd_t *bis);
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+#if defined(CONFIG_MXC_FEC)
+ rc = mxc_fec_initialize(bis);
+#endif
+
+ return rc;
+}
+
+void reset_cpu(ulong addr)
+{
+ __raw_writew(4, WDOG1_BASE_ADDR);
+}
diff --git a/cpu/arm_cortexa8/mx51/timer.c b/cpu/arm_cortexa8/mx51/timer.c
new file mode 100644
index 0000000..5201768
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/timer.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx51.h>
+
+/* General purpose timers registers */
+#define GPTCR GPT1_BASE_ADDR /* Control register */
+#define GPTPR (GPT1_BASE_ADDR + 0x4) /* Prescaler register */
+#define GPTSR (GPT1_BASE_ADDR + 0x8) /* Status register */
+#define GPTCNT (GPT1_BASE_ADDR + 0x24) /* Counter register */
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR (1<<15) /* Software reset */
+#define GPTCR_FRR (1<<9) /* Freerun / restart */
+#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
+#define GPTCR_TEN (1) /* Timer enable */
+
+int timer_init(void)
+{
+ int i;
+
+ /* setup GP Timer 1 */
+ __raw_writel(GPTCR_SWR, GPTCR);
+ for (i = 0; i < 100; i++)
+ __raw_writel(0, GPTCR); /* We have no udelay by now */
+
+ __raw_writel(0, GPTPR); /* 32Khz */
+
+ /* Freerun Mode, PERCLK1 input */
+ i = __raw_readl(GPTCR);
+ __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, GPTCR);
+ return 0;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+void reset_timer_masked(void)
+{
+ __raw_writel(0, GPTCR);
+ /* Freerun Mode, PERCLK1 input */
+ __raw_writel(GPTCR_CLKSOURCE_32 | GPTCR_TEN, GPTCR);
+}
+
+ulong get_timer_masked(void)
+{
+ ulong val = __raw_readl(GPTCNT);
+ return val;
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay(unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ /* if "big" number, spread normalization to seconds */
+ if (usec >= 1000) {
+ /* start to normalize for usec to ticks per sec */
+ tmo = usec / 1000;
+ /* find number of "ticks" to wait to achieve target */
+ tmo *= CONFIG_SYS_HZ;
+ tmo /= 1000; /* finish normalize. */
+ } else {/* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CONFIG_SYS_HZ;
+ tmo /= (1000 * 1000);
+ }
+
+ tmp = get_timer(0); /* get current timestamp */
+ /* if setting this forward will roll time stamp */
+ if ((tmo + tmp + 1) < tmp)
+ /* reset "advancing" timestamp to 0, set lastinc value */
+ reset_timer_masked();
+ else /* else, set advancing stamp wake up time */
+ tmo += tmp;
+ while (get_timer_masked() < tmo) /* loop till event */
+ /*NOP*/;
+}
diff --git a/include/asm-arm/arch-mx51/iomux.h b/include/asm-arm/arch-mx51/iomux.h
new file mode 100644
index 0000000..fa02984
--- /dev/null
+++ b/include/asm-arm/arch-mx51/iomux.h
@@ -0,0 +1,240 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later@the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MACH_MX51_IOMUX_H__
+#define __MACH_MX51_IOMUX_H__
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx51.h>
+#include <asm/arch/mx51_pins.h>
+
+/*!
+ * @file iomux.h
+ *
+ * @brief I/O Muxing control definitions and functions
+ *
+ * @ingroup GPIO_MX51
+ */
+
+typedef unsigned int iomux_pin_name_t;
+
+/*!
+ * various IOMUX output functions
+ */
+typedef enum iomux_config {
+ IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
+ IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
+ IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
+ IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
+ IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
+ IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
+ IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
+ IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
+ IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
+ IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
+} iomux_pin_cfg_t;
+
+/*!
+ * various IOMUX pad functions
+ */
+typedef enum iomux_pad_config {
+ PAD_CTL_SRE_SLOW = 0x0 << 0,
+ PAD_CTL_SRE_FAST = 0x1 << 0,
+ PAD_CTL_DRV_LOW = 0x0 << 1,
+ PAD_CTL_DRV_MEDIUM = 0x1 << 1,
+ PAD_CTL_DRV_HIGH = 0x2 << 1,
+ PAD_CTL_DRV_MAX = 0x3 << 1,
+ PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,
+ PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
+ PAD_CTL_100K_PD = 0x0 << 4,
+ PAD_CTL_47K_PU = 0x1 << 4,
+ PAD_CTL_100K_PU = 0x2 << 4,
+ PAD_CTL_22K_PU = 0x3 << 4,
+ PAD_CTL_PUE_KEEPER = 0x0 << 6,
+ PAD_CTL_PUE_PULL = 0x1 << 6,
+ PAD_CTL_PKE_NONE = 0x0 << 7,
+ PAD_CTL_PKE_ENABLE = 0x1 << 7,
+ PAD_CTL_HYS_NONE = 0x0 << 8,
+ PAD_CTL_HYS_ENABLE = 0x1 << 8,
+ PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,
+ PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
+ PAD_CTL_DRV_VOT_LOW = 0x0 << 13,
+ PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
+} iomux_pad_config_t;
+
+/*!
+ * various IOMUX input select register index
+ */
+typedef enum iomux_input_select {
+ MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+ MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+ MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
+ MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
+ MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
+ MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
+ MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
+ MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
+ MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
+ MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
+ MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
+ MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
+ MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
+ MUX_IN_FEC_FEC_COL_SELECT_INPUT,
+ MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
+ MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
+ MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
+ MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
+ MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
+ MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
+ MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
+ MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
+
+ MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
+
+ MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
+
+ MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
+ MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
+ MUX_INPUT_NUM_MUX,
+} iomux_input_select_t;
+
+/*!
+ * various IOMUX input functions
+ */
+typedef enum iomux_input_config {
+ INPUT_CTL_PATH0 = 0x0,
+ INPUT_CTL_PATH1,
+ INPUT_CTL_PATH2,
+ INPUT_CTL_PATH3,
+ INPUT_CTL_PATH4,
+ INPUT_CTL_PATH5,
+ INPUT_CTL_PATH6,
+ INPUT_CTL_PATH7,
+} iomux_input_config_t;
+
+/*!
+ * Request ownership for an IO pin. This function has to be the first one
+ * being called before that pin is used. The caller has to check the
+ * return value to make sure it returns 0.
+ *
+ * @param pin a name defined by \b iomux_pin_name_t
+ * @param config config as defined in \b #iomux_pin_ocfg_t
+ *
+ * @return 0 if successful; Non-zero otherwise
+ */
+int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
+
+/*!
+ * Release ownership for an IO pin
+ *
+ * @param pin a name defined by \b iomux_pin_name_t
+ * @param config config as defined in \b #iomux_pin_ocfg_t
+ */
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
+
+/*!
+ * This function configures the pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param config the ORed value of elements defined in
+ * \b #iomux_pad_config_t
+ */
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
+
+/*!
+ * This function gets the current pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @return current pad value
+ */
+unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
+
+/*!
+ * This function configures input path.
+ *
+ * @param input index of input select register as defined in
+ * \b #iomux_input_select_t
+ * @param config the binary value of elements defined in
+ * \b #iomux_input_config_t
+ */
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
+
+#endif /* __MACH_MX51_IOMUX_H__ */
diff --git a/include/asm-arm/arch-mx51/mx51.h b/include/asm-arm/arch-mx51/mx51.h
new file mode 100644
index 0000000..4532a10
--- /dev/null
+++ b/include/asm-arm/arch-mx51/mx51.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_MX51_H__
+#define __ASM_ARCH_MXC_MX51_H__
+
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
+/*
+ * Graphics Memory of GPU
+ */
+#define GPU_BASE_ADDR 0x20000000
+#define GPU_CTRL_BASE_ADDR 0x30000000
+#define IPU_CTRL_BASE_ADDR 0x40000000
+/*
+ * Debug
+ */
+#define DEBUG_BASE_ADDR 0x60000000
+#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
+#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
+#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
+#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
+#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
+#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
+#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
+#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR 0x70000000
+
+#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
+#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
+#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
+#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
+#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
+#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
+#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
+#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR 0x73F00000
+
+#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
+#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
+#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
+#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
+#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
+#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
+#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
+#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
+#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
+#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
+#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
+#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
+#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
+#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
+#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
+#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
+#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
+#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
+#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
+#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR 0x83F00000
+
+#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
+#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
+#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
+#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
+#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
+#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
+#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
+#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
+#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
+#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
+#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
+#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
+#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
+#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
+#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
+#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
+#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
+#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
+#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
+#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
+#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
+#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
+#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
+#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
+#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
+#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
+#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
+#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
+#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
+#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
+#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
+#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
+
+#define TZIC_BASE_ADDR 0x8FFFC000
+
+/*
+ * Memory regions and CS
+ */
+#define CSD0_BASE_ADDR 0x90000000
+#define CSD1_BASE_ADDR 0xA0000000
+#define CS0_BASE_ADDR 0xB0000000
+#define CS1_BASE_ADDR 0xB8000000
+#define CS2_BASE_ADDR 0xC0000000
+#define CS3_BASE_ADDR 0xC8000000
+#define CS4_BASE_ADDR 0xCC000000
+#define CS5_BASE_ADDR 0xCE000000
+
+/*
+ * NFC
+ */
+#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */
+
+/*!
+ * defines for SPBA modules
+ */
+#define SPBA_SDHC1 0x04
+#define SPBA_SDHC2 0x08
+#define SPBA_UART3 0x0C
+#define SPBA_CSPI1 0x10
+#define SPBA_SSI2 0x14
+#define SPBA_SDHC3 0x20
+#define SPBA_SDHC4 0x24
+#define SPBA_SPDIF 0x28
+#define SPBA_ATA 0x30
+#define SPBA_SLIM 0x34
+#define SPBA_HSI2C 0x38
+#define SPBA_CTRL 0x3C
+
+/*
+ * Interrupt numbers
+ */
+#define MXC_INT_BASE 0
+#define MXC_INT_RESV0 0
+#define MXC_INT_MMC_SDHC1 1
+#define MXC_INT_MMC_SDHC2 2
+#define MXC_INT_MMC_SDHC3 3
+#define MXC_INT_MMC_SDHC4 4
+#define MXC_INT_RESV5 5
+#define MXC_INT_SDMA 6
+#define MXC_INT_IOMUX 7
+#define MXC_INT_NFC 8
+#define MXC_INT_VPU 9
+#define MXC_INT_IPU_ERR 10
+#define MXC_INT_IPU_SYN 11
+#define MXC_INT_GPU 12
+#define MXC_INT_RESV13 13
+#define MXC_INT_USB_H1 14
+#define MXC_INT_EMI 15
+#define MXC_INT_USB_H2 16
+#define MXC_INT_USB_H3 17
+#define MXC_INT_USB_OTG 18
+#define MXC_INT_SAHARA_H0 19
+#define MXC_INT_SAHARA_H1 20
+#define MXC_INT_SCC_SMN 21
+#define MXC_INT_SCC_STZ 22
+#define MXC_INT_SCC_SCM 23
+#define MXC_INT_SRTC_NTZ 24
+#define MXC_INT_SRTC_TZ 25
+#define MXC_INT_RTIC 26
+#define MXC_INT_CSU 27
+#define MXC_INT_SLIM_B 28
+#define MXC_INT_SSI1 29
+#define MXC_INT_SSI2 30
+#define MXC_INT_UART1 31
+#define MXC_INT_UART2 32
+#define MXC_INT_UART3 33
+#define MXC_INT_RESV34 34
+#define MXC_INT_RESV35 35
+#define MXC_INT_CSPI1 36
+#define MXC_INT_CSPI2 37
+#define MXC_INT_CSPI 38
+#define MXC_INT_GPT 39
+#define MXC_INT_EPIT1 40
+#define MXC_INT_EPIT2 41
+#define MXC_INT_GPIO1_INT7 42
+#define MXC_INT_GPIO1_INT6 43
+#define MXC_INT_GPIO1_INT5 44
+#define MXC_INT_GPIO1_INT4 45
+#define MXC_INT_GPIO1_INT3 46
+#define MXC_INT_GPIO1_INT2 47
+#define MXC_INT_GPIO1_INT1 48
+#define MXC_INT_GPIO1_INT0 49
+#define MXC_INT_GPIO1_LOW 50
+#define MXC_INT_GPIO1_HIGH 51
+#define MXC_INT_GPIO2_LOW 52
+#define MXC_INT_GPIO2_HIGH 53
+#define MXC_INT_GPIO3_LOW 54
+#define MXC_INT_GPIO3_HIGH 55
+#define MXC_INT_GPIO4_LOW 56
+#define MXC_INT_GPIO4_HIGH 57
+#define MXC_INT_WDOG1 58
+#define MXC_INT_WDOG2 59
+#define MXC_INT_KPP 60
+#define MXC_INT_PWM1 61
+#define MXC_INT_I2C1 62
+#define MXC_INT_I2C2 63
+#define MXC_INT_HS_I2C 64
+#define MXC_INT_RESV65 65
+#define MXC_INT_RESV66 66
+#define MXC_INT_SIM_IPB 67
+#define MXC_INT_SIM_DAT 68
+#define MXC_INT_IIM 69
+#define MXC_INT_ATA 70
+#define MXC_INT_CCM1 71
+#define MXC_INT_CCM2 72
+#define MXC_INT_GPC1 73
+#define MXC_INT_GPC2 74
+#define MXC_INT_SRC 75
+#define MXC_INT_NM 76
+#define MXC_INT_PMU 77
+#define MXC_INT_CTI_IRQ 78
+#define MXC_INT_CTI1_TG0 79
+#define MXC_INT_CTI1_TG1 80
+#define MXC_INT_MCG_ERR 81
+#define MXC_INT_MCG_TMR 82
+#define MXC_INT_MCG_FUNC 83
+#define MXC_INT_RESV84 84
+#define MXC_INT_RESV85 85
+#define MXC_INT_RESV86 86
+#define MXC_INT_FEC 87
+#define MXC_INT_OWIRE 88
+#define MXC_INT_CTI1_TG2 89
+#define MXC_INT_SJC 90
+#define MXC_INT_SPDIF 91
+#define MXC_INT_TVE 92
+#define MXC_INT_FIRI 93
+#define MXC_INT_PWM2 94
+#define MXC_INT_SLIM_EXP 95
+#define MXC_INT_SSI3 96
+#define MXC_INT_RESV97 97
+#define MXC_INT_CTI1_TG3 98
+#define MXC_INT_SMC_RX 99
+#define MXC_INT_VPU_IDLE 100
+#define MXC_INT_RESV101 101
+#define MXC_INT_GPU_IDLE 102
+
+#define MXC_MAX_INT_LINES 128
+
+#define MXC_GPIO_INT_BASE (MXC_MAX_INT_LINES)
+
+/*!
+ * Number of GPIO port as defined in the IC Spec
+ */
+#define GPIO_PORT_NUM 4
+/*!
+ * Number of GPIO pins per port
+ */
+#define GPIO_NUM_PIN 32
+
+#define MXC_GPIO_SPLIT_IRQ_2
+
+#define IIM_SREV 0x24
+#define ROM_SI_REV 0x48
+
+#define NFC_BUF_SIZE 0x1000
+
+/* WEIM registers */
+#define CSGCR1 0x00
+#define CSGCR2 0x04
+#define CSRCR1 0x08
+#define CSRCR2 0x0C
+#define CSWCR1 0x10
+
+/* M4IF */
+#define M4IF_FBPM0 0x40
+#define M4IF_FIDBP 0x48
+
+/* ESDCTL */
+#define ESDCTL_ESDCTL0 0x00
+#define ESDCTL_ESDCFG0 0x04
+#define ESDCTL_ESDCTL1 0x08
+#define ESDCTL_ESDCFG1 0x0C
+#define ESDCTL_ESDMISC 0x10
+#define ESDCTL_ESDSCR 0x14
+#define ESDCTL_ESDCDLY1 0x20
+#define ESDCTL_ESDCDLY2 0x24
+#define ESDCTL_ESDCDLY3 0x28
+#define ESDCTL_ESDCDLY4 0x2C
+#define ESDCTL_ESDCDLY5 0x30
+#define ESDCTL_ESDCDLYGD 0x34
+
+/* CCM */
+#define CLKCTL_CCR 0x00
+#define CLKCTL_CCDR 0x04
+#define CLKCTL_CSR 0x08
+#define CLKCTL_CCSR 0x0C
+#define CLKCTL_CACRR 0x10
+#define CLKCTL_CBCDR 0x14
+#define CLKCTL_CBCMR 0x18
+#define CLKCTL_CSCMR1 0x1C
+#define CLKCTL_CSCMR2 0x20
+#define CLKCTL_CSCDR1 0x24
+#define CLKCTL_CS1CDR 0x28
+#define CLKCTL_CS2CDR 0x2C
+#define CLKCTL_CDCDR 0x30
+#define CLKCTL_CHSCCDR 0x34
+#define CLKCTL_CSCDR2 0x38
+#define CLKCTL_CSCDR3 0x3C
+#define CLKCTL_CSCDR4 0x40
+#define CLKCTL_CWDR 0x44
+#define CLKCTL_CDHIPR 0x48
+#define CLKCTL_CDCR 0x4C
+#define CLKCTL_CTOR 0x50
+#define CLKCTL_CLPCR 0x54
+#define CLKCTL_CISR 0x58
+#define CLKCTL_CIMR 0x5C
+#define CLKCTL_CCOSR 0x60
+#define CLKCTL_CGPR 0x64
+#define CLKCTL_CCGR0 0x68
+#define CLKCTL_CCGR1 0x6C
+#define CLKCTL_CCGR2 0x70
+#define CLKCTL_CCGR3 0x74
+#define CLKCTL_CCGR4 0x78
+#define CLKCTL_CCGR5 0x7C
+#define CLKCTL_CCGR6 0x80
+#define CLKCTL_CMEOR 0x84
+
+/* DPLL */
+#define PLL_DP_CTL 0x00
+#define PLL_DP_CONFIG 0x04
+#define PLL_DP_OP 0x08
+#define PLL_DP_MFD 0x0C
+#define PLL_DP_MFN 0x10
+#define PLL_DP_MFNMINUS 0x14
+#define PLL_DP_MFNPLUS 0x18
+#define PLL_DP_HFS_OP 0x1C
+#define PLL_DP_HFS_MFD 0x20
+#define PLL_DP_HFS_MFN 0x24
+#define PLL_DP_TOGC 0x28
+#define PLL_DP_DESTAT 0x2C
+
+/* Assuming 24MHz input clock with doubler ON */
+/* MFI PDF */
+#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
+#define DP_MFD_850 (48 - 1)
+#define DP_MFN_850 41
+
+#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
+#define DP_MFD_800 (3 - 1)
+#define DP_MFN_800 1
+
+#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
+#define DP_MFD_700 (24 - 1)
+#define DP_MFN_700 7
+
+#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
+#define DP_MFD_665 (96 - 1)
+#define DP_MFN_665 89
+
+#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
+#define DP_MFD_532 (24 - 1)
+#define DP_MFN_532 13
+
+#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
+#define DP_MFD_400 (3 - 1)
+#define DP_MFN_400 1
+
+#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+#define DP_MFD_216 (4 - 1)
+#define DP_MFN_216 3
+
+#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_1 0x11
+#define CHIP_REV_2_0 0x20
+#define CHIP_REV_2_5 0x120
+
+#define BOARD_REV_1_0 0x0
+#define BOARD_REV_2_0 0x1
+
+#ifndef __ASSEMBLER__
+
+enum mxc_clock {
+MXC_ARM_CLK = 0,
+MXC_AHB_CLK,
+MXC_IPG_CLK,
+MXC_IPG_PERCLK,
+MXC_UART_CLK,
+MXC_CSPI_CLK,
+MXC_FEC_CLK,
+};
+
+extern unsigned int mxc_get_clock(enum mxc_clock clk);
+extern unsigned int get_board_rev(void);
+extern int is_soc_rev(int rev);
+
+#endif /* __ASSEMBLER__*/
+
+#endif /* __ASM_ARCH_MXC_MX51_H__ */
diff --git a/include/asm-arm/arch-mx51/mx51_pins.h b/include/asm-arm/arch-mx51/mx51_pins.h
new file mode 100644
index 0000000..63fdd8c
--- /dev/null
+++ b/include/asm-arm/arch-mx51/mx51_pins.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
+#define __ASM_ARCH_MXC_MX51_PINS_H__
+
+/*!
+ * @file arch-mxc/mx51_pins.h
+ *
+ * @brief MX51 I/O Pin List
+ *
+ * @ingroup GPIO_MX51
+ */
+
+#ifndef __ASSEMBLY__
+
+/*!
+ * @name IOMUX/PAD Bit field definitions
+ */
+
+/*! @{ */
+
+/*!
+ * In order to identify pins more effectively, each mux-controlled pin's
+ * enumerated value is constructed in the following way:
+ *
+ * -------------------------------------------------------------------
+ * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
+ * -------------------------------------------------------------------
+ * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
+ * -------------------------------------------------------------------
+ *
+ * Bit 0 to 9 contains MUX_I used to identify the register
+ * offset (0-based. base is IOMUX_module_base) defined in the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
+ * similar field definitions are used for the pad control register.
+ * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
+ * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
+ * It means the mux control register is@register offset 0x28. The pad control
+ * register offset is: 0x250 and also occupy the least significant bits
+ * within the register.
+ */
+
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * MUX control register offset
+ */
+#define MUX_I 0
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * PAD control register offset
+ */
+#define PAD_I 10
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent which
+ * mux mode is for GPIO (0-based)
+ */
+#define GPIO_I 21
+
+#define MUX_IO_P 29
+#define MUX_IO_I 24
+#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
+ GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
+ ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
+#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
+#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
+#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
+
+#define NON_GPIO_PORT 0x7
+#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
+#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
+#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
+
+#define NON_MUX_I PIN_TO_MUX_MASK
+#define MUX_I_START 0x001C
+#define PAD_I_START 0x3F0
+#define INPUT_CTL_START 0x8C4
+#define INPUT_CTL_START_TO1 0x928
+#define MUX_I_END (PAD_I_START - 4)
+
+#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
+ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
+ ((mi) << MUX_I) | \
+ ((pi - PAD_I_START) << PAD_I) | \
+ ((ga) << GPIO_I))
+
+#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
+ _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
+
+#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
+ _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
+
+#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
+#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
+#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
+#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
+
+/*! @} End IOMUX/PAD Bit field definitions */
+
+/*!
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+enum iomux_pins {
+ MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
+ MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
+ MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
+ MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
+ MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
+ MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
+ MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
+ MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
+ MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
+ MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
+ MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
+ MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
+ MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
+ MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
+ MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
+ MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
+ MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
+ MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
+ MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
+ MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
+ MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
+ MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
+ MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
+ MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
+ MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
+ MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
+ MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
+ MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
+ MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
+ MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
+ MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
+ MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
+ MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
+ MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
+ MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
+ MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
+ MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
+ MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
+ MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
+ MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
+ MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
+ MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
+ MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
+ MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
+ MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
+ MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
+ MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
+ MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
+ MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
+ MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
+ MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
+ MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
+ MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
+ MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
+ MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
+ MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
+ MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
+ MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
+ MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
+ MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
+ MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
+ MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
+ MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
+ MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
+ MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
+ MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
+ MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
+ MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
+ MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
+ MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
+ MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
+ MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
+ MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
+ MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
+ MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
+ MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
+ MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
+ MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
+ MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
+ MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
+ MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
+ MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
+ MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
+ MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
+ MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
+ MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
+ MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
+ MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
+ MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
+ MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
+ MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
+ MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
+ MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
+ MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
+ MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
+ MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
+ MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
+ MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
+ MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
+ MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
+ MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
+ MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
+ MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
+ MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
+ MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
+ MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
+ MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
+ MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
+ MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
+ MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
+ MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
+ MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
+ MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
+ MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
+ MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
+ MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
+ MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
+ MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
+ MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
+ MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
+ MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
+ MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
+ MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
+ MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
+ MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
+ MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
+ MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
+ MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
+ MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
+ MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
+ MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
+ MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
+ MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
+ MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
+ MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
+ MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
+ MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
+ MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
+ MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
+ MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
+ MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
+ MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
+ MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
+ MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
+ MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
+ MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
+ MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
+ MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
+ MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
+ MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
+ MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
+ MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
+ MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
+ MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
+ MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
+ MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
+ MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
+ MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
+ MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
+ MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
+ MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
+ MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
+ MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
+ MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
+ MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
+ MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
+ MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
+ MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
+ MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
+ MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
+ MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
+ MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
+ MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
+ MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
+ MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
+ MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
+ MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
+ MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
+ MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
+ MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
+ MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
+ MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
+ MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
+ MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
+ MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
+ MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
+ MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
+ MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
+ MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
+ MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
+ MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
+ MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
+ MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
+ MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
+ MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
+ MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
+ MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
+ MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
+ MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
+ MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
+ MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
+ MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
+ MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
+ MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
+ MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
+ MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
+ MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
+ MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
+ MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
+ MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
+ MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
+ MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
+ MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
+ MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
+ MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
+ MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
+ MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
+ MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
+ MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
+ MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
+ MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
+ MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
+ MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
+ MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
+ MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
+ MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
+ MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
+ MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
+ MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
+ MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
+ MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
+ MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
+ MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
+ MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
+ MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
+ MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
+ MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
+ MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
+ MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
+ MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
+ MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
+ MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
+ MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
+ MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
+ MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
+ MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
+ MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
+ MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
+ MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
+ MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
+ MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
+ MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */
diff --git a/include/configs/imx51.h b/include/configs/imx51.h
new file mode 100644
index 0000000..f0def4e
--- /dev/null
+++ b/include/configs/imx51.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51-3Stack Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx51.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
+#define CONFIG_L2_OFF
+
+#define CONFIG_MXC 1
+#define CONFIG_MX51_BBG 1 /* in a mx51 */
+#define CONFIG_FLASH_HEADER 1
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#define CONFIG_FLASH_HEADER_BARKER 0xB1
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_MX51_HCLK_FREQ 24000000
+#define CONFIG_MX51_CLK32 32768
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define BOARD_LATE_INIT
+/*
+ * Disabled for now due to build problems under Debian and a significant
+ * increase in the final file size: 144260 vs. 109536 Bytes.
+ */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_DOS_PARTITION 1
+/*
+ * Hardware drivers
+ */
+#define CONFIG_SERIAL UART1_BASE_ADDR
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot_addr=0xa0000000\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+
+/*
+ * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "BBG U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ CONFIG_MX51_CLK32/* use 32kHz clock as source */
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+#if defined(CONFIG_CMD_SF)
+ #define CONFIG_FSL_ENV_IN_SF
+#elif defined(CONFIG_CMD_MMC)
+ #define CONFIG_FSL_ENV_IN_MMC
+#endif
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_IS_EMBEDDED 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+
+#endif /* __CONFIG_H */
--
1.6.0.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
2009-09-20 17:28 [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board gareatech at gmail.com
@ 2009-09-21 17:55 ` Magnus Lilja
2009-09-21 20:58 ` Fabio Estevam
[not found] ` <2f495dc80909221219n2f6f303dw478871aede988a7a@mail.gmail.com>
0 siblings, 2 replies; 15+ messages in thread
From: Magnus Lilja @ 2009-09-21 17:55 UTC (permalink / raw)
To: u-boot
Hi
I've scanned the patch briefly and have some comments below.
gareatech at gmail.com wrote:
> From: Fred Fan <fanyefeng@gmail.com>
>
> This patch just supports boot into u-boot from mmc or spi-nor flash.
> It just implements console, iomux and clock. There are no ethernet,
> nor-flash, mmc or other peripheral drivers.
>
> Sign-of-by: Fred.Fan <fanyefeng@gmail.com>
> Sign-of-by: Fred.Fan <r01011@freescale.com>
Should be 'Signed-off-by: FredFan <fanyefeng@gmail.com>'.
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 620604c..5fb1221 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -549,6 +549,10 @@ Fabio Estevam <Fabio.Estevam@freescale.com>
>
> mx31pdk i.MX31
>
> +Fred Fan <fanyefeng@gmail.com>
> +
> + imx51 i.MX51
> +
Is imx51 really the name of this board? Later on it looks like the name is MX51_BABBAGE.
> Peter Figuli <peposh@etc.sk>
>
> wepep250 xscale
> diff --git a/MAKEALL b/MAKEALL
> index edebaea..ed8c437 100755
> --- a/MAKEALL
> +++ b/MAKEALL
<snip>
> diff --git a/board/freescale/imx51/Makefile b/board/freescale/imx51/Makefile
> new file mode 100644
> index 0000000..fbd40f2
> --- /dev/null
> +++ b/board/freescale/imx51/Makefile
<snip>
> diff --git a/board/freescale/imx51/board-imx51.h b/board/freescale/imx51/board-imx51.h
> new file mode 100644
> index 0000000..7a2cae0
> --- /dev/null
> +++ b/board/freescale/imx51/board-imx51.h
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#ifndef __BOARD_FREESCALE_BOARD_IMX51_H__
> +#define __BOARD_FREESCALE_BOARD_IMX51_H__
> +
> +/*!
> + * @defgroup BRDCFG_MX51 Board Configuration Options
> + * @ingroup MSL_MX51
> + */
> +
> +/*!
> + * @file mx51_3stack/board-imx51.h
> + *
> + * @brief This file contains all the board level configuration options.
> + *
> + * It currently hold the options defined for MX51 3Stack Platform.
> + *
> + * @ingroup BRDCFG_IMX51
> + */
> +
> +/* CPLD offsets */
> +#define PBC_LED_CTRL (0x20000)
> +#define PBC_SB_STAT (0x20008)
> +#define PBC_ID_AAAA (0x20040)
> +#define PBC_ID_5555 (0x20048)
> +#define PBC_VERSION (0x20050)
> +#define PBC_ID_CAFE (0x20058)
> +#define PBC_INT_STAT (0x20010)
> +#define PBC_INT_MASK (0x20038)
> +#define PBC_INT_REST (0x20020)
> +#define PBC_SW_RESET (0x20060)
> +
> +/* LED switchs */
> +#define LED_SWITCH_REG 0x00
> +/* buttons */
> +#define SWITCH_BUTTONS_REG 0x08
> +/* status, interrupt */
> +#define INTR_STATUS_REG 0x10
> +#define INTR_MASK_REG 0x38
> +#define INTR_RESET_REG 0x20
> +/* magic word for debug CPLD */
> +#define MAGIC_NUMBER1_REG 0x40
> +#define MAGIC_NUMBER2_REG 0x48
> +/* CPLD code version */
> +#define CPLD_CODE_VER_REG 0x50
> +/* magic word for debug CPLD */
> +#define MAGIC_NUMBER3_REG 0x58
> +/* module reset register*/
> +#define MODULE_RESET_REG 0x60
> +/* CPU ID and Personality ID */
> +#define MCU_BOARD_ID_REG 0x68
> +
> +#endif /* __BOARD_FREESCALE_BOARD_IMX51_H__ */
> diff --git a/board/freescale/imx51/config.mk b/board/freescale/imx51/config.mk
> new file mode 100644
> index 0000000..d8b0f10
> --- /dev/null
> +++ b/board/freescale/imx51/config.mk
> @@ -0,0 +1,2 @@
> +LDSCRIPT = board/$(VENDOR)/$(BOARD)/u-boot.lds
> +TEXT_BASE = 0x97800000
> diff --git a/board/freescale/imx51/flash_header.S b/board/freescale/imx51/flash_header.S
> new file mode 100644
> index 0000000..6790679
> --- /dev/null
> +++ b/board/freescale/imx51/flash_header.S
> @@ -0,0 +1,113 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
I wouldn't mind a short description of what this file does and why it's needed.
> +#include <config.h>
> +#include <asm/arch/mx51.h>
> +#include "board-imx51.h"
> +
> +#ifdef CONFIG_FLASH_HEADER
> +#ifndef CONFIG_FLASH_HEADER_OFFSET
> +# error "Must define the offset of flash header"
> +#endif
> +#define MXC_DCD_ITEM(i, type, addr, val) \
> +dcd_node_##i: \
> + .word type ; \
> + .word addr ; \
> + .word val ; \
> +
> +.section ".text.flasheader", "x"
> + b _start
> + .org CONFIG_FLASH_HEADER_OFFSET
> +app_code_jump_v: .word _start
> +app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER
> +app_code_csf: .word 0
> +dcd_ptr_ptr: .word dcd_ptr
> +super_root_key: .word 0
> +dcd_ptr: .word dcd_array_start
> +app_dest_ptr: .word TEXT_BASE
> +dcd_array_start:
> +magic: .word 0xB17219E9
> +dcd_array_size: .word dcd_data_end - dcd_array_start - 8
> +/* DCD */
> +/* DDR2 IOMUX configuration */
> +MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
> +MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
> +MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
> +MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
> +MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
> +MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
> +MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
> +MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
> +MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
> +MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
> +MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
> +MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
> +MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
> +MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
> +MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
> +MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
> +MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
> +MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
> +/* Set drive strength to MAX */
> +MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6)
> +MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6)
> +MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6)
> +MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6)
> +/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
> +/* CAS=3, BL=4 */
> +MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
> +MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
> +MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
> +MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
> +MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
> +/* Init DRAM on CS0 */
> +MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
> +MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
> +MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
> +MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
> +MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
> +MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
> +MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
> +MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
> +MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
> +MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
> +MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
> +MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
> +/* Init DRAM on CS1 */
> +MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
> +MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
> +MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
> +MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
> +MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
> +MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
> +MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
> +MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
> +MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
> +MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
> +MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
> +MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
> +MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
> +MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
> +MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
> +MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
> +MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
> +dcd_data_end:
> +image_len: .word 0x100000
> +//image_len: .word _end - _start
> +#endif
> diff --git a/board/freescale/imx51/imx51.c b/board/freescale/imx51/imx51.c
> new file mode 100644
> index 0000000..f152c9a
> --- /dev/null
> +++ b/board/freescale/imx51/imx51.c
> @@ -0,0 +1,233 @@
> +/*
> + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
> + *
> + * (C) Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/mx51.h>
> +#include <asm/arch/mx51_pins.h>
> +#include <asm/arch/iomux.h>
> +#include <asm/errno.h>
> +#include <i2c.h>
> +#include "board-imx51.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static u32 system_rev;
> +u32 mx51_io_base_addr;
> +volatile u32 *esdhc_base_pointer;
> +
> +u32 get_board_rev(void)
> +{
> + return system_rev;
> +}
> +
> +static inline void setup_soc_rev(void)
> +{
> + int reg;
Add empty line after variable declarations? (makes the code more readable imo)
> + reg = __raw_readl(ROM_SI_REV);
> + switch (reg) {
> + case 0x02:
> + system_rev = 0x51000 | CHIP_REV_1_1;
> + break;
> + case 0x10:
> + if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) {
> + system_rev = 0x51000 | CHIP_REV_2_5;
> + } else {
> + system_rev = 0x51000 | CHIP_REV_2_0;
> + }
> + break;
> + default:
> + system_rev = 0x51000 | CHIP_REV_1_0;
Add a 'break;' to the default even though it's the last one.
> + }
> +}
> +
> +static inline void set_board_rev(int rev)
> +{
> + system_rev |= (rev & 0xF) << 8;
> +}
> +
> +inline int is_soc_rev(int rev)
> +{
> + return (system_rev & 0xFF) - rev;
> +}
> +
> +int dram_init(void)
> +{
> + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
> + return 0;
> +}
> +
> +static void setup_uart(void)
> +{
> + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
Add empty line after variable declarations.
> + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
> + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
> + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
> + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
> +}
> +
> +void setup_nfc(void)
> +{
> + /* Enable NFC IOMUX */
> + mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
> + mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
> +}
Since it's very likely that setup_nfc() and setup_uart() will be used in other i.MX51 boards as well it's a good idea to
place these functions in cpu/arm_cortexa8/mx51/devices.c (or something similar).
> +
> +static void setup_expio(void)
> +{
> + u32 reg;
Add empty line after variable declarations.
> + /* CS5 setup */
> + mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
> + writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1);
> + writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2);
> + /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
> + writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1);
> + /* APR = 0 */
> + writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2);
> + /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
> + * WCSA=0, WCSN=0
> + */
> + writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1);
> + if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) &&
> + (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) {
> + if (is_soc_rev(CHIP_REV_2_0) < 0) {
> + reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
> + reg = (reg & (~0x70000)) | 0x30000;
> + writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
> + /* make sure divider effective */
> + while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
> + ;
> + writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
> + }
> + mx51_io_base_addr = CS5_BASE_ADDR;
> + } else {
> + /* CS1 */
> + writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1);
> + writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2);
> + /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
> + writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1);
> + /* APR=0 */
> + writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2);
> + /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
> + * WEN=0, WCSA=0, WCSN=0
> + */
> + writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1);
> + mx51_io_base_addr = CS1_BASE_ADDR;
> + }
> +
> + /* Reset interrupt status reg */
> + writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
> + writew(0x00, mx51_io_base_addr + PBC_INT_REST);
> + writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
> +
> + /* Reset the XUART and Ethernet controllers */
> + reg = readw(mx51_io_base_addr + PBC_SW_RESET);
> + reg |= 0x9;
> + writew(reg, mx51_io_base_addr + PBC_SW_RESET);
> + reg &= ~0x9;
> + writew(reg, mx51_io_base_addr + PBC_SW_RESET);
> +}
> +
> +#ifdef CONFIG_NET_MULTI
> +
> +#if defined(CONFIG_DRIVER_SMC911X)
> +extern int smc911x_initialize(bd_t *bis);
> +#endif
> +int board_eth_init(bd_t *bis)
> +{
> + int rc = -ENODEV;
> +
> +#if defined(CONFIG_DRIVER_SMC911X)
> + rc = smc911x_initialize(bis);
> +#endif
> +
> + return rc;
> +}
> +#endif
> +
> +int board_init(void)
> +{
> + setup_soc_rev();
> +
> + gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE; /* board id for linux */
> + /* address of boot parameters */
> + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
> +
> + setup_uart();
> + setup_nfc();
> + setup_expio();
> + return 0;
> +}
> +
> +#ifdef BOARD_LATE_INIT
> +int board_late_init(void)
> +{
> + return 0;
> +}
> +#endif
> +
> +int checkboard(void)
> +{
> + printf("Board: MX51 BABBAGE ");
> +
> + if (system_rev & CHIP_REV_2_5) {
> + printf("2.5 [");
> + } else if (system_rev & CHIP_REV_2_0) {
> + printf("2.0 [");
> + } else if (system_rev & CHIP_REV_1_1) {
> + printf("1.1 [");
> + } else {
> + printf("1.0 [");
> + }
> +
> + switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
> + case 0x0001:
> + printf("POR");
> + break;
> + case 0x0009:
> + printf("RST");
> + break;
> + case 0x0010:
> + case 0x0011:
> + printf("WDOG");
> + break;
> + default:
> + printf("unknown");
> + }
> + printf("]\n");
> + return 0;
> +}
> +
> diff --git a/board/freescale/imx51/lowlevel_init.S b/board/freescale/imx51/lowlevel_init.S
> new file mode 100644
> index 0000000..e1296f8
> --- /dev/null
> +++ b/board/freescale/imx51/lowlevel_init.S
> @@ -0,0 +1,281 @@
> +/*
> + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
> + *
> + * (C) Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <asm/arch/mx51.h>
> +#include "board-imx51.h"
> +
> +/*
> + * return soc version
> + * 0x10: TO1
> + * 0x20: TO2
> + * 0x30: TO3
> + */
> +.macro check_soc_version ret, tmp
> +.endm
> +
> +/*
> + * L2CC Cache setup/invalidation/disable
> + */
> +.macro init_l2cc
> + /* reconfigure L2 cache aux control reg */
> + ldr r0, =0x03C000C4
> + mcr p15, 1, r0, c9, c0, 2
> +.endm /* init_l2cc */
> +
> +/* AIPS setup - Only setup MPROTx registers.
> + * The PACR default values are good.*/
> +.macro init_aips
> + /*
> + * Set all MPROTx to be non-bufferable, trusted for R/W,
> + * not forced to user-mode.
> + */
> + ldr r0, =AIPS1_BASE_ADDR
> + ldr r1, =0x77777777
> + str r1, [r0, #0x0]
> + str r1, [r0, #0x4]
> + ldr r0, =AIPS2_BASE_ADDR
> + str r1, [r0, #0x0]
> + str r1, [r0, #0x4]
> + /*
> + * Clear the on and off peripheral modules Supervisor Protect bit
> + * for SDMA to access them. Did not change the AIPS control registers
> + * (offset 0x20) access type
> + */
> +.endm /* init_aips */
> +
> +/* MAX (Multi-Layer AHB Crossbar Switch) setup */
> +.macro init_max
> +.endm /* init_max */
> +
> +/* M4IF setup */
> +.macro init_m4if
> + /* VPU and IPU given higher priority (0x4)
> + * IPU accesses with ID=0x1 given highest priority (=0xA)
> + */
> + ldr r0, =M4IF_BASE_ADDR
> +
> + ldr r1, =0x00000203
> + str r1, [r0, #0x40]
> +
> + ldr r1, =0x0
> + str r1, [r0, #0x44]
> +
> + ldr r1, =0x00120125
> + str r1, [r0, #0x9C]
> +
> + ldr r1, =0x001901A3
> + str r1, [r0, #0x48]
> +
> +/*
> + ldr r1, =0x00000a01
> + str r1, [r0, #0x48]
> + ldr r1, =0x00000404
> + str r1, [r0, #0x40]
> +*/
> +.endm /* init_m4if */
> +
> +/* To support 133MHz DDR */
> +.macro init_drive_strength
> +.endm /* init_drive_strength */
> +
> +/* CPLD on CS5 setup */
> +.macro init_debug_board
> +.endm /* init_debug_board */
Remove these two since they don't do anything?
> +
> +.macro setup_pll pll, freq
> + ldr r2, =\pll
> + ldr r1, =0x00001232
> + str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
> + mov r1, #0x2
> + str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
> +
> + str r3, [r2, #PLL_DP_OP]
> + str r3, [r2, #PLL_DP_HFS_OP]
> +
> + str r4, [r2, #PLL_DP_MFD]
> + str r4, [r2, #PLL_DP_HFS_MFD]
> +
> + str r5, [r2, #PLL_DP_MFN]
> + str r5, [r2, #PLL_DP_HFS_MFN]
> +
> + ldr r1, =0x00001232
> + str r1, [r2, #PLL_DP_CTL]
> +1: ldr r1, [r2, #PLL_DP_CTL]
> + ands r1, r1, #0x1
> + beq 1b
> +.endm
> +
> +.macro init_clock
> + ldr r0, =CCM_BASE_ADDR
> + mov r1, #0x00060000
> + str r1, [r0, #CLKCTL_CCDR]
> +
> + /* Switch ARM to step clock */
> + mov r1, #0x4
> + str r1, [r0, #CLKCTL_CCSR]
> +
> + mov r3, #DP_OP_800
> + mov r4, #DP_MFD_800
> + mov r5, #DP_MFN_800
> + setup_pll PLL1_BASE_ADDR
> + mov r3, #DP_OP_665
> + mov r4, #DP_MFD_665
> + mov r5, #DP_MFN_665
> + setup_pll PLL3_BASE_ADDR
> +
> + /* Switch peripheral to PLL 3 */
> + ldr r1, =0x0000D3C0
> + str r1, [r0, #CLKCTL_CBCMR]
> + ldr r1, =0x033B9145
> + str r1, [r0, #CLKCTL_CBCDR]
> + mov r3, #DP_OP_665
> + mov r4, #DP_MFD_665
> + mov r5, #DP_MFN_665
> + setup_pll PLL2_BASE_ADDR
> +
> + /* Switch peripheral to PLL2 */
> + ldr r1, =0x013B9145
> + str r1, [r0, #CLKCTL_CBCDR]
> + ldr r1, =0x0000E3C0
> + str r1, [r0, #CLKCTL_CBCMR]
> +
> + mov r3, #DP_OP_216
> + mov r4, #DP_MFD_216
> + mov r5, #DP_MFN_216
> + setup_pll PLL3_BASE_ADDR
> +
> + /* Set the platform clock dividers */
> + ldr r2, =ARM_BASE_ADDR
> + ldr r1, =0x00000725
> + str r1, [r2, #0x14]
> +
> + /* Switch ARM back to PLL 1 */
> + mov r1, #0
> + str r1, [r0, #CLKCTL_CCSR]
> + str r1, [r0, #CLKCTL_CACRR]
> +
> + /* Use lp_apm (24MHz) source for perclk */
> + mov r2, #0x48
> + ldr r2, [r0]
> + cmp r2, #0x10
> + ldrhs r1, =0x000020C2
> + ldrlo r1, =0x0000E3C2
> + str r1, [r0, #CLKCTL_CBCMR]
> + /* TO1.x emi = ahb, all perclk dividers are 1 since using 24MHz */
> + /* TO2.x ddr from PLL1, all perclk dividers are 1 since using 24MHz */
> + ldrhs r1, =0x59239100
> + ldrlo r1, =0x013D9100
> + strlo r1, [r0, #CLKCTL_CBCDR]
> +
> + /* use PLL2 for UART source, get 66.5MHz */
> + ldr r1, =0xA5A2A020
> + str r1, [r0, #CLKCTL_CSCMR1]
> + ldr r1, =0x00C30321
> + str r1, [r0, #CLKCTL_CSCDR1]
> +
> + /* make sure divider effective */
> +1: ldr r1, [r0, #CLKCTL_CDHIPR]
> + cmp r1, #0
> + bne 1b
> +
> + mov r1, #0x0
> + str r1, [r0, #CLKCTL_CCDR]
> +.endm
> +
> +.macro setup_wdog
> + ldr r0, =WDOG1_BASE_ADDR
> + mov r1, #0x30
> + strh r1, [r0]
> +.endm
> +
> +.section ".text.init", "x"
> +
> +.globl lowlevel_init
> +lowlevel_init:
> + /* Platform CHIP level init*/
> + ldr r0, =GPIO1_BASE_ADDR
> + ldr r1, [r0, #0x0]
> + orr r1, r1, #(1 << 23)
> + str r1, [r0, #0x0]
> + ldr r1, [r0, #0x4]
> + orr r1, r1, #(1 << 23)
> + str r1, [r0, #0x4]
What does the above code do? It seems to do something with a GPIO.
> +
> +#ifdef TURN_OFF_IMPRECISE_ABORT
> + mrs r0, cpsr
> + bic r0, r0, #0x100
> + msr cpsr, r0
> +#endif
> +
> + mrc 15, 0, r1, c1, c0, 0
> +
> +#ifndef BRANCH_PREDICTION_ENABLE
> + mrc 15, 0, r0, c1, c0, 1
> + bic r0, r0, #7
> + mcr 15, 0, r0, c1, c0, 1
> +#else
> + mrc 15, 0, r0, c1, c0, 1
> + orr r0, r0, #7
> + mcr 15, 0, r0, c1, c0, 1
> + orr r1, r1, #(1<<11)
> +#endif
> +
> +#ifdef UNALIGNED_ACCESS_ENABLE
> + orr r1, r1, #(1<<22)
> +#endif
> +
> +#ifdef LOW_INT_LATENCY_ENABLE
> + orr r1, r1, #(1<<21)
> +#endif
> + mcr 15, 0, r1, c1, c0, 0
> +
> + mov r0, #0
> +#ifdef BRANCH_PREDICTION_ENABLE
> + mcr 15, 0, r0, c15, c2, 4
> +#endif
The above #ifdef's should be documented/commented or removed if they're not needed.
> + mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
> +
> + init_l2cc
> +
> + init_aips
> +
> + init_max
> +
> + init_m4if
> +
> + init_drive_strength
> +
> + init_clock
> + init_debug_board
> + /*init_sdram*/
> +
> + /* return from mxc_nand_load */
> + /* r12 saved upper lr*/
> + mov pc, lr
> +
> +/* Board level setting value */
> +DDR_PERCHARGE_CMD: .word 0x04008008
> +DDR_REFRESH_CMD: .word 0x00008010
> +DDR_LMR1_W: .word 0x00338018
> +DDR_LMR_CMD: .word 0xB2220000
> +DDR_TIMING_W: .word 0xB02567A9
> +DDR_MISC_W: .word 0x000A0104
Parts of lowlevel_init.S uses space instead of tabs for indentation.
> diff --git a/board/freescale/imx51/u-boot.lds b/board/freescale/imx51/u-boot.lds
> new file mode 100644
> index 0000000..8cf619f
> --- /dev/null
> +++ b/board/freescale/imx51/u-boot.lds
<snip>
> diff --git a/cpu/arm_cortexa8/mx51/Makefile b/cpu/arm_cortexa8/mx51/Makefile
> new file mode 100644
> index 0000000..ee241ca
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/Makefile
<snip>
> diff --git a/cpu/arm_cortexa8/mx51/clock.c b/cpu/arm_cortexa8/mx51/clock.c
> new file mode 100644
> index 0000000..64f2c61
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/clock.c
> @@ -0,0 +1,229 @@
> +/*
> + * (C) Copyright 2007
> + * Sascha Hauer, Pengutronix
> + *
> + * (C) Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/mx51.h>
> +#include <asm/errno.h>
> +#include "crm_regs.h"
> +
> +enum pll_clocks {
> +PLL1_CLK = MXC_DPLL1_BASE,
> +PLL2_CLK = MXC_DPLL2_BASE,
> +PLL3_CLK = MXC_DPLL3_BASE,
Indent these?
> +};
> +
> +enum pll_sw_clocks {
> +PLL1_SW_CLK,
> +PLL2_SW_CLK,
> +PLL3_SW_CLK,
Indent these?
> +};
> +
> +static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
> +{
> + u32 mfi, mfn, mfd, pd;
> +
> + mfn = __raw_readl(pll + MXC_PLL_DP_MFN);
> + mfd = __raw_readl(pll + MXC_PLL_DP_MFD) + 1;
> + mfi = __raw_readl(pll + MXC_PLL_DP_OP);
> + pd = (mfi & 0xF) + 1;
> + mfi = (mfi >> 4) & 0xF;
> + mfi = (mfi >= 5) ? mfi : 5;
> +
> + return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
> +}
> +
> +u32 __get_mcu_main_clk(void)
> +{
> + u32 reg, freq;
Insert empty line after variable declarations for readability.
> + reg = (__raw_readl(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
> + MXC_CCM_CACRR_ARM_PODF_OFFSET;
> + freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> + return freq / (reg + 1);
> +}
> +
> +static u32 __get_periph_clk(void)
> +{
> + u32 reg;
Insert empty line after variable declarations for readability.
> + reg = __raw_readl(MXC_CCM_CBCDR);
> + if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
> + reg = __raw_readl(MXC_CCM_CBCMR);
> + switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
> + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
> + case 0:
> + return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> + case 1:
> + return __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
> + default:
> + return 0;
> + }
> + }
> + return __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
> +}
> +
> +static u32 __get_ipg_clk(void)
> +{
> + u32 ahb_podf, ipg_podf;
> +
> + ahb_podf = __raw_readl(MXC_CCM_CBCDR);
> + ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
> + MXC_CCM_CBCDR_IPG_PODF_OFFSET;
> + ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
> + MXC_CCM_CBCDR_AHB_PODF_OFFSET;
> + return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
> +}
> +
> +static u32 __get_ipg_per_clk(void)
> +{
> + u32 pred1, pred2, podf;
Insert empty line after variable declarations for readability.
> + if (__raw_readl(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
> + return __get_ipg_clk();
> + /* Fixme: not handle what about lpm*/
> + podf = __raw_readl(MXC_CCM_CBCDR);
> + pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
> + pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
> + podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
> +
> + return __get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
> +}
> +
> +static u32 __get_uart_clk(void)
> +{
> + unsigned int freq, reg, pred, podf;
Insert empty line after variable declarations for readability.
> + reg = __raw_readl(MXC_CCM_CSCMR1);
> + switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
> + MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
> + case 0x0:
> + freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> + break;
> + case 0x1:
> + freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
> + break;
> + case 0x2:
> + freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
> + break;
> + default:
> + return 66500000;
> + }
> +
> + reg = __raw_readl(MXC_CCM_CSCDR1);
> +
> + pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
> +
> + podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
> + freq /= (pred + 1) * (podf + 1);
> +
> + return freq;
> +}
> +
> +/*!
> ++ * This function returns the low power audio clock.
> ++ */
> +u32 get_lp_apm(void)
> +{
> + u32 ret_val = 0;
> + u32 ccsr = __raw_readl(MXC_CCM_CCSR);
> +
> + if (((ccsr >> 9) & 1) == 0)
> + ret_val = CONFIG_MX51_HCLK_FREQ;
> + else
> + ret_val = ((32768 * 1024));
> +
> + return ret_val;
> +}
> +
> +static u32 __get_cspi_clk(void)
> +{
> + u32 ret_val = 0, pdf, pre_pdf, clk_sel;
> + u32 cscmr1 = __raw_readl(MXC_CCM_CSCMR1);
> + u32 cscdr2 = __raw_readl(MXC_CCM_CSCDR2);
> +
> + pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
> + >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
> + pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
> + >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
> + clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
> + >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
> +
> + switch (clk_sel) {
> + case 0:
> + ret_val = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1));
> + break;
> + case 1:
> + ret_val = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1));
> + break;
> + case 2:
> + ret_val = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ) / ((pre_pdf + 1) * (pdf + 1));
> + break;
> + default:
> + ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
> + break;
> + }
> +
> + return ret_val;
> +}
> +
> +unsigned int mxc_get_clock(enum mxc_clock clk)
> +{
> + switch (clk) {
> + case MXC_ARM_CLK:
> + return __get_mcu_main_clk();
> + case MXC_AHB_CLK:
> + break;
> + case MXC_IPG_CLK:
> + return __get_ipg_clk();
> + case MXC_IPG_PERCLK:
> + return __get_ipg_per_clk();
> + case MXC_UART_CLK:
> + return __get_uart_clk();
> + case MXC_CSPI_CLK:
> + return __get_cspi_clk();
> + case MXC_FEC_CLK:
> + return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> + default:
> + break;
> + }
> + return -1;
> +}
> +
> +void mxc_show_clocks(void)
> +{
> + u32 freq;
Insert empty line after variable declarations for readability.
> + freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> + printf("mx51 pll1: %dMHz\n", freq / 1000000);
> + freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
> + printf("mx51 pll2: %dMHz\n", freq / 1000000);
> + freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
> + printf("mx51 pll3: %dMHz\n", freq / 1000000);
> + printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
> + printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
> + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
> + printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK));
> +}
> diff --git a/cpu/arm_cortexa8/mx51/crm_regs.h b/cpu/arm_cortexa8/mx51/crm_regs.h
> new file mode 100644
> index 0000000..6436bed
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/crm_regs.h
> @@ -0,0 +1,673 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
> +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
> +
> +#define MXC_CCM_BASE CCM_BASE_ADDR
> +#define MXC_DPLL1_BASE PLL1_BASE_ADDR
> +#define MXC_DPLL2_BASE PLL2_BASE_ADDR
> +#define MXC_DPLL3_BASE PLL3_BASE_ADDR
> +
> +/* PLL Register Offsets */
> +#define MXC_PLL_DP_CTL 0x00
> +#define MXC_PLL_DP_CONFIG 0x04
> +#define MXC_PLL_DP_OP 0x08
> +#define MXC_PLL_DP_MFD 0x0C
> +#define MXC_PLL_DP_MFN 0x10
> +#define MXC_PLL_DP_MFNMINUS 0x14
> +#define MXC_PLL_DP_MFNPLUS 0x18
> +#define MXC_PLL_DP_HFS_OP 0x1C
> +#define MXC_PLL_DP_HFS_MFD 0x20
> +#define MXC_PLL_DP_HFS_MFN 0x24
> +#define MXC_PLL_DP_MFN_TOGC 0x28
> +#define MXC_PLL_DP_DESTAT 0x2c
> +
> +/* PLL Register Bit definitions */
> +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
> +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
> +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
> +#define MXC_PLL_DP_CTL_ADE 0x800
> +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
> +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
> +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
> +#define MXC_PLL_DP_CTL_HFSM 0x80
> +#define MXC_PLL_DP_CTL_PRE 0x40
> +#define MXC_PLL_DP_CTL_UPEN 0x20
> +#define MXC_PLL_DP_CTL_RST 0x10
> +#define MXC_PLL_DP_CTL_RCP 0x8
> +#define MXC_PLL_DP_CTL_PLM 0x4
> +#define MXC_PLL_DP_CTL_BRM0 0x2
> +#define MXC_PLL_DP_CTL_LRF 0x1
> +
> +#define MXC_PLL_DP_CONFIG_BIST 0x8
> +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
> +#define MXC_PLL_DP_CONFIG_AREN 0x2
> +#define MXC_PLL_DP_CONFIG_LDREQ 0x1
> +
> +#define MXC_PLL_DP_OP_MFI_OFFSET 4
> +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
> +#define MXC_PLL_DP_OP_PDF_OFFSET 0
> +#define MXC_PLL_DP_OP_PDF_MASK 0xF
> +
> +#define MXC_PLL_DP_MFD_OFFSET 0
> +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
> +
> +#define MXC_PLL_DP_MFN_OFFSET 0x0
> +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
> +
> +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
> +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
> +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
> +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
> +
> +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
> +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
> +
> +/* Register addresses of CCM*/
> +#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
> +#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
> +#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
> +#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
> +#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
> +#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
> +#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
> +#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
> +#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
> +#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
> +#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
> +#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
> +#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
> +#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
> +#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
> +#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
> +#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
> +#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
> +#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
> +#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
> +#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
> +#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
> +#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
> +#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
> +#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
> +#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
> +#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
> +#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
> +#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
> +#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
> +#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
> +#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
> +#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
> +#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x84)
> +
> +/* Define the bits in register CCR */
> +#define MXC_CCM_CCR_COSC_EN (1 << 12)
> +#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
> +#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
> +#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
> +#define MXC_CCM_CCR_FPM_EN (1 << 8)
> +#define MXC_CCM_CCR_OSCNT_OFFSET (0)
> +#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
> +
> +/* Define the bits in register CCDR */
> +#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
> +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
> +#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
> +
> +/* Define the bits in register CSR */
> +#define MXC_CCM_CSR_COSR_READY (1 << 5)
> +#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
> +#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
> +#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
> +#define MXC_CCM_CSR_FPM_READY (1 << 1)
> +#define MXC_CCM_CSR_REF_EN_B (1 << 0)
> +
> +/* Define the bits in register CCSR */
> +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
> +#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
> +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
> +#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
> +#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
> +#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
> +#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
> +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
> +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
> +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
> +
> +/* Define the bits in register CACRR */
> +#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
> +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
> +
> +/* Define the bits in register CBCDR */
> +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
> +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
> +#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
> +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
> +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
> +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
> +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
> +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
> +#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
> +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
> +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
> +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
> +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
> +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
> +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
> +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
> +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
> +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
> +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
> +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
> +
> +/* Define the bits in register CBCMR */
> +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
> +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
> +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
> +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
> +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
> +#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
> +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
> +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
> +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
> +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
> +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
> +#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
> +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
> +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
> +
> +/* Define the bits in register CSCMR1 */
> +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
> +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
> +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
> +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
> +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
> +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
> +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
> +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
> +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
> +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
> +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
> +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
> +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
> +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
> +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
> +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
> +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
> +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
> +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
> +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
> +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
> +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
> +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
> +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
> +#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
> +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
> +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
> +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
> +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
> +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
> +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
> +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
> +
> +/* Define the bits in register CSCMR2 */
> +#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET (26)
> +#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK (0x7 << 26)
> +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
> +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
> +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
> +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
> +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
> +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
> +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
> +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
> +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
> +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
> +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
> +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
> +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
> +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
> +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
> +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
> +#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
> +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
> +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
> +#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
> +#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
> +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
> +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
> +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
> +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
> +
> +/* Define the bits in register CSCDR1 */
> +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
> +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
> +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
> +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
> +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
> +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
> +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
> +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
> +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
> +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
> +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
> +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
> +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
> +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
> +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
> +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
> +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
> +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
> +
> +/* Define the bits in register CS1CDR and CS2CDR */
> +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
> +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
> +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
> +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
> +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
> +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
> +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
> +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
> +
> +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
> +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
> +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
> +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
> +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
> +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
> +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
> +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
> +
> +/* Define the bits in register CDCDR */
> +#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
> +#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
> +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
> +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
> +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
> +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
> +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
> +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
> +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
> +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
> +#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
> +#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
> +#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
> +#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
> +#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
> +#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
> +
> +/* Define the bits in register CHSCCDR */
> +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
> +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
> +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
> +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
> +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
> +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
> +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
> +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
> +
> +/* Define the bits in register CSCDR2 */
> +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
> +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
> +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
> +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
> +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
> +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
> +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
> +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
> +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
> +#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
> +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
> +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
> +
> +/* Define the bits in register CSCDR3 */
> +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
> +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
> +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
> +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
> +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
> +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
> +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
> +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
> +
> +/* Define the bits in register CSCDR4 */
> +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
> +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
> +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
> +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
> +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
> +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
> +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
> +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
> +
> +/* Define the bits in register CDHIPR */
> +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
> +#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
> +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
> +#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
> +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
> +#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
> +#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
> +#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
> +
> +/* Define the bits in register CDCR */
> +#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
> +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
> +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
> +
> +/* Define the bits in register CLPCR */
> +#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
> +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
> +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
> +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
> +#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
> +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
> +#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
> +#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
> +#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
> +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
> +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
> +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
> +#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
> +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
> +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
> +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
> +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
> +#define MXC_CCM_CLPCR_LPM_OFFSET (0)
> +#define MXC_CCM_CLPCR_LPM_MASK (0x3)
> +
> +/* Define the bits in register CISR */
> +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
> +#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
> +#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
> +#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
> +#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
> +#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
> +#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
> +#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
> +#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
> +#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
> +#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
> +#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
> +#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
> +#define MXC_CCM_CISR_LRF_PLL1 (0x1)
> +
> +/* Define the bits in register CIMR */
> +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
> +#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
> +#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
> +#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
> +#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
> +#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
> +#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
> +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
> +#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
> +#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
> +#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
> +#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
> +#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
> +
> +/* Define the bits in register CCOSR */
> +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
> +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
> +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
> +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
> +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
> +#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
> +#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
> +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
> +#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
> +#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
> +
> +/* Define the bits in registers CGPR */
> +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
> +#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
> +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
> +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
> +
> +/* Define the bits in registers CCGRx */
> +#define MXC_CCM_CCGR_CG_MASK 0x3
> +
> +#define MXC_CCM_CCGR0_CG15_OFFSET 30
> +#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
> +#define MXC_CCM_CCGR0_CG14_OFFSET 28
> +#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
> +#define MXC_CCM_CCGR0_CG13_OFFSET 26
> +#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
> +#define MXC_CCM_CCGR0_CG12_OFFSET 24
> +#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
> +#define MXC_CCM_CCGR0_CG11_OFFSET 22
> +#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
> +#define MXC_CCM_CCGR0_CG10_OFFSET 20
> +#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
> +#define MXC_CCM_CCGR0_CG9_OFFSET 18
> +#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
> +#define MXC_CCM_CCGR0_CG8_OFFSET 16
> +#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
> +#define MXC_CCM_CCGR0_CG7_OFFSET 14
> +#define MXC_CCM_CCGR0_CG6_OFFSET 12
> +#define MXC_CCM_CCGR0_CG5_OFFSET 10
> +#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
> +#define MXC_CCM_CCGR0_CG4_OFFSET 8
> +#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
> +#define MXC_CCM_CCGR0_CG3_OFFSET 6
> +#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
> +#define MXC_CCM_CCGR0_CG2_OFFSET 4
> +#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
> +#define MXC_CCM_CCGR0_CG1_OFFSET 2
> +#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
> +#define MXC_CCM_CCGR0_CG0_OFFSET 0
> +#define MXC_CCM_CCGR0_CG0_MASK 0x3
> +
> +#define MXC_CCM_CCGR1_CG15_OFFSET 30
> +#define MXC_CCM_CCGR1_CG14_OFFSET 28
> +#define MXC_CCM_CCGR1_CG13_OFFSET 26
> +#define MXC_CCM_CCGR1_CG12_OFFSET 24
> +#define MXC_CCM_CCGR1_CG11_OFFSET 22
> +#define MXC_CCM_CCGR1_CG10_OFFSET 20
> +#define MXC_CCM_CCGR1_CG9_OFFSET 18
> +#define MXC_CCM_CCGR1_CG8_OFFSET 16
> +#define MXC_CCM_CCGR1_CG7_OFFSET 14
> +#define MXC_CCM_CCGR1_CG6_OFFSET 12
> +#define MXC_CCM_CCGR1_CG5_OFFSET 10
> +#define MXC_CCM_CCGR1_CG4_OFFSET 8
> +#define MXC_CCM_CCGR1_CG3_OFFSET 6
> +#define MXC_CCM_CCGR1_CG2_OFFSET 4
> +#define MXC_CCM_CCGR1_CG1_OFFSET 2
> +#define MXC_CCM_CCGR1_CG0_OFFSET 0
> +
> +#define MXC_CCM_CCGR2_CG15_OFFSET 30
> +#define MXC_CCM_CCGR2_CG14_OFFSET 28
> +#define MXC_CCM_CCGR2_CG13_OFFSET 26
> +#define MXC_CCM_CCGR2_CG12_OFFSET 24
> +#define MXC_CCM_CCGR2_CG11_OFFSET 22
> +#define MXC_CCM_CCGR2_CG10_OFFSET 20
> +#define MXC_CCM_CCGR2_CG9_OFFSET 18
> +#define MXC_CCM_CCGR2_CG8_OFFSET 16
> +#define MXC_CCM_CCGR2_CG7_OFFSET 14
> +#define MXC_CCM_CCGR2_CG6_OFFSET 12
> +#define MXC_CCM_CCGR2_CG5_OFFSET 10
> +#define MXC_CCM_CCGR2_CG4_OFFSET 8
> +#define MXC_CCM_CCGR2_CG3_OFFSET 6
> +#define MXC_CCM_CCGR2_CG2_OFFSET 4
> +#define MXC_CCM_CCGR2_CG1_OFFSET 2
> +#define MXC_CCM_CCGR2_CG0_OFFSET 0
> +
> +#define MXC_CCM_CCGR3_CG15_OFFSET 30
> +#define MXC_CCM_CCGR3_CG14_OFFSET 28
> +#define MXC_CCM_CCGR3_CG13_OFFSET 26
> +#define MXC_CCM_CCGR3_CG12_OFFSET 24
> +#define MXC_CCM_CCGR3_CG11_OFFSET 22
> +#define MXC_CCM_CCGR3_CG10_OFFSET 20
> +#define MXC_CCM_CCGR3_CG9_OFFSET 18
> +#define MXC_CCM_CCGR3_CG8_OFFSET 16
> +#define MXC_CCM_CCGR3_CG7_OFFSET 14
> +#define MXC_CCM_CCGR3_CG6_OFFSET 12
> +#define MXC_CCM_CCGR3_CG5_OFFSET 10
> +#define MXC_CCM_CCGR3_CG4_OFFSET 8
> +#define MXC_CCM_CCGR3_CG3_OFFSET 6
> +#define MXC_CCM_CCGR3_CG2_OFFSET 4
> +#define MXC_CCM_CCGR3_CG1_OFFSET 2
> +#define MXC_CCM_CCGR3_CG0_OFFSET 0
> +
> +#define MXC_CCM_CCGR4_CG15_OFFSET 30
> +#define MXC_CCM_CCGR4_CG14_OFFSET 28
> +#define MXC_CCM_CCGR4_CG13_OFFSET 26
> +#define MXC_CCM_CCGR4_CG12_OFFSET 24
> +#define MXC_CCM_CCGR4_CG11_OFFSET 22
> +#define MXC_CCM_CCGR4_CG10_OFFSET 20
> +#define MXC_CCM_CCGR4_CG9_OFFSET 18
> +#define MXC_CCM_CCGR4_CG8_OFFSET 16
> +#define MXC_CCM_CCGR4_CG7_OFFSET 14
> +#define MXC_CCM_CCGR4_CG6_OFFSET 12
> +#define MXC_CCM_CCGR4_CG5_OFFSET 10
> +#define MXC_CCM_CCGR4_CG4_OFFSET 8
> +#define MXC_CCM_CCGR4_CG3_OFFSET 6
> +#define MXC_CCM_CCGR4_CG2_OFFSET 4
> +#define MXC_CCM_CCGR4_CG1_OFFSET 2
> +#define MXC_CCM_CCGR4_CG0_OFFSET 0
> +
> +#define MXC_CCM_CCGR5_CG15_OFFSET 30
> +#define MXC_CCM_CCGR5_CG14_OFFSET 28
> +#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
> +#define MXC_CCM_CCGR5_CG13_OFFSET 26
> +#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
> +#define MXC_CCM_CCGR5_CG12_OFFSET 24
> +#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
> +#define MXC_CCM_CCGR5_CG11_OFFSET 22
> +#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
> +#define MXC_CCM_CCGR5_CG10_OFFSET 20
> +#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
> +#define MXC_CCM_CCGR5_CG9_OFFSET 18
> +#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
> +#define MXC_CCM_CCGR5_CG8_OFFSET 16
> +#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
> +#define MXC_CCM_CCGR5_CG7_OFFSET 14
> +#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
> +#define MXC_CCM_CCGR5_CG6_OFFSET 12
> +#define MXC_CCM_CCGR5_CG5_OFFSET 10
> +#define MXC_CCM_CCGR5_CG4_OFFSET 8
> +#define MXC_CCM_CCGR5_CG3_OFFSET 6
> +#define MXC_CCM_CCGR5_CG2_OFFSET 4
> +#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
> +#define MXC_CCM_CCGR5_CG1_OFFSET 2
> +#define MXC_CCM_CCGR5_CG0_OFFSET 0
> +
> +#define MXC_CCM_CCGR6_CG4_OFFSET 8
> +#define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8)
> +#define MXC_CCM_CCGR6_CG3_OFFSET 6
> +#define MXC_CCM_CCGR6_CG2_OFFSET 4
> +#define MXC_CCM_CCGR6_CG1_OFFSET 2
> +#define MXC_CCM_CCGR6_CG0_OFFSET 0
> +
> +#define MXC_CORTEXA8_BASE ARM_BASE_ADDR
> +#define MXC_GPC_BASE GPC_BASE_ADDR
> +#define MXC_DPTC_LP_BASE (GPC_BASE_ADDR + 0x80)
> +#define MXC_DPTC_GP_BASE (GPC_BASE_ADDR + 0x100)
> +#define MXC_DVFS_CORE_BASE (GPC_BASE_ADDR + 0x180)
> +#define MXC_DPTC_PER_BASE (GPC_BASE_ADDR + 0x1C0)
> +#define MXC_PGC_IPU_BASE (GPC_BASE_ADDR + 0x220)
> +#define MXC_PGC_VPU_BASE (GPC_BASE_ADDR + 0x240)
> +#define MXC_PGC_GPU_BASE (GPC_BASE_ADDR + 0x260)
> +#define MXC_SRPG_NEON_BASE (GPC_BASE_ADDR + 0x280)
> +#define MXC_SRPG_ARM_BASE (GPC_BASE_ADDR + 0x2A0)
> +#define MXC_SRPG_EMPGC0_BASE (GPC_BASE_ADDR + 0x2C0)
> +#define MXC_SRPG_EMPGC1_BASE (GPC_BASE_ADDR + 0x2D0)
> +#define MXC_SRPG_MEGAMIX_BASE (GPC_BASE_ADDR + 0x2E0)
> +#define MXC_SRPG_EMI_BASE (GPC_BASE_ADDR + 0x300)
> +
> +/* CORTEXA8 platform */
> +#define MXC_CORTEXA8_PLAT_PVID (MXC_CORTEXA8_BASE + 0x0)
> +#define MXC_CORTEXA8_PLAT_GPC (MXC_CORTEXA8_BASE + 0x4)
> +#define MXC_CORTEXA8_PLAT_PIC (MXC_CORTEXA8_BASE + 0x8)
> +#define MXC_CORTEXA8_PLAT_LPC (MXC_CORTEXA8_BASE + 0xC)
> +#define MXC_CORTEXA8_PLAT_NEON_LPC (MXC_CORTEXA8_BASE + 0x10)
> +#define MXC_CORTEXA8_PLAT_ICGC (MXC_CORTEXA8_BASE + 0x14)
> +#define MXC_CORTEXA8_PLAT_AMC (MXC_CORTEXA8_BASE + 0x18)
> +#define MXC_CORTEXA8_PLAT_NMC (MXC_CORTEXA8_BASE + 0x20)
> +#define MXC_CORTEXA8_PLAT_NMS (MXC_CORTEXA8_BASE + 0x24)
> +
> +/* DVFS CORE */
> +#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
> +#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
> +#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
> +#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
> +#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
> +#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
> +#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
> +#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
> +#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
> +#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
> +#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
> +#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
> +#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
> +#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
> +#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
> +#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
> +#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
> +
> +/* GPC */
> +#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
> +#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
> +#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
> +#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC)
> +#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10)
> +#define MXC_GPC_PGR_ARMPG_OFFSET 8
> +#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
> +
> +/* PGC */
> +#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
> +#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
> +#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
> +#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
> +#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
> +#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
> +
> +#define MXC_PGCR_PCR 1
> +#define MXC_SRPGCR_PCR 1
> +#define MXC_EMPGCR_PCR 1
> +#define MXC_PGSR_PSR 1
> +
> +
> +#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
> +#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
> +
> +/* SRPG */
> +#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
> +#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
> +#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
> +
> +#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
> +#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
> +#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
> +
> +#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
> +#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
> +#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
> +
> +#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
> +#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
> +#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
> +
> +#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
> +#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
> +#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
> +
> +#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
> +#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
> +#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
> +
Are all of the above #defines needed/expected to be needed by U-boot?
> +#ifndef __ASSEMBLE__
> +extern unsigned int __get_mcu_main_clk(void);
> +extern void mxc_show_clocks(void);
> +#endif
> +#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
> diff --git a/cpu/arm_cortexa8/mx51/interrupts.c b/cpu/arm_cortexa8/mx51/interrupts.c
> new file mode 100644
> index 0000000..c0d70ac
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/interrupts.c
<snip>
> diff --git a/cpu/arm_cortexa8/mx51/iomux.c b/cpu/arm_cortexa8/mx51/iomux.c
> new file mode 100644
> index 0000000..80082aa
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/iomux.c
<snip>
> diff --git a/cpu/arm_cortexa8/mx51/serial.c b/cpu/arm_cortexa8/mx51/serial.c
> new file mode 100644
> index 0000000..580ac13
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/serial.c
I haven't looked in the details of the serial driver, but would it be possible to use drivers/serial/serial_mxc.c
instead? It looks very similar.
> diff --git a/cpu/arm_cortexa8/mx51/soc.c b/cpu/arm_cortexa8/mx51/soc.c
> new file mode 100644
> index 0000000..cd8ce9d
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/soc.c
<snip>
> diff --git a/cpu/arm_cortexa8/mx51/timer.c b/cpu/arm_cortexa8/mx51/timer.c
> new file mode 100644
> index 0000000..5201768
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/timer.c
<snip>
> diff --git a/include/asm-arm/arch-mx51/iomux.h b/include/asm-arm/arch-mx51/iomux.h
> new file mode 100644
> index 0000000..fa02984
> --- /dev/null
> +++ b/include/asm-arm/arch-mx51/iomux.h
<snip>
> diff --git a/include/asm-arm/arch-mx51/mx51.h b/include/asm-arm/arch-mx51/mx51.h
> new file mode 100644
> index 0000000..4532a10
> --- /dev/null
> +++ b/include/asm-arm/arch-mx51/mx51.h
> @@ -0,0 +1,416 @@
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#ifndef __ASM_ARCH_MXC_MX51_H__
> +#define __ASM_ARCH_MXC_MX51_H__
> +
> +/*
> + * IRAM
> + */
> +#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
> +/*
> + * Graphics Memory of GPU
> + */
> +#define GPU_BASE_ADDR 0x20000000
> +#define GPU_CTRL_BASE_ADDR 0x30000000
> +#define IPU_CTRL_BASE_ADDR 0x40000000
> +/*
> + * Debug
> + */
> +#define DEBUG_BASE_ADDR 0x60000000
> +#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
> +#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
> +#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
> +#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
> +#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
> +#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
> +#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
> +#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
> +
> +/*
> + * SPBA global module enabled #0
> + */
> +#define SPBA0_BASE_ADDR 0x70000000
> +
> +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
> +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
> +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
> +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
> +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
> +#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
> +#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
> +#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
> +#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
> +#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
> +#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
> +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
> +
> +/*
> + * AIPS 1
> + */
> +#define AIPS1_BASE_ADDR 0x73F00000
> +
> +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
> +#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
> +#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
> +#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
> +#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
> +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
> +#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
> +#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
> +#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
> +#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
> +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
> +#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
> +#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
> +#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
> +#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
> +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
> +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
> +#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
> +#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
> +#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
> +
> +/*
> + * AIPS 2
> + */
> +#define AIPS2_BASE_ADDR 0x83F00000
> +
> +#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
> +#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
> +#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
> +#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
> +#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
> +#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
> +#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
> +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
> +#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
> +#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
> +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
> +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
> +#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
> +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
> +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
> +#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
> +#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
> +#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
> +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
> +#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
> +#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
> +#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
> +#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
> +#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
> +#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
> +#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
> +#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
> +#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
> +#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
> +#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
> +#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
> +#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
> +
> +#define TZIC_BASE_ADDR 0x8FFFC000
> +
> +/*
> + * Memory regions and CS
> + */
> +#define CSD0_BASE_ADDR 0x90000000
> +#define CSD1_BASE_ADDR 0xA0000000
> +#define CS0_BASE_ADDR 0xB0000000
> +#define CS1_BASE_ADDR 0xB8000000
> +#define CS2_BASE_ADDR 0xC0000000
> +#define CS3_BASE_ADDR 0xC8000000
> +#define CS4_BASE_ADDR 0xCC000000
> +#define CS5_BASE_ADDR 0xCE000000
> +
> +/*
> + * NFC
> + */
> +#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */
> +
> +/*!
> + * defines for SPBA modules
> + */
> +#define SPBA_SDHC1 0x04
> +#define SPBA_SDHC2 0x08
> +#define SPBA_UART3 0x0C
> +#define SPBA_CSPI1 0x10
> +#define SPBA_SSI2 0x14
> +#define SPBA_SDHC3 0x20
> +#define SPBA_SDHC4 0x24
> +#define SPBA_SPDIF 0x28
> +#define SPBA_ATA 0x30
> +#define SPBA_SLIM 0x34
> +#define SPBA_HSI2C 0x38
> +#define SPBA_CTRL 0x3C
> +
> +/*
> + * Interrupt numbers
> + */
> +#define MXC_INT_BASE 0
> +#define MXC_INT_RESV0 0
> +#define MXC_INT_MMC_SDHC1 1
> +#define MXC_INT_MMC_SDHC2 2
> +#define MXC_INT_MMC_SDHC3 3
> +#define MXC_INT_MMC_SDHC4 4
> +#define MXC_INT_RESV5 5
> +#define MXC_INT_SDMA 6
> +#define MXC_INT_IOMUX 7
> +#define MXC_INT_NFC 8
> +#define MXC_INT_VPU 9
> +#define MXC_INT_IPU_ERR 10
> +#define MXC_INT_IPU_SYN 11
> +#define MXC_INT_GPU 12
> +#define MXC_INT_RESV13 13
> +#define MXC_INT_USB_H1 14
> +#define MXC_INT_EMI 15
> +#define MXC_INT_USB_H2 16
> +#define MXC_INT_USB_H3 17
> +#define MXC_INT_USB_OTG 18
> +#define MXC_INT_SAHARA_H0 19
> +#define MXC_INT_SAHARA_H1 20
> +#define MXC_INT_SCC_SMN 21
> +#define MXC_INT_SCC_STZ 22
> +#define MXC_INT_SCC_SCM 23
> +#define MXC_INT_SRTC_NTZ 24
> +#define MXC_INT_SRTC_TZ 25
> +#define MXC_INT_RTIC 26
> +#define MXC_INT_CSU 27
> +#define MXC_INT_SLIM_B 28
> +#define MXC_INT_SSI1 29
> +#define MXC_INT_SSI2 30
> +#define MXC_INT_UART1 31
> +#define MXC_INT_UART2 32
> +#define MXC_INT_UART3 33
> +#define MXC_INT_RESV34 34
> +#define MXC_INT_RESV35 35
> +#define MXC_INT_CSPI1 36
> +#define MXC_INT_CSPI2 37
> +#define MXC_INT_CSPI 38
> +#define MXC_INT_GPT 39
> +#define MXC_INT_EPIT1 40
> +#define MXC_INT_EPIT2 41
> +#define MXC_INT_GPIO1_INT7 42
> +#define MXC_INT_GPIO1_INT6 43
> +#define MXC_INT_GPIO1_INT5 44
> +#define MXC_INT_GPIO1_INT4 45
> +#define MXC_INT_GPIO1_INT3 46
> +#define MXC_INT_GPIO1_INT2 47
> +#define MXC_INT_GPIO1_INT1 48
> +#define MXC_INT_GPIO1_INT0 49
> +#define MXC_INT_GPIO1_LOW 50
> +#define MXC_INT_GPIO1_HIGH 51
> +#define MXC_INT_GPIO2_LOW 52
> +#define MXC_INT_GPIO2_HIGH 53
> +#define MXC_INT_GPIO3_LOW 54
> +#define MXC_INT_GPIO3_HIGH 55
> +#define MXC_INT_GPIO4_LOW 56
> +#define MXC_INT_GPIO4_HIGH 57
> +#define MXC_INT_WDOG1 58
> +#define MXC_INT_WDOG2 59
> +#define MXC_INT_KPP 60
> +#define MXC_INT_PWM1 61
> +#define MXC_INT_I2C1 62
> +#define MXC_INT_I2C2 63
> +#define MXC_INT_HS_I2C 64
> +#define MXC_INT_RESV65 65
> +#define MXC_INT_RESV66 66
> +#define MXC_INT_SIM_IPB 67
> +#define MXC_INT_SIM_DAT 68
> +#define MXC_INT_IIM 69
> +#define MXC_INT_ATA 70
> +#define MXC_INT_CCM1 71
> +#define MXC_INT_CCM2 72
> +#define MXC_INT_GPC1 73
> +#define MXC_INT_GPC2 74
> +#define MXC_INT_SRC 75
> +#define MXC_INT_NM 76
> +#define MXC_INT_PMU 77
> +#define MXC_INT_CTI_IRQ 78
> +#define MXC_INT_CTI1_TG0 79
> +#define MXC_INT_CTI1_TG1 80
> +#define MXC_INT_MCG_ERR 81
> +#define MXC_INT_MCG_TMR 82
> +#define MXC_INT_MCG_FUNC 83
> +#define MXC_INT_RESV84 84
> +#define MXC_INT_RESV85 85
> +#define MXC_INT_RESV86 86
> +#define MXC_INT_FEC 87
> +#define MXC_INT_OWIRE 88
> +#define MXC_INT_CTI1_TG2 89
> +#define MXC_INT_SJC 90
> +#define MXC_INT_SPDIF 91
> +#define MXC_INT_TVE 92
> +#define MXC_INT_FIRI 93
> +#define MXC_INT_PWM2 94
> +#define MXC_INT_SLIM_EXP 95
> +#define MXC_INT_SSI3 96
> +#define MXC_INT_RESV97 97
> +#define MXC_INT_CTI1_TG3 98
> +#define MXC_INT_SMC_RX 99
> +#define MXC_INT_VPU_IDLE 100
> +#define MXC_INT_RESV101 101
> +#define MXC_INT_GPU_IDLE 102
> +
> +#define MXC_MAX_INT_LINES 128
> +
> +#define MXC_GPIO_INT_BASE (MXC_MAX_INT_LINES)
> +
> +/*!
> + * Number of GPIO port as defined in the IC Spec
> + */
> +#define GPIO_PORT_NUM 4
> +/*!
> + * Number of GPIO pins per port
> + */
> +#define GPIO_NUM_PIN 32
> +
> +#define MXC_GPIO_SPLIT_IRQ_2
> +
> +#define IIM_SREV 0x24
> +#define ROM_SI_REV 0x48
> +
> +#define NFC_BUF_SIZE 0x1000
> +
> +/* WEIM registers */
> +#define CSGCR1 0x00
> +#define CSGCR2 0x04
> +#define CSRCR1 0x08
> +#define CSRCR2 0x0C
> +#define CSWCR1 0x10
> +
> +/* M4IF */
> +#define M4IF_FBPM0 0x40
> +#define M4IF_FIDBP 0x48
> +
> +/* ESDCTL */
> +#define ESDCTL_ESDCTL0 0x00
> +#define ESDCTL_ESDCFG0 0x04
> +#define ESDCTL_ESDCTL1 0x08
> +#define ESDCTL_ESDCFG1 0x0C
> +#define ESDCTL_ESDMISC 0x10
> +#define ESDCTL_ESDSCR 0x14
> +#define ESDCTL_ESDCDLY1 0x20
> +#define ESDCTL_ESDCDLY2 0x24
> +#define ESDCTL_ESDCDLY3 0x28
> +#define ESDCTL_ESDCDLY4 0x2C
> +#define ESDCTL_ESDCDLY5 0x30
> +#define ESDCTL_ESDCDLYGD 0x34
> +
> +/* CCM */
> +#define CLKCTL_CCR 0x00
> +#define CLKCTL_CCDR 0x04
> +#define CLKCTL_CSR 0x08
> +#define CLKCTL_CCSR 0x0C
> +#define CLKCTL_CACRR 0x10
> +#define CLKCTL_CBCDR 0x14
> +#define CLKCTL_CBCMR 0x18
> +#define CLKCTL_CSCMR1 0x1C
> +#define CLKCTL_CSCMR2 0x20
> +#define CLKCTL_CSCDR1 0x24
> +#define CLKCTL_CS1CDR 0x28
> +#define CLKCTL_CS2CDR 0x2C
> +#define CLKCTL_CDCDR 0x30
> +#define CLKCTL_CHSCCDR 0x34
> +#define CLKCTL_CSCDR2 0x38
> +#define CLKCTL_CSCDR3 0x3C
> +#define CLKCTL_CSCDR4 0x40
> +#define CLKCTL_CWDR 0x44
> +#define CLKCTL_CDHIPR 0x48
> +#define CLKCTL_CDCR 0x4C
> +#define CLKCTL_CTOR 0x50
> +#define CLKCTL_CLPCR 0x54
> +#define CLKCTL_CISR 0x58
> +#define CLKCTL_CIMR 0x5C
> +#define CLKCTL_CCOSR 0x60
> +#define CLKCTL_CGPR 0x64
> +#define CLKCTL_CCGR0 0x68
> +#define CLKCTL_CCGR1 0x6C
> +#define CLKCTL_CCGR2 0x70
> +#define CLKCTL_CCGR3 0x74
> +#define CLKCTL_CCGR4 0x78
> +#define CLKCTL_CCGR5 0x7C
> +#define CLKCTL_CCGR6 0x80
> +#define CLKCTL_CMEOR 0x84
> +
> +/* DPLL */
> +#define PLL_DP_CTL 0x00
> +#define PLL_DP_CONFIG 0x04
> +#define PLL_DP_OP 0x08
> +#define PLL_DP_MFD 0x0C
> +#define PLL_DP_MFN 0x10
> +#define PLL_DP_MFNMINUS 0x14
> +#define PLL_DP_MFNPLUS 0x18
> +#define PLL_DP_HFS_OP 0x1C
> +#define PLL_DP_HFS_MFD 0x20
> +#define PLL_DP_HFS_MFN 0x24
> +#define PLL_DP_TOGC 0x28
> +#define PLL_DP_DESTAT 0x2C
> +
> +/* Assuming 24MHz input clock with doubler ON */
> +/* MFI PDF */
> +#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
> +#define DP_MFD_850 (48 - 1)
> +#define DP_MFN_850 41
> +
> +#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
> +#define DP_MFD_800 (3 - 1)
> +#define DP_MFN_800 1
> +
> +#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
> +#define DP_MFD_700 (24 - 1)
> +#define DP_MFN_700 7
> +
> +#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
> +#define DP_MFD_665 (96 - 1)
> +#define DP_MFN_665 89
> +
> +#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
> +#define DP_MFD_532 (24 - 1)
> +#define DP_MFN_532 13
> +
> +#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
> +#define DP_MFD_400 (3 - 1)
> +#define DP_MFN_400 1
> +
> +#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
> +#define DP_MFD_216 (4 - 1)
> +#define DP_MFN_216 3
> +
> +#define CHIP_REV_1_0 0x10
> +#define CHIP_REV_1_1 0x11
> +#define CHIP_REV_2_0 0x20
> +#define CHIP_REV_2_5 0x120
> +
> +#define BOARD_REV_1_0 0x0
> +#define BOARD_REV_2_0 0x1
> +
> +#ifndef __ASSEMBLER__
> +
> +enum mxc_clock {
> +MXC_ARM_CLK = 0,
> +MXC_AHB_CLK,
> +MXC_IPG_CLK,
> +MXC_IPG_PERCLK,
> +MXC_UART_CLK,
> +MXC_CSPI_CLK,
> +MXC_FEC_CLK,
Indent this.
> +};
I don't think everything in this file is needed by U-Boot, e.g. the interrupt definitions.
> +
> +extern unsigned int mxc_get_clock(enum mxc_clock clk);
> +extern unsigned int get_board_rev(void);
> +extern int is_soc_rev(int rev);
> +
> +#endif /* __ASSEMBLER__*/
> +
> +#endif /* __ASM_ARCH_MXC_MX51_H__ */
> diff --git a/include/asm-arm/arch-mx51/mx51_pins.h b/include/asm-arm/arch-mx51/mx51_pins.h
> new file mode 100644
> index 0000000..63fdd8c
> --- /dev/null
> +++ b/include/asm-arm/arch-mx51/mx51_pins.h
<snip>
> diff --git a/include/configs/imx51.h b/include/configs/imx51.h
> new file mode 100644
> index 0000000..f0def4e
> --- /dev/null
> +++ b/include/configs/imx51.h
> @@ -0,0 +1,177 @@
> +/*
> + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
> + *
> + * (C) Copyright 2009 Freescale Semiconductor, Inc.
> + *
> + * Configuration settings for the MX51-3Stack Freescale board.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <asm/arch/mx51.h>
> +
> + /* High Level Configuration Options */
> +#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
> +#define CONFIG_L2_OFF
> +
> +#define CONFIG_MXC 1
> +#define CONFIG_MX51_BBG 1 /* in a mx51 */
Can't see that this is used anywhere.
> +#define CONFIG_FLASH_HEADER 1
> +#define CONFIG_FLASH_HEADER_OFFSET 0x400
> +#define CONFIG_FLASH_HEADER_BARKER 0xB1
Looks like a new config option that needs documentation.
> +
> +#define CONFIG_SKIP_RELOCATE_UBOOT
> +
> +#define CONFIG_MX51_HCLK_FREQ 24000000
> +#define CONFIG_MX51_CLK32 32768
> +#define CONFIG_DISPLAY_CPUINFO
> +#define CONFIG_DISPLAY_BOARDINFO
> +
> +#define BOARD_LATE_INIT
> +/*
> + * Disabled for now due to build problems under Debian and a significant
> + * increase in the final file size: 144260 vs. 109536 Bytes.
> + */
What is disabled?
> +
> +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
> +#define CONFIG_REVISION_TAG 1
> +#define CONFIG_SETUP_MEMORY_TAGS 1
> +#define CONFIG_INITRD_TAG 1
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
> +/* size in bytes reserved for initial data */
> +#define CONFIG_SYS_GBL_DATA_SIZE 128
> +
> +#define CONFIG_DOS_PARTITION 1
> +/*
> + * Hardware drivers
> + */
> +#define CONFIG_SERIAL UART1_BASE_ADDR
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_CONS_INDEX 1
> +#define CONFIG_BAUDRATE 115200
> +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
> +
> +/***********************************************************
> + * Command definition
> + ***********************************************************/
> +
> +#undef CONFIG_CMD_IMLS
> +
> +#define CONFIG_BOOTDELAY 3
> +
> +#define CONFIG_PRIME "FEC0"
> +
> +#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "netdev=eth0\0" \
> + "ethprime=FEC0\0" \
> + "uboot_addr=0xa0000000\0" \
> + "uboot=u-boot.bin\0" \
> + "kernel=uImage\0" \
> + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
> + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
> + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
> + "bootcmd=run bootcmd_net\0" \
> + "bootcmd_net=run bootargs_base bootargs_nfs; " \
> + "tftpboot ${loadaddr} ${kernel}; bootm\0" \
> +
> +/*
> + * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under
> + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
> + * controller inverted. The controller is capable of detecting and correcting
> + * this, but it needs 4 network packets for that. Which means, at startup, you
> + * will not receive answers to the first 4 packest, unless there have been some
> + * broadcasts on the network, or your board is on a hub. Reducing the ARP
> + * timeout from default 5 seconds to 200ms we speed up the initial TFTP
> + * transfer, should the user wish one, significantly.
> + */
> +#define CONFIG_ARP_TIMEOUT 200UL
> +
> +/*
> + * Miscellaneous configurable options
> + */
> +#define CONFIG_SYS_LONGHELP /* undef to save memory */
> +#define CONFIG_SYS_PROMPT "BBG U-Boot > "
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
> +
> +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
Is there a RAM/SDRAM on address 0?
> +#define CONFIG_SYS_MEMTEST_END 0x10000
> +
> +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
> +
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_HZ CONFIG_MX51_CLK32/* use 32kHz clock as source */
CONFIG_SYS_HZ should be 1000 on all boards if I remember correctly.
Regards, Magnus
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
2009-09-21 17:55 ` Magnus Lilja
@ 2009-09-21 20:58 ` Fabio Estevam
[not found] ` <2f495dc80909221219n2f6f303dw478871aede988a7a@mail.gmail.com>
1 sibling, 0 replies; 15+ messages in thread
From: Fabio Estevam @ 2009-09-21 20:58 UTC (permalink / raw)
To: u-boot
Hi Fred,
--- On Mon, 9/21/09, Magnus Lilja <lilja.magnus@gmail.com> wrote:
> From: Magnus Lilja <lilja.magnus@gmail.com>
> Subject: Re: [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
> To: gareatech at gmail.com
> Cc: u-boot at lists.denx.de
> Date: Monday, September 21, 2009, 2:55 PM
> Hi
>
>
> I've scanned the patch briefly and have some comments
> below.
>
> gareatech at gmail.com
> wrote:
> > From: Fred Fan <fanyefeng@gmail.com>
> >
> > This patch just supports boot into u-boot from mmc or
> spi-nor flash.
> > It just implements console, iomux and clock. There are
> no ethernet,
> > nor-flash, mmc or other peripheral drivers.
> >
> > Sign-of-by: Fred.Fan <fanyefeng@gmail.com>
> > Sign-of-by: Fred.Fan <r01011@freescale.com>
>
> Should be 'Signed-off-by: FredFan <fanyefeng@gmail.com>'.
>
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 620604c..5fb1221 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -549,6 +549,10 @@ Fabio Estevam <Fabio.Estevam@freescale.com>
> >?
> >? ??? mx31pdk???
> ??? i.MX31
> >?
> > +Fred Fan <fanyefeng@gmail.com>
> > +
> > +??? imx51???
> ??? i.MX51
> > +
>
> Is imx51 really the name of this board? Later on it looks
> like the name is MX51_BABBAGE.
I agree with Magnus. You should use the board name here, not the processor name.
>
> >? Peter Figuli <peposh@etc.sk>
> >?
> >? ??? wepep250???
> xscale
> > diff --git a/MAKEALL b/MAKEALL
> > index edebaea..ed8c437 100755
> > --- a/MAKEALL
> > +++ b/MAKEALL
> <snip>
>
> > diff --git a/board/freescale/imx51/Makefile
> b/board/freescale/imx51/Makefile
> > new file mode 100644
> > index 0000000..fbd40f2
> > --- /dev/null
> > +++ b/board/freescale/imx51/Makefile
As Magnus pointed out you should use /board/freescale/mx51babbage/...
>
> > diff --git a/board/freescale/imx51/board-imx51.h
Ditto
> b/board/freescale/imx51/board-imx51.h
> > new file mode 100644
> > index 0000000..7a2cae0
> > --- /dev/null
> > +++ b/board/freescale/imx51/board-imx51.h
> > @@ -0,0 +1,64 @@
> > +/*
> > + * Copyright 2009 Freescale Semiconductor, Inc. All
> Rights Reserved.
> > + */
> > +
> > +/*
> > + * The code contained herein is licensed under the
> GNU General Public
> > + * License. You may obtain a copy of the GNU General
> Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +#ifndef __BOARD_FREESCALE_BOARD_IMX51_H__
> > +#define __BOARD_FREESCALE_BOARD_IMX51_H__
> > +
> > +/*!
> > + * @defgroup BRDCFG_MX51 Board Configuration Options
> > + * @ingroup MSL_MX51
> > + */
> > +
> > +/*!
> > + * @file mx51_3stack/board-imx51.h
> > + *
> > + * @brief This file contains all the board level
> configuration options.
> > + *
> > + * It currently hold the options defined for MX51
> 3Stack Platform.
I think you should remove MX51 3stack references as it can cause confusion.
> > + *
> > + * @ingroup BRDCFG_IMX51
> > + */
> > +
> > +/* CPLD offsets */
> > +#define PBC_LED_CTRL???
> ??? (0x20000)
> > +#define PBC_SB_STAT???
> ??? (0x20008)
> > +#define PBC_ID_AAAA???
> ??? (0x20040)
> > +#define PBC_ID_5555???
> ??? (0x20048)
> > +#define PBC_VERSION???
> ??? (0x20050)
> > +#define PBC_ID_CAFE???
> ??? (0x20058)
> > +#define PBC_INT_STAT???
> ??? (0x20010)
> > +#define PBC_INT_MASK???
> ??? (0x20038)
> > +#define PBC_INT_REST???
> ??? (0x20020)
> > +#define PBC_SW_RESET???
> ??? (0x20060)
> > +
> > +/* LED switchs */
> > +#define LED_SWITCH_REG???
> ??? 0x00
> > +/* buttons */
> > +#define SWITCH_BUTTONS_REG??? 0x08
> > +/* status, interrupt */
> > +#define INTR_STATUS_REG??? 0x10
> > +#define INTR_MASK_REG???
> ??? 0x38
> > +#define INTR_RESET_REG???
> ??? 0x20
> > +/* magic word for debug CPLD */
> > +#define MAGIC_NUMBER1_REG??? 0x40
> > +#define MAGIC_NUMBER2_REG??? 0x48
> > +/* CPLD code version */
> > +#define CPLD_CODE_VER_REG??? 0x50
> > +/* magic word for debug CPLD */
> > +#define MAGIC_NUMBER3_REG??? 0x58
> > +/* module reset register*/
> > +#define MODULE_RESET_REG??? 0x60
> > +/* CPU ID and Personality ID */
> > +#define MCU_BOARD_ID_REG??? 0x68
> > +
> > +#endif??? ???
> ??? ??? /*
> __BOARD_FREESCALE_BOARD_IMX51_H__ */
> > diff --git a/board/freescale/imx51/config.mk
> b/board/freescale/imx51/config.mk
> > new file mode 100644
> > index 0000000..d8b0f10
> > --- /dev/null
> > +++ b/board/freescale/imx51/config.mk
> > @@ -0,0 +1,2 @@
> > +LDSCRIPT = board/$(VENDOR)/$(BOARD)/u-boot.lds
> > +TEXT_BASE = 0x97800000
> > diff --git a/board/freescale/imx51/flash_header.S
> b/board/freescale/imx51/flash_header.S
> > new file mode 100644
> > index 0000000..6790679
> > --- /dev/null
> > +++ b/board/freescale/imx51/flash_header.S
> > @@ -0,0 +1,113 @@
> > +/*
> > + * Copyright 2009 Freescale Semiconductor, Inc.
> > + *
> > + * This program is free software; you can
> redistribute it and/or
> > + * modify it under the terms of the GNU General
> Public License as
> > + * published by the Free Software Foundation; either
> version 2 of
> > + * the License, or (at your option) any later
> version.
> > + *
> > + * This program is distributed in the hope that it
> will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied
> warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR
> PURPOSE.? See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General
> Public License
> > + * along with this program; if not, write to the Free
> Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330,
> Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
>
> I wouldn't mind a short description of what this file does
> and why it's needed.
Yes, please mention that this is needed for the internal boot mode.
Regards,
Fabio Estevam
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
[not found] ` <2f495dc80909221219n2f6f303dw478871aede988a7a@mail.gmail.com>
@ 2009-09-22 19:52 ` Magnus Lilja
2009-09-22 20:28 ` Fred Fan
2009-09-22 20:04 ` Magnus Lilja
1 sibling, 1 reply; 15+ messages in thread
From: Magnus Lilja @ 2009-09-22 19:52 UTC (permalink / raw)
To: u-boot
Hi
2009/9/22 Fred Fan <fanyefeng@gmail.com>:
> Hi Magnus Liljia:
> ??? Thanks for your comments.
> ???? Best Regards
> Fred
>
> 2009/9/22, Magnus Lilja <lilja.magnus@gmail.com>:
>>
>> Hi
>>
>>
>> I've scanned the patch briefly and have some comments below.
>>
>> gareatech at gmail.com wrote:
>> > diff --git a/MAKEALL b/MAKEALL
>> > index edebaea..ed8c437 100755
>> > --- a/MAKEALL
>> > +++ b/MAKEALL
>> <snip>
>
>
> Does means use new board name?
Heh, no. <snip> just means that I've removed parts of your patch
(those parts which I don't have any comments on). Sorry for the
confusion.
>> > +++ b/board/freescale/imx51/Makefile
>> <snip>
>> Does means use new board name?
The board name should be used instead of the imx51 name.
>> > +???? mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
>> > +???? mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
>> > +???? mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
>> > +???? mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
>> > +???? mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
>> > +???? mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
>> > +???? mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
>> > +???? mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
>> > +}
>> > +
>> > +void setup_nfc(void)
>> > +{
>> > +???? /* Enable NFC IOMUX */
>> > +???? mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
>> > +???? mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
>> > +???? mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
>> > +???? mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
>> > +???? mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
>> > +???? mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
>> > +???? mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
>> > +???? mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
>> > +}
>>
>> Since it's very likely that setup_nfc() and setup_uart() will be used in
>> other i.MX51 boards as well it's a good idea to
>> place these functions in cpu/arm_cortexa8/mx51/devices.c (or something
>> similar).
>> I think it should be board level. Some board based on i.MX51 maybe has
>> differenent choice.
That can be handed with #ifdef's just like in the i.MX31 case.
<...>
>> > +#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
>> > +#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
>> > +#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
>> > +
>>
>> Are all of the above #defines needed/expected to be needed by U-boot?
>
> ? No. It just copy from linux kernel code. Does need remove them?
Don't no what the policy is.
>> > diff --git a/cpu/arm_cortexa8/mx51/interrupts.c
>> > b/cpu/arm_cortexa8/mx51/interrupts.c
>> > new file mode 100644
>> > index 0000000..c0d70ac
>> > --- /dev/null
>> > +++ b/cpu/arm_cortexa8/mx51/interrupts.c
>> <snip>
>> What's means?
Ignore the <snip> comments.
>> > diff --git a/cpu/arm_cortexa8/mx51/serial.c
>> > b/cpu/arm_cortexa8/mx51/serial.c
>> > new file mode 100644
>> > index 0000000..580ac13
>> > --- /dev/null
>> > +++ b/cpu/arm_cortexa8/mx51/serial.c
>>
>> I haven't looked in the details of the serial driver, but would it be
>> possible to use drivers/serial/serial_mxc.c
>> instead? It looks very similar.
>> I don't like the implement of this?driver. It contains the chip details in
>> driver code.
>>
>> But I will do what as your said. And restructure this driver in another
>> patch.
That sounds like a good idea if you want to improve the serial driver.
Create a separate standalone patch so people can review and test that.
Regards, Magnus
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
[not found] ` <2f495dc80909221219n2f6f303dw478871aede988a7a@mail.gmail.com>
2009-09-22 19:52 ` Magnus Lilja
@ 2009-09-22 20:04 ` Magnus Lilja
2009-09-22 20:29 ` Fred Fan
1 sibling, 1 reply; 15+ messages in thread
From: Magnus Lilja @ 2009-09-22 20:04 UTC (permalink / raw)
To: u-boot
Hmm, for some reason "Reply" in gmail cut part of the qouted message so
here's the rest of the followup.
Fred Fan skrev:
> Hi Magnus Liljia:
> Thanks for your comments.
> Best Regards
> Fred
>
> 2009/9/22, Magnus Lilja <lilja.magnus@gmail.com>:
>
>> Hi
>>
>>
>> I've scanned the patch briefly and have some comments below.
>>
>> gareatech at gmail.com wrote:
>> I don't think everything in this file is needed by U-Boot, e.g. the
>> interrupt definitions.
>> Yes. But interrupt maybe use when interrupt is supportted. Do I need remove
>> the definitions which are not used?
Don't know.
>>> diff --git a/include/configs/imx51.h b/include/configs/imx51.h
>>> new file mode 100644
>>> index 0000000..f0def4e
>>> --- /dev/null
>>> +++ b/include/configs/imx51.h
>>> @@ -0,0 +1,177 @@
>>> +/*
>>> + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
>>> + *
>>> + * (C) Copyright 2009 Freescale Semiconductor, Inc.
>>> + *
>>> + * Configuration settings for the MX51-3Stack Freescale board.
>>> + *
>>> + * This program is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation; either version 2 of
>>> + * the License, or (at your option) any later version.
>>> + *
>>> + * This program is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>>> + * GNU General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU General Public License
>>> + * along with this program; if not, write to the Free Software
>>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
>>> + * MA 02111-1307 USA
>>> + */
>>> +
>>> +#ifndef __CONFIG_H
>>> +#define __CONFIG_H
>>> +
>>> +#include <asm/arch/mx51.h>
>>> +
>>> + /* High Level Configuration Options */
>>> +#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core
>> */
>>> +#define CONFIG_L2_OFF
>>> +
>>> +#define CONFIG_MXC 1
>>> +#define CONFIG_MX51_BBG 1 /* in a mx51 */
>> Can't see that this is used anywhere.
>> OK. I will remove them;
Only remove MX51_BBG, I didn't check if CONFIG_MXC is used anywhere.
Regards, Magnus
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
2009-09-22 19:52 ` Magnus Lilja
@ 2009-09-22 20:28 ` Fred Fan
0 siblings, 0 replies; 15+ messages in thread
From: Fred Fan @ 2009-09-22 20:28 UTC (permalink / raw)
To: u-boot
HI Magnus Lilja:
Best Regards
Fred
2009/9/23, Magnus Lilja <lilja.magnus@gmail.com>:
>
> Hi
>
> 2009/9/22 Fred Fan <fanyefeng@gmail.com>:
> > Hi Magnus Liljia:
> > Thanks for your comments.
> > Best Regards
> > Fred
> >
> > 2009/9/22, Magnus Lilja <lilja.magnus@gmail.com>:
> >>
> >> Hi
> >>
> >>
> >> I've scanned the patch briefly and have some comments below.
> >>
> >> gareatech at gmail.com wrote:
> >> > diff --git a/MAKEALL b/MAKEALL
> >> > index edebaea..ed8c437 100755
> >> > --- a/MAKEALL
> >> > +++ b/MAKEALL
> >> <snip>
> >
> >
> > Does means use new board name?
>
> Heh, no. <snip> just means that I've removed parts of your patch
> (those parts which I don't have any comments on). Sorry for the
> confusion.
> OK
> >> > +++ b/board/freescale/imx51/Makefile
> >> <snip>
> >> Does means use new board name?
>
> The board name should be used instead of the imx51 name.
OK
>> > + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> >> > + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
> >> > + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> >> > + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
> >> > + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> >> > + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
> >> > + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> >> > + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
> >> > +}
> >> > +
> >> > +void setup_nfc(void)
> >> > +{
> >> > + /* Enable NFC IOMUX */
> >> > + mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
> >> > + mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
> >> > + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
> >> > + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
> >> > + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
> >> > + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
> >> > + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
> >> > + mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
> >> > +}
> >>
> >> Since it's very likely that setup_nfc() and setup_uart() will be used in
> >> other i.MX51 boards as well it's a good idea to
> >> place these functions in cpu/arm_cortexa8/mx51/devices.c (or something
> >> similar).
> >> I think it should be board level. Some board based on i.MX51 maybe has
> >> differenent choice.
>
> That can be handed with #ifdef's just like in the i.MX31 case.
> If we do like i.MX31, the code in soc level has the details of board level.
we should reduce the block of #ifdef.
> <...>
> >> > +#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
> >> > +#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
> >> > +#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
> >> > +
> >>
> >> Are all of the above #defines needed/expected to be needed by U-boot?
> >
> > No. It just copy from linux kernel code. Does need remove them?
>
> Don't no what the policy is.
we prefer to keep the sync with the file in kernel source code.
>> > diff --git a/cpu/arm_cortexa8/mx51/interrupts.c
> >> > b/cpu/arm_cortexa8/mx51/interrupts.c
> >> > new file mode 100644
> >> > index 0000000..c0d70ac
> >> > --- /dev/null
> >> > +++ b/cpu/arm_cortexa8/mx51/interrupts.c
> >> <snip>
> >> What's means?
>
> Ignore the <snip> comments.
>
> >> > diff --git a/cpu/arm_cortexa8/mx51/serial.c
> >> > b/cpu/arm_cortexa8/mx51/serial.c
> >> > new file mode 100644
> >> > index 0000000..580ac13
> >> > --- /dev/null
> >> > +++ b/cpu/arm_cortexa8/mx51/serial.c
> >>
> >> I haven't looked in the details of the serial driver, but would it be
> >> possible to use drivers/serial/serial_mxc.c
> >> instead? It looks very similar.
> >> I don't like the implement of this driver. It contains the chip details
> in
> >> driver code.
> >>
> >> But I will do what as your said. And restructure this driver in another
> >> patch.
>
> That sounds like a good idea if you want to improve the serial driver.
> Create a separate standalone patch so people can review and test that.
>
> Regards, Magnus
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
2009-09-22 20:04 ` Magnus Lilja
@ 2009-09-22 20:29 ` Fred Fan
0 siblings, 0 replies; 15+ messages in thread
From: Fred Fan @ 2009-09-22 20:29 UTC (permalink / raw)
To: u-boot
HI Magnus Lilja:
Best Regards
Fred
2009/9/23, Magnus Lilja <lilja.magnus@gmail.com>:
>
>
> Hmm, for some reason "Reply" in gmail cut part of the qouted message so
> here's the rest of the followup.
>
> Fred Fan skrev:
> > Hi Magnus Liljia:
> > Thanks for your comments.
> > Best Regards
> > Fred
> >
> > 2009/9/22, Magnus Lilja <lilja.magnus@gmail.com>:
> >
> >> Hi
> >>
> >>
> >> I've scanned the patch briefly and have some comments below.
> >>
> >> gareatech at gmail.com wrote:
> >> I don't think everything in this file is needed by U-Boot, e.g. the
> >> interrupt definitions.
> >> Yes. But interrupt maybe use when interrupt is supportted. Do I need
> remove
> >> the definitions which are not used?
>
> Don't know.
> We have plan to support interrupt in furture.
>>> diff --git a/include/configs/imx51.h b/include/configs/imx51.h
> >>> new file mode 100644
> >>> index 0000000..f0def4e
> >>> --- /dev/null
> >>> +++ b/include/configs/imx51.h
> >>> @@ -0,0 +1,177 @@
> >>> +/*
> >>> + * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
> >>> + *
> >>> + * (C) Copyright 2009 Freescale Semiconductor, Inc.
> >>> + *
> >>> + * Configuration settings for the MX51-3Stack Freescale board.
> >>> + *
> >>> + * This program is free software; you can redistribute it and/or
> >>> + * modify it under the terms of the GNU General Public License as
> >>> + * published by the Free Software Foundation; either version 2 of
> >>> + * the License, or (at your option) any later version.
> >>> + *
> >>> + * This program is distributed in the hope that it will be useful,
> >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >>> + * GNU General Public License for more details.
> >>> + *
> >>> + * You should have received a copy of the GNU General Public License
> >>> + * along with this program; if not, write to the Free Software
> >>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> >>> + * MA 02111-1307 USA
> >>> + */
> >>> +
> >>> +#ifndef __CONFIG_H
> >>> +#define __CONFIG_H
> >>> +
> >>> +#include <asm/arch/mx51.h>
> >>> +
> >>> + /* High Level Configuration Options */
> >>> +#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU
> core
> >> */
> >>> +#define CONFIG_L2_OFF
> >>> +
> >>> +#define CONFIG_MXC 1
> >>> +#define CONFIG_MX51_BBG 1 /* in a mx51 */
> >> Can't see that this is used anywhere.
> >> OK. I will remove them;
>
> Only remove MX51_BBG, I didn't check if CONFIG_MXC is used anywhere.
> OK.
>
> Regards, Magnus
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
@ 2009-09-23 14:47 Fred Fan
2009-09-23 21:47 ` Wolfgang Denk
2009-09-24 4:35 ` Prafulla Wadaskar
0 siblings, 2 replies; 15+ messages in thread
From: Fred Fan @ 2009-09-23 14:47 UTC (permalink / raw)
To: u-boot
This patch just supports boot into u-boot from mmc or spi-nor flash.
It just implements console, iomux and clock. There are no ethernet,
nor-flash, mmc or other peripheral drivers.
Signed-off-by: Fred.Fan <fanyefeng@gmail.com>
Signed-off-by: Fred.Fan <r01011@freescale.com>
---
MAINTAINERS | 4 +
MAKEALL | 1 +
Makefile | 3 +
board/freescale/mx51_babbage/Makefile | 49 ++
board/freescale/mx51_babbage/board-mx51_babbage.h | 64 ++
board/freescale/mx51_babbage/config.mk | 2 +
| 119 ++++
board/freescale/mx51_babbage/lowlevel_init.S | 245 ++++++++
board/freescale/mx51_babbage/mx51_babbage.c | 237 ++++++++
board/freescale/mx51_babbage/u-boot.lds | 72 +++
cpu/arm_cortexa8/mx51/Makefile | 50 ++
cpu/arm_cortexa8/mx51/clock.c | 237 ++++++++
cpu/arm_cortexa8/mx51/crm_regs.h | 673 +++++++++++++++++++++
cpu/arm_cortexa8/mx51/interrupts.c | 33 +
cpu/arm_cortexa8/mx51/iomux.c | 199 ++++++
cpu/arm_cortexa8/mx51/soc.c | 66 ++
cpu/arm_cortexa8/mx51/timer.c | 112 ++++
drivers/serial/serial_mxc.c | 6 +
include/asm-arm/arch-mx51/iomux.h | 240 ++++++++
include/asm-arm/arch-mx51/mx51.h | 416 +++++++++++++
include/asm-arm/arch-mx51/mx51_pins.h | 370 +++++++++++
include/configs/mx51_babbage.h | 174 ++++++
22 files changed, 3372 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 620604c..260c37e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -549,6 +549,10 @@ Fabio Estevam <Fabio.Estevam@freescale.com>
mx31pdk i.MX31
+Fred Fan <fanyefeng@gmail.com>
+
+ mx51_babbage i.MX51
+
Peter Figuli <peposh@etc.sk>
wepep250 xscale
diff --git a/MAKEALL b/MAKEALL
index edebaea..852baf1 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -581,6 +581,7 @@ LIST_ARM_CORTEX_A8=" \
omap3_pandora \
omap3_zoom1 \
omap3_zoom2 \
+ mx51_babbage \
"
#########################################################################
diff --git a/Makefile b/Makefile
index e4499d7..b4e65ff 100644
--- a/Makefile
+++ b/Makefile
@@ -3229,6 +3229,9 @@ mx31pdk_nand_config : unconfig
fi
@$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
+mx51_babbage_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51_babbage freescale mx51
+
omap2420h4_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx
diff --git a/board/freescale/mx51_babbage/Makefile b/board/freescale/mx51_babbage/Makefile
new file mode 100644
index 0000000..7e33861
--- /dev/null
+++ b/board/freescale/mx51_babbage/Makefile
@@ -0,0 +1,49 @@
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := mx51_babbage.o
+SOBJS := lowlevel_init.o flash_header.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx51_babbage/board-mx51_babbage.h b/board/freescale/mx51_babbage/board-mx51_babbage.h
new file mode 100644
index 0000000..31e3875
--- /dev/null
+++ b/board/freescale/mx51_babbage/board-mx51_babbage.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __BOARD_FREESCALE_BOARD_MX51_BABBAGE_H__
+#define __BOARD_FREESCALE_BOARD_MX51_BABBAGE_H__
+
+/*!
+ * @defgroup BRDCFG_MX51_BABBAGE Board Configuration Options
+ * @ingroup MSL_MX51_BABBAGE
+ */
+
+/*!
+ * @file mx51_babbage/board-mx51_babbage.h
+ *
+ * @brief This file contains all the board level configuration options.
+ *
+ * It currently hold the options defined for MX51 babbage Platform.
+ *
+ * @ingroup BRDCFG_MX51_BABBAGE
+ */
+
+/* CPLD offsets */
+#define PBC_LED_CTRL (0x20000)
+#define PBC_SB_STAT (0x20008)
+#define PBC_ID_AAAA (0x20040)
+#define PBC_ID_5555 (0x20048)
+#define PBC_VERSION (0x20050)
+#define PBC_ID_CAFE (0x20058)
+#define PBC_INT_STAT (0x20010)
+#define PBC_INT_MASK (0x20038)
+#define PBC_INT_REST (0x20020)
+#define PBC_SW_RESET (0x20060)
+
+/* LED switchs */
+#define LED_SWITCH_REG 0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG 0x08
+/* status, interrupt */
+#define INTR_STATUS_REG 0x10
+#define INTR_MASK_REG 0x38
+#define INTR_RESET_REG 0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG 0x40
+#define MAGIC_NUMBER2_REG 0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG 0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG 0x58
+/* module reset register*/
+#define MODULE_RESET_REG 0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG 0x68
+
+#endif /* __BOARD_FREESCALE_BOARD_MX51_BABBAGE_H__ */
diff --git a/board/freescale/mx51_babbage/config.mk b/board/freescale/mx51_babbage/config.mk
new file mode 100644
index 0000000..d8b0f10
--- /dev/null
+++ b/board/freescale/mx51_babbage/config.mk
@@ -0,0 +1,2 @@
+LDSCRIPT = board/$(VENDOR)/$(BOARD)/u-boot.lds
+TEXT_BASE = 0x97800000
--git a/board/freescale/mx51_babbage/flash_header.S b/board/freescale/mx51_babbage/flash_header.S
new file mode 100644
index 0000000..bbac2c1
--- /dev/null
+++ b/board/freescale/mx51_babbage/flash_header.S
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*!
+ * @file mx51_babbage/flash_head.S
+ * @brief Thie file contains the information as the image header for boot.
+ * The boot rom code will parse this structure , load image and initial
+ * hardware as the description of hardware setting.
+ */
+
+#include <config.h>
+#include <asm/arch/mx51.h>
+#include "board-mx51_babbage.h"
+
+#ifdef CONFIG_FLASH_HEADER
+#ifndef CONFIG_FLASH_HEADER_OFFSET
+# error "Must define the offset of flash header"
+#endif
+#define MXC_DCD_ITEM(i, type, addr, val) \
+dcd_node_##i: \
+ .word type ; \
+ .word addr ; \
+ .word val ; \
+
+.section ".text.flasheader", "x"
+ b _start
+ .org CONFIG_FLASH_HEADER_OFFSET
+app_code_jump_v: .word _start
+app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER
+app_code_csf: .word 0
+dcd_ptr_ptr: .word dcd_ptr
+super_root_key: .word 0
+dcd_ptr: .word dcd_array_start
+app_dest_ptr: .word TEXT_BASE
+dcd_array_start:
+magic: .word 0xB17219E9
+dcd_array_size: .word dcd_data_end - dcd_array_start - 8
+/* DCD */
+/* DDR2 IOMUX configuration */
+MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
+MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
+MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
+MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
+MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
+MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
+MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
+MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
+MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
+MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
+MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
+MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
+MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
+MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
+MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
+MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
+MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
+MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
+/* Set drive strength to MAX */
+MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6)
+MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6)
+MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6)
+MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6)
+/* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
+/* CAS=3, BL=4 */
+MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
+MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
+MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
+MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
+MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
+/* Init DRAM on CS0 */
+MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
+MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
+MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
+MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
+MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
+MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
+MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
+MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
+/* Init DRAM on CS1 */
+MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
+MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
+MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
+MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
+MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
+MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
+MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
+MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
+MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
+MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
+MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
+MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
+MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
+dcd_data_end:
+image_len: .word 0x100000
+#endif
diff --git a/board/freescale/mx51_babbage/lowlevel_init.S b/board/freescale/mx51_babbage/lowlevel_init.S
new file mode 100644
index 0000000..bf536b1
--- /dev/null
+++ b/board/freescale/mx51_babbage/lowlevel_init.S
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/mx51.h>
+#include "board-mx51_babbage.h"
+
+/*
+ * return soc version
+ * 0x10: TO1
+ * 0x20: TO2
+ * 0x30: TO3
+ */
+.macro check_soc_version ret, tmp
+.endm
+
+/*
+ * L2CC Cache setup/invalidation/disable
+ */
+.macro init_l2cc
+ /* reconfigure L2 cache aux control reg */
+ ldr r0, =0x03C000C4
+ mcr p15, 1, r0, c9, c0, 2
+.endm /* init_l2cc */
+
+/* AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.*/
+.macro init_aips
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ ldr r0, =AIPS1_BASE_ADDR
+ ldr r1, =0x77777777
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+ ldr r0, =AIPS2_BASE_ADDR
+ str r1, [r0, #0x0]
+ str r1, [r0, #0x4]
+ /*
+ * Clear the on and off peripheral modules Supervisor Protect bit
+ * for SDMA to access them. Did not change the AIPS control registers
+ * (offset 0x20) access type
+ */
+.endm /* init_aips */
+
+/* MAX (Multi-Layer AHB Crossbar Switch) setup */
+.macro init_max
+.endm /* init_max */
+
+/* M4IF setup */
+.macro init_m4if
+ /* VPU and IPU given higher priority (0x4)
+ * IPU accesses with ID=0x1 given highest priority (=0xA)
+ */
+ ldr r0, =M4IF_BASE_ADDR
+
+ ldr r1, =0x00000203
+ str r1, [r0, #0x40]
+
+ ldr r1, =0x0
+ str r1, [r0, #0x44]
+
+ ldr r1, =0x00120125
+ str r1, [r0, #0x9C]
+
+ ldr r1, =0x001901A3
+ str r1, [r0, #0x48]
+
+/*
+ ldr r1, =0x00000a01
+ str r1, [r0, #0x48]
+ ldr r1, =0x00000404
+ str r1, [r0, #0x40]
+*/
+.endm /* init_m4if */
+
+.macro setup_pll pll, freq
+ ldr r2, =\pll
+ ldr r1, =0x00001232
+ str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ mov r1, #0x2
+ str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+ str r3, [r2, #PLL_DP_OP]
+ str r3, [r2, #PLL_DP_HFS_OP]
+
+ str r4, [r2, #PLL_DP_MFD]
+ str r4, [r2, #PLL_DP_HFS_MFD]
+
+ str r5, [r2, #PLL_DP_MFN]
+ str r5, [r2, #PLL_DP_HFS_MFN]
+
+ ldr r1, =0x00001232
+ str r1, [r2, #PLL_DP_CTL]
+1: ldr r1, [r2, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+ beq 1b
+.endm
+
+.macro init_clock
+ ldr r0, =CCM_BASE_ADDR
+ mov r1, #0x00060000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+
+ mov r3, #DP_OP_800
+ mov r4, #DP_MFD_800
+ mov r5, #DP_MFN_800
+ setup_pll PLL1_BASE_ADDR
+ mov r3, #DP_OP_665
+ mov r4, #DP_MFD_665
+ mov r5, #DP_MFN_665
+ setup_pll PLL3_BASE_ADDR
+
+ /* Switch peripheral to PLL 3 */
+ ldr r1, =0x0000D3C0
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, =0x033B9145
+ str r1, [r0, #CLKCTL_CBCDR]
+ mov r3, #DP_OP_665
+ mov r4, #DP_MFD_665
+ mov r5, #DP_MFN_665
+ setup_pll PLL2_BASE_ADDR
+
+ /* Switch peripheral to PLL2 */
+ ldr r1, =0x013B9145
+ str r1, [r0, #CLKCTL_CBCDR]
+ ldr r1, =0x0000E3C0
+ str r1, [r0, #CLKCTL_CBCMR]
+
+ mov r3, #DP_OP_216
+ mov r4, #DP_MFD_216
+ mov r5, #DP_MFN_216
+ setup_pll PLL3_BASE_ADDR
+
+ /* Set the platform clock dividers */
+ ldr r2, =ARM_BASE_ADDR
+ ldr r1, =0x00000725
+ str r1, [r2, #0x14]
+
+ /* Switch ARM back to PLL 1 */
+ mov r1, #0
+ str r1, [r0, #CLKCTL_CCSR]
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Use lp_apm (24MHz) source for perclk */
+ mov r2, #0x48
+ ldr r2, [r0]
+ cmp r2, #0x10
+ ldrhs r1, =0x000020C2
+ ldrlo r1, =0x0000E3C2
+ str r1, [r0, #CLKCTL_CBCMR]
+ /* TO1.x emi = ahb, all perclk dividers are 1 since using 24MHz */
+ /* TO2.x ddr from PLL1, all perclk dividers are 1 since using 24MHz */
+ ldrhs r1, =0x59239100
+ ldrlo r1, =0x013D9100
+ strlo r1, [r0, #CLKCTL_CBCDR]
+
+ /* use PLL2 for UART source, get 66.5MHz */
+ ldr r1, =0xA5A2A020
+ str r1, [r0, #CLKCTL_CSCMR1]
+ ldr r1, =0x00C30321
+ str r1, [r0, #CLKCTL_CSCDR1]
+
+ /* make sure divider effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0
+ bne 1b
+
+ mov r1, #0x0
+ str r1, [r0, #CLKCTL_CCDR]
+.endm
+
+.macro setup_wdog
+ ldr r0, =WDOG1_BASE_ADDR
+ mov r1, #0x30
+ strh r1, [r0]
+.endm
+
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+ /* Platform CHIP level init*/
+ ldr r0, =GPIO1_BASE_ADDR
+ ldr r1, [r0, #0x0]
+ orr r1, r1, #(1 << 23)
+ str r1, [r0, #0x0]
+ ldr r1, [r0, #0x4]
+ orr r1, r1, #(1 << 23)
+ str r1, [r0, #0x4]
+
+ mrc 15, 0, r1, c1, c0, 0
+
+ mrc 15, 0, r0, c1, c0, 1
+ bic r0, r0, #7
+ mcr 15, 0, r0, c1, c0, 1
+
+ mcr 15, 0, r1, c1, c0, 0
+
+ mov r0, #0
+ mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
+ init_l2cc
+
+ init_aips
+
+ init_max
+
+ init_m4if
+
+ init_clock
+
+ /* r12 saved upper lr*/
+ mov pc, lr
+
+/* Board level setting value */
+DDR_PERCHARGE_CMD: .word 0x04008008
+DDR_REFRESH_CMD: .word 0x00008010
+DDR_LMR1_W: .word 0x00338018
+DDR_LMR_CMD: .word 0xB2220000
+DDR_TIMING_W: .word 0xB02567A9
+DDR_MISC_W: .word 0x000A0104
diff --git a/board/freescale/mx51_babbage/mx51_babbage.c b/board/freescale/mx51_babbage/mx51_babbage.c
new file mode 100644
index 0000000..54c1c3e
--- /dev/null
+++ b/board/freescale/mx51_babbage/mx51_babbage.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx51.h>
+#include <asm/arch/mx51_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/errno.h>
+#include <i2c.h>
+#include "board-mx51_babbage.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u32 system_rev;
+u32 mx51_io_base_addr;
+volatile u32 *esdhc_base_pointer;
+
+u32 get_board_rev(void)
+{
+ return system_rev;
+}
+
+static inline void setup_soc_rev(void)
+{
+ int reg;
+
+ reg = __raw_readl(ROM_SI_REV);
+ switch (reg) {
+ case 0x02:
+ system_rev = 0x51000 | CHIP_REV_1_1;
+ break;
+ case 0x10:
+ if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
+ system_rev = 0x51000 | CHIP_REV_2_5;
+ else
+ system_rev = 0x51000 | CHIP_REV_2_0;
+ break;
+ default:
+ system_rev = 0x51000 | CHIP_REV_1_0;
+ break;
+ }
+}
+
+static inline void set_board_rev(int rev)
+{
+ system_rev |= (rev & 0xF) << 8;
+}
+
+inline int is_soc_rev(int rev)
+{
+ return (system_rev & 0xFF) - rev;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+static void setup_uart(void)
+{
+ unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
+ PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
+
+ mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
+ mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
+ mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
+}
+
+void setup_nfc(void)
+{
+ /* Enable NFC IOMUX */
+ mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT0);
+ mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT0);
+}
+
+static void setup_expio(void)
+{
+ u32 reg;
+
+ /* CS5 setup */
+ mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
+ writel(0x00410089, WEIM_BASE_ADDR + 0x78 + CSGCR1);
+ writel(0x00000002, WEIM_BASE_ADDR + 0x78 + CSGCR2);
+ /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
+ writel(0x32260000, WEIM_BASE_ADDR + 0x78 + CSRCR1);
+ /* APR = 0 */
+ writel(0x00000000, WEIM_BASE_ADDR + 0x78 + CSRCR2);
+ /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
+ * WCSA=0, WCSN=0
+ */
+ writel(0x72080F00, WEIM_BASE_ADDR + 0x78 + CSWCR1);
+ if ((readw(CS5_BASE_ADDR + PBC_ID_AAAA) == 0xAAAA) &&
+ (readw(CS5_BASE_ADDR + PBC_ID_5555) == 0x5555)) {
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
+ reg = readl(CCM_BASE_ADDR + CLKCTL_CBCDR);
+ reg = (reg & (~0x70000)) | 0x30000;
+ writel(reg, CCM_BASE_ADDR + CLKCTL_CBCDR);
+ /* make sure divider effective */
+ while (readl(CCM_BASE_ADDR + CLKCTL_CDHIPR) != 0)
+ ;
+ writel(0x0, CCM_BASE_ADDR + CLKCTL_CCDR);
+ }
+ mx51_io_base_addr = CS5_BASE_ADDR;
+ } else {
+ /* CS1 */
+ writel(0x00410089, WEIM_BASE_ADDR + 0x18 + CSGCR1);
+ writel(0x00000002, WEIM_BASE_ADDR + 0x18 + CSGCR2);
+ /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
+ writel(0x32260000, WEIM_BASE_ADDR + 0x18 + CSRCR1);
+ /* APR=0 */
+ writel(0x00000000, WEIM_BASE_ADDR + 0x18 + CSRCR2);
+ /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
+ * WEN=0, WCSA=0, WCSN=0
+ */
+ writel(0x72080F00, WEIM_BASE_ADDR + 0x18 + CSWCR1);
+ mx51_io_base_addr = CS1_BASE_ADDR;
+ }
+
+ /* Reset interrupt status reg */
+ writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
+ writew(0x00, mx51_io_base_addr + PBC_INT_REST);
+ writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
+
+ /* Reset the XUART and Ethernet controllers */
+ reg = readw(mx51_io_base_addr + PBC_SW_RESET);
+ reg |= 0x9;
+ writew(reg, mx51_io_base_addr + PBC_SW_RESET);
+ reg &= ~0x9;
+ writew(reg, mx51_io_base_addr + PBC_SW_RESET);
+}
+
+#ifdef CONFIG_NET_MULTI
+
+#if defined(CONFIG_DRIVER_SMC911X)
+extern int smc911x_initialize(bd_t *bis);
+#endif
+int board_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+#if defined(CONFIG_DRIVER_SMC911X)
+ rc = smc911x_initialize(bis);
+#endif
+
+ return rc;
+}
+#endif
+
+int board_init(void)
+{
+ setup_soc_rev();
+
+ /* board id for linux */
+ gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ setup_uart();
+ setup_nfc();
+ setup_expio();
+ return 0;
+}
+
+#ifdef BOARD_LATE_INIT
+int board_late_init(void)
+{
+ return 0;
+}
+#endif
+
+int checkboard(void)
+{
+ printf("Board: MX51 BABBAGE ");
+
+ if (system_rev & CHIP_REV_2_5)
+ printf("2.5 [");
+ else if (system_rev & CHIP_REV_2_0)
+ printf("2.0 [");
+ else if (system_rev & CHIP_REV_1_1)
+ printf("1.1 [");
+ else
+ printf("1.0 [");
+
+ switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
+ case 0x0001:
+ printf("POR");
+ break;
+ case 0x0009:
+ printf("RST");
+ break;
+ case 0x0010:
+ case 0x0011:
+ printf("WDOG");
+ break;
+ default:
+ printf("unknown");
+ break;
+ }
+ printf("]\n");
+ return 0;
+}
+
diff --git a/board/freescale/mx51_babbage/u-boot.lds b/board/freescale/mx51_babbage/u-boot.lds
new file mode 100644
index 0000000..f608a6d
--- /dev/null
+++ b/board/freescale/mx51_babbage/u-boot.lds
@@ -0,0 +1,72 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+ board/freescale/mx51_babbage/flash_header.o (.text.flasheader)
+ cpu/arm_cortexa8/start.o
+ board/freescale/mx51_babbage/libmx51_babbage.a (.text)
+ lib_arm/libarm.a (.text)
+ net/libnet.a (.text)
+ drivers/mtd/libmtd.a (.text)
+ drivers/mmc/libmmc.a (.text)
+
+ . = DEFINED(env_offset) ? env_offset : .;
+
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/cpu/arm_cortexa8/mx51/Makefile b/cpu/arm_cortexa8/mx51/Makefile
new file mode 100644
index 0000000..fc7e755
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS-y = soc.o timer.o clock.o iomux.o
+SOBJS-y =
+
+COBJS-$(CONFIG_USE_IRQ) += interrupts.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm_cortexa8/mx51/clock.c b/cpu/arm_cortexa8/mx51/clock.c
new file mode 100644
index 0000000..3abcdc8
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/clock.c
@@ -0,0 +1,237 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx51.h>
+#include <asm/errno.h>
+#include "crm_regs.h"
+
+enum pll_clocks {
+ PLL1_CLK = MXC_DPLL1_BASE,
+ PLL2_CLK = MXC_DPLL2_BASE,
+ PLL3_CLK = MXC_DPLL3_BASE,
+};
+
+enum pll_sw_clocks {
+ PLL1_SW_CLK,
+ PLL2_SW_CLK,
+ PLL3_SW_CLK,
+};
+
+static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
+{
+ u32 mfi, mfn, mfd, pd;
+
+ mfn = __raw_readl(pll + MXC_PLL_DP_MFN);
+ mfd = __raw_readl(pll + MXC_PLL_DP_MFD) + 1;
+ mfi = __raw_readl(pll + MXC_PLL_DP_OP);
+ pd = (mfi & 0xF) + 1;
+ mfi = (mfi >> 4) & 0xF;
+ mfi = (mfi >= 5) ? mfi : 5;
+
+ return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
+}
+
+u32 __get_mcu_main_clk(void)
+{
+ u32 reg, freq;
+
+ reg = (__raw_readl(MXC_CCM_CACRR) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
+ MXC_CCM_CACRR_ARM_PODF_OFFSET;
+ freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
+ return freq / (reg + 1);
+}
+
+static u32 __get_periph_clk(void)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+ reg = __raw_readl(MXC_CCM_CBCMR);
+ switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
+ MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+ case 0:
+ return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
+ case 1:
+ return __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
+ default:
+ return 0;
+ }
+ }
+ return __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
+}
+
+static u32 __get_ipg_clk(void)
+{
+ u32 ahb_podf, ipg_podf;
+
+ ahb_podf = __raw_readl(MXC_CCM_CBCDR);
+ ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
+ MXC_CCM_CBCDR_IPG_PODF_OFFSET;
+ ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
+ MXC_CCM_CBCDR_AHB_PODF_OFFSET;
+ return __get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1));
+}
+
+static u32 __get_ipg_per_clk(void)
+{
+ u32 pred1, pred2, podf;
+
+ if (__raw_readl(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
+ return __get_ipg_clk();
+ /* Fixme: not handle what about lpm*/
+ podf = __raw_readl(MXC_CCM_CBCDR);
+ pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
+ pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
+ podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
+ MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
+
+ return __get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
+}
+
+static u32 __get_uart_clk(void)
+{
+ unsigned int freq, reg, pred, podf;
+
+ reg = __raw_readl(MXC_CCM_CSCMR1);
+ switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
+ MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
+ case 0x0:
+ freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
+ break;
+ case 0x1:
+ freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
+ break;
+ case 0x2:
+ freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
+ break;
+ default:
+ return 66500000;
+ }
+
+ reg = __raw_readl(MXC_CCM_CSCDR1);
+
+ pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
+ MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
+
+ podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+ freq /= (pred + 1) * (podf + 1);
+
+ return freq;
+}
+
+/*!
++ * This function returns the low power audio clock.
++ */
+u32 get_lp_apm(void)
+{
+ u32 ret_val = 0;
+ u32 ccsr = __raw_readl(MXC_CCM_CCSR);
+
+ if (((ccsr >> 9) & 1) == 0)
+ ret_val = CONFIG_MX51_HCLK_FREQ;
+ else
+ ret_val = ((32768 * 1024));
+
+ return ret_val;
+}
+
+static u32 __get_cspi_clk(void)
+{
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel;
+ u32 cscmr1 = __raw_readl(MXC_CCM_CSCMR1);
+ u32 cscdr2 = __raw_readl(MXC_CCM_CSCDR2);
+
+ pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
+ >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
+ pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
+ >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
+ clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
+ >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+
+ switch (clk_sel) {
+ case 0:
+ ret_val = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case 1:
+ ret_val = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ case 2:
+ ret_val = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ) /
+ ((pre_pdf + 1) * (pdf + 1));
+ break;
+ default:
+ ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
+ break;
+ }
+
+ return ret_val;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return __get_mcu_main_clk();
+ case MXC_AHB_CLK:
+ break;
+ case MXC_IPG_CLK:
+ return __get_ipg_clk();
+ case MXC_IPG_PERCLK:
+ return __get_ipg_per_clk();
+ case MXC_UART_CLK:
+ return __get_uart_clk();
+ case MXC_CSPI_CLK:
+ return __get_cspi_clk();
+ case MXC_FEC_CLK:
+ return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
+ default:
+ break;
+ }
+ return -1;
+}
+
+void mxc_show_clocks(void)
+{
+ u32 freq;
+
+ freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
+ printf("mx51 pll1: %dMHz\n", freq / 1000000);
+ freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
+ printf("mx51 pll2: %dMHz\n", freq / 1000000);
+ freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
+ printf("mx51 pll3: %dMHz\n", freq / 1000000);
+ printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
+ printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
+ printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
+ printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK));
+}
diff --git a/cpu/arm_cortexa8/mx51/crm_regs.h b/cpu/arm_cortexa8/mx51/crm_regs.h
new file mode 100644
index 0000000..6436bed
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/crm_regs.h
@@ -0,0 +1,673 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
+
+#define MXC_CCM_BASE CCM_BASE_ADDR
+#define MXC_DPLL1_BASE PLL1_BASE_ADDR
+#define MXC_DPLL2_BASE PLL2_BASE_ADDR
+#define MXC_DPLL3_BASE PLL3_BASE_ADDR
+
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL 0x00
+#define MXC_PLL_DP_CONFIG 0x04
+#define MXC_PLL_DP_OP 0x08
+#define MXC_PLL_DP_MFD 0x0C
+#define MXC_PLL_DP_MFN 0x10
+#define MXC_PLL_DP_MFNMINUS 0x14
+#define MXC_PLL_DP_MFNPLUS 0x18
+#define MXC_PLL_DP_HFS_OP 0x1C
+#define MXC_PLL_DP_HFS_MFD 0x20
+#define MXC_PLL_DP_HFS_MFN 0x24
+#define MXC_PLL_DP_MFN_TOGC 0x28
+#define MXC_PLL_DP_DESTAT 0x2c
+
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
+#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12
+#define MXC_PLL_DP_CTL_ADE 0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8)
+#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8
+#define MXC_PLL_DP_CTL_HFSM 0x80
+#define MXC_PLL_DP_CTL_PRE 0x40
+#define MXC_PLL_DP_CTL_UPEN 0x20
+#define MXC_PLL_DP_CTL_RST 0x10
+#define MXC_PLL_DP_CTL_RCP 0x8
+#define MXC_PLL_DP_CTL_PLM 0x4
+#define MXC_PLL_DP_CTL_BRM0 0x2
+#define MXC_PLL_DP_CTL_LRF 0x1
+
+#define MXC_PLL_DP_CONFIG_BIST 0x8
+#define MXC_PLL_DP_CONFIG_SJC_CE 0x4
+#define MXC_PLL_DP_CONFIG_AREN 0x2
+#define MXC_PLL_DP_CONFIG_LDREQ 0x1
+
+#define MXC_PLL_DP_OP_MFI_OFFSET 4
+#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4)
+#define MXC_PLL_DP_OP_PDF_OFFSET 0
+#define MXC_PLL_DP_OP_PDF_MASK 0xF
+
+#define MXC_PLL_DP_MFD_OFFSET 0
+#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_OFFSET 0x0
+#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF
+
+#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17)
+#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16)
+#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0
+#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF
+
+#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31)
+#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF
+
+/* Register addresses of CCM*/
+#define MXC_CCM_CCR (MXC_CCM_BASE + 0x00)
+#define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04)
+#define MXC_CCM_CSR (MXC_CCM_BASE + 0x08)
+#define MXC_CCM_CCSR (MXC_CCM_BASE + 0x0C)
+#define MXC_CCM_CACRR (MXC_CCM_BASE + 0x10)
+#define MXC_CCM_CBCDR (MXC_CCM_BASE + 0x14)
+#define MXC_CCM_CBCMR (MXC_CCM_BASE + 0x18)
+#define MXC_CCM_CSCMR1 (MXC_CCM_BASE + 0x1C)
+#define MXC_CCM_CSCMR2 (MXC_CCM_BASE + 0x20)
+#define MXC_CCM_CSCDR1 (MXC_CCM_BASE + 0x24)
+#define MXC_CCM_CS1CDR (MXC_CCM_BASE + 0x28)
+#define MXC_CCM_CS2CDR (MXC_CCM_BASE + 0x2C)
+#define MXC_CCM_CDCDR (MXC_CCM_BASE + 0x30)
+#define MXC_CCM_CHSCDR (MXC_CCM_BASE + 0x34)
+#define MXC_CCM_CSCDR2 (MXC_CCM_BASE + 0x38)
+#define MXC_CCM_CSCDR3 (MXC_CCM_BASE + 0x3C)
+#define MXC_CCM_CSCDR4 (MXC_CCM_BASE + 0x40)
+#define MXC_CCM_CWDR (MXC_CCM_BASE + 0x44)
+#define MXC_CCM_CDHIPR (MXC_CCM_BASE + 0x48)
+#define MXC_CCM_CDCR (MXC_CCM_BASE + 0x4C)
+#define MXC_CCM_CTOR (MXC_CCM_BASE + 0x50)
+#define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x54)
+#define MXC_CCM_CISR (MXC_CCM_BASE + 0x58)
+#define MXC_CCM_CIMR (MXC_CCM_BASE + 0x5C)
+#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x60)
+#define MXC_CCM_CGPR (MXC_CCM_BASE + 0x64)
+#define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x68)
+#define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x6C)
+#define MXC_CCM_CCGR2 (MXC_CCM_BASE + 0x70)
+#define MXC_CCM_CCGR3 (MXC_CCM_BASE + 0x74)
+#define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78)
+#define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C)
+#define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80)
+#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x84)
+
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN (1 << 12)
+#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11)
+#define MXC_CCM_CCR_CAMP2_EN (1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN (1 << 9)
+#define MXC_CCM_CCR_FPM_EN (1 << 8)
+#define MXC_CCM_CCR_OSCNT_OFFSET (0)
+#define MXC_CCM_CCR_OSCNT_MASK (0xFF)
+
+/* Define the bits in register CCDR */
+#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18)
+#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
+#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16)
+
+/* Define the bits in register CSR */
+#define MXC_CCM_CSR_COSR_READY (1 << 5)
+#define MXC_CCM_CSR_LVS_VALUE (1 << 4)
+#define MXC_CCM_CSR_CAMP2_READY (1 << 3)
+#define MXC_CCM_CSR_CAMP1_READY (1 << 2)
+#define MXC_CCM_CSR_FPM_READY (1 << 1)
+#define MXC_CCM_CSR_REF_EN_B (1 << 0)
+
+/* Define the bits in register CCSR */
+#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9)
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7)
+#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
+#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5)
+#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5)
+#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3)
+#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
+
+/* Define the bits in register CACRR */
+#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0)
+#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7)
+
+/* Define the bits in register CBCDR */
+#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
+#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
+#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22)
+#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19)
+#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16)
+#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13)
+#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
+#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10)
+#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8)
+#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0)
+#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7)
+
+/* Define the bits in register CBCMR */
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
+
+/* Define the bits in register CSCMR1 */
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26)
+#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
+#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
+#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
+#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
+#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1)
+
+/* Define the bits in register CSCMR2 */
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET (26)
+#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK (0x7 << 26)
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24)
+#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22)
+#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22)
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20)
+#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18)
+#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18)
+#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16)
+#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14)
+#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12)
+#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10)
+#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9)
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6)
+#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6)
+#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5)
+#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2)
+#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0)
+#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3)
+
+/* Define the bits in register CSCDR1 */
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7)
+
+/* Define the bits in register CS1CDR and CS2CDR */
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16)
+#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F)
+
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16)
+#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F)
+
+/* Define the bits in register CDCDR */
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28)
+#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3)
+#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0)
+#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7)
+
+/* Define the bits in register CHSCCDR */
+#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6)
+#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6)
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3)
+#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3)
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7)
+
+/* Define the bits in register CSCDR2 */
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F)
+
+/* Define the bits in register CSCDR3 */
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F)
+
+/* Define the bits in register CSCDR4 */
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9)
+#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0)
+#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F)
+
+/* Define the bits in register CDHIPR */
+#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
+#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6)
+#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
+#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4)
+#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3)
+#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2)
+#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1)
+#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0)
+
+/* Define the bits in register CDCR */
+#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0)
+#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3)
+
+/* Define the bits in register CLPCR */
+#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
+#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
+#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
+#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
+#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
+#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
+#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17)
+#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16)
+#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11)
+#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9)
+#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
+#define MXC_CCM_CLPCR_VSTBY (0x1 << 8)
+#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7)
+#define MXC_CCM_CLPCR_SBYOS (0x1 << 6)
+#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3)
+#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
+#define MXC_CCM_CLPCR_LPM_OFFSET (0)
+#define MXC_CCM_CLPCR_LPM_MASK (0x3)
+
+/* Define the bits in register CISR */
+#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25)
+#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
+#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20)
+#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19)
+#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18)
+#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17)
+#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16)
+#define MXC_CCM_CISR_COSC_READY (0x1 << 6)
+#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5)
+#define MXC_CCM_CISR_CKIH_READY (0x1 << 4)
+#define MXC_CCM_CISR_FPM_READY (0x1 << 3)
+#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2)
+#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1)
+#define MXC_CCM_CISR_LRF_PLL1 (0x1)
+
+/* Define the bits in register CIMR */
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25)
+#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21)
+#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20)
+#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19)
+#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18)
+#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17)
+#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16)
+#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5)
+#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4)
+#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3)
+#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2)
+#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1)
+#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1)
+
+/* Define the bits in register CCOSR */
+#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24)
+#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21)
+#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
+#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16)
+#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
+#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
+#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4)
+#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
+#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0)
+#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF)
+
+/* Define the bits in registers CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4)
+#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3)
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0)
+#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7)
+
+/* Define the bits in registers CCGRx */
+#define MXC_CCM_CCGR_CG_MASK 0x3
+
+#define MXC_CCM_CCGR0_CG15_OFFSET 30
+#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
+#define MXC_CCM_CCGR0_CG14_OFFSET 28
+#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
+#define MXC_CCM_CCGR0_CG13_OFFSET 26
+#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
+#define MXC_CCM_CCGR0_CG12_OFFSET 24
+#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
+#define MXC_CCM_CCGR0_CG11_OFFSET 22
+#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
+#define MXC_CCM_CCGR0_CG10_OFFSET 20
+#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
+#define MXC_CCM_CCGR0_CG9_OFFSET 18
+#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
+#define MXC_CCM_CCGR0_CG8_OFFSET 16
+#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
+#define MXC_CCM_CCGR0_CG7_OFFSET 14
+#define MXC_CCM_CCGR0_CG6_OFFSET 12
+#define MXC_CCM_CCGR0_CG5_OFFSET 10
+#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
+#define MXC_CCM_CCGR0_CG4_OFFSET 8
+#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
+#define MXC_CCM_CCGR0_CG3_OFFSET 6
+#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
+#define MXC_CCM_CCGR0_CG2_OFFSET 4
+#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
+#define MXC_CCM_CCGR0_CG1_OFFSET 2
+#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
+#define MXC_CCM_CCGR0_CG0_OFFSET 0
+#define MXC_CCM_CCGR0_CG0_MASK 0x3
+
+#define MXC_CCM_CCGR1_CG15_OFFSET 30
+#define MXC_CCM_CCGR1_CG14_OFFSET 28
+#define MXC_CCM_CCGR1_CG13_OFFSET 26
+#define MXC_CCM_CCGR1_CG12_OFFSET 24
+#define MXC_CCM_CCGR1_CG11_OFFSET 22
+#define MXC_CCM_CCGR1_CG10_OFFSET 20
+#define MXC_CCM_CCGR1_CG9_OFFSET 18
+#define MXC_CCM_CCGR1_CG8_OFFSET 16
+#define MXC_CCM_CCGR1_CG7_OFFSET 14
+#define MXC_CCM_CCGR1_CG6_OFFSET 12
+#define MXC_CCM_CCGR1_CG5_OFFSET 10
+#define MXC_CCM_CCGR1_CG4_OFFSET 8
+#define MXC_CCM_CCGR1_CG3_OFFSET 6
+#define MXC_CCM_CCGR1_CG2_OFFSET 4
+#define MXC_CCM_CCGR1_CG1_OFFSET 2
+#define MXC_CCM_CCGR1_CG0_OFFSET 0
+
+#define MXC_CCM_CCGR2_CG15_OFFSET 30
+#define MXC_CCM_CCGR2_CG14_OFFSET 28
+#define MXC_CCM_CCGR2_CG13_OFFSET 26
+#define MXC_CCM_CCGR2_CG12_OFFSET 24
+#define MXC_CCM_CCGR2_CG11_OFFSET 22
+#define MXC_CCM_CCGR2_CG10_OFFSET 20
+#define MXC_CCM_CCGR2_CG9_OFFSET 18
+#define MXC_CCM_CCGR2_CG8_OFFSET 16
+#define MXC_CCM_CCGR2_CG7_OFFSET 14
+#define MXC_CCM_CCGR2_CG6_OFFSET 12
+#define MXC_CCM_CCGR2_CG5_OFFSET 10
+#define MXC_CCM_CCGR2_CG4_OFFSET 8
+#define MXC_CCM_CCGR2_CG3_OFFSET 6
+#define MXC_CCM_CCGR2_CG2_OFFSET 4
+#define MXC_CCM_CCGR2_CG1_OFFSET 2
+#define MXC_CCM_CCGR2_CG0_OFFSET 0
+
+#define MXC_CCM_CCGR3_CG15_OFFSET 30
+#define MXC_CCM_CCGR3_CG14_OFFSET 28
+#define MXC_CCM_CCGR3_CG13_OFFSET 26
+#define MXC_CCM_CCGR3_CG12_OFFSET 24
+#define MXC_CCM_CCGR3_CG11_OFFSET 22
+#define MXC_CCM_CCGR3_CG10_OFFSET 20
+#define MXC_CCM_CCGR3_CG9_OFFSET 18
+#define MXC_CCM_CCGR3_CG8_OFFSET 16
+#define MXC_CCM_CCGR3_CG7_OFFSET 14
+#define MXC_CCM_CCGR3_CG6_OFFSET 12
+#define MXC_CCM_CCGR3_CG5_OFFSET 10
+#define MXC_CCM_CCGR3_CG4_OFFSET 8
+#define MXC_CCM_CCGR3_CG3_OFFSET 6
+#define MXC_CCM_CCGR3_CG2_OFFSET 4
+#define MXC_CCM_CCGR3_CG1_OFFSET 2
+#define MXC_CCM_CCGR3_CG0_OFFSET 0
+
+#define MXC_CCM_CCGR4_CG15_OFFSET 30
+#define MXC_CCM_CCGR4_CG14_OFFSET 28
+#define MXC_CCM_CCGR4_CG13_OFFSET 26
+#define MXC_CCM_CCGR4_CG12_OFFSET 24
+#define MXC_CCM_CCGR4_CG11_OFFSET 22
+#define MXC_CCM_CCGR4_CG10_OFFSET 20
+#define MXC_CCM_CCGR4_CG9_OFFSET 18
+#define MXC_CCM_CCGR4_CG8_OFFSET 16
+#define MXC_CCM_CCGR4_CG7_OFFSET 14
+#define MXC_CCM_CCGR4_CG6_OFFSET 12
+#define MXC_CCM_CCGR4_CG5_OFFSET 10
+#define MXC_CCM_CCGR4_CG4_OFFSET 8
+#define MXC_CCM_CCGR4_CG3_OFFSET 6
+#define MXC_CCM_CCGR4_CG2_OFFSET 4
+#define MXC_CCM_CCGR4_CG1_OFFSET 2
+#define MXC_CCM_CCGR4_CG0_OFFSET 0
+
+#define MXC_CCM_CCGR5_CG15_OFFSET 30
+#define MXC_CCM_CCGR5_CG14_OFFSET 28
+#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
+#define MXC_CCM_CCGR5_CG13_OFFSET 26
+#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
+#define MXC_CCM_CCGR5_CG12_OFFSET 24
+#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
+#define MXC_CCM_CCGR5_CG11_OFFSET 22
+#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
+#define MXC_CCM_CCGR5_CG10_OFFSET 20
+#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
+#define MXC_CCM_CCGR5_CG9_OFFSET 18
+#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
+#define MXC_CCM_CCGR5_CG8_OFFSET 16
+#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
+#define MXC_CCM_CCGR5_CG7_OFFSET 14
+#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
+#define MXC_CCM_CCGR5_CG6_OFFSET 12
+#define MXC_CCM_CCGR5_CG5_OFFSET 10
+#define MXC_CCM_CCGR5_CG4_OFFSET 8
+#define MXC_CCM_CCGR5_CG3_OFFSET 6
+#define MXC_CCM_CCGR5_CG2_OFFSET 4
+#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
+#define MXC_CCM_CCGR5_CG1_OFFSET 2
+#define MXC_CCM_CCGR5_CG0_OFFSET 0
+
+#define MXC_CCM_CCGR6_CG4_OFFSET 8
+#define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8)
+#define MXC_CCM_CCGR6_CG3_OFFSET 6
+#define MXC_CCM_CCGR6_CG2_OFFSET 4
+#define MXC_CCM_CCGR6_CG1_OFFSET 2
+#define MXC_CCM_CCGR6_CG0_OFFSET 0
+
+#define MXC_CORTEXA8_BASE ARM_BASE_ADDR
+#define MXC_GPC_BASE GPC_BASE_ADDR
+#define MXC_DPTC_LP_BASE (GPC_BASE_ADDR + 0x80)
+#define MXC_DPTC_GP_BASE (GPC_BASE_ADDR + 0x100)
+#define MXC_DVFS_CORE_BASE (GPC_BASE_ADDR + 0x180)
+#define MXC_DPTC_PER_BASE (GPC_BASE_ADDR + 0x1C0)
+#define MXC_PGC_IPU_BASE (GPC_BASE_ADDR + 0x220)
+#define MXC_PGC_VPU_BASE (GPC_BASE_ADDR + 0x240)
+#define MXC_PGC_GPU_BASE (GPC_BASE_ADDR + 0x260)
+#define MXC_SRPG_NEON_BASE (GPC_BASE_ADDR + 0x280)
+#define MXC_SRPG_ARM_BASE (GPC_BASE_ADDR + 0x2A0)
+#define MXC_SRPG_EMPGC0_BASE (GPC_BASE_ADDR + 0x2C0)
+#define MXC_SRPG_EMPGC1_BASE (GPC_BASE_ADDR + 0x2D0)
+#define MXC_SRPG_MEGAMIX_BASE (GPC_BASE_ADDR + 0x2E0)
+#define MXC_SRPG_EMI_BASE (GPC_BASE_ADDR + 0x300)
+
+/* CORTEXA8 platform */
+#define MXC_CORTEXA8_PLAT_PVID (MXC_CORTEXA8_BASE + 0x0)
+#define MXC_CORTEXA8_PLAT_GPC (MXC_CORTEXA8_BASE + 0x4)
+#define MXC_CORTEXA8_PLAT_PIC (MXC_CORTEXA8_BASE + 0x8)
+#define MXC_CORTEXA8_PLAT_LPC (MXC_CORTEXA8_BASE + 0xC)
+#define MXC_CORTEXA8_PLAT_NEON_LPC (MXC_CORTEXA8_BASE + 0x10)
+#define MXC_CORTEXA8_PLAT_ICGC (MXC_CORTEXA8_BASE + 0x14)
+#define MXC_CORTEXA8_PLAT_AMC (MXC_CORTEXA8_BASE + 0x18)
+#define MXC_CORTEXA8_PLAT_NMC (MXC_CORTEXA8_BASE + 0x20)
+#define MXC_CORTEXA8_PLAT_NMS (MXC_CORTEXA8_BASE + 0x24)
+
+/* DVFS CORE */
+#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
+#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
+#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08)
+#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C)
+#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10)
+#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14)
+#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18)
+#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C)
+#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20)
+#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24)
+#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28)
+#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C)
+#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30)
+#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34)
+#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38)
+#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
+#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
+
+/* GPC */
+#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0)
+#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
+#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
+#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC)
+#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10)
+#define MXC_GPC_PGR_ARMPG_OFFSET 8
+#define MXC_GPC_PGR_ARMPG_MASK (3 << 8)
+
+/* PGC */
+#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0)
+#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC)
+#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0)
+#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC)
+#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0)
+#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC)
+
+#define MXC_PGCR_PCR 1
+#define MXC_SRPGCR_PCR 1
+#define MXC_EMPGCR_PCR 1
+#define MXC_PGSR_PSR 1
+
+
+#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0)
+#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1)
+
+/* SRPG */
+#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0)
+#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4)
+#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8)
+
+#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0)
+#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4)
+#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8)
+
+#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0)
+#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4)
+#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8)
+
+#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0)
+#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4)
+#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8)
+
+#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0)
+#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4)
+#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8)
+
+#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0)
+#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4)
+#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8)
+
+#ifndef __ASSEMBLE__
+extern unsigned int __get_mcu_main_clk(void);
+extern void mxc_show_clocks(void);
+#endif
+#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
diff --git a/cpu/arm_cortexa8/mx51/interrupts.c b/cpu/arm_cortexa8/mx51/interrupts.c
new file mode 100644
index 0000000..c0d70ac
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/interrupts.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx51.h>
+
+/* nothing really to do with interrupts. */
+int interrupt_init(void)
+{
+ return 0;
+}
diff --git a/cpu/arm_cortexa8/mx51/iomux.c b/cpu/arm_cortexa8/mx51/iomux.c
new file mode 100644
index 0000000..80082aa
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/iomux.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup GPIO_MX51 Board GPIO and Muxing Setup
+ * @ingroup MSL_MX51
+ */
+/*!
+ * @file mach-mx51/iomux.c
+ *
+ * @brief I/O Muxing control functions
+ *
+ * @ingroup GPIO_MX51
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx51.h>
+#include <asm/arch/mx51_pins.h>
+#include <asm/arch/iomux.h>
+
+/*!
+ * IOMUX register (base) addresses
+ */
+enum iomux_reg_addr {
+ IOMUXGPR0 = IOMUXC_BASE_ADDR,
+ IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
+ IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
+ IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
+ IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
+ IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
+};
+
+#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
+
+static inline u32 _get_mux_reg(iomux_pin_name_t pin)
+{
+ u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
+
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
+ if ((pin == MX51_PIN_NANDF_RB5) ||
+ (pin == MX51_PIN_NANDF_RB6) ||
+ (pin == MX51_PIN_NANDF_RB7))
+ ; /* Do nothing */
+ else if (mux_reg >= 0x2FC)
+ mux_reg += 8;
+ else if (mux_reg >= 0x130)
+ mux_reg += 0xC;
+ }
+ mux_reg += IOMUXSW_MUX_CTL;
+ return mux_reg;
+}
+
+static inline u32 _get_pad_reg(iomux_pin_name_t pin)
+{
+ u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
+
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
+ if ((pin == MX51_PIN_NANDF_RB5) ||
+ (pin == MX51_PIN_NANDF_RB6) ||
+ (pin == MX51_PIN_NANDF_RB7))
+ ; /* Do nothing */
+ else if (pad_reg == 0x4D0 - PAD_I_START)
+ pad_reg += 0x4C;
+ else if (pad_reg == 0x860 - PAD_I_START)
+ pad_reg += 0x9C;
+ else if (pad_reg >= 0x804 - PAD_I_START)
+ pad_reg += 0xB0;
+ else if (pad_reg >= 0x7FC - PAD_I_START)
+ pad_reg += 0xB4;
+ else if (pad_reg >= 0x4E4 - PAD_I_START)
+ pad_reg += 0xCC;
+ else
+ pad_reg += 8;
+ }
+ pad_reg += IOMUXSW_PAD_CTL;
+ return pad_reg;
+}
+
+static inline u32 _get_mux_end(void)
+{
+ if (is_soc_rev(CHIP_REV_2_0) < 0)
+ return IOMUXC_BASE_ADDR + (0x3F8 - 4);
+ else
+ return IOMUXC_BASE_ADDR + (0x3F0 - 4);
+}
+
+/*!
+ * This function is used to configure a pin through the IOMUX module.
+ * FIXED ME: for backward compatible. Will be static function!
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param cfg an output function as defined in \b #iomux_pin_cfg_t
+ *
+ * @return 0 if successful; Non-zero otherwise
+ */
+static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+ u32 mux_reg = _get_mux_reg(pin);
+
+ if ((mux_reg > _get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
+ return -1;
+ if (cfg == IOMUX_CONFIG_GPIO)
+ writel(PIN_TO_ALT_GPIO(pin), mux_reg);
+ else
+ writel(cfg, mux_reg);
+
+ return 0;
+}
+
+/*!
+ * Request ownership for an IO pin. This function has to be the first one
+ * being called before that pin is used. The caller has to check the
+ * return value to make sure it returns 0.
+ *
+ * @param pin a name defined by \b iomux_pin_name_t
+ * @param cfg an input function as defined in \b #iomux_pin_cfg_t
+ *
+ * @return 0 if successful; Non-zero otherwise
+ */
+int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+ int ret = iomux_config_mux(pin, cfg);
+ return ret;
+}
+
+/*!
+ * Release ownership for an IO pin
+ *
+ * @param pin a name defined by \b iomux_pin_name_t
+ * @param cfg an input function as defined in \b #iomux_pin_cfg_t
+ */
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
+{
+}
+
+/*!
+ * This function configures the pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param config the ORed value of elements defined in \b #iomux_pad_config_t
+ */
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
+{
+ u32 pad_reg = _get_pad_reg(pin);
+ writel(config, pad_reg);
+}
+
+unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
+{
+ u32 pad_reg = _get_pad_reg(pin);
+ return readl(pad_reg);
+}
+/*!
+ * This function configures input path.
+ *
+ * @param input index of input select register as defined in \b
+ * #iomux_input_select_t
+ * @param config the binary value of elements defined in \b
+ * #iomux_input_config_t
+ */
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
+{
+ u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
+
+ if (is_soc_rev(CHIP_REV_2_0) < 0) {
+ if (input == MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT)
+ input -= 4;
+ else if (input ==
+ MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT)
+ input -= 3;
+ else if (input >= MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT)
+ input -= 2;
+ else if (input >=
+ MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT)
+ input -= 5;
+ else if (input >=
+ MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT)
+ input -= 3;
+ else if (input >= MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT)
+ input -= 2;
+ else if (input >= MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT)
+ input -= 1;
+
+ reg += INPUT_CTL_START_TO1;
+ } else {
+ reg += INPUT_CTL_START;
+ }
+
+ writel(config, reg);
+}
diff --git a/cpu/arm_cortexa8/mx51/soc.c b/cpu/arm_cortexa8/mx51/soc.c
new file mode 100644
index 0000000..cd8ce9d
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/soc.c
@@ -0,0 +1,66 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx51.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include "crm_regs.h"
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+ printf("CPU: Freescale i.MX51 family %d.%dV at %d MHz\n",
+ (get_board_rev() & 0xFF) >> 4,
+ (get_board_rev() & 0xF),
+ __get_mcu_main_clk() / 1000000);
+ mxc_show_clocks();
+ return 0;
+}
+#endif
+
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
+#if defined(CONFIG_MXC_FEC)
+extern int mxc_fec_initialize(bd_t *bis);
+#endif
+
+int cpu_eth_init(bd_t *bis)
+{
+ int rc = -ENODEV;
+
+#if defined(CONFIG_MXC_FEC)
+ rc = mxc_fec_initialize(bis);
+#endif
+
+ return rc;
+}
+
+void reset_cpu(ulong addr)
+{
+ __raw_writew(4, WDOG1_BASE_ADDR);
+}
diff --git a/cpu/arm_cortexa8/mx51/timer.c b/cpu/arm_cortexa8/mx51/timer.c
new file mode 100644
index 0000000..5201768
--- /dev/null
+++ b/cpu/arm_cortexa8/mx51/timer.c
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx51.h>
+
+/* General purpose timers registers */
+#define GPTCR GPT1_BASE_ADDR /* Control register */
+#define GPTPR (GPT1_BASE_ADDR + 0x4) /* Prescaler register */
+#define GPTSR (GPT1_BASE_ADDR + 0x8) /* Status register */
+#define GPTCNT (GPT1_BASE_ADDR + 0x24) /* Counter register */
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR (1<<15) /* Software reset */
+#define GPTCR_FRR (1<<9) /* Freerun / restart */
+#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
+#define GPTCR_TEN (1) /* Timer enable */
+
+int timer_init(void)
+{
+ int i;
+
+ /* setup GP Timer 1 */
+ __raw_writel(GPTCR_SWR, GPTCR);
+ for (i = 0; i < 100; i++)
+ __raw_writel(0, GPTCR); /* We have no udelay by now */
+
+ __raw_writel(0, GPTPR); /* 32Khz */
+
+ /* Freerun Mode, PERCLK1 input */
+ i = __raw_readl(GPTCR);
+ __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, GPTCR);
+ return 0;
+}
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+void reset_timer_masked(void)
+{
+ __raw_writel(0, GPTCR);
+ /* Freerun Mode, PERCLK1 input */
+ __raw_writel(GPTCR_CLKSOURCE_32 | GPTCR_TEN, GPTCR);
+}
+
+ulong get_timer_masked(void)
+{
+ ulong val = __raw_readl(GPTCNT);
+ return val;
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay(unsigned long usec)
+{
+ ulong tmo, tmp;
+
+ /* if "big" number, spread normalization to seconds */
+ if (usec >= 1000) {
+ /* start to normalize for usec to ticks per sec */
+ tmo = usec / 1000;
+ /* find number of "ticks" to wait to achieve target */
+ tmo *= CONFIG_SYS_HZ;
+ tmo /= 1000; /* finish normalize. */
+ } else {/* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CONFIG_SYS_HZ;
+ tmo /= (1000 * 1000);
+ }
+
+ tmp = get_timer(0); /* get current timestamp */
+ /* if setting this forward will roll time stamp */
+ if ((tmo + tmp + 1) < tmp)
+ /* reset "advancing" timestamp to 0, set lastinc value */
+ reset_timer_masked();
+ else /* else, set advancing stamp wake up time */
+ tmo += tmp;
+ while (get_timer_masked() < tmo) /* loop till event */
+ /*NOP*/;
+}
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index acc5b7d..c8acfb8 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -20,6 +20,8 @@
#include <common.h>
#ifdef CONFIG_MX31
#include <asm/arch/mx31.h>
+#elif defined(CONFIG_MX51)
+#include <asm/arch/mx51.h>
#else
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
@@ -37,6 +39,8 @@
#define UART_PHYS 0x43fb0000
#elif defined(CONFIG_SYS_MX31_UART5)
#define UART_PHYS 0x43fb4000
+#elif defined(CONFIG_SYS_MX51_UART1)
+#define UART_PHYS UART1_BASE_ADDR
#elif defined(CONFIG_SYS_MX27_UART1)
#define UART_PHYS 0x1000a000
#elif defined(CONFIG_SYS_MX27_UART2)
@@ -168,6 +172,8 @@ void serial_setbrg (void)
{
#ifdef CONFIG_MX31
u32 clk = mx31_get_ipg_clk();
+#elif defined(CONFIG_MX51)
+ u32 clk = mxc_get_clock(MXC_UART_CLK);
#else
u32 clk = imx_get_perclk1();
#endif
diff --git a/include/asm-arm/arch-mx51/iomux.h b/include/asm-arm/arch-mx51/iomux.h
new file mode 100644
index 0000000..fa02984
--- /dev/null
+++ b/include/asm-arm/arch-mx51/iomux.h
@@ -0,0 +1,240 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MACH_MX51_IOMUX_H__
+#define __MACH_MX51_IOMUX_H__
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mx51.h>
+#include <asm/arch/mx51_pins.h>
+
+/*!
+ * @file iomux.h
+ *
+ * @brief I/O Muxing control definitions and functions
+ *
+ * @ingroup GPIO_MX51
+ */
+
+typedef unsigned int iomux_pin_name_t;
+
+/*!
+ * various IOMUX output functions
+ */
+typedef enum iomux_config {
+ IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */
+ IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */
+ IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */
+ IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */
+ IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */
+ IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */
+ IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */
+ IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */
+ IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */
+ IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */
+} iomux_pin_cfg_t;
+
+/*!
+ * various IOMUX pad functions
+ */
+typedef enum iomux_pad_config {
+ PAD_CTL_SRE_SLOW = 0x0 << 0,
+ PAD_CTL_SRE_FAST = 0x1 << 0,
+ PAD_CTL_DRV_LOW = 0x0 << 1,
+ PAD_CTL_DRV_MEDIUM = 0x1 << 1,
+ PAD_CTL_DRV_HIGH = 0x2 << 1,
+ PAD_CTL_DRV_MAX = 0x3 << 1,
+ PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,
+ PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
+ PAD_CTL_100K_PD = 0x0 << 4,
+ PAD_CTL_47K_PU = 0x1 << 4,
+ PAD_CTL_100K_PU = 0x2 << 4,
+ PAD_CTL_22K_PU = 0x3 << 4,
+ PAD_CTL_PUE_KEEPER = 0x0 << 6,
+ PAD_CTL_PUE_PULL = 0x1 << 6,
+ PAD_CTL_PKE_NONE = 0x0 << 7,
+ PAD_CTL_PKE_ENABLE = 0x1 << 7,
+ PAD_CTL_HYS_NONE = 0x0 << 8,
+ PAD_CTL_HYS_ENABLE = 0x1 << 8,
+ PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,
+ PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
+ PAD_CTL_DRV_VOT_LOW = 0x0 << 13,
+ PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
+} iomux_pad_config_t;
+
+/*!
+ * various IOMUX input select register index
+ */
+typedef enum iomux_input_select {
+ MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
+ MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
+ MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
+ MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
+ MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
+ MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
+ MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
+ MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
+ MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
+ MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
+ MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
+ MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
+ MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
+ MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
+ MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
+ MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
+ MUX_IN_FEC_FEC_COL_SELECT_INPUT,
+ MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
+ MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
+ MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
+ MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
+ MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
+ MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
+ MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
+ /* TO2 */
+ MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
+ MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
+ MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
+ MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
+ MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
+ MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
+
+ MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
+
+ MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
+
+ MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
+ MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
+ MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
+ MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
+ MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
+ MUX_INPUT_NUM_MUX,
+} iomux_input_select_t;
+
+/*!
+ * various IOMUX input functions
+ */
+typedef enum iomux_input_config {
+ INPUT_CTL_PATH0 = 0x0,
+ INPUT_CTL_PATH1,
+ INPUT_CTL_PATH2,
+ INPUT_CTL_PATH3,
+ INPUT_CTL_PATH4,
+ INPUT_CTL_PATH5,
+ INPUT_CTL_PATH6,
+ INPUT_CTL_PATH7,
+} iomux_input_config_t;
+
+/*!
+ * Request ownership for an IO pin. This function has to be the first one
+ * being called before that pin is used. The caller has to check the
+ * return value to make sure it returns 0.
+ *
+ * @param pin a name defined by \b iomux_pin_name_t
+ * @param config config as defined in \b #iomux_pin_ocfg_t
+ *
+ * @return 0 if successful; Non-zero otherwise
+ */
+int mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
+
+/*!
+ * Release ownership for an IO pin
+ *
+ * @param pin a name defined by \b iomux_pin_name_t
+ * @param config config as defined in \b #iomux_pin_ocfg_t
+ */
+void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
+
+/*!
+ * This function configures the pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @param config the ORed value of elements defined in
+ * \b #iomux_pad_config_t
+ */
+void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
+
+/*!
+ * This function gets the current pad value for a IOMUX pin.
+ *
+ * @param pin a pin number as defined in \b #iomux_pin_name_t
+ * @return current pad value
+ */
+unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
+
+/*!
+ * This function configures input path.
+ *
+ * @param input index of input select register as defined in
+ * \b #iomux_input_select_t
+ * @param config the binary value of elements defined in
+ * \b #iomux_input_config_t
+ */
+void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
+
+#endif /* __MACH_MX51_IOMUX_H__ */
diff --git a/include/asm-arm/arch-mx51/mx51.h b/include/asm-arm/arch-mx51/mx51.h
new file mode 100644
index 0000000..cf51945
--- /dev/null
+++ b/include/asm-arm/arch-mx51/mx51.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_MX51_H__
+#define __ASM_ARCH_MXC_MX51_H__
+
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
+/*
+ * Graphics Memory of GPU
+ */
+#define GPU_BASE_ADDR 0x20000000
+#define GPU_CTRL_BASE_ADDR 0x30000000
+#define IPU_CTRL_BASE_ADDR 0x40000000
+/*
+ * Debug
+ */
+#define DEBUG_BASE_ADDR 0x60000000
+#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
+#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
+#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
+#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
+#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
+#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
+#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
+#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
+
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR 0x70000000
+
+#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
+#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
+#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
+#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
+#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
+#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
+#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
+#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR 0x73F00000
+
+#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
+#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
+#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
+#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
+#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
+#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
+#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
+#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
+#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
+#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
+#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
+#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
+#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
+#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
+#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
+#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
+#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000)
+#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
+#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
+#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR 0x83F00000
+
+#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
+#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
+#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
+#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
+#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
+#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
+#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
+#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
+#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
+#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
+#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
+#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
+#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
+#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
+#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
+#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
+#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
+#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
+#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
+#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
+#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
+#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
+#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
+#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
+#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
+#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
+#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
+#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
+#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
+#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
+#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
+#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
+
+#define TZIC_BASE_ADDR 0x8FFFC000
+
+/*
+ * Memory regions and CS
+ */
+#define CSD0_BASE_ADDR 0x90000000
+#define CSD1_BASE_ADDR 0xA0000000
+#define CS0_BASE_ADDR 0xB0000000
+#define CS1_BASE_ADDR 0xB8000000
+#define CS2_BASE_ADDR 0xC0000000
+#define CS3_BASE_ADDR 0xC8000000
+#define CS4_BASE_ADDR 0xCC000000
+#define CS5_BASE_ADDR 0xCE000000
+
+/*
+ * NFC
+ */
+#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */
+
+/*!
+ * defines for SPBA modules
+ */
+#define SPBA_SDHC1 0x04
+#define SPBA_SDHC2 0x08
+#define SPBA_UART3 0x0C
+#define SPBA_CSPI1 0x10
+#define SPBA_SSI2 0x14
+#define SPBA_SDHC3 0x20
+#define SPBA_SDHC4 0x24
+#define SPBA_SPDIF 0x28
+#define SPBA_ATA 0x30
+#define SPBA_SLIM 0x34
+#define SPBA_HSI2C 0x38
+#define SPBA_CTRL 0x3C
+
+/*
+ * Interrupt numbers
+ */
+#define MXC_INT_BASE 0
+#define MXC_INT_RESV0 0
+#define MXC_INT_MMC_SDHC1 1
+#define MXC_INT_MMC_SDHC2 2
+#define MXC_INT_MMC_SDHC3 3
+#define MXC_INT_MMC_SDHC4 4
+#define MXC_INT_RESV5 5
+#define MXC_INT_SDMA 6
+#define MXC_INT_IOMUX 7
+#define MXC_INT_NFC 8
+#define MXC_INT_VPU 9
+#define MXC_INT_IPU_ERR 10
+#define MXC_INT_IPU_SYN 11
+#define MXC_INT_GPU 12
+#define MXC_INT_RESV13 13
+#define MXC_INT_USB_H1 14
+#define MXC_INT_EMI 15
+#define MXC_INT_USB_H2 16
+#define MXC_INT_USB_H3 17
+#define MXC_INT_USB_OTG 18
+#define MXC_INT_SAHARA_H0 19
+#define MXC_INT_SAHARA_H1 20
+#define MXC_INT_SCC_SMN 21
+#define MXC_INT_SCC_STZ 22
+#define MXC_INT_SCC_SCM 23
+#define MXC_INT_SRTC_NTZ 24
+#define MXC_INT_SRTC_TZ 25
+#define MXC_INT_RTIC 26
+#define MXC_INT_CSU 27
+#define MXC_INT_SLIM_B 28
+#define MXC_INT_SSI1 29
+#define MXC_INT_SSI2 30
+#define MXC_INT_UART1 31
+#define MXC_INT_UART2 32
+#define MXC_INT_UART3 33
+#define MXC_INT_RESV34 34
+#define MXC_INT_RESV35 35
+#define MXC_INT_CSPI1 36
+#define MXC_INT_CSPI2 37
+#define MXC_INT_CSPI 38
+#define MXC_INT_GPT 39
+#define MXC_INT_EPIT1 40
+#define MXC_INT_EPIT2 41
+#define MXC_INT_GPIO1_INT7 42
+#define MXC_INT_GPIO1_INT6 43
+#define MXC_INT_GPIO1_INT5 44
+#define MXC_INT_GPIO1_INT4 45
+#define MXC_INT_GPIO1_INT3 46
+#define MXC_INT_GPIO1_INT2 47
+#define MXC_INT_GPIO1_INT1 48
+#define MXC_INT_GPIO1_INT0 49
+#define MXC_INT_GPIO1_LOW 50
+#define MXC_INT_GPIO1_HIGH 51
+#define MXC_INT_GPIO2_LOW 52
+#define MXC_INT_GPIO2_HIGH 53
+#define MXC_INT_GPIO3_LOW 54
+#define MXC_INT_GPIO3_HIGH 55
+#define MXC_INT_GPIO4_LOW 56
+#define MXC_INT_GPIO4_HIGH 57
+#define MXC_INT_WDOG1 58
+#define MXC_INT_WDOG2 59
+#define MXC_INT_KPP 60
+#define MXC_INT_PWM1 61
+#define MXC_INT_I2C1 62
+#define MXC_INT_I2C2 63
+#define MXC_INT_HS_I2C 64
+#define MXC_INT_RESV65 65
+#define MXC_INT_RESV66 66
+#define MXC_INT_SIM_IPB 67
+#define MXC_INT_SIM_DAT 68
+#define MXC_INT_IIM 69
+#define MXC_INT_ATA 70
+#define MXC_INT_CCM1 71
+#define MXC_INT_CCM2 72
+#define MXC_INT_GPC1 73
+#define MXC_INT_GPC2 74
+#define MXC_INT_SRC 75
+#define MXC_INT_NM 76
+#define MXC_INT_PMU 77
+#define MXC_INT_CTI_IRQ 78
+#define MXC_INT_CTI1_TG0 79
+#define MXC_INT_CTI1_TG1 80
+#define MXC_INT_MCG_ERR 81
+#define MXC_INT_MCG_TMR 82
+#define MXC_INT_MCG_FUNC 83
+#define MXC_INT_RESV84 84
+#define MXC_INT_RESV85 85
+#define MXC_INT_RESV86 86
+#define MXC_INT_FEC 87
+#define MXC_INT_OWIRE 88
+#define MXC_INT_CTI1_TG2 89
+#define MXC_INT_SJC 90
+#define MXC_INT_SPDIF 91
+#define MXC_INT_TVE 92
+#define MXC_INT_FIRI 93
+#define MXC_INT_PWM2 94
+#define MXC_INT_SLIM_EXP 95
+#define MXC_INT_SSI3 96
+#define MXC_INT_RESV97 97
+#define MXC_INT_CTI1_TG3 98
+#define MXC_INT_SMC_RX 99
+#define MXC_INT_VPU_IDLE 100
+#define MXC_INT_RESV101 101
+#define MXC_INT_GPU_IDLE 102
+
+#define MXC_MAX_INT_LINES 128
+
+#define MXC_GPIO_INT_BASE (MXC_MAX_INT_LINES)
+
+/*!
+ * Number of GPIO port as defined in the IC Spec
+ */
+#define GPIO_PORT_NUM 4
+/*!
+ * Number of GPIO pins per port
+ */
+#define GPIO_NUM_PIN 32
+
+#define MXC_GPIO_SPLIT_IRQ_2
+
+#define IIM_SREV 0x24
+#define ROM_SI_REV 0x48
+
+#define NFC_BUF_SIZE 0x1000
+
+/* WEIM registers */
+#define CSGCR1 0x00
+#define CSGCR2 0x04
+#define CSRCR1 0x08
+#define CSRCR2 0x0C
+#define CSWCR1 0x10
+
+/* M4IF */
+#define M4IF_FBPM0 0x40
+#define M4IF_FIDBP 0x48
+
+/* ESDCTL */
+#define ESDCTL_ESDCTL0 0x00
+#define ESDCTL_ESDCFG0 0x04
+#define ESDCTL_ESDCTL1 0x08
+#define ESDCTL_ESDCFG1 0x0C
+#define ESDCTL_ESDMISC 0x10
+#define ESDCTL_ESDSCR 0x14
+#define ESDCTL_ESDCDLY1 0x20
+#define ESDCTL_ESDCDLY2 0x24
+#define ESDCTL_ESDCDLY3 0x28
+#define ESDCTL_ESDCDLY4 0x2C
+#define ESDCTL_ESDCDLY5 0x30
+#define ESDCTL_ESDCDLYGD 0x34
+
+/* CCM */
+#define CLKCTL_CCR 0x00
+#define CLKCTL_CCDR 0x04
+#define CLKCTL_CSR 0x08
+#define CLKCTL_CCSR 0x0C
+#define CLKCTL_CACRR 0x10
+#define CLKCTL_CBCDR 0x14
+#define CLKCTL_CBCMR 0x18
+#define CLKCTL_CSCMR1 0x1C
+#define CLKCTL_CSCMR2 0x20
+#define CLKCTL_CSCDR1 0x24
+#define CLKCTL_CS1CDR 0x28
+#define CLKCTL_CS2CDR 0x2C
+#define CLKCTL_CDCDR 0x30
+#define CLKCTL_CHSCCDR 0x34
+#define CLKCTL_CSCDR2 0x38
+#define CLKCTL_CSCDR3 0x3C
+#define CLKCTL_CSCDR4 0x40
+#define CLKCTL_CWDR 0x44
+#define CLKCTL_CDHIPR 0x48
+#define CLKCTL_CDCR 0x4C
+#define CLKCTL_CTOR 0x50
+#define CLKCTL_CLPCR 0x54
+#define CLKCTL_CISR 0x58
+#define CLKCTL_CIMR 0x5C
+#define CLKCTL_CCOSR 0x60
+#define CLKCTL_CGPR 0x64
+#define CLKCTL_CCGR0 0x68
+#define CLKCTL_CCGR1 0x6C
+#define CLKCTL_CCGR2 0x70
+#define CLKCTL_CCGR3 0x74
+#define CLKCTL_CCGR4 0x78
+#define CLKCTL_CCGR5 0x7C
+#define CLKCTL_CCGR6 0x80
+#define CLKCTL_CMEOR 0x84
+
+/* DPLL */
+#define PLL_DP_CTL 0x00
+#define PLL_DP_CONFIG 0x04
+#define PLL_DP_OP 0x08
+#define PLL_DP_MFD 0x0C
+#define PLL_DP_MFN 0x10
+#define PLL_DP_MFNMINUS 0x14
+#define PLL_DP_MFNPLUS 0x18
+#define PLL_DP_HFS_OP 0x1C
+#define PLL_DP_HFS_MFD 0x20
+#define PLL_DP_HFS_MFN 0x24
+#define PLL_DP_TOGC 0x28
+#define PLL_DP_DESTAT 0x2C
+
+/* Assuming 24MHz input clock with doubler ON */
+/* MFI PDF */
+#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
+#define DP_MFD_850 (48 - 1)
+#define DP_MFN_850 41
+
+#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
+#define DP_MFD_800 (3 - 1)
+#define DP_MFN_800 1
+
+#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
+#define DP_MFD_700 (24 - 1)
+#define DP_MFN_700 7
+
+#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
+#define DP_MFD_665 (96 - 1)
+#define DP_MFN_665 89
+
+#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
+#define DP_MFD_532 (24 - 1)
+#define DP_MFN_532 13
+
+#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
+#define DP_MFD_400 (3 - 1)
+#define DP_MFN_400 1
+
+#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+#define DP_MFD_216 (4 - 1)
+#define DP_MFN_216 3
+
+#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_1 0x11
+#define CHIP_REV_2_0 0x20
+#define CHIP_REV_2_5 0x120
+
+#define BOARD_REV_1_0 0x0
+#define BOARD_REV_2_0 0x1
+
+#ifndef __ASSEMBLER__
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_IPG_PERCLK,
+ MXC_UART_CLK,
+ MXC_CSPI_CLK,
+ MXC_FEC_CLK,
+};
+
+extern unsigned int mxc_get_clock(enum mxc_clock clk);
+extern unsigned int get_board_rev(void);
+extern int is_soc_rev(int rev);
+
+#endif /* __ASSEMBLER__*/
+
+#endif /* __ASM_ARCH_MXC_MX51_H__ */
diff --git a/include/asm-arm/arch-mx51/mx51_pins.h b/include/asm-arm/arch-mx51/mx51_pins.h
new file mode 100644
index 0000000..63fdd8c
--- /dev/null
+++ b/include/asm-arm/arch-mx51/mx51_pins.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __ASM_ARCH_MXC_MX51_PINS_H__
+#define __ASM_ARCH_MXC_MX51_PINS_H__
+
+/*!
+ * @file arch-mxc/mx51_pins.h
+ *
+ * @brief MX51 I/O Pin List
+ *
+ * @ingroup GPIO_MX51
+ */
+
+#ifndef __ASSEMBLY__
+
+/*!
+ * @name IOMUX/PAD Bit field definitions
+ */
+
+/*! @{ */
+
+/*!
+ * In order to identify pins more effectively, each mux-controlled pin's
+ * enumerated value is constructed in the following way:
+ *
+ * -------------------------------------------------------------------
+ * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0
+ * -------------------------------------------------------------------
+ * IO_P | IO_I | GPIO_I | PAD_I | MUX_I
+ * -------------------------------------------------------------------
+ *
+ * Bit 0 to 9 contains MUX_I used to identify the register
+ * offset (0-based. base is IOMUX_module_base) defined in the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The
+ * similar field definitions are used for the pad control register.
+ * For example, the MX51_PIN_ETM_D0 is defined in the enumeration:
+ * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I)
+ * It means the mux control register is@register offset 0x28. The pad control
+ * register offset is: 0x250 and also occupy the least significant bits
+ * within the register.
+ */
+
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * MUX control register offset
+ */
+#define MUX_I 0
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent the
+ * PAD control register offset
+ */
+#define PAD_I 10
+/*!
+ * Starting bit position within each entry of \b iomux_pins to represent which
+ * mux mode is for GPIO (0-based)
+ */
+#define GPIO_I 21
+
+#define MUX_IO_P 29
+#define MUX_IO_I 24
+#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \
+ GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\
+ ((1 << (MUX_IO_P - MUX_IO_I)) - 1)))
+#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin))
+#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
+#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
+
+#define NON_GPIO_PORT 0x7
+#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1)
+#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1)
+#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1)
+
+#define NON_MUX_I PIN_TO_MUX_MASK
+#define MUX_I_START 0x001C
+#define PAD_I_START 0x3F0
+#define INPUT_CTL_START 0x8C4
+#define INPUT_CTL_START_TO1 0x928
+#define MUX_I_END (PAD_I_START - 4)
+
+#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \
+ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \
+ ((mi) << MUX_I) | \
+ ((pi - PAD_I_START) << PAD_I) | \
+ ((ga) << GPIO_I))
+
+#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \
+ _MXC_BUILD_PIN(gp, gi, ga, mi, pi)
+
+#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \
+ _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi)
+
+#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK)
+#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK)
+#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK)
+#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2)
+
+/*! @} End IOMUX/PAD Bit field definitions */
+
+/*!
+ * This enumeration is constructed based on the Section
+ * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated
+ * value is constructed based on the rules described above.
+ */
+enum iomux_pins {
+ MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8),
+ MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8),
+ MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8),
+ MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8),
+ MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC),
+ MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC),
+ MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC),
+ MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC),
+ MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0),
+ MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0),
+ MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0),
+ MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0),
+ MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC),
+ MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC),
+ MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC),
+ MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC),
+ MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0),
+ MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4),
+ MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8),
+ MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC),
+ MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400),
+ MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404),
+ MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408),
+ MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C),
+ MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410),
+ MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414),
+ MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418),
+ MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C),
+ MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420),
+ MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424),
+ MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428),
+ MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C),
+ MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430),
+ MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434),
+ MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438),
+ MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C),
+ MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440),
+ MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444),
+ MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448),
+ MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C),
+ MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450),
+ MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454),
+ MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458),
+ MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C),
+ MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460),
+ MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464),
+ MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468),
+ MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C),
+ MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470),
+ MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474),
+ MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478),
+ MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C),
+ MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480),
+ MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484),
+ MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488),
+ MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C),
+ MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494),
+ MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0),
+ MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0),
+ MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4),
+ MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8),
+ MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC),
+ MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0),
+ MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4),
+ MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8),
+ MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC),
+ MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500),
+ MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504),
+ MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514),
+ MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND,
+ MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8),
+ MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC),
+ MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0),
+ MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518),
+ MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C),
+ MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520),
+ MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524),
+ MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528),
+ MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C),
+ MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530),
+ MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534),
+ MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538),
+ MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C),
+ MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540),
+ MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544),
+ MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548),
+ MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C),
+ MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550),
+ MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554),
+ MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558),
+ MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C),
+ MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560),
+ MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564),
+ MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568),
+ MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C),
+ MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570),
+ MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574),
+ MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578),
+ MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C),
+ MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580),
+ MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584),
+ MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588),
+ MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C),
+ MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590),
+ MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594),
+ MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598),
+ MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C),
+ MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0),
+ MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4),
+ MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8),
+ MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC),
+ MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0),
+ MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4),
+ MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8),
+ MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860),
+ MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC),
+ MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0),
+ MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4),
+ MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8),
+ MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC),
+ MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0),
+ MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4),
+ MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8),
+ MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC),
+ MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0),
+ MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4),
+ MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C),
+ MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8),
+ MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC),
+ MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0),
+ MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4),
+ MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8),
+ MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC),
+ MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600),
+ MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604),
+ MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608),
+ MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C),
+ MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610),
+ MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614),
+ MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618),
+ MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C),
+ MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620),
+ MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624),
+ MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628),
+ MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C),
+ MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630),
+ MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634),
+ MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638),
+ MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C),
+ MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640),
+ MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644),
+ MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648),
+ MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C),
+ MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650),
+ MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654),
+ MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658),
+ MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C),
+ MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660),
+ MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678),
+ MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C),
+ MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680),
+ MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684),
+ MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688),
+ MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C),
+ MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690),
+ MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694),
+ MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698),
+ MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C),
+ MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0),
+ MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4),
+ MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8),
+ MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC),
+ MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0),
+ MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4),
+ MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8),
+ MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC),
+ MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0),
+ MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4),
+ MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8),
+ MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC),
+ MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0),
+ MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4),
+ MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8),
+ MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC),
+ MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0),
+ MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4),
+ MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8),
+ MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC),
+ MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0),
+ MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4),
+ MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8),
+ MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC),
+ MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700),
+ MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704),
+ MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708),
+ MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C),
+ MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710),
+ MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714),
+ MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718),
+ MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C),
+ MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720),
+ MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724),
+ MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728),
+ MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C),
+ MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734),
+ MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C),
+ MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740),
+ MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744),
+ MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748),
+ MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C),
+ MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750),
+ MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754),
+ MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758),
+ MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C),
+ MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760),
+ MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764),
+ MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768),
+ MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C),
+ MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770),
+ MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774),
+ MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778),
+ MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C),
+ MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780),
+ MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784),
+ MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788),
+ MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C),
+ MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790),
+ MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794),
+ MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798),
+ MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C),
+ MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0),
+ MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4),
+ MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8),
+ MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC),
+ MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0),
+ MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4),
+ MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8),
+ MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC),
+ MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0),
+ MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4),
+ MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8),
+ MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC),
+ MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0),
+ MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4),
+ MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8),
+ MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC),
+ MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804),
+ MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808),
+ MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C),
+ MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810),
+ MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814),
+ MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818),
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */
diff --git a/include/configs/mx51_babbage.h b/include/configs/mx51_babbage.h
new file mode 100644
index 0000000..a24b39b
--- /dev/null
+++ b/include/configs/mx51_babbage.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the MX51-3Stack Freescale board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/mx51.h>
+
+ /* High Level Configuration Options */
+#define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */
+#define CONFIG_L2_OFF
+
+#define CONFIG_MXC 1
+#define CONFIG_MX51 1
+#define CONFIG_FLASH_HEADER 1
+#define CONFIG_FLASH_HEADER_OFFSET 0x400
+#define CONFIG_FLASH_HEADER_BARKER 0xB1
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_MX51_HCLK_FREQ 24000000
+#define CONFIG_MX51_CLK32 32768
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define BOARD_LATE_INIT
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+#define CONFIG_DOS_PARTITION 1
+/*
+ * Hardware drivers
+ */
+#define CONFIG_MXC_UART 1
+#define CONFIG_SYS_MX51_UART1 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_PRIME "FEC0"
+
+#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "ethprime=FEC0\0" \
+ "uboot_addr=0xa0000000\0" \
+ "uboot=u-boot.bin\0" \
+ "kernel=uImage\0" \
+ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\
+ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
+ "bootcmd=run bootcmd_net\0" \
+ "bootcmd_net=run bootargs_base bootargs_nfs; " \
+ "tftpboot ${loadaddr} ${kernel}; bootm\0" \
+
+/*
+ * The MX51 babbage board seems to have a hardware "peculiarity" confirmed under
+ * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the ethernet
+ * controller inverted. The controller is capable of detecting and correcting
+ * this, but it needs 4 network packets for that. Which means, at startup, you
+ * will not receive answers to the first 4 packest, unless there have been some
+ * broadcasts on the network, or your board is on a hub. Reducing the ARP
+ * timeout from default 5 seconds to 200ms we speed up the initial TFTP
+ * transfer, should the user wish one, significantly.
+ */
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "BBG U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x10000
+
+#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_HZ CONFIG_MX51_CLK32/* use 32kHz clock as source */
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CSD0_BASE_ADDR
+#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH
+
+/* Monitor at beginning of flash */
+#if defined(CONFIG_CMD_SF)
+ #define CONFIG_FSL_ENV_IN_SF
+#elif defined(CONFIG_CMD_MMC)
+ #define CONFIG_FSL_ENV_IN_MMC
+#endif
+
+#define CONFIG_ENV_SECT_SIZE (128 * 1024)
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+
+#if defined(CONFIG_FSL_ENV_IN_MMC)
+ #define CONFIG_ENV_IS_IN_MMC 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#elif defined(CONFIG_FSL_ENV_IN_SF)
+ #define CONFIG_ENV_IS_IN_SPI_FLASH 1
+ #define CONFIG_ENV_IS_EMBEDDED 1
+ #define CONFIG_ENV_SPI_CS 1
+ #define CONFIG_ENV_OFFSET (768 * 1024)
+#else
+ #define CONFIG_ENV_IS_NOWHERE 1
+#endif
+
+#endif /* __CONFIG_H */
--
1.6.0.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
2009-09-23 14:47 Fred Fan
@ 2009-09-23 21:47 ` Wolfgang Denk
2009-12-01 16:44 ` Fred Fan
2009-09-24 4:35 ` Prafulla Wadaskar
1 sibling, 1 reply; 15+ messages in thread
From: Wolfgang Denk @ 2009-09-23 21:47 UTC (permalink / raw)
To: u-boot
Dear Fred Fan,
In message <12537172421605-git-send-email-fanyefeng@gmail.com> you wrote:
> This patch just supports boot into u-boot from mmc or spi-nor flash.
> It just implements console, iomux and clock. There are no ethernet,
> nor-flash, mmc or other peripheral drivers.
>
> Signed-off-by: Fred.Fan <fanyefeng@gmail.com>
> Signed-off-by: Fred.Fan <r01011@freescale.com>
Please use a shorter subject (it gets tructaed), something like:
mx51_babbage: add support for Freescale iMX51 board
> diff --git a/MAKEALL b/MAKEALL
> index edebaea..852baf1 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -581,6 +581,7 @@ LIST_ARM_CORTEX_A8=" \
> omap3_pandora \
> omap3_zoom1 \
> omap3_zoom2 \
> + mx51_babbage \
Please keep lists sorted.
> diff --git a/board/freescale/mx51_babbage/board-mx51_babbage.h b/board/freescale/mx51_babbage/board-mx51_babbage.h
> new file mode 100644
> index 0000000..31e3875
> --- /dev/null
> +++ b/board/freescale/mx51_babbage/board-mx51_babbage.h
Please drop the "board-" part of the file name.
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
Please use correct licnese terms. Specify which version of the license
applies, i. e. use something like:
This code is licensed under the GPL, version 2 (or any later version).
> +/*!
> + * @defgroup BRDCFG_MX51_BABBAGE Board Configuration Options
> + * @ingroup MSL_MX51_BABBAGE
> + */
Please get rid of this "!", "@defgroup", "@ingroup" etc. stuff.
> +/*!
> + * @file mx51_babbage/board-mx51_babbage.h
Drop this line. It carries no information.
> + * @brief This file contains all the board level configuration options.
> + *
Drop the blank line.
> + * It currently hold the options defined for MX51 babbage Platform.
> + *
> + * @ingroup BRDCFG_MX51_BABBAGE
Drop this line, Please apply similar to the rest of the code.
> +/* CPLD offsets */
> +#define PBC_LED_CTRL (0x20000)
> +#define PBC_SB_STAT (0x20008)
> +#define PBC_ID_AAAA (0x20040)
> +#define PBC_ID_5555 (0x20048)
> +#define PBC_VERSION (0x20050)
> +#define PBC_ID_CAFE (0x20058)
> +#define PBC_INT_STAT (0x20010)
> +#define PBC_INT_MASK (0x20038)
> +#define PBC_INT_REST (0x20020)
> +#define PBC_SW_RESET (0x20060)
Don't use base address + offsets, but declare proper C structures to
describe the register layout. Then use I/O accessors to access
registers.
> diff --git a/board/freescale/mx51_babbage/config.mk b/board/freescale/mx51_babbage/config.mk
> new file mode 100644
> index 0000000..d8b0f10
> --- /dev/null
> +++ b/board/freescale/mx51_babbage/config.mk
> @@ -0,0 +1,2 @@
> +LDSCRIPT = board/$(VENDOR)/$(BOARD)/u-boot.lds
> +TEXT_BASE = 0x97800000
Even though the file is short, please add a (C) and license header.
> diff --git a/board/freescale/mx51_babbage/flash_header.S b/board/freescale/mx51_babbage/flash_header.S
> new file mode 100644
> index 0000000..bbac2c1
> --- /dev/null
> +++ b/board/freescale/mx51_babbage/flash_header.S
...
> +/*!
> + * @file mx51_babbage/flash_head.S
> + * @brief Thie file contains the information as the image header for boot.
S/Thie/This/ ?
Please explain what "image header" means. U-Boot has an image geader,
too, but you probably refer to something different.
> + * The boot rom code will parse this structure , load image and initial
> + * hardware as the description of hardware setting.
> + */
I read: "The ROM code will ... load ... initial hardware" ?
Something seems to be missing, or do you mean s/initial/initialize/ ?
Please clean up.
> +#include <config.h>
> +#include <asm/arch/mx51.h>
> +#include "board-mx51_babbage.h"
> +
> +#ifdef CONFIG_FLASH_HEADER
> +#ifndef CONFIG_FLASH_HEADER_OFFSET
It seems this is a iMX51 specific thing, right? Then please make this
clear in the name oif the file and the macro names. "FLASH_HEADER" or
"flash_head" is way too generic.
> diff --git a/board/freescale/mx51_babbage/lowlevel_init.S b/board/freescale/mx51_babbage/lowlevel_init.S
> new file mode 100644
> index 0000000..bf536b1
> --- /dev/null
> +++ b/board/freescale/mx51_babbage/lowlevel_init.S
How much of this is really board specific code, or how much of it
should be moved to the CPU directory instead?
> +int dram_init(void)
> +{
> + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
Please use get_ram_size() for autosizing and (simple) RAM test.
> +}
> +
> +static void setup_uart(void)
> +{
> + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
> +
> + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
> + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
> + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
> + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
Hmm... the comment in the code for mxc_request_iomux() reads:
* Request ownership for an IO pin. This function has to be the first one
* being called before that pin is used. The caller has to check the
* return value to make sure it returns 0.
I do not see any such checks in your code?
Either they are missing here, or the whole mxc_request_iomux() is not
needed at all.
> +static void setup_expio(void)
> +{
...
> + /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
> + * WEN=0, WCSA=0, WCSN=0
> + */
Incorrect multiline comment. Please fix globally.
> + /* Reset interrupt status reg */
> + writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
> + writew(0x00, mx51_io_base_addr + PBC_INT_REST);
> + writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
As mentioned above: do not use base address plus offset, but use a
proper C structure to define the register map.
> +#ifdef BOARD_LATE_INIT
> +int board_late_init(void)
> +{
> + return 0;
> +}
> +#endif
If the function is not needed, then don't implement it. Don;t add dead
code.
> +int checkboard(void)
> +{
> + printf("Board: MX51 BABBAGE ");
> +
> + if (system_rev & CHIP_REV_2_5)
> + printf("2.5 [");
> + else if (system_rev & CHIP_REV_2_0)
> + printf("2.0 [");
> + else if (system_rev & CHIP_REV_1_1)
> + printf("1.1 [");
> + else
> + printf("1.0 [");
Please use puts() for constant strings that don;t need any formatting.
> diff --git a/board/freescale/mx51_babbage/u-boot.lds b/board/freescale/mx51_babbage/u-boot.lds
> new file mode 100644
> index 0000000..f608a6d
> --- /dev/null
> +++ b/board/freescale/mx51_babbage/u-boot.lds
Does this board really need a specific linker script? Can we not use a
generic one for all (or most of the) i.MX51 boards?
> + . = ALIGN(4);
> + .text :
> + {
> + /* WARNING - the following is hand-optimized to fit within */
> + /* the sector layout of our flash chips! XXX FIXME XXX */
Why is this needed / useful? It doesn't seem to match the environment
definitions in your board config file.
...
> diff --git a/cpu/arm_cortexa8/mx51/clock.c b/cpu/arm_cortexa8/mx51/clock.c
> new file mode 100644
> index 0000000..3abcdc8
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/clock.c
...
> +static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
...
> +u32 __get_mcu_main_clk(void)
...
> +static u32 __get_periph_clk(void)
Is there any special reason for the "__" pat in all these names? You
are aware that this has a special meaning in standard conforming C
code, aren't you?
Please also add comments what all these functions are doing.
Hey, and add comments what the code is doing. It's not exactly obvious
to me.
> + u32 reg;
> +
> + reg = __raw_readl(MXC_CCM_CBCDR);
> + if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
> + reg = __raw_readl(MXC_CCM_CBCMR);
> + switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
> + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
> + case 0:
> + return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> + case 1:
> + return __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
> + default:
> + return 0;
> + }
> + }
> + return __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
In such cases it's better to turn around the logig, i. e. write:
if ((reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) == 0)
return __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
reg = __raw_readl(MXC_CCM_CBCMR);
switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
case 0:
return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
case 1:
return __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
default:
return 0;
}
/* NOTREACHED */
You see? Less indentation = easier to read.
...
> +void mxc_show_clocks(void)
> +{
> + u32 freq;
> +
> + freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> + printf("mx51 pll1: %dMHz\n", freq / 1000000);
> + freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
> + printf("mx51 pll2: %dMHz\n", freq / 1000000);
> + freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
> + printf("mx51 pll3: %dMHz\n", freq / 1000000);
> + printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
> + printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
> + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
> + printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK));
Please don't print too much during regular boot. Either make this
debug() code, or provide a separate command so the user can print this
if he is interested in this information. Standard boot output shall
be terse, as it affects boot ime.
> diff --git a/cpu/arm_cortexa8/mx51/crm_regs.h b/cpu/arm_cortexa8/mx51/crm_regs.h
> new file mode 100644
> index 0000000..6436bed
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/crm_regs.h
Should this file go to include/... ?
> +/*
> + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
See license header comments above.
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
> +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
> +
> +#define MXC_CCM_BASE CCM_BASE_ADDR
> +#define MXC_DPLL1_BASE PLL1_BASE_ADDR
> +#define MXC_DPLL2_BASE PLL2_BASE_ADDR
> +#define MXC_DPLL3_BASE PLL3_BASE_ADDR
> +
> +/* PLL Register Offsets */
> +#define MXC_PLL_DP_CTL 0x00
> +#define MXC_PLL_DP_CONFIG 0x04
> +#define MXC_PLL_DP_OP 0x08
> +#define MXC_PLL_DP_MFD 0x0C
> +#define MXC_PLL_DP_MFN 0x10
> +#define MXC_PLL_DP_MFNMINUS 0x14
> +#define MXC_PLL_DP_MFNPLUS 0x18
> +#define MXC_PLL_DP_HFS_OP 0x1C
> +#define MXC_PLL_DP_HFS_MFD 0x20
> +#define MXC_PLL_DP_HFS_MFN 0x24
> +#define MXC_PLL_DP_MFN_TOGC 0x28
> +#define MXC_PLL_DP_DESTAT 0x2c
See comments above - use C structs instead of offset definitions.
> diff --git a/cpu/arm_cortexa8/mx51/iomux.c b/cpu/arm_cortexa8/mx51/iomux.c
> new file mode 100644
> index 0000000..80082aa
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/iomux.c
...
> +static inline u32 _get_mux_reg(iomux_pin_name_t pin)
> +{
> + u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
> +
> + if (is_soc_rev(CHIP_REV_2_0) < 0) {
> + if ((pin == MX51_PIN_NANDF_RB5) ||
> + (pin == MX51_PIN_NANDF_RB6) ||
> + (pin == MX51_PIN_NANDF_RB7))
> + ; /* Do nothing */
> + else if (mux_reg >= 0x2FC)
> + mux_reg += 8;
> + else if (mux_reg >= 0x130)
> + mux_reg += 0xC;
> + }
> + mux_reg += IOMUXSW_MUX_CTL;
> + return mux_reg;
> +}
> +
> +static inline u32 _get_pad_reg(iomux_pin_name_t pin)
> +{
Please add comments what all this stuff is supposed to do.
> +
> + if (is_soc_rev(CHIP_REV_2_0) < 0) {
> + if ((pin == MX51_PIN_NANDF_RB5) ||
> + (pin == MX51_PIN_NANDF_RB6) ||
> + (pin == MX51_PIN_NANDF_RB7))
> + ; /* Do nothing */
> + else if (pad_reg == 0x4D0 - PAD_I_START)
> + pad_reg += 0x4C;
> + else if (pad_reg == 0x860 - PAD_I_START)
> + pad_reg += 0x9C;
> + else if (pad_reg >= 0x804 - PAD_I_START)
> + pad_reg += 0xB0;
> + else if (pad_reg >= 0x7FC - PAD_I_START)
> + pad_reg += 0xB4;
> + else if (pad_reg >= 0x4E4 - PAD_I_START)
> + pad_reg += 0xCC;
> + else
> + pad_reg += 8;
You may also want to explain suchblack magic like the code here.
And please add parens around the (0x??? - PAD_I_START) parts.
...
> +/*!
> + * This function is used to configure a pin through the IOMUX module.
> + * FIXED ME: for backward compatible. Will be static function!
I don't understand what this means. Please explain.
> + * @param pin a pin number as defined in \b #iomux_pin_name_t
> + * @param cfg an output function as defined in \b #iomux_pin_cfg_t
> + *
> + * @return 0 if successful; Non-zero otherwise
> + */
> +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
...
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int print_cpuinfo(void)
> +{
> + printf("CPU: Freescale i.MX51 family %d.%dV at %d MHz\n",
> + (get_board_rev() & 0xFF) >> 4,
> + (get_board_rev() & 0xF),
> + __get_mcu_main_clk() / 1000000);
> + mxc_show_clocks();
Please see above - please be terse.
> diff --git a/cpu/arm_cortexa8/mx51/timer.c b/cpu/arm_cortexa8/mx51/timer.c
> new file mode 100644
> index 0000000..5201768
> --- /dev/null
> +++ b/cpu/arm_cortexa8/mx51/timer.c
...
> +/* General purpose timers registers */
> +#define GPTCR GPT1_BASE_ADDR /* Control register */
> +#define GPTPR (GPT1_BASE_ADDR + 0x4) /* Prescaler register */
> +#define GPTSR (GPT1_BASE_ADDR + 0x8) /* Status register */
> +#define GPTCNT (GPT1_BASE_ADDR + 0x24) /* Counter register */
> +
> +/* General purpose timers bitfields */
> +#define GPTCR_SWR (1<<15) /* Software reset */
> +#define GPTCR_FRR (1<<9) /* Freerun / restart */
> +#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
> +#define GPTCR_TEN (1) /* Timer enable */
Move to header file. Use C struct instead of base addr + offsets.
...
> +/*!
> + * defines for SPBA modules
> + */
> +#define SPBA_SDHC1 0x04
> +#define SPBA_SDHC2 0x08
> +#define SPBA_UART3 0x0C
> +#define SPBA_CSPI1 0x10
> +#define SPBA_SSI2 0x14
> +#define SPBA_SDHC3 0x20
> +#define SPBA_SDHC4 0x24
> +#define SPBA_SPDIF 0x28
> +#define SPBA_ATA 0x30
> +#define SPBA_SLIM 0x34
> +#define SPBA_HSI2C 0x38
> +#define SPBA_CTRL 0x3C
Use C struct ?
> +/*
> + * Interrupt numbers
> + */
> +#define MXC_INT_BASE 0
> +#define MXC_INT_RESV0 0
> +#define MXC_INT_MMC_SDHC1 1
> +#define MXC_INT_MMC_SDHC2 2
> +#define MXC_INT_MMC_SDHC3 3
> +#define MXC_INT_MMC_SDHC4 4
> +#define MXC_INT_RESV5 5
> +#define MXC_INT_SDMA 6
> +#define MXC_INT_IOMUX 7
> +#define MXC_INT_NFC 8
> +#define MXC_INT_VPU 9
> +#define MXC_INT_IPU_ERR 10
> +#define MXC_INT_IPU_SYN 11
> +#define MXC_INT_GPU 12
> +#define MXC_INT_RESV13 13
> +#define MXC_INT_USB_H1 14
> +#define MXC_INT_EMI 15
> +#define MXC_INT_USB_H2 16
> +#define MXC_INT_USB_H3 17
> +#define MXC_INT_USB_OTG 18
> +#define MXC_INT_SAHARA_H0 19
> +#define MXC_INT_SAHARA_H1 20
> +#define MXC_INT_SCC_SMN 21
> +#define MXC_INT_SCC_STZ 22
> +#define MXC_INT_SCC_SCM 23
> +#define MXC_INT_SRTC_NTZ 24
> +#define MXC_INT_SRTC_TZ 25
> +#define MXC_INT_RTIC 26
> +#define MXC_INT_CSU 27
> +#define MXC_INT_SLIM_B 28
> +#define MXC_INT_SSI1 29
> +#define MXC_INT_SSI2 30
> +#define MXC_INT_UART1 31
> +#define MXC_INT_UART2 32
> +#define MXC_INT_UART3 33
> +#define MXC_INT_RESV34 34
> +#define MXC_INT_RESV35 35
> +#define MXC_INT_CSPI1 36
> +#define MXC_INT_CSPI2 37
> +#define MXC_INT_CSPI 38
> +#define MXC_INT_GPT 39
> +#define MXC_INT_EPIT1 40
> +#define MXC_INT_EPIT2 41
> +#define MXC_INT_GPIO1_INT7 42
> +#define MXC_INT_GPIO1_INT6 43
> +#define MXC_INT_GPIO1_INT5 44
> +#define MXC_INT_GPIO1_INT4 45
> +#define MXC_INT_GPIO1_INT3 46
> +#define MXC_INT_GPIO1_INT2 47
> +#define MXC_INT_GPIO1_INT1 48
> +#define MXC_INT_GPIO1_INT0 49
> +#define MXC_INT_GPIO1_LOW 50
> +#define MXC_INT_GPIO1_HIGH 51
> +#define MXC_INT_GPIO2_LOW 52
> +#define MXC_INT_GPIO2_HIGH 53
> +#define MXC_INT_GPIO3_LOW 54
> +#define MXC_INT_GPIO3_HIGH 55
> +#define MXC_INT_GPIO4_LOW 56
> +#define MXC_INT_GPIO4_HIGH 57
> +#define MXC_INT_WDOG1 58
> +#define MXC_INT_WDOG2 59
> +#define MXC_INT_KPP 60
> +#define MXC_INT_PWM1 61
> +#define MXC_INT_I2C1 62
> +#define MXC_INT_I2C2 63
> +#define MXC_INT_HS_I2C 64
> +#define MXC_INT_RESV65 65
> +#define MXC_INT_RESV66 66
> +#define MXC_INT_SIM_IPB 67
> +#define MXC_INT_SIM_DAT 68
> +#define MXC_INT_IIM 69
> +#define MXC_INT_ATA 70
> +#define MXC_INT_CCM1 71
> +#define MXC_INT_CCM2 72
> +#define MXC_INT_GPC1 73
> +#define MXC_INT_GPC2 74
> +#define MXC_INT_SRC 75
> +#define MXC_INT_NM 76
> +#define MXC_INT_PMU 77
> +#define MXC_INT_CTI_IRQ 78
> +#define MXC_INT_CTI1_TG0 79
> +#define MXC_INT_CTI1_TG1 80
> +#define MXC_INT_MCG_ERR 81
> +#define MXC_INT_MCG_TMR 82
> +#define MXC_INT_MCG_FUNC 83
> +#define MXC_INT_RESV84 84
> +#define MXC_INT_RESV85 85
> +#define MXC_INT_RESV86 86
> +#define MXC_INT_FEC 87
> +#define MXC_INT_OWIRE 88
> +#define MXC_INT_CTI1_TG2 89
> +#define MXC_INT_SJC 90
> +#define MXC_INT_SPDIF 91
> +#define MXC_INT_TVE 92
> +#define MXC_INT_FIRI 93
> +#define MXC_INT_PWM2 94
> +#define MXC_INT_SLIM_EXP 95
> +#define MXC_INT_SSI3 96
> +#define MXC_INT_RESV97 97
> +#define MXC_INT_CTI1_TG3 98
> +#define MXC_INT_SMC_RX 99
> +#define MXC_INT_VPU_IDLE 100
> +#define MXC_INT_RESV101 101
> +#define MXC_INT_GPU_IDLE 102
> +
> +#define MXC_MAX_INT_LINES 128
Use C struct ?
And so on and on ...
> diff --git a/include/configs/mx51_babbage.h b/include/configs/mx51_babbage.h
> new file mode 100644
> index 0000000..a24b39b
> --- /dev/null
> +++ b/include/configs/mx51_babbage.h
...
> +#define BOARD_LATE_INIT
Why do you #define this, when you don't need it at all?
> +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
> +#define CONFIG_SYS_MEMTEST_END 0x10000
That's not exactly a thorough testing, then. And is low memory really
unused? Please check!
> +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
Don't undef what doesn't exist.
> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> +
> +#define CONFIG_SYS_HZ CONFIG_MX51_CLK32/* use 32kHz clock as source */
CONFIG_SYS_HZ must be 1000.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Voodoo Programming: Things programmers do that they know shouldn't
work but they try anyway, and which sometimes actually work, such as
recompiling everything. - Karl Lehenbauer
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
2009-09-23 14:47 Fred Fan
2009-09-23 21:47 ` Wolfgang Denk
@ 2009-09-24 4:35 ` Prafulla Wadaskar
1 sibling, 0 replies; 15+ messages in thread
From: Prafulla Wadaskar @ 2009-09-24 4:35 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Fred Fan
> Sent: Wednesday, September 23, 2009 8:17 PM
> To: u-boot at lists.denx.de
> Cc: Fred.Fan
> Subject: [U-Boot] [PATCH] imx51:Add support basic boot code
> of freescale imx51 bbg board
>
> This patch just supports boot into u-boot from mmc or spi-nor flash.
> It just implements console, iomux and clock. There are no ethernet,
> nor-flash, mmc or other peripheral drivers.
>
> Signed-off-by: Fred.Fan <fanyefeng@gmail.com>
> Signed-off-by: Fred.Fan <r01011@freescale.com>
Do you really need two email references for the same person here?
Regards..
Prafulla . .
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
2009-09-23 21:47 ` Wolfgang Denk
@ 2009-12-01 16:44 ` Fred Fan
2009-12-01 21:15 ` Wolfgang Denk
2009-12-04 11:16 ` Stefano Babic
0 siblings, 2 replies; 15+ messages in thread
From: Fred Fan @ 2009-12-01 16:44 UTC (permalink / raw)
To: u-boot
Dear wolfgang,
I almost fixed all of your comments.
By some of them I can not fix them now.
1) Copyright block. It defined freescale other team. I can not change them
directly.
2) iomux module can not use C structure to access registers. Because
register has
encoded in to pin definition.
When I tested the new code on target board, I will send out to review
again.
Best Regards
Fred
2009/9/24 Wolfgang Denk <wd@denx.de>
> Dear Fred Fan,
>
> In message <12537172421605-git-send-email-fanyefeng@gmail.com> you wrote:
> > This patch just supports boot into u-boot from mmc or spi-nor flash.
> > It just implements console, iomux and clock. There are no ethernet,
> > nor-flash, mmc or other peripheral drivers.
> >
> > Signed-off-by: Fred.Fan <fanyefeng@gmail.com>
> > Signed-off-by: Fred.Fan <r01011@freescale.com>
>
> Please use a shorter subject (it gets tructaed), something like:
>
> mx51_babbage: add support for Freescale iMX51 board
> [Fred] ok
> > diff --git a/MAKEALL b/MAKEALL
> > index edebaea..852baf1 100755
> > --- a/MAKEALL
> > +++ b/MAKEALL
> > @@ -581,6 +581,7 @@ LIST_ARM_CORTEX_A8=" \
> > omap3_pandora \
> > omap3_zoom1 \
> > omap3_zoom2 \
> > + mx51_babbage \
>
> Please keep lists sorted.
> [Fred] ok.
> > diff --git a/board/freescale/mx51_babbage/board-mx51_babbage.h
> b/board/freescale/mx51_babbage/board-mx51_babbage.h
> > new file mode 100644
> > index 0000000..31e3875
> > --- /dev/null
> > +++ b/board/freescale/mx51_babbage/board-mx51_babbage.h
>
> Please drop the "board-" part of the file name.
> [Fred] ok.
> > +/*
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
>
> Please use correct licnese terms. Specify which version of the license
> applies, i. e. use something like:
>
> This code is licensed under the GPL, version 2 (or any later version).
> [Fred] Thanks. But this copyright block is defined by freescale.
>
It is used at the latest freescale's source or header file in linux
kernel.
I will tell our team about this comment.
Could I keep the block until it is changed by freescale?
> > +/*!
> > + * @defgroup BRDCFG_MX51_BABBAGE Board Configuration Options
> > + * @ingroup MSL_MX51_BABBAGE
> > + */
>
> Please get rid of this "!", "@defgroup", "@ingroup" etc. stuff.
> [Fred] ok
> > +/*!
> > + * @file mx51_babbage/board-mx51_babbage.h
>
> Drop this line. It carries no information.
> [Fred] ok
> > + * @brief This file contains all the board level configuration options.
> > + *
>
> Drop the blank line.
> [Fred] ok.
> > + * It currently hold the options defined for MX51 babbage Platform.
> > + *
> > + * @ingroup BRDCFG_MX51_BABBAGE
>
> Drop this line, Please apply similar to the rest of the code.
> [Fred] ok.
> > +/* CPLD offsets */
> > +#define PBC_LED_CTRL (0x20000)
> > +#define PBC_SB_STAT (0x20008)
> > +#define PBC_ID_AAAA (0x20040)
> > +#define PBC_ID_5555 (0x20048)
> > +#define PBC_VERSION (0x20050)
> > +#define PBC_ID_CAFE (0x20058)
> > +#define PBC_INT_STAT (0x20010)
> > +#define PBC_INT_MASK (0x20038)
> > +#define PBC_INT_REST (0x20020)
> > +#define PBC_SW_RESET (0x20060)
>
> Don't use base address + offsets, but declare proper C structures to
> describe the register layout. Then use I/O accessors to access
> registers.
> [Fred] ok
>
> > diff --git a/board/freescale/mx51_babbage/config.mkb/board/freescale/mx51_babbage/
> config.mk
> > new file mode 100644
> > index 0000000..d8b0f10
> > --- /dev/null
> > +++ b/board/freescale/mx51_babbage/config.mk
> > @@ -0,0 +1,2 @@
> > +LDSCRIPT = board/$(VENDOR)/$(BOARD)/u-boot.lds
> > +TEXT_BASE = 0x97800000
>
> Even though the file is short, please add a (C) and license header.
> [Fred] ok
> > diff --git a/board/freescale/mx51_babbage/flash_header.S
> b/board/freescale/mx51_babbage/flash_header.S
> > new file mode 100644
> > index 0000000..bbac2c1
> > --- /dev/null
> > +++ b/board/freescale/mx51_babbage/flash_header.S
> ...
> > +/*!
> > + * @file mx51_babbage/flash_head.S
> > + * @brief Thie file contains the information as the image header for
> boot.
>
> S/Thie/This/ ?
> [Fred] ok
> Please explain what "image header" means. U-Boot has an image geader,
> too, but you probably refer to something different.
>
> > + * The boot rom code will parse this structure , load image and initial
> > + * hardware as the description of hardware setting.
> > + */
>
> I read: "The ROM code will ... load ... initial hardware" ?
> [Fred] MX family soc has internal boot mode. At this mode, the rom code in
> soc will
>
read the setting array to initial hardware.
Something seems to be missing, or do you mean s/initial/initialize/ ?
>
> Please clean up.
> [Fred] Changed
>
> > +#include <config.h>
> > +#include <asm/arch/mx51.h>
> > +#include "board-mx51_babbage.h"
> > +
> > +#ifdef CONFIG_FLASH_HEADER
> > +#ifndef CONFIG_FLASH_HEADER_OFFSET
>
> It seems this is a iMX51 specific thing, right? Then please make this
> clear in the name oif the file and the macro names. "FLASH_HEADER" or
> "flash_head" is way too generic.
> [Fred] It is coming from freescale spec. It is the header of boot image for
> freescale internal boot mode.
>
> > diff --git a/board/freescale/mx51_babbage/lowlevel_init.S
> b/board/freescale/mx51_babbage/lowlevel_init.S
> > new file mode 100644
> > index 0000000..bf536b1
> > --- /dev/null
> > +++ b/board/freescale/mx51_babbage/lowlevel_init.S
>
> How much of this is really board specific code, or how much of it
> should be moved to the CPU directory instead?
> [Fred] Although freescale's boards use same configuration about M4IF, AIPS
> or others.
>
we can not sure other boards will use same configuration use freescale
boards.
>
> > +int dram_init(void)
> > +{
> > + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
> > + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
>
> Please use get_ram_size() for autosizing and (simple) RAM test.
> [Fred] ok
> > +}
> > +
> > +static void setup_uart(void)
> > +{
> > + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
> > + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
> > +
> > + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
> > + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
> > + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
> > + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
> > + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
> > + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
> > + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
> > + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
>
> Hmm... the comment in the code for mxc_request_iomux() reads:
>
> * Request ownership for an IO pin. This function has to be the first one
> * being called before that pin is used. The caller has to check the
> * return value to make sure it returns 0.
>
> I do not see any such checks in your code?
>
> Either they are missing here, or the whole mxc_request_iomux() is not
> needed at all.
> [Fred] OK. I changed these functions to non return function.
>
Because boot load is not dynamic active or modules, there are no modules
with muxed pins.
> > +static void setup_expio(void)
> > +{
> ...
> > + /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
> > + * WEN=0, WCSA=0, WCSN=0
> > + */
>
> Incorrect multiline comment. Please fix globally.
> [Fred] oK
> > + /* Reset interrupt status reg */
> > + writew(0x1F, mx51_io_base_addr + PBC_INT_REST);
> > + writew(0x00, mx51_io_base_addr + PBC_INT_REST);
> > + writew(0xFFFF, mx51_io_base_addr + PBC_INT_MASK);
>
> As mentioned above: do not use base address plus offset, but use a
> proper C structure to define the register map.
> [Fred] ok.
>
> > +#ifdef BOARD_LATE_INIT
> > +int board_late_init(void)
> > +{
> > + return 0;
> > +}
> > +#endif
>
> If the function is not needed, then don't implement it. Don;t add dead
> code.
> [Fred] ok.
> > +int checkboard(void)
> > +{
> > + printf("Board: MX51 BABBAGE ");
> > +
> > + if (system_rev & CHIP_REV_2_5)
> > + printf("2.5 [");
> > + else if (system_rev & CHIP_REV_2_0)
> > + printf("2.0 [");
> > + else if (system_rev & CHIP_REV_1_1)
> > + printf("1.1 [");
> > + else
> > + printf("1.0 [");
>
> Please use puts() for constant strings that don;t need any formatting.
> [Fred] ok.
>
> > diff --git a/board/freescale/mx51_babbage/u-boot.lds
> b/board/freescale/mx51_babbage/u-boot.lds
> > new file mode 100644
> > index 0000000..f608a6d
> > --- /dev/null
> > +++ b/board/freescale/mx51_babbage/u-boot.lds
>
> Does this board really need a specific linker script? Can we not use a
> generic one for all (or most of the) i.MX51 boards?
> [Fred] Need link flash header at the top of image.
>
Later tefano Babic will fix it.
> > + . = ALIGN(4);
> > + .text :
> > + {
> > + /* WARNING - the following is hand-optimized to fit within */
> > + /* the sector layout of our flash chips! XXX FIXME XXX */
>
> Why is this needed / useful? It doesn't seem to match the environment
> definitions in your board config file.
> [Fred] i.MX51 babbage no such issue.
> ...
> > diff --git a/cpu/arm_cortexa8/mx51/clock.c
> b/cpu/arm_cortexa8/mx51/clock.c
> > new file mode 100644
> > index 0000000..3abcdc8
> > --- /dev/null
> > +++ b/cpu/arm_cortexa8/mx51/clock.c
> ...
> > +static u32 __decode_pll(enum pll_clocks pll, u32 infreq)
> ...
> > +u32 __get_mcu_main_clk(void)
> ...
> > +static u32 __get_periph_clk(void)
>
> Is there any special reason for the "__" pat in all these names? You
> are aware that this has a special meaning in standard conforming C
> code, aren't you?
>
>
> Please also add comments what all these functions are doing.
>
> Hey, and add comments what the code is doing. It's not exactly obvious
> to me.
> [Fred] OK.
>
> > + u32 reg;
> > +
> > + reg = __raw_readl(MXC_CCM_CBCDR);
> > + if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
> > + reg = __raw_readl(MXC_CCM_CBCMR);
> > + switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
> > + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
> > + case 0:
> > + return __decode_pll(PLL1_CLK,
> CONFIG_MX51_HCLK_FREQ);
> > + case 1:
> > + return __decode_pll(PLL3_CLK,
> CONFIG_MX51_HCLK_FREQ);
> > + default:
> > + return 0;
> > + }
> > + }
> > + return __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
>
> In such cases it's better to turn around the logig, i. e. write:
>
> if ((reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) == 0)
> return __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
>
> reg = __raw_readl(MXC_CCM_CBCMR);
> switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
> MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
> case 0:
> return __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> case 1:
> return __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
> default:
> return 0;
> }
> /* NOTREACHED */
>
> You see? Less indentation = easier to read.
> [Fred] Thanks very mush.
> ...
> > +void mxc_show_clocks(void)
> > +{
> > + u32 freq;
> > +
> > + freq = __decode_pll(PLL1_CLK, CONFIG_MX51_HCLK_FREQ);
> > + printf("mx51 pll1: %dMHz\n", freq / 1000000);
> > + freq = __decode_pll(PLL2_CLK, CONFIG_MX51_HCLK_FREQ);
> > + printf("mx51 pll2: %dMHz\n", freq / 1000000);
> > + freq = __decode_pll(PLL3_CLK, CONFIG_MX51_HCLK_FREQ);
> > + printf("mx51 pll3: %dMHz\n", freq / 1000000);
> > + printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
> > + printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
> > + printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
> > + printf("cspi clock : %dHz\n", mxc_get_clock(MXC_CSPI_CLK));
>
> Please don't print too much during regular boot. Either make this
> debug() code, or provide a separate command so the user can print this
> if he is interested in this information. Standard boot output shall
> be terse, as it affects boot ime.
> [Fred] OK. I just keep some core clock.
>
> > diff --git a/cpu/arm_cortexa8/mx51/crm_regs.h
> b/cpu/arm_cortexa8/mx51/crm_regs.h
> > new file mode 100644
> > index 0000000..6436bed
> > --- /dev/null
> > +++ b/cpu/arm_cortexa8/mx51/crm_regs.h
>
> Should this file go to include/... ?
> [Fred] ok.
> > +/*
> > + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
> > + */
> > +
> > +/*
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
>
> See license header comments above.
> [Fred] Could I keep our block until freescale agree to change them?
>
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html> + */
> > +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
> > +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
> > +
> > +#define MXC_CCM_BASE CCM_BASE_ADDR
> > +#define MXC_DPLL1_BASE PLL1_BASE_ADDR
> > +#define MXC_DPLL2_BASE PLL2_BASE_ADDR
> > +#define MXC_DPLL3_BASE PLL3_BASE_ADDR
> > +
> > +/* PLL Register Offsets */
> > +#define MXC_PLL_DP_CTL 0x00
> > +#define MXC_PLL_DP_CONFIG 0x04
> > +#define MXC_PLL_DP_OP 0x08
> > +#define MXC_PLL_DP_MFD 0x0C
> > +#define MXC_PLL_DP_MFN 0x10
> > +#define MXC_PLL_DP_MFNMINUS 0x14
> > +#define MXC_PLL_DP_MFNPLUS 0x18
> > +#define MXC_PLL_DP_HFS_OP 0x1C
> > +#define MXC_PLL_DP_HFS_MFD 0x20
> > +#define MXC_PLL_DP_HFS_MFN 0x24
> > +#define MXC_PLL_DP_MFN_TOGC 0x28
> > +#define MXC_PLL_DP_DESTAT 0x2c
>
> See comments above - use C structs instead of offset definitions.
>
> > diff --git a/cpu/arm_cortexa8/mx51/iomux.c
> b/cpu/arm_cortexa8/mx51/iomux.c
> > new file mode 100644
> > index 0000000..80082aa
> > --- /dev/null
> > +++ b/cpu/arm_cortexa8/mx51/iomux.c
> ...
> > +static inline u32 _get_mux_reg(iomux_pin_name_t pin)
> > +{
> > + u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
> > +
> > + if (is_soc_rev(CHIP_REV_2_0) < 0) {
> > + if ((pin == MX51_PIN_NANDF_RB5) ||
> > + (pin == MX51_PIN_NANDF_RB6) ||
> > + (pin == MX51_PIN_NANDF_RB7))
> > + ; /* Do nothing */
> > + else if (mux_reg >= 0x2FC)
> > + mux_reg += 8;
> > + else if (mux_reg >= 0x130)
> > + mux_reg += 0xC;
> > + }
> > + mux_reg += IOMUXSW_MUX_CTL;
> > + return mux_reg;
> > +}
> > +
> > +static inline u32 _get_pad_reg(iomux_pin_name_t pin)
> > +{
>
>
>
> Please add comments what all this stuff is supposed to do.
> [Fred] OK.
> > +
> > + if (is_soc_rev(CHIP_REV_2_0) < 0) {
> > + if ((pin == MX51_PIN_NANDF_RB5) ||
> > + (pin == MX51_PIN_NANDF_RB6) ||
> > + (pin == MX51_PIN_NANDF_RB7))
> > + ; /* Do nothing */
> > + else if (pad_reg == 0x4D0 - PAD_I_START)
> > + pad_reg += 0x4C;
> > + else if (pad_reg == 0x860 - PAD_I_START)
> > + pad_reg += 0x9C;
> > + else if (pad_reg >= 0x804 - PAD_I_START)
> > + pad_reg += 0xB0;
> > + else if (pad_reg >= 0x7FC - PAD_I_START)
> > + pad_reg += 0xB4;
> > + else if (pad_reg >= 0x4E4 - PAD_I_START)
> > + pad_reg += 0xCC;
> > + else
> > + pad_reg += 8;
>
> You may also want to explain suchblack magic like the code here.
>
> And please add parens around the (0x??? - PAD_I_START) parts.
> [Fred] OK.
> iomux also use base + offset to access register. Because freescale
>
encode the register information into the pin definition. It is not easy to
change to structure access.
> +/*!
> > + * This function is used to configure a pin through the IOMUX module.
> > + * FIXED ME: for backward compatible. Will be static function!
>
> I don't understand what this means. Please explain.
> [Fred] It is copied from kernel source code. At the old version in kernel,
>
there are different implementation.
> > + * @param pin a pin number as defined in \b
> #iomux_pin_name_t
> > + * @param cfg an output function as defined in \b
> #iomux_pin_cfg_t
> > + *
> > + * @return 0 if successful; Non-zero otherwise
> > + */
> > +static int iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
>
> ...
>
> > +#if defined(CONFIG_DISPLAY_CPUINFO)
> > +int print_cpuinfo(void)
> > +{
> > + printf("CPU: Freescale i.MX51 family %d.%dV at %d MHz\n",
> > + (get_board_rev() & 0xFF) >> 4,
> > + (get_board_rev() & 0xF),
> > + __get_mcu_main_clk() / 1000000);
> > + mxc_show_clocks();
>
> Please see above - please be terse.
> [Fred] We want to show the chip version: TO1 version or TO2, etc.
>
So customer get the hardware information about soc level.
> > diff --git a/cpu/arm_cortexa8/mx51/timer.c
> b/cpu/arm_cortexa8/mx51/timer.c
> > new file mode 100644
> > index 0000000..5201768
> > --- /dev/null
> > +++ b/cpu/arm_cortexa8/mx51/timer.c
> ...
> > +/* General purpose timers registers */
> > +#define GPTCR GPT1_BASE_ADDR /* Control register */
> > +#define GPTPR (GPT1_BASE_ADDR + 0x4) /* Prescaler register */
> > +#define GPTSR (GPT1_BASE_ADDR + 0x8) /* Status register */
> > +#define GPTCNT (GPT1_BASE_ADDR + 0x24) /* Counter register */
> > +
> > +/* General purpose timers bitfields */
> > +#define GPTCR_SWR (1<<15) /* Software reset */
> > +#define GPTCR_FRR (1<<9) /* Freerun / restart */
> > +#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
> > +#define GPTCR_TEN (1) /* Timer enable */
>
> Move to header file. Use C struct instead of base addr + offsets.
> [Fred] ok.
> ...
> > +/*!
> > + * defines for SPBA modules
> > + */
> > +#define SPBA_SDHC1 0x04
> > +#define SPBA_SDHC2 0x08
> > +#define SPBA_UART3 0x0C
> > +#define SPBA_CSPI1 0x10
> > +#define SPBA_SSI2 0x14
> > +#define SPBA_SDHC3 0x20
> > +#define SPBA_SDHC4 0x24
> > +#define SPBA_SPDIF 0x28
> > +#define SPBA_ATA 0x30
> > +#define SPBA_SLIM 0x34
> > +#define SPBA_HSI2C 0x38
> > +#define SPBA_CTRL 0x3C
>
> Use C struct ?
> [Fred] ok.
> > +/*
> > + * Interrupt numbers
> > + */
> > +#define MXC_INT_BASE 0
> > +#define MXC_INT_RESV0 0
> > +#define MXC_INT_MMC_SDHC1 1
> > +#define MXC_INT_MMC_SDHC2 2
> > +#define MXC_INT_MMC_SDHC3 3
> > +#define MXC_INT_MMC_SDHC4 4
> > +#define MXC_INT_RESV5 5
> > +#define MXC_INT_SDMA 6
> > +#define MXC_INT_IOMUX 7
> > +#define MXC_INT_NFC 8
> > +#define MXC_INT_VPU 9
> > +#define MXC_INT_IPU_ERR 10
> > +#define MXC_INT_IPU_SYN 11
> > +#define MXC_INT_GPU 12
> > +#define MXC_INT_RESV13 13
> > +#define MXC_INT_USB_H1 14
> > +#define MXC_INT_EMI 15
> > +#define MXC_INT_USB_H2 16
> > +#define MXC_INT_USB_H3 17
> > +#define MXC_INT_USB_OTG 18
> > +#define MXC_INT_SAHARA_H0 19
> > +#define MXC_INT_SAHARA_H1 20
> > +#define MXC_INT_SCC_SMN 21
> > +#define MXC_INT_SCC_STZ 22
> > +#define MXC_INT_SCC_SCM 23
> > +#define MXC_INT_SRTC_NTZ 24
> > +#define MXC_INT_SRTC_TZ 25
> > +#define MXC_INT_RTIC 26
> > +#define MXC_INT_CSU 27
> > +#define MXC_INT_SLIM_B 28
> > +#define MXC_INT_SSI1 29
> > +#define MXC_INT_SSI2 30
> > +#define MXC_INT_UART1 31
> > +#define MXC_INT_UART2 32
> > +#define MXC_INT_UART3 33
> > +#define MXC_INT_RESV34 34
> > +#define MXC_INT_RESV35 35
> > +#define MXC_INT_CSPI1 36
> > +#define MXC_INT_CSPI2 37
> > +#define MXC_INT_CSPI 38
> > +#define MXC_INT_GPT 39
> > +#define MXC_INT_EPIT1 40
> > +#define MXC_INT_EPIT2 41
> > +#define MXC_INT_GPIO1_INT7 42
> > +#define MXC_INT_GPIO1_INT6 43
> > +#define MXC_INT_GPIO1_INT5 44
> > +#define MXC_INT_GPIO1_INT4 45
> > +#define MXC_INT_GPIO1_INT3 46
> > +#define MXC_INT_GPIO1_INT2 47
> > +#define MXC_INT_GPIO1_INT1 48
> > +#define MXC_INT_GPIO1_INT0 49
> > +#define MXC_INT_GPIO1_LOW 50
> > +#define MXC_INT_GPIO1_HIGH 51
> > +#define MXC_INT_GPIO2_LOW 52
> > +#define MXC_INT_GPIO2_HIGH 53
> > +#define MXC_INT_GPIO3_LOW 54
> > +#define MXC_INT_GPIO3_HIGH 55
> > +#define MXC_INT_GPIO4_LOW 56
> > +#define MXC_INT_GPIO4_HIGH 57
> > +#define MXC_INT_WDOG1 58
> > +#define MXC_INT_WDOG2 59
> > +#define MXC_INT_KPP 60
> > +#define MXC_INT_PWM1 61
> > +#define MXC_INT_I2C1 62
> > +#define MXC_INT_I2C2 63
> > +#define MXC_INT_HS_I2C 64
> > +#define MXC_INT_RESV65 65
> > +#define MXC_INT_RESV66 66
> > +#define MXC_INT_SIM_IPB 67
> > +#define MXC_INT_SIM_DAT 68
> > +#define MXC_INT_IIM 69
> > +#define MXC_INT_ATA 70
> > +#define MXC_INT_CCM1 71
> > +#define MXC_INT_CCM2 72
> > +#define MXC_INT_GPC1 73
> > +#define MXC_INT_GPC2 74
> > +#define MXC_INT_SRC 75
> > +#define MXC_INT_NM 76
> > +#define MXC_INT_PMU 77
> > +#define MXC_INT_CTI_IRQ 78
> > +#define MXC_INT_CTI1_TG0 79
> > +#define MXC_INT_CTI1_TG1 80
> > +#define MXC_INT_MCG_ERR 81
> > +#define MXC_INT_MCG_TMR 82
> > +#define MXC_INT_MCG_FUNC 83
> > +#define MXC_INT_RESV84 84
> > +#define MXC_INT_RESV85 85
> > +#define MXC_INT_RESV86 86
> > +#define MXC_INT_FEC 87
> > +#define MXC_INT_OWIRE 88
> > +#define MXC_INT_CTI1_TG2 89
> > +#define MXC_INT_SJC 90
> > +#define MXC_INT_SPDIF 91
> > +#define MXC_INT_TVE 92
> > +#define MXC_INT_FIRI 93
> > +#define MXC_INT_PWM2 94
> > +#define MXC_INT_SLIM_EXP 95
> > +#define MXC_INT_SSI3 96
> > +#define MXC_INT_RESV97 97
> > +#define MXC_INT_CTI1_TG3 98
> > +#define MXC_INT_SMC_RX 99
> > +#define MXC_INT_VPU_IDLE 100
> > +#define MXC_INT_RESV101 101
> > +#define MXC_INT_GPU_IDLE 102
> > +
> > +#define MXC_MAX_INT_LINES 128
>
> Use C struct ?
>
> And so on and on ...
> [Fred] It is not register definitions. It is irq number. But uboot is not
> enable them.
>
I will remove them.
And there are some definitions will be used in assemble code.
Must keep them.
> diff --git a/include/configs/mx51_babbage.h
> b/include/configs/mx51_babbage.h
> > new file mode 100644
> > index 0000000..a24b39b
> > --- /dev/null
> > +++ b/include/configs/mx51_babbage.h
> ...
> > +#define BOARD_LATE_INIT
>
> Why do you #define this, when you don't need it at all?
> [Fred] I removed. But it will be added in the furture for power supply
> operation.
>
> > +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
> > +#define CONFIG_SYS_MEMTEST_END 0x10000
>
> That's not exactly a thorough testing, then. And is low memory really
> unused? Please check!
> [Fred] yes. It is not used. We just the bottom of ram.
>
> > +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board
> info, in Hz */
>
> Don't undef what doesn't exist.
> [Fred] OK. I will fix them.
> > +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
> > +
> > +#define CONFIG_SYS_HZ CONFIG_MX51_CLK32/* use 32kHz clock as
> source */
>
> CONFIG_SYS_HZ must be 1000.
> [Fred] done.
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> Voodoo Programming: Things programmers do that they know shouldn't
> work but they try anyway, and which sometimes actually work, such as
> recompiling everything. - Karl Lehenbauer
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
2009-12-01 16:44 ` Fred Fan
@ 2009-12-01 21:15 ` Wolfgang Denk
2009-12-04 11:16 ` Stefano Babic
1 sibling, 0 replies; 15+ messages in thread
From: Wolfgang Denk @ 2009-12-01 21:15 UTC (permalink / raw)
To: u-boot
Dear Fred Fan,
In message <2f495dc80912010844h6b4aa1e4i4588f808384b6272@mail.gmail.com> you wrote:
>
> I almost fixed all of your comments.
> By some of them I can not fix them now.
> 1) Copyright block. It defined freescale other team. I can not change them
> directly.
I see. We will have to wait for this change, then.
> 2) iomux module can not use C structure to access registers. Because
> register has
> encoded in to pin definition.
I don't understand this statement. Why do you think this cannot be
done with C structs and I/O accessors?
> When I tested the new code on target board, I will send out to review
> again.
I'm looking forward to get this mainlined, but please fix all issues
first. Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Even if you can deceive people about a product through misleading
statements, sooner or later the product will speak for itself.
- Hajime Karatsu
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
2009-12-01 16:44 ` Fred Fan
2009-12-01 21:15 ` Wolfgang Denk
@ 2009-12-04 11:16 ` Stefano Babic
2009-12-14 2:28 ` Fred Fan
1 sibling, 1 reply; 15+ messages in thread
From: Stefano Babic @ 2009-12-04 11:16 UTC (permalink / raw)
To: u-boot
Fred Fan wrote:
> Dear wolfgang,
> I almost fixed all of your comments.
Hi Fred,
I have already tested your patch on the babbage2 board and I would ask
you about the status. The boot loader does not start (I have tried
flashing the SPI NOR, and this seems ok. The code seems loaded from the
flash) but the board hangs. With the debugger seems that it hangs in the
init_clock assemby routine in lowlevel_init.S.
Have you seen the same behavior or do you think it depens on my
environment ?
Regards,
Stefano
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
2009-12-04 11:16 ` Stefano Babic
@ 2009-12-14 2:28 ` Fred Fan
2009-12-29 22:41 ` stefano babic
0 siblings, 1 reply; 15+ messages in thread
From: Fred Fan @ 2009-12-14 2:28 UTC (permalink / raw)
To: u-boot
HI Stefano Babic,
Sorry, I just see your and wolfgang's mail. In this days, I am prepare
new soc's kernel MSL code.
When I just finished my coding, I have same issue too. But during I identify
this issue, the issue is
disappeared.
I does not change lowlevel_init.s. Maybe I removed some definitions of
clock register.
I will check it ASAP.
Best Regard
Fred
2009/12/4 Stefano Babic <sbabic@denx.de>
> Fred Fan wrote:
> > Dear wolfgang,
> > I almost fixed all of your comments.
>
> Hi Fred,
>
> I have already tested your patch on the babbage2 board and I would ask
> you about the status. The boot loader does not start (I have tried
> flashing the SPI NOR, and this seems ok. The code seems loaded from the
> flash) but the board hangs. With the debugger seems that it hangs in the
> init_clock assemby routine in lowlevel_init.S.
>
> Have you seen the same behavior or do you think it depens on my
> environment ?
>
> Regards,
> Stefano
>
> --
> =====================================================================
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
> =====================================================================
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board
2009-12-14 2:28 ` Fred Fan
@ 2009-12-29 22:41 ` stefano babic
0 siblings, 0 replies; 15+ messages in thread
From: stefano babic @ 2009-12-29 22:41 UTC (permalink / raw)
To: u-boot
Fred Fan wrote:
> HI Stefano Babic,
> Sorry, I just see your and wolfgang's mail. In this days, I am
> prepare new soc's kernel MSL code.
> When I just finished my coding, I have same issue too. But during I
> identify this issue, the issue is
> disappeared.
> I does not change lowlevel_init.s. Maybe I removed some definitions
> of clock register.
> I will check it ASAP.
Hi Fred,
do not worry, I could find where the problem is located. I started from
the IMX51 BSP, changing code to adapt for the u-boot top of tree, and
then I applied all changes you sent in your patchset. So I could check
step by step where I had to look.
I do not find any issue in the cpu/mx51/clock.c and in the clock
definitions, that you rearranged after the first review, so in this file
everything seems ok ;)
Definitely I checked with the debugger that the problem arises in the
first initialization of the clock registers in lowlevel_init.S (after
the init_clock label).
I replaced the file with the one I found in the BSP and the board runs
now flawlessly.
I have already removed the flashHeader.S, adding a new image format to
support the i.MX51 processor and its DCD table.
I have opened another issue, too. I have seen that the name "babbage" is
quite disappeared and on the Freescale's website this board is named now
"mx51evk". I know you have already changed the name of the board, but I
think the name "babbage" can confuse. Better should be to rename the
board with the name we find in the official documentation. I know you
already did this job, I can only volunteer myself to do that...
What do you think if I take over the job and I will resend all patches
to the ML ? In this way I can easier integrate my changes, if you agree.
Should be ok for you ?
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2009-12-29 22:41 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-09-20 17:28 [U-Boot] [PATCH] imx51:Add support basic boot code of freescale imx51 bbg board gareatech at gmail.com
2009-09-21 17:55 ` Magnus Lilja
2009-09-21 20:58 ` Fabio Estevam
[not found] ` <2f495dc80909221219n2f6f303dw478871aede988a7a@mail.gmail.com>
2009-09-22 19:52 ` Magnus Lilja
2009-09-22 20:28 ` Fred Fan
2009-09-22 20:04 ` Magnus Lilja
2009-09-22 20:29 ` Fred Fan
-- strict thread matches above, loose matches on Subject: below --
2009-09-23 14:47 Fred Fan
2009-09-23 21:47 ` Wolfgang Denk
2009-12-01 16:44 ` Fred Fan
2009-12-01 21:15 ` Wolfgang Denk
2009-12-04 11:16 ` Stefano Babic
2009-12-14 2:28 ` Fred Fan
2009-12-29 22:41 ` stefano babic
2009-09-24 4:35 ` Prafulla Wadaskar
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