* [U-Boot] [PATCH 0/5 v2] ARM:OMAP3:SDP3430 initial support
@ 2009-10-07 2:17 Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init Nishanth Menon
0 siblings, 1 reply; 19+ messages in thread
From: Nishanth Menon @ 2009-10-07 2:17 UTC (permalink / raw)
To: u-boot
This series of patch provides minimal support for
OMAP3430 based SDP3430 platform
Ref: http://focus.ti.com/general/docs/wtbu/wtbugencontent.tsp?templateId=6123&navigationId=12013&contentId=28741
Rev 1 of this patch series was discussed in:
http://www.nabble.com/forum/Permalink.jtp?root=25518020&post=25518020&page=y
1 patch was removed from the series and 2 patches were reworked
but the entire series is being send out after being rebased to:
http://git.denx.de/?p=u-boot/u-boot-ti.git;a=summary
This is to ensure continuity of discussion.
David Brownell (1):
ARM:OMAP3:SDP3430: initial support (v2)
Nishanth Menon (4):
OMAP3: Fix SDRC init (v2)
OMAP3: export enable_gpmc_cs_config to board files
OMAP3: make gpmc_config as const
OMAP3: fix warnings when NAND/ONENAND is not used
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 3 +
board/ti/sdp3430/Makefile | 49 ++++
board/ti/sdp3430/config.mk | 33 +++
board/ti/sdp3430/sdp.c | 204 ++++++++++++++++
board/ti/sdp3430/sdp.h | 417 ++++++++++++++++++++++++++++++++
cpu/arm_cortexa8/omap3/mem.c | 15 +-
include/asm-arm/arch-omap3/cpu.h | 1 +
include/asm-arm/arch-omap3/mem.h | 8 +-
include/asm-arm/arch-omap3/sys_proto.h | 2 +
include/configs/omap3_sdp3430.h | 366 ++++++++++++++++++++++++++++
12 files changed, 1091 insertions(+), 9 deletions(-)
create mode 100644 board/ti/sdp3430/Makefile
create mode 100644 board/ti/sdp3430/config.mk
create mode 100644 board/ti/sdp3430/sdp.c
create mode 100644 board/ti/sdp3430/sdp.h
create mode 100644 include/configs/omap3_sdp3430.h
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init
2009-10-07 2:17 [U-Boot] [PATCH 0/5 v2] ARM:OMAP3:SDP3430 initial support Nishanth Menon
@ 2009-10-07 2:17 ` Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 2/5] OMAP3: export enable_gpmc_cs_config to board files Nishanth Menon
` (2 more replies)
0 siblings, 3 replies; 19+ messages in thread
From: Nishanth Menon @ 2009-10-07 2:17 UTC (permalink / raw)
To: u-boot
Defaults are for Infineon DDR timings.
Since none of the supported boards currently do
XIP boot, these seem to be faulty. fix the values
as per the calculations(ACTIMA,B), conf
the sdrc power with pwdnen and wakeupproc bits
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: David B <david-b@pacbell.net>
Cc: Vikram Pandita <vikram.pandita@ti.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rix <tom.rix@windriver.com>
Cc: Dirk Behme <dirk.behme@googlemail.com>
---
cpu/arm_cortexa8/omap3/mem.c | 3 ++-
include/asm-arm/arch-omap3/cpu.h | 1 +
include/asm-arm/arch-omap3/mem.h | 8 ++++----
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 079c848..8731c9d 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -164,7 +164,8 @@ void do_sdrc_init(u32 cs, u32 early)
writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
/* Disable Power Down of CKE cuz of 1 CKE on combo part */
- writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
+ writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
+ &sdrc_base->power);
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);
diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
index 8ab2e39..e51c4f3 100644
--- a/include/asm-arm/arch-omap3/cpu.h
+++ b/include/asm-arm/arch-omap3/cpu.h
@@ -222,6 +222,7 @@ struct sdrc {
#define PAGEPOLICY_HIGH (0x1 << 0)
#define SRFRONRESET (0x1 << 7)
+#define PWDNEN (0x1 << 2)
#define WAKEUPPROC (0x1 << 26)
#define DDR_SDRAM (0x1 << 0)
diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
index 5b9ac75..31cbdef 100644
--- a/include/asm-arm/arch-omap3/mem.h
+++ b/include/asm-arm/arch-omap3/mem.h
@@ -78,16 +78,16 @@ enum {
#define TRP_165 3
#define TRAS_165 7
#define TRC_165 10
-#define TRFC_165 21
+#define TRFC_165 12
#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \
(TRAS_165 << 18) | (TRP_165 << 15) | \
(TRCD_165 << 12) | (TRRD_165 << 9) | \
(TDPL_165 << 6) | (TDAL_165))
#define TWTR_165 1
-#define TCKE_165 1
-#define TXP_165 5
-#define XSR_165 23
+#define TCKE_165 2
+#define TXP_165 2
+#define XSR_165 20
#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
(TXP_165 << 8) | (TWTR_165 << 16))
--
1.6.0.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 2/5] OMAP3: export enable_gpmc_cs_config to board files
2009-10-07 2:17 ` [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init Nishanth Menon
@ 2009-10-07 2:17 ` Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const Nishanth Menon
2009-10-10 19:18 ` [U-Boot] [PATCH 2/5] OMAP3: export enable_gpmc_cs_config to board files Paulraj, Sandeep
2009-10-10 19:24 ` [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init Paulraj, Sandeep
2009-10-19 14:53 ` Steve Sakoman
2 siblings, 2 replies; 19+ messages in thread
From: Nishanth Menon @ 2009-10-07 2:17 UTC (permalink / raw)
To: u-boot
Export enable_gpmc_cs_config into common header to
prevent warning:
warning: implicit declaration of function 'enable_gpmc_cs_config'
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: David B <david-b@pacbell.net>
Cc: Vikram Pandita <vikram.pandita@ti.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rix <tom.rix@windriver.com>
Cc: Dirk Behme <dirk.behme@googlemail.com>
---
include/asm-arm/arch-omap3/sys_proto.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h
index 2246f80..e59021e 100644
--- a/include/asm-arm/arch-omap3/sys_proto.h
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -34,6 +34,8 @@ void memif_init(void);
void sdrc_init(void);
void do_sdrc_init(u32, u32);
void gpmc_init(void);
+void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+ u32 size);
void watchdog_init(void);
void set_muxconf_regs(void);
--
1.6.0.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const
2009-10-07 2:17 ` [U-Boot] [PATCH 2/5] OMAP3: export enable_gpmc_cs_config to board files Nishanth Menon
@ 2009-10-07 2:17 ` Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 4/5] OMAP3: fix warnings when NAND/ONENAND is not used Nishanth Menon
` (2 more replies)
2009-10-10 19:18 ` [U-Boot] [PATCH 2/5] OMAP3: export enable_gpmc_cs_config to board files Paulraj, Sandeep
1 sibling, 3 replies; 19+ messages in thread
From: Nishanth Menon @ 2009-10-07 2:17 UTC (permalink / raw)
To: u-boot
gpmc_config should not be a variant as it is board specific
hence make it a const parameter
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: David B <david-b@pacbell.net>
Cc: Vikram Pandita <vikram.pandita@ti.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rix <tom.rix@windriver.com>
Cc: Dirk Behme <dirk.behme@googlemail.com>
---
cpu/arm_cortexa8/omap3/mem.c | 6 +++---
include/asm-arm/arch-omap3/sys_proto.h | 2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 8731c9d..8d64478 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -44,7 +44,7 @@ volatile unsigned int boot_flash_env_addr;
struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND)
-static u32 gpmc_m_nand[GPMC_MAX_REG] = {
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG3,
@@ -62,7 +62,7 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
#endif
#if defined(CONFIG_CMD_ONENAND)
-static u32 gpmc_onenand[GPMC_MAX_REG] = {
+static const u32 gpmc_onenand[GPMC_MAX_REG] = {
ONENAND_GPMC_CONFIG1,
ONENAND_GPMC_CONFIG2,
ONENAND_GPMC_CONFIG3,
@@ -193,7 +193,7 @@ void do_sdrc_init(u32 cs, u32 early)
writel(0, &sdrc_base->cs[cs].mcfg);
}
-void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size)
{
writel(0, &cs->config7);
diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h
index e59021e..34bd515 100644
--- a/include/asm-arm/arch-omap3/sys_proto.h
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -34,7 +34,7 @@ void memif_init(void);
void sdrc_init(void);
void do_sdrc_init(u32, u32);
void gpmc_init(void);
-void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size);
void watchdog_init(void);
--
1.6.0.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 4/5] OMAP3: fix warnings when NAND/ONENAND is not used
2009-10-07 2:17 ` [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const Nishanth Menon
@ 2009-10-07 2:17 ` Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 5/5 v2] ARM:OMAP3:SDP3430: initial support Nishanth Menon
2009-10-10 19:20 ` [U-Boot] [PATCH 4/5] OMAP3: fix warnings when NAND/ONENAND is not used Paulraj, Sandeep
2009-10-10 19:29 ` [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const Paulraj, Sandeep
2009-10-11 7:54 ` Dirk Behme
2 siblings, 2 replies; 19+ messages in thread
From: Nishanth Menon @ 2009-10-07 2:17 UTC (permalink / raw)
To: u-boot
Fix build warnings by putting specific used variables
under required #ifdefs for removing:
mem.c:227: warning: unused variable 'f_sec'
mem.c:226: warning: unused variable 'f_off'
mem.c:225: warning: unused variable 'size'
mem.c:224: warning: unused variable 'base'
mem.c:222: warning: unused variable 'gpmc_config'
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: David B <david-b@pacbell.net>
Cc: Vikram Pandita <vikram.pandita@ti.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rix <tom.rix@windriver.com>
Cc: Dirk Behme <dirk.behme@googlemail.com>
---
cpu/arm_cortexa8/omap3/mem.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 8d64478..e93343c 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -219,12 +219,16 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
void gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
- u32 *gpmc_config = NULL;
gpmc_cfg = (struct gpmc *)GPMC_BASE;
+#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
+ u32 *gpmc_config = NULL;
u32 base = 0;
u32 size = 0;
+#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_ONENAND)
u32 f_off = CONFIG_SYS_MONITOR_LEN;
u32 f_sec = 0;
+#endif
+#endif
u32 config = 0;
/* global settings */
--
1.6.0.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 5/5 v2] ARM:OMAP3:SDP3430: initial support
2009-10-07 2:17 ` [U-Boot] [PATCH 4/5] OMAP3: fix warnings when NAND/ONENAND is not used Nishanth Menon
@ 2009-10-07 2:17 ` Nishanth Menon
2009-10-10 19:20 ` [U-Boot] [PATCH 4/5] OMAP3: fix warnings when NAND/ONENAND is not used Paulraj, Sandeep
1 sibling, 0 replies; 19+ messages in thread
From: Nishanth Menon @ 2009-10-07 2:17 UTC (permalink / raw)
To: u-boot
From: David Brownell <david-b@pacbell.net>
Start of support of
Texas Instruments Software Development Platform(SDP)
for OMAP3430 - SDP3430
Highlights of this platform are:
Flash Memory devices:
Sibley NOR, Micron 8bit NAND and OneNAND
Connectivity:
3 UARTs and expanded 4 UART ports + IrDA
Ethernet, USB
Other peripherals:
TWL5030 PMIC+Audio+Keypad
VGA display
Expansion ports:
Memory devices plugin boards (PISMO)
Connectivity board for GPS,WLAN etc..
Completely configurable boot sequence and device mapping
etc..
For more details, please refer:
http://focus.ti.com/general/docs/wtbu/wtbugencontent.tsp?templateId=6123&navigationId=12013&contentId=28741
U-boot support introduced for:
Support default jumpering and:
- UART1/ttyS0 console(legacy sdp3430 u-boot)
- UART3/ttyS2 console (matching other boards,
and SDP HW docs)
- Ethernet
- mmc0
- NOR boot
TODO:
- mmc1
- NAND (boot or 128M storage)
- OneNAND (boot or 256M storage)
- Fix NOR env variable load
- Review SDRC timing configuration/DPLL
configuration
- Dynamically read FPGA dip switch settings and
map NOR/NAND/ONENAND devices to right
chipselects
Currently the UART1 is enabled by default. for
compatibility with other OMAP3 u-boot platforms,
enable the #define of CONSOLE_J9.
Signed-off-by: David Brownell <david-b@pacbell.net>
Signed-off-by: Nishanth Menon <nm@ti.com>
Cc: Vikram Pandita <vikram.pandita@ti.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Tom Rix <tom.rix@windriver.com>
Cc: Dirk Behme <dirk.behme@googlemail.com>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 3 +
board/ti/sdp3430/Makefile | 49 +++++
board/ti/sdp3430/config.mk | 33 +++
board/ti/sdp3430/sdp.c | 204 +++++++++++++++++++
board/ti/sdp3430/sdp.h | 417 +++++++++++++++++++++++++++++++++++++++
include/configs/omap3_sdp3430.h | 366 ++++++++++++++++++++++++++++++++++
8 files changed, 1074 insertions(+), 0 deletions(-)
create mode 100644 board/ti/sdp3430/Makefile
create mode 100644 board/ti/sdp3430/config.mk
create mode 100644 board/ti/sdp3430/sdp.c
create mode 100644 board/ti/sdp3430/sdp.h
create mode 100644 include/configs/omap3_sdp3430.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2297651..5742782 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -628,6 +628,7 @@ Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Nishanth Menon <nm@ti.com>
+ omap3_sdp3430 ARM CORTEX-A8 (OMAP3xx SoC)
omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC)
David M?ller <d.mueller@elsoft.ch>
diff --git a/MAKEALL b/MAKEALL
index 38cd076..9bf75e8 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -603,6 +603,7 @@ LIST_ARM_CORTEX_A8=" \
omap3_overo \
omap3_evm \
omap3_pandora \
+ omap3_sdp3430 \
omap3_zoom1 \
omap3_zoom2 \
"
diff --git a/Makefile b/Makefile
index 9637643..8dbe552 100644
--- a/Makefile
+++ b/Makefile
@@ -3144,6 +3144,9 @@ omap3_zoom1_config : unconfig
omap3_zoom2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
+omap3_sdp3430_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3
+
#########################################################################
## XScale Systems
#########################################################################
diff --git a/board/ti/sdp3430/Makefile b/board/ti/sdp3430/Makefile
new file mode 100644
index 0000000..2554c7b
--- /dev/null
+++ b/board/ti/sdp3430/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := sdp.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/sdp3430/config.mk b/board/ti/sdp3430/config.mk
new file mode 100644
index 0000000..3726634
--- /dev/null
+++ b/board/ti/sdp3430/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006-2009
+# Texas Instruments, <www.ti.com>
+#
+# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c
new file mode 100644
index 0000000..425fdfc
--- /dev/null
+++ b/board/ti/sdp3430/sdp.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2004-2009
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "sdp.h"
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 SDP3430 board",
+#if defined(CONFIG_ENV_IS_IN_ONENAND)
+ "OneNAND",
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+ "NAND",
+#else
+ "NOR",
+#endif
+};
+
+/* Timing definitions for GPMC controller for Sibley NOR */
+static const u32 gpmc_sdp_nor[] = {
+ SDP3430_NOR_GPMC_CONF1,
+ SDP3430_NOR_GPMC_CONF2,
+ SDP3430_NOR_GPMC_CONF3,
+ SDP3430_NOR_GPMC_CONF4,
+ SDP3430_NOR_GPMC_CONF5,
+ SDP3430_NOR_GPMC_CONF6,
+ /*CONF7- computed as params */
+};
+
+/*
+ * Timing definitions for GPMC controller for Debug Board
+ * Debug board contains access to ethernet and DIP Switch setting
+ * information etc.
+ */
+static const u32 gpmc_sdp_debug[] = {
+ SDP3430_DEBUG_GPMC_CONF1,
+ SDP3430_DEBUG_GPMC_CONF2,
+ SDP3430_DEBUG_GPMC_CONF3,
+ SDP3430_DEBUG_GPMC_CONF4,
+ SDP3430_DEBUG_GPMC_CONF5,
+ SDP3430_DEBUG_GPMC_CONF6,
+ /*CONF7- computed as params */
+};
+
+/* Timing defintions for GPMC OneNAND */
+static const u32 gpmc_sdp_onenand[] = {
+ SDP3430_ONENAND_GPMC_CONF1,
+ SDP3430_ONENAND_GPMC_CONF2,
+ SDP3430_ONENAND_GPMC_CONF3,
+ SDP3430_ONENAND_GPMC_CONF4,
+ SDP3430_ONENAND_GPMC_CONF5,
+ SDP3430_ONENAND_GPMC_CONF6,
+ /*CONF7- computed as params */
+};
+
+/* GPMC definitions for GPMC NAND */
+static const u32 gpmc_sdp_nand[] = {
+ SDP3430_NAND_GPMC_CONF1,
+ SDP3430_NAND_GPMC_CONF2,
+ SDP3430_NAND_GPMC_CONF3,
+ SDP3430_NAND_GPMC_CONF4,
+ SDP3430_NAND_GPMC_CONF5,
+ SDP3430_NAND_GPMC_CONF6,
+ /*CONF7- computed as params */
+};
+
+/* gpmc_cfg is initialized by gpmc_init and we use it here */
+extern struct gpmc *gpmc_cfg;
+
+/**
+ * @brief board_init - gpmc and basic setup as phase1 of boot sequence
+ *
+ * @return 0
+ */
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* TODO: Dynamically pop out CS mapping and program accordingly */
+ /* Configure devices for default ON ON ON settings */
+ enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
+ CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
+ enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
+ GPMC_SIZE_16M);
+ enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
+ GPMC_SIZE_16M);
+ enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
+ GPMC_SIZE_16M);
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+#define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c)
+#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b)
+
+/**
+ * @brief ether_init Take the Ethernet controller out of reset and wait
+ * for the EEPROM load to complete.
+ */
+static void ether_init(void)
+{
+#ifdef CONFIG_DRIVER_LAN91C96
+ int cnt = 20;
+
+ writew(0x0, LAN_RESET_REGISTER);
+ do {
+ writew(0x1, LAN_RESET_REGISTER);
+ udelay(100);
+ if (cnt == 0)
+ goto reset_err_out;
+ --cnt;
+ } while (readw(LAN_RESET_REGISTER) != 0x1);
+
+ cnt = 20;
+
+ do {
+ writew(0x0, LAN_RESET_REGISTER);
+ udelay(100);
+ if (cnt == 0)
+ goto reset_err_out;
+ --cnt;
+ } while (readw(LAN_RESET_REGISTER) != 0x0000);
+ udelay(1000);
+
+ writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
+ udelay(1000);
+reset_err_out:
+ return;
+
+#endif
+}
+
+/**
+ * @brief misc_init_r - Configure SDP board specific configurations
+ * such as power configurations, ethernet initialization as phase2 of
+ * boot sequence
+ *
+ * @return 0
+ */
+int misc_init_r(void)
+{
+ /* Partial setup:
+ * VAUX3 - 2.8V for DVI
+ * VPLL1 - 1.8V
+ * VDAC - 1.8V
+ * and turns on LEDA/LEDB (not needed ... NOP?)
+ */
+ twl4030_power_init();
+
+ /* FIXME finish setup:
+ * VAUX1 - 2.8V for mainboard I/O
+ * VAUX2 - 2.8V for camera
+ * VAUX4 - 1.8V for OMAP3 CSI
+ * VMMC1 - 3.15V (init, variable) for MMC1
+ * VMMC2 - 1.85V for MMC2
+ * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM
+ * VPLL2 - 1.8V
+ */
+ ether_init();
+
+ return 0;
+}
+
+/**
+ * @brief set_muxconf_regs Setting up the configuration Mux registers
+ * specific to the hardware. Many pins need to be moved from protect
+ * to primary mode.
+ */
+void set_muxconf_regs(void)
+{
+ /* platform specific muxes */
+ MUX_SDP3430();
+}
diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h
new file mode 100644
index 0000000..e2f604c
--- /dev/null
+++ b/board/ti/sdp3430/sdp.h
@@ -0,0 +1,417 @@
+/*
+ * (C) Copyright 2004-2006
+ * Texas Instruments
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _BOARD_SDP_H_
+#define _BOARD_SDP_H_
+
+#define OFF_IN_PD 0
+#define OFF_OUT_PD 0
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_SDP3430()\
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\
+ MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\
+ MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\
+ MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\
+ MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\
+ MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\
+ MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\
+ MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\
+ MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\
+ MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ /*Audio InterfACe */\
+ MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ /*Expansion Card */\
+ MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ /*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\
+ MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\
+ MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\
+ MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\
+ MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\
+ MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\
+ MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\
+ MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ /* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\
+ MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\
+ MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\
+ MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\
+ MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\
+ MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\
+ MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\
+ MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\
+ MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
+ MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\
+ MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ /*Die to Die */\
+ MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
+ MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\
+ MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/
+
+/*
+ * GPMC Timing definitions for SDP3430
+ * at L3 = 166Mhz
+ */
+
+/* Timing definitions for GPMC controller for Sibley NOR */
+#define SDP3430_NOR_GPMC_CONF1 0x00001200
+#define SDP3430_NOR_GPMC_CONF2 0x001F1F00
+#define SDP3430_NOR_GPMC_CONF3 0x00080802
+#define SDP3430_NOR_GPMC_CONF4 0x1C091C09
+#define SDP3430_NOR_GPMC_CONF5 0x01131F1F
+#define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2
+
+/*
+ * Timing definitions for GPMC controller for Debug Board
+ * Debug board contains access to ethernet and DIP Switch setting
+ * information etc.
+ */
+#define SDP3430_DEBUG_GPMC_CONF1 0x00611200
+#define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01
+#define SDP3430_DEBUG_GPMC_CONF3 0x00080803
+#define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09
+#define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F
+#define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4
+
+/* Timing defintions for GPMC OneNAND */
+#define SDP3430_ONENAND_GPMC_CONF1 0x00001200
+#define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01
+#define SDP3430_ONENAND_GPMC_CONF3 0x00030301
+#define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04
+#define SDP3430_ONENAND_GPMC_CONF5 0x010F1010
+#define SDP3430_ONENAND_GPMC_CONF6 0x1F060000
+
+/* GPMC definitions for GPMC NAND */
+#define SDP3430_NAND_GPMC_CONF1 0x00000800
+#define SDP3430_NAND_GPMC_CONF2 0x00141400
+#define SDP3430_NAND_GPMC_CONF3 0x00141400
+#define SDP3430_NAND_GPMC_CONF4 0x0F010F01
+#define SDP3430_NAND_GPMC_CONF5 0x010C1414
+#define SDP3430_NAND_GPMC_CONF6 0x1F040A80
+
+#endif /* _BOARD_SDP_H_ */
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
new file mode 100644
index 0000000..9e176b5
--- /dev/null
+++ b/include/configs/omap3_sdp3430.h
@@ -0,0 +1,366 @@
+/*
+ * (C) Copyright 2006-2009
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ * Nishanth Menon <nm@ti.com>
+ *
+ * Configuration settings for the 3430 TI SDP3430 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * NOTE: these #defines presume standard SDP jumper settings.
+ * In particular:
+ * - 26 MHz clock (not 19.2 or 38.4 MHz)
+ * - Boot from 128MB NOR, not NAND or OneNAND
+ *
+ * At this writing, OMAP3 U-Boot support doesn't permit concurrent
+ * support for all the flash types the board supports.
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+
+/*
+ * Size of malloc() pool
+ * Total Size Environment - 128K
+ * Malloc - add 128K
+ */
+#define CONFIG_ENV_SIZE 0x00040000
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x00040000)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
+ /* initial data */
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/*
+ * serial port - NS16550 compatible
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be
+ * swapped with UART2 via jumpering. Downsides of using J8: it doesn't
+ * support UART boot (that's only for UART3); it prevents sharing a Linux
+ * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards.
+ *
+ * UART boot uses UART3 on J9, and the SDP user's guide says to use
+ * that for console. Downsides of using J9: you can't use IRDA too;
+ * since UART3 isn't in the CORE power domain, it may be a bit less
+ * usable in certain PM-sensitive debug scenarios.
+ */
+#undef CONSOLE_J9 /* else J8/UART1 (innermost) */
+
+#ifdef CONSOLE_J9
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 */
+#else
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
+#define CONFIG_SERIAL1 1 /* UART1 */
+#endif
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+/*
+ * I2C for power management setup
+ */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_BUS 0
+#define CONFIG_SYS_I2C_BUS_SELECT 1
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+
+/* OMITTED: single 1 Gbit MT29F1G NAND flash */
+
+/*
+ * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash
+ */
+#define CONFIG_SYS_FLASH_BASE 0x10000000
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
+#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */
+#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
+
+#define CONFIG_SYS_FLASH_CFI_WIDTH 2
+#define PHYS_FLASH_SIZE 0x08000000 /* 128Meg */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */
+
+/* timeout values are in milliseconds */
+#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+
+/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_SYS_ENV_SECT_SIZE 0x00040000 /* 256k */
+#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE)
+/*--------------------------------------------------------------------------*/
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+/* Enabled commands */
+#define CONFIG_CMD_DHCP /* DHCP Support */
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NET
+
+/* Disabled commands */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+/*--------------------------------------------------------------------------*/
+/*
+ * MMC boot support
+ */
+
+#if defined(CONFIG_CMD_MMC)
+#define CONFIG_MMC 1
+#define CONFIG_OMAP3_MMC 1
+#define CONFIG_DOS_PARTITION 1
+#endif
+
+/*----------------------------------------------------------------------------
+ * SMSC9115 Ethernet from SMSC9118 family
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_DRIVER_LAN91C96
+#define CONFIG_LAN91C96_BASE DEBUG_BASE
+#define CONFIG_LAN91C96_EXT_PHY
+
+#define CONFIG_BOOTP_SEND_HOSTNAME
+/*
+ * BOOTP fields
+ */
+#define CONFIG_BOOTP_SUBNETMASK 0x00000001
+#define CONFIG_BOOTP_GATEWAY 0x00000002
+#define CONFIG_BOOTP_HOSTNAME 0x00000004
+#define CONFIG_BOOTP_BOOTPATH 0x00000010
+#endif /* (CONFIG_CMD_NET) */
+
+/*
+ * Environment setup
+ *
+ * Default boot order: mmc bootscript, MMC uImage, NOR image.
+ * Network booting environment must be configured at site.
+ */
+
+/* allow overwriting serial config and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "console=ttyS0,115200n8\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "root=/dev/mmcblk0p2 rw " \
+ "rootfstype=ext3 rootwait\0" \
+ "norargs=setenv bootargs console=${console} " \
+ "root=/dev/mtdblock3 rw " \
+ "rootfstype=jffs2\0" \
+ "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from MMC/SD ...; " \
+ "autoscr ${loadaddr}\0" \
+ "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from MMC/SD ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "norboot=echo Booting from NOR ...; " \
+ "run norargs; " \
+ "bootm 0x80000\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "if mmcinit; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run norboot; " \
+ "fi; " \
+ "fi; " \
+ "else run norboot; fi"
+
+#define CONFIG_AUTO_COMPLETE 1
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT "OMAP34XX SDP # "
+
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT V_PROMPT
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg -
+ * a basic sanity check ONLY
+ * IF you would like to increase coverage, increase the end address
+ * or run the test with custom options
+ */
+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000)
+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x02000000)
+
+/* Default load address */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE 0x00020000 /* 128K - regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ 0x00001000 /* 4K - IRQ stack */
+#define CONFIG_STACKSIZE_FIQ 0x00001000 /* 4K - FIQ stack */
+#endif
+
+/*
+ * SDRAM Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* at least 32 meg */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+/*--------------------------------------------------------------------------*/
+
+/*
+ * NOR FLASH usage ... default nCS0:
+ * - one 256KB sector for U-Boot
+ * - one 256KB sector for its parameters (not all used)
+ * - eight sectors (2 MB) for kernel
+ * - rest for JFFS2
+ */
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256K */
+
+#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+
+/*
+ * NAND FLASH usage ... default nCS1:
+ * - four 128KB sectors for X-Loader
+ * - four 128KB sectors for U-Boot
+ * - two 128KB sector for its parameters
+ * - 32 sectors (4 MB) for kernel
+ * - rest for filesystem
+ */
+
+/*
+ * OneNAND FLASH usage ... default nCS2:
+ * - four 128KB sectors for X-Loader
+ * - two 128KB sectors for U-Boot
+ * - one 128KB sector for its parameters
+ * - sixteen sectors (2 MB) for kernel
+ * - rest for filesystem
+ */
+
+/*--------------------------------------------------------------------------*/
+
+#ifndef __ASSEMBLY__
+extern struct gpmc *gpmc_cfg;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */
--
1.6.0.4
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 2/5] OMAP3: export enable_gpmc_cs_config to board files
2009-10-07 2:17 ` [U-Boot] [PATCH 2/5] OMAP3: export enable_gpmc_cs_config to board files Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const Nishanth Menon
@ 2009-10-10 19:18 ` Paulraj, Sandeep
1 sibling, 0 replies; 19+ messages in thread
From: Paulraj, Sandeep @ 2009-10-10 19:18 UTC (permalink / raw)
To: u-boot
>
> Export enable_gpmc_cs_config into common header to
> prevent warning:
> warning: implicit declaration of function 'enable_gpmc_cs_config'
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Cc: David B <david-b@pacbell.net>
> Cc: Vikram Pandita <vikram.pandita@ti.com>
> Cc: Richard Woodruff <r-woodruff2@ti.com>
> Cc: Sandeep Paulraj <s-paulraj@ti.com>
> Cc: Tom Rix <tom.rix@windriver.com>
> Cc: Dirk Behme <dirk.behme@googlemail.com>
> ---
> include/asm-arm/arch-omap3/sys_proto.h | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
Pushed to u-boot-ti next
http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commitdiff;h=79d072ada0eb7ecfbe49cfc2b0c249a7d705f086
Sandeep
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 4/5] OMAP3: fix warnings when NAND/ONENAND is not used
2009-10-07 2:17 ` [U-Boot] [PATCH 4/5] OMAP3: fix warnings when NAND/ONENAND is not used Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 5/5 v2] ARM:OMAP3:SDP3430: initial support Nishanth Menon
@ 2009-10-10 19:20 ` Paulraj, Sandeep
1 sibling, 0 replies; 19+ messages in thread
From: Paulraj, Sandeep @ 2009-10-10 19:20 UTC (permalink / raw)
To: u-boot
>
> Fix build warnings by putting specific used variables
> under required #ifdefs for removing:
> mem.c:227: warning: unused variable 'f_sec'
> mem.c:226: warning: unused variable 'f_off'
> mem.c:225: warning: unused variable 'size'
> mem.c:224: warning: unused variable 'base'
> mem.c:222: warning: unused variable 'gpmc_config'
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Cc: David B <david-b@pacbell.net>
> Cc: Vikram Pandita <vikram.pandita@ti.com>
> Cc: Richard Woodruff <r-woodruff2@ti.com>
> Cc: Sandeep Paulraj <s-paulraj@ti.com>
> Cc: Tom Rix <tom.rix@windriver.com>
> Cc: Dirk Behme <dirk.behme@googlemail.com>
> ---
> cpu/arm_cortexa8/omap3/mem.c | 6 +++++-
> 1 files changed, 5 insertions(+), 1 deletions(-)
Pushed to u-boot-ti next
http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commitdiff;h=9a6856e54708598902eba30bb030b917778bbb8b
Thanks,
Sandeep
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init
2009-10-07 2:17 ` [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 2/5] OMAP3: export enable_gpmc_cs_config to board files Nishanth Menon
@ 2009-10-10 19:24 ` Paulraj, Sandeep
2009-10-19 14:53 ` Steve Sakoman
2 siblings, 0 replies; 19+ messages in thread
From: Paulraj, Sandeep @ 2009-10-10 19:24 UTC (permalink / raw)
To: u-boot
>
> Defaults are for Infineon DDR timings.
> Since none of the supported boards currently do
> XIP boot, these seem to be faulty. fix the values
> as per the calculations(ACTIMA,B), conf
> the sdrc power with pwdnen and wakeupproc bits
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Cc: David B <david-b@pacbell.net>
> Cc: Vikram Pandita <vikram.pandita@ti.com>
> Cc: Richard Woodruff <r-woodruff2@ti.com>
> Cc: Sandeep Paulraj <s-paulraj@ti.com>
> Cc: Tom Rix <tom.rix@windriver.com>
> Cc: Dirk Behme <dirk.behme@googlemail.com>
> ---
> cpu/arm_cortexa8/omap3/mem.c | 3 ++-
> include/asm-arm/arch-omap3/cpu.h | 1 +
> include/asm-arm/arch-omap3/mem.h | 8 ++++----
> 3 files changed, 7 insertions(+), 5 deletions(-)
>
Pushed to u-boot-ti next
http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commitdiff;h=f714f3a12c09260c500e0f7c5ff40f15d66ab579
Thanks,
Sandeep
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const
2009-10-07 2:17 ` [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 4/5] OMAP3: fix warnings when NAND/ONENAND is not used Nishanth Menon
@ 2009-10-10 19:29 ` Paulraj, Sandeep
2009-10-11 7:54 ` Dirk Behme
2 siblings, 0 replies; 19+ messages in thread
From: Paulraj, Sandeep @ 2009-10-10 19:29 UTC (permalink / raw)
To: u-boot
>
> gpmc_config should not be a variant as it is board specific
> hence make it a const parameter
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Cc: David B <david-b@pacbell.net>
> Cc: Vikram Pandita <vikram.pandita@ti.com>
> Cc: Richard Woodruff <r-woodruff2@ti.com>
> Cc: Sandeep Paulraj <s-paulraj@ti.com>
> Cc: Tom Rix <tom.rix@windriver.com>
> Cc: Dirk Behme <dirk.behme@googlemail.com>
> ---
> cpu/arm_cortexa8/omap3/mem.c | 6 +++---
> include/asm-arm/arch-omap3/sys_proto.h | 2 +-
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
Pushed to u-boot-ti next
http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commitdiff;h=c27339b41e49cd89c2ea802a490b175ac7ad89ff
Thanks,
Sandeep
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const
2009-10-07 2:17 ` [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 4/5] OMAP3: fix warnings when NAND/ONENAND is not used Nishanth Menon
2009-10-10 19:29 ` [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const Paulraj, Sandeep
@ 2009-10-11 7:54 ` Dirk Behme
2009-10-11 12:22 ` Paulraj, Sandeep
2009-10-11 14:35 ` Nishanth Menon
2 siblings, 2 replies; 19+ messages in thread
From: Dirk Behme @ 2009-10-11 7:54 UTC (permalink / raw)
To: u-boot
Nishanth Menon wrote:
> gpmc_config should not be a variant as it is board specific
> hence make it a const parameter
Having this in u-boot-ti/next results in
- All non-SDP3430 boards have
mem.c: In function 'gpmc_init':
mem.c:250: warning: assignment discards qualifiers from pointer target
type
- Zoom2 fails to build with
zoom2.c:54: error: conflicting types for 'enable_gpmc_cs_config'
/include/asm/arch/sys_proto.h:38: error: previous declaration of
'enable_gpmc_cs_config' was here
Reverting this patch makes both go away.
Then we get
sdp.c: In function 'board_init':
sdp.c:109: warning: passing argument 1 of 'enable_gpmc_cs_config'
discards qualifiers from pointer target type
sdp.c:111: warning: passing argument 1 of 'enable_gpmc_cs_config'
discards qualifiers from pointer target type
sdp.c:113: warning: passing argument 1 of 'enable_gpmc_cs_config'
discards qualifiers from pointer target type
sdp.c:115: warning: passing argument 1 of 'enable_gpmc_cs_config'
discards qualifiers from pointer target type
for SDP3430 only, though.
So I'd like to have this patch reverted in u-boot-ti/next and then
a) Fix sdp.c only
or
b) test the other boards, too, before applying this patch.
Best regards
Dirk
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Cc: David B <david-b@pacbell.net>
> Cc: Vikram Pandita <vikram.pandita@ti.com>
> Cc: Richard Woodruff <r-woodruff2@ti.com>
> Cc: Sandeep Paulraj <s-paulraj@ti.com>
> Cc: Tom Rix <tom.rix@windriver.com>
> Cc: Dirk Behme <dirk.behme@googlemail.com>
> ---
> cpu/arm_cortexa8/omap3/mem.c | 6 +++---
> include/asm-arm/arch-omap3/sys_proto.h | 2 +-
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
> index 8731c9d..8d64478 100644
> --- a/cpu/arm_cortexa8/omap3/mem.c
> +++ b/cpu/arm_cortexa8/omap3/mem.c
> @@ -44,7 +44,7 @@ volatile unsigned int boot_flash_env_addr;
> struct gpmc *gpmc_cfg;
>
> #if defined(CONFIG_CMD_NAND)
> -static u32 gpmc_m_nand[GPMC_MAX_REG] = {
> +static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
> M_NAND_GPMC_CONFIG1,
> M_NAND_GPMC_CONFIG2,
> M_NAND_GPMC_CONFIG3,
> @@ -62,7 +62,7 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
> #endif
>
> #if defined(CONFIG_CMD_ONENAND)
> -static u32 gpmc_onenand[GPMC_MAX_REG] = {
> +static const u32 gpmc_onenand[GPMC_MAX_REG] = {
> ONENAND_GPMC_CONFIG1,
> ONENAND_GPMC_CONFIG2,
> ONENAND_GPMC_CONFIG3,
> @@ -193,7 +193,7 @@ void do_sdrc_init(u32 cs, u32 early)
> writel(0, &sdrc_base->cs[cs].mcfg);
> }
>
> -void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
> +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
> u32 size)
> {
> writel(0, &cs->config7);
> diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h
> index e59021e..34bd515 100644
> --- a/include/asm-arm/arch-omap3/sys_proto.h
> +++ b/include/asm-arm/arch-omap3/sys_proto.h
> @@ -34,7 +34,7 @@ void memif_init(void);
> void sdrc_init(void);
> void do_sdrc_init(u32, u32);
> void gpmc_init(void);
> -void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
> +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
> u32 size);
>
> void watchdog_init(void);
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const
2009-10-11 7:54 ` Dirk Behme
@ 2009-10-11 12:22 ` Paulraj, Sandeep
2009-10-11 14:35 ` Nishanth Menon
1 sibling, 0 replies; 19+ messages in thread
From: Paulraj, Sandeep @ 2009-10-11 12:22 UTC (permalink / raw)
To: u-boot
>
> Nishanth Menon wrote:
> > gpmc_config should not be a variant as it is board specific
> > hence make it a const parameter
>
> Having this in u-boot-ti/next results in
>
> - All non-SDP3430 boards have
>
> mem.c: In function 'gpmc_init':
> mem.c:250: warning: assignment discards qualifiers from pointer target
> type
>
> - Zoom2 fails to build with
>
> zoom2.c:54: error: conflicting types for 'enable_gpmc_cs_config'
> /include/asm/arch/sys_proto.h:38: error: previous declaration of
> 'enable_gpmc_cs_config' was here
>
> Reverting this patch makes both go away.
>
> Then we get
>
> sdp.c: In function 'board_init':
> sdp.c:109: warning: passing argument 1 of 'enable_gpmc_cs_config'
> discards qualifiers from pointer target type
> sdp.c:111: warning: passing argument 1 of 'enable_gpmc_cs_config'
> discards qualifiers from pointer target type
> sdp.c:113: warning: passing argument 1 of 'enable_gpmc_cs_config'
> discards qualifiers from pointer target type
> sdp.c:115: warning: passing argument 1 of 'enable_gpmc_cs_config'
> discards qualifiers from pointer target type
>
> for SDP3430 only, though.
>
> So I'd like to have this patch reverted in u-boot-ti/next and then
>
> a) Fix sdp.c only
>
> or
>
> b) test the other boards, too, before applying this patch.
>
> Best regards
>
> Dirk
>
My bad, should have compiled all other boards as well.
I have reverted.
Thanks,
Sandeep
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const
2009-10-11 7:54 ` Dirk Behme
2009-10-11 12:22 ` Paulraj, Sandeep
@ 2009-10-11 14:35 ` Nishanth Menon
2009-10-11 14:48 ` Paulraj, Sandeep
1 sibling, 1 reply; 19+ messages in thread
From: Nishanth Menon @ 2009-10-11 14:35 UTC (permalink / raw)
To: u-boot
Dirk Behme said the following on 10/11/2009 02:54 AM:
> Nishanth Menon wrote:
>
>> gpmc_config should not be a variant as it is board specific
>> hence make it a const parameter
>>
>
> Having this in u-boot-ti/next results in
>
> - All non-SDP3430 boards have
>
> mem.c: In function 'gpmc_init':
> mem.c:250: warning: assignment discards qualifiers from pointer target
> type
>
> - Zoom2 fails to build with
>
> zoom2.c:54: error: conflicting types for 'enable_gpmc_cs_config'
> /include/asm/arch/sys_proto.h:38: error: previous declaration of
> 'enable_gpmc_cs_config' was here
>
> Reverting this patch makes both go away
Redone patch attached - MAKEALL tested ONLY. apologies on the noise.
ethernet still pending..
Regards,
Nishanth Menon
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const
2009-10-11 14:35 ` Nishanth Menon
@ 2009-10-11 14:48 ` Paulraj, Sandeep
2009-10-11 15:01 ` Nishanth Menon
0 siblings, 1 reply; 19+ messages in thread
From: Paulraj, Sandeep @ 2009-10-11 14:48 UTC (permalink / raw)
To: u-boot
>
> Dirk Behme said the following on 10/11/2009 02:54 AM:
> > Nishanth Menon wrote:
> >
> >> gpmc_config should not be a variant as it is board specific
> >> hence make it a const parameter
> >>
> >
> > Having this in u-boot-ti/next results in
> >
> > - All non-SDP3430 boards have
> >
> > mem.c: In function 'gpmc_init':
> > mem.c:250: warning: assignment discards qualifiers from pointer target
> > type
> >
> > - Zoom2 fails to build with
> >
> > zoom2.c:54: error: conflicting types for 'enable_gpmc_cs_config'
> > /include/asm/arch/sys_proto.h:38: error: previous declaration of
> > 'enable_gpmc_cs_config' was here
> >
> > Reverting this patch makes both go away
> Redone patch attached - MAKEALL tested ONLY. apologies on the noise.
Pushed to u-boot-ti next
http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commit;h=78c38ce87f7423eedba844e8594cfc5a4fa6051b
>
> ethernet still pending..
> Regards,
> Nishanth Menon
Thanks,
Sandeep
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const
2009-10-11 14:48 ` Paulraj, Sandeep
@ 2009-10-11 15:01 ` Nishanth Menon
0 siblings, 0 replies; 19+ messages in thread
From: Nishanth Menon @ 2009-10-11 15:01 UTC (permalink / raw)
To: u-boot
Paulraj, Sandeep said the following on 10/11/2009 09:48 AM:
>
>> Dirk Behme said the following on 10/11/2009 02:54 AM:
>>
>>> Nishanth Menon wrote:
>>>
>>>
>>>> gpmc_config should not be a variant as it is board specific
>>>> hence make it a const parameter
>>>>
>>>>
>>> Having this in u-boot-ti/next results in
>>>
>>> - All non-SDP3430 boards have
>>>
>>> mem.c: In function 'gpmc_init':
>>> mem.c:250: warning: assignment discards qualifiers from pointer target
>>> type
>>>
>>> - Zoom2 fails to build with
>>>
>>> zoom2.c:54: error: conflicting types for 'enable_gpmc_cs_config'
>>> /include/asm/arch/sys_proto.h:38: error: previous declaration of
>>> 'enable_gpmc_cs_config' was here
>>>
>>> Reverting this patch makes both go away
>>>
>> Redone patch attached - MAKEALL tested ONLY. apologies on the noise.
>>
>
> Pushed to u-boot-ti next
>
> http://git.denx.de/?p=u-boot/u-boot-ti.git;a=commit;h=78c38ce87f7423eedba844e8594cfc5a4fa6051b
>
>
thanks. i have an ethernet patch.. but i need to reach office later
today to test it..
Regards,
Nishanth Menon
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init
2009-10-07 2:17 ` [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 2/5] OMAP3: export enable_gpmc_cs_config to board files Nishanth Menon
2009-10-10 19:24 ` [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init Paulraj, Sandeep
@ 2009-10-19 14:53 ` Steve Sakoman
2009-10-19 14:55 ` Dirk Behme
2 siblings, 1 reply; 19+ messages in thread
From: Steve Sakoman @ 2009-10-19 14:53 UTC (permalink / raw)
To: u-boot
On Tue, Oct 6, 2009 at 7:17 PM, Nishanth Menon <nm@ti.com> wrote:
> Defaults are for Infineon DDR timings.
> Since none of the supported boards currently do
> XIP boot, these seem to be faulty. fix the values
> as per the calculations(ACTIMA,B), conf
> the sdrc power with pwdnen and wakeupproc bits
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Cc: David B <david-b@pacbell.net>
> Cc: Vikram Pandita <vikram.pandita@ti.com>
> Cc: Richard Woodruff <r-woodruff2@ti.com>
> Cc: Sandeep Paulraj <s-paulraj@ti.com>
> Cc: Tom Rix <tom.rix@windriver.com>
> Cc: Dirk Behme <dirk.behme@googlemail.com>
> ---
> ?cpu/arm_cortexa8/omap3/mem.c ? ? | ? ?3 ++-
> ?include/asm-arm/arch-omap3/cpu.h | ? ?1 +
> ?include/asm-arm/arch-omap3/mem.h | ? ?8 ++++----
> ?3 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
> index 079c848..8731c9d 100644
> --- a/cpu/arm_cortexa8/omap3/mem.c
> +++ b/cpu/arm_cortexa8/omap3/mem.c
> @@ -164,7 +164,8 @@ void do_sdrc_init(u32 cs, u32 early)
> ? ? ? ? ? ? ? ?writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
>
> ? ? ? ? ? ? ? ?/* Disable Power Down of CKE cuz of 1 CKE on combo part */
> - ? ? ? ? ? ? ? writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
> + ? ? ? ? ? ? ? writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &sdrc_base->power);
>
> ? ? ? ? ? ? ? ?writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
> ? ? ? ? ? ? ? ?sdelay(0x20000);
> diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
> index 8ab2e39..e51c4f3 100644
> --- a/include/asm-arm/arch-omap3/cpu.h
> +++ b/include/asm-arm/arch-omap3/cpu.h
> @@ -222,6 +222,7 @@ struct sdrc {
>
> ?#define PAGEPOLICY_HIGH ? ? ? ? ? ? ? ?(0x1 << 0)
> ?#define SRFRONRESET ? ? ? ? ? ?(0x1 << 7)
> +#define PWDNEN ? ? ? ? ? ? ? ? (0x1 << 2)
> ?#define WAKEUPPROC ? ? ? ? ? ? (0x1 << 26)
>
> ?#define DDR_SDRAM ? ? ? ? ? ? ?(0x1 << 0)
> diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
> index 5b9ac75..31cbdef 100644
> --- a/include/asm-arm/arch-omap3/mem.h
> +++ b/include/asm-arm/arch-omap3/mem.h
> @@ -78,16 +78,16 @@ enum {
> ?#define TRP_165 ? ? ? ? ? ? ? ?3
> ?#define TRAS_165 ? ? ? 7
> ?#define TRC_165 ? ? ? ? ? ? ? ?10
> -#define TRFC_165 ? ? ? 21
> +#define TRFC_165 ? ? ? 12
> ?#define V_ACTIMA_165 ? ((TRFC_165 << 27) | (TRC_165 << 22) | \
> ? ? ? ? ? ? ? ? ? ? ? ?(TRAS_165 << 18) | (TRP_165 << 15) | ?\
> ? ? ? ? ? ? ? ? ? ? ? ?(TRCD_165 << 12) | (TRRD_165 << 9) | ?\
> ? ? ? ? ? ? ? ? ? ? ? ?(TDPL_165 << 6) | (TDAL_165))
>
> ?#define TWTR_165 ? ? ? 1
> -#define TCKE_165 ? ? ? 1
> -#define TXP_165 ? ? ? ? ? ? ? ?5
> -#define XSR_165 ? ? ? ? ? ? ? ?23
> +#define TCKE_165 ? ? ? 2
> +#define TXP_165 ? ? ? ? ? ? ? ?2
> +#define XSR_165 ? ? ? ? ? ? ? ?20
> ?#define V_ACTIMB_165 ? (((TCKE_165 << 12) | (XSR_165 << 0)) | ?\
> ? ? ? ? ? ? ? ? ? ? ? ?(TXP_165 << 8) | (TWTR_165 << 16))
>
> --
> 1.6.0.4
I see issues after applying this patch (Overo/Beagle).
In about half of my boot attempts I get a hang after Uncompressing Linux....
In the other half I get many many errors of this type:
SLAB: cache with size 192 has lost its name
Reverting the patch restores normal operation.
So it seems that the Infineon timings do not work on systems with Micron memory.
Steve
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init
2009-10-19 14:53 ` Steve Sakoman
@ 2009-10-19 14:55 ` Dirk Behme
2009-10-19 15:06 ` Steve Sakoman
0 siblings, 1 reply; 19+ messages in thread
From: Dirk Behme @ 2009-10-19 14:55 UTC (permalink / raw)
To: u-boot
Steve Sakoman wrote:
> On Tue, Oct 6, 2009 at 7:17 PM, Nishanth Menon <nm@ti.com> wrote:
>> Defaults are for Infineon DDR timings.
>> Since none of the supported boards currently do
>> XIP boot, these seem to be faulty. fix the values
>> as per the calculations(ACTIMA,B), conf
>> the sdrc power with pwdnen and wakeupproc bits
>>
>> Signed-off-by: Nishanth Menon <nm@ti.com>
>> Cc: David B <david-b@pacbell.net>
>> Cc: Vikram Pandita <vikram.pandita@ti.com>
>> Cc: Richard Woodruff <r-woodruff2@ti.com>
>> Cc: Sandeep Paulraj <s-paulraj@ti.com>
>> Cc: Tom Rix <tom.rix@windriver.com>
>> Cc: Dirk Behme <dirk.behme@googlemail.com>
>> ---
>> cpu/arm_cortexa8/omap3/mem.c | 3 ++-
>> include/asm-arm/arch-omap3/cpu.h | 1 +
>> include/asm-arm/arch-omap3/mem.h | 8 ++++----
>> 3 files changed, 7 insertions(+), 5 deletions(-)
>>
>> diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
>> index 079c848..8731c9d 100644
>> --- a/cpu/arm_cortexa8/omap3/mem.c
>> +++ b/cpu/arm_cortexa8/omap3/mem.c
>> @@ -164,7 +164,8 @@ void do_sdrc_init(u32 cs, u32 early)
>> writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
>>
>> /* Disable Power Down of CKE cuz of 1 CKE on combo part */
>> - writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
>> + writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
>> + &sdrc_base->power);
>>
>> writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
>> sdelay(0x20000);
>> diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
>> index 8ab2e39..e51c4f3 100644
>> --- a/include/asm-arm/arch-omap3/cpu.h
>> +++ b/include/asm-arm/arch-omap3/cpu.h
>> @@ -222,6 +222,7 @@ struct sdrc {
>>
>> #define PAGEPOLICY_HIGH (0x1 << 0)
>> #define SRFRONRESET (0x1 << 7)
>> +#define PWDNEN (0x1 << 2)
>> #define WAKEUPPROC (0x1 << 26)
>>
>> #define DDR_SDRAM (0x1 << 0)
>> diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
>> index 5b9ac75..31cbdef 100644
>> --- a/include/asm-arm/arch-omap3/mem.h
>> +++ b/include/asm-arm/arch-omap3/mem.h
>> @@ -78,16 +78,16 @@ enum {
>> #define TRP_165 3
>> #define TRAS_165 7
>> #define TRC_165 10
>> -#define TRFC_165 21
>> +#define TRFC_165 12
>> #define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \
>> (TRAS_165 << 18) | (TRP_165 << 15) | \
>> (TRCD_165 << 12) | (TRRD_165 << 9) | \
>> (TDPL_165 << 6) | (TDAL_165))
>>
>> #define TWTR_165 1
>> -#define TCKE_165 1
>> -#define TXP_165 5
>> -#define XSR_165 23
>> +#define TCKE_165 2
>> +#define TXP_165 2
>> +#define XSR_165 20
>> #define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
>> (TXP_165 << 8) | (TWTR_165 << 16))
>>
>> --
>> 1.6.0.4
>
> I see issues after applying this patch (Overo/Beagle).
>
> In about half of my boot attempts I get a hang after Uncompressing Linux....
>
> In the other half I get many many errors of this type:
>
> SLAB: cache with size 192 has lost its name
>
> Reverting the patch restores normal operation.
What's about removing it from recent ARM pull request than and do some
further testing?
Thanks for testing
Dirk
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init
2009-10-19 14:55 ` Dirk Behme
@ 2009-10-19 15:06 ` Steve Sakoman
2009-10-20 2:19 ` [U-Boot] OMAP3 DDR Fix patches (was Re: [PATCH 1/5 v2] OMAP3: Fix SDRC init) Nishanth Menon
0 siblings, 1 reply; 19+ messages in thread
From: Steve Sakoman @ 2009-10-19 15:06 UTC (permalink / raw)
To: u-boot
On Mon, Oct 19, 2009 at 7:55 AM, Dirk Behme <dirk.behme@googlemail.com> wrote:
> Steve Sakoman wrote:
>>
>> On Tue, Oct 6, 2009 at 7:17 PM, Nishanth Menon <nm@ti.com> wrote:
>>>
>>> Defaults are for Infineon DDR timings.
>>> Since none of the supported boards currently do
>>> XIP boot, these seem to be faulty. fix the values
>>> as per the calculations(ACTIMA,B), conf
>>> the sdrc power with pwdnen and wakeupproc bits
>>>
>>> Signed-off-by: Nishanth Menon <nm@ti.com>
>>> Cc: David B <david-b@pacbell.net>
>>> Cc: Vikram Pandita <vikram.pandita@ti.com>
>>> Cc: Richard Woodruff <r-woodruff2@ti.com>
>>> Cc: Sandeep Paulraj <s-paulraj@ti.com>
>>> Cc: Tom Rix <tom.rix@windriver.com>
>>> Cc: Dirk Behme <dirk.behme@googlemail.com>
>>> ---
>>> ?cpu/arm_cortexa8/omap3/mem.c ? ? | ? ?3 ++-
>>> ?include/asm-arm/arch-omap3/cpu.h | ? ?1 +
>>> ?include/asm-arm/arch-omap3/mem.h | ? ?8 ++++----
>>> ?3 files changed, 7 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
>>> index 079c848..8731c9d 100644
>>> --- a/cpu/arm_cortexa8/omap3/mem.c
>>> +++ b/cpu/arm_cortexa8/omap3/mem.c
>>> @@ -164,7 +164,8 @@ void do_sdrc_init(u32 cs, u32 early)
>>> ? ? ? ? ? ? ? writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
>>>
>>> ? ? ? ? ? ? ? /* Disable Power Down of CKE cuz of 1 CKE on combo part */
>>> - ? ? ? ? ? ? ? writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
>>> + ? ? ? ? ? ? ? writel(WAKEUPPROC | PWDNEN | SRFRONRESET |
>>> PAGEPOLICY_HIGH,
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &sdrc_base->power);
>>>
>>> ? ? ? ? ? ? ? writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
>>> ? ? ? ? ? ? ? sdelay(0x20000);
>>> diff --git a/include/asm-arm/arch-omap3/cpu.h
>>> b/include/asm-arm/arch-omap3/cpu.h
>>> index 8ab2e39..e51c4f3 100644
>>> --- a/include/asm-arm/arch-omap3/cpu.h
>>> +++ b/include/asm-arm/arch-omap3/cpu.h
>>> @@ -222,6 +222,7 @@ struct sdrc {
>>>
>>> ?#define PAGEPOLICY_HIGH ? ? ? ? ? ? ? ?(0x1 << 0)
>>> ?#define SRFRONRESET ? ? ? ? ? ?(0x1 << 7)
>>> +#define PWDNEN ? ? ? ? ? ? ? ? (0x1 << 2)
>>> ?#define WAKEUPPROC ? ? ? ? ? ? (0x1 << 26)
>>>
>>> ?#define DDR_SDRAM ? ? ? ? ? ? ?(0x1 << 0)
>>> diff --git a/include/asm-arm/arch-omap3/mem.h
>>> b/include/asm-arm/arch-omap3/mem.h
>>> index 5b9ac75..31cbdef 100644
>>> --- a/include/asm-arm/arch-omap3/mem.h
>>> +++ b/include/asm-arm/arch-omap3/mem.h
>>> @@ -78,16 +78,16 @@ enum {
>>> ?#define TRP_165 ? ? ? ? ? ? ? ?3
>>> ?#define TRAS_165 ? ? ? 7
>>> ?#define TRC_165 ? ? ? ? ? ? ? ?10
>>> -#define TRFC_165 ? ? ? 21
>>> +#define TRFC_165 ? ? ? 12
>>> ?#define V_ACTIMA_165 ? ((TRFC_165 << 27) | (TRC_165 << 22) | \
>>> ? ? ? ? ? ? ? ? ? ? ? (TRAS_165 << 18) | (TRP_165 << 15) | ?\
>>> ? ? ? ? ? ? ? ? ? ? ? (TRCD_165 << 12) | (TRRD_165 << 9) | ?\
>>> ? ? ? ? ? ? ? ? ? ? ? (TDPL_165 << 6) | (TDAL_165))
>>>
>>> ?#define TWTR_165 ? ? ? 1
>>> -#define TCKE_165 ? ? ? 1
>>> -#define TXP_165 ? ? ? ? ? ? ? ?5
>>> -#define XSR_165 ? ? ? ? ? ? ? ?23
>>> +#define TCKE_165 ? ? ? 2
>>> +#define TXP_165 ? ? ? ? ? ? ? ?2
>>> +#define XSR_165 ? ? ? ? ? ? ? ?20
>>> ?#define V_ACTIMB_165 ? (((TCKE_165 << 12) | (XSR_165 << 0)) | ?\
>>> ? ? ? ? ? ? ? ? ? ? ? (TXP_165 << 8) | (TWTR_165 << 16))
>>>
>>> --
>>> 1.6.0.4
>>
>> I see issues after applying this patch (Overo/Beagle).
>>
>> In about half of my boot attempts I get a hang after Uncompressing
>> Linux....
>>
>> In the other half I get many many errors of this type:
>>
>> SLAB: cache with size 192 has lost its name
>>
>> Reverting the patch restores normal operation.
>
> What's about removing it from recent ARM pull request than and do some
> further testing?
That sounds like a good plan to me.
Steve
^ permalink raw reply [flat|nested] 19+ messages in thread
* [U-Boot] OMAP3 DDR Fix patches (was Re: [PATCH 1/5 v2] OMAP3: Fix SDRC init)
2009-10-19 15:06 ` Steve Sakoman
@ 2009-10-20 2:19 ` Nishanth Menon
0 siblings, 0 replies; 19+ messages in thread
From: Nishanth Menon @ 2009-10-20 2:19 UTC (permalink / raw)
To: u-boot
Steve Sakoman had written, on 10/19/2009 10:06 AM, the following:
> On Mon, Oct 19, 2009 at 7:55 AM, Dirk Behme <dirk.behme@googlemail.com> wrote:
>> Steve Sakoman wrote:
>>> On Tue, Oct 6, 2009 at 7:17 PM, Nishanth Menon <nm@ti.com> wrote:
>>>> Defaults are for Infineon DDR timings.
>>>> Since none of the supported boards currently do
>>>> XIP boot, these seem to be faulty. fix the values
>>>> as per the calculations(ACTIMA,B), conf
>>>> the sdrc power with pwdnen and wakeupproc bits
>>>>
>>>> Signed-off-by: Nishanth Menon <nm@ti.com>
>>>> Cc: David B <david-b@pacbell.net>
>>>> Cc: Vikram Pandita <vikram.pandita@ti.com>
>>>> Cc: Richard Woodruff <r-woodruff2@ti.com>
>>>> Cc: Sandeep Paulraj <s-paulraj@ti.com>
>>>> Cc: Tom Rix <tom.rix@windriver.com>
>>>> Cc: Dirk Behme <dirk.behme@googlemail.com>
>>>> ---
>>>> cpu/arm_cortexa8/omap3/mem.c | 3 ++-
>>>> include/asm-arm/arch-omap3/cpu.h | 1 +
>>>> include/asm-arm/arch-omap3/mem.h | 8 ++++----
>>>> 3 files changed, 7 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
>>>> index 079c848..8731c9d 100644
>>>> --- a/cpu/arm_cortexa8/omap3/mem.c
>>>> +++ b/cpu/arm_cortexa8/omap3/mem.c
>>>> @@ -164,7 +164,8 @@ void do_sdrc_init(u32 cs, u32 early)
>>>> writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
>>>>
>>>> /* Disable Power Down of CKE cuz of 1 CKE on combo part */
>>>> - writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
>>>> + writel(WAKEUPPROC | PWDNEN | SRFRONRESET |
>>>> PAGEPOLICY_HIGH,
>>>> + &sdrc_base->power);
>>>>
>>>> writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
>>>> sdelay(0x20000);
>>>> diff --git a/include/asm-arm/arch-omap3/cpu.h
>>>> b/include/asm-arm/arch-omap3/cpu.h
>>>> index 8ab2e39..e51c4f3 100644
>>>> --- a/include/asm-arm/arch-omap3/cpu.h
>>>> +++ b/include/asm-arm/arch-omap3/cpu.h
>>>> @@ -222,6 +222,7 @@ struct sdrc {
>>>>
>>>> #define PAGEPOLICY_HIGH (0x1 << 0)
>>>> #define SRFRONRESET (0x1 << 7)
>>>> +#define PWDNEN (0x1 << 2)
>>>> #define WAKEUPPROC (0x1 << 26)
>>>>
>>>> #define DDR_SDRAM (0x1 << 0)
>>>> diff --git a/include/asm-arm/arch-omap3/mem.h
>>>> b/include/asm-arm/arch-omap3/mem.h
>>>> index 5b9ac75..31cbdef 100644
>>>> --- a/include/asm-arm/arch-omap3/mem.h
>>>> +++ b/include/asm-arm/arch-omap3/mem.h
>>>> @@ -78,16 +78,16 @@ enum {
>>>> #define TRP_165 3
>>>> #define TRAS_165 7
>>>> #define TRC_165 10
>>>> -#define TRFC_165 21
>>>> +#define TRFC_165 12
>>>> #define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \
>>>> (TRAS_165 << 18) | (TRP_165 << 15) | \
>>>> (TRCD_165 << 12) | (TRRD_165 << 9) | \
>>>> (TDPL_165 << 6) | (TDAL_165))
>>>>
>>>> #define TWTR_165 1
>>>> -#define TCKE_165 1
>>>> -#define TXP_165 5
>>>> -#define XSR_165 23
>>>> +#define TCKE_165 2
>>>> +#define TXP_165 2
>>>> +#define XSR_165 20
>>>> #define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \
>>>> (TXP_165 << 8) | (TWTR_165 << 16))
>>>>
>>>> --
>>>> 1.6.0.4
>>> I see issues after applying this patch (Overo/Beagle).
>>>
>>> In about half of my boot attempts I get a hang after Uncompressing
>>> Linux....
>>>
>>> In the other half I get many many errors of this type:
>>>
>>> SLAB: cache with size 192 has lost its name
>>>
>>> Reverting the patch restores normal operation.
>> What's about removing it from recent ARM pull request than and do some
>> further testing?
>
> That sounds like a good plan to me.
Original patch was send on 6th Oct. sad that we will need to break
complete SDP3430 boot support.. How about fixing it properly once for
all-> looks like a previous commit hacked the timings meant for INFINEON
DDR with MICRON values for few of them causing this mess. attached is a
patchset to fix it.
Tested on SDP3430, buildtested for others - Steve do try it on your
platform to confirm. more testing invited..
--
Regards,
Nishanth Menon
-------------- next part --------------
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^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2009-10-20 2:19 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-10-07 2:17 [U-Boot] [PATCH 0/5 v2] ARM:OMAP3:SDP3430 initial support Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 2/5] OMAP3: export enable_gpmc_cs_config to board files Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 4/5] OMAP3: fix warnings when NAND/ONENAND is not used Nishanth Menon
2009-10-07 2:17 ` [U-Boot] [PATCH 5/5 v2] ARM:OMAP3:SDP3430: initial support Nishanth Menon
2009-10-10 19:20 ` [U-Boot] [PATCH 4/5] OMAP3: fix warnings when NAND/ONENAND is not used Paulraj, Sandeep
2009-10-10 19:29 ` [U-Boot] [PATCH 3/5] OMAP3: make gpmc_config as const Paulraj, Sandeep
2009-10-11 7:54 ` Dirk Behme
2009-10-11 12:22 ` Paulraj, Sandeep
2009-10-11 14:35 ` Nishanth Menon
2009-10-11 14:48 ` Paulraj, Sandeep
2009-10-11 15:01 ` Nishanth Menon
2009-10-10 19:18 ` [U-Boot] [PATCH 2/5] OMAP3: export enable_gpmc_cs_config to board files Paulraj, Sandeep
2009-10-10 19:24 ` [U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init Paulraj, Sandeep
2009-10-19 14:53 ` Steve Sakoman
2009-10-19 14:55 ` Dirk Behme
2009-10-19 15:06 ` Steve Sakoman
2009-10-20 2:19 ` [U-Boot] OMAP3 DDR Fix patches (was Re: [PATCH 1/5 v2] OMAP3: Fix SDRC init) Nishanth Menon
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