[U-Boot] [PATCH 0/4] mpc52xx: IPEK01 board support

[U-Boot] [PATCH 0/4] mpc52xx: IPEK01 board support

[Wolfgang Grandegegr]

From: Wolfgang Grandegger <wg@denx.de>

This patch add support for the IPEK01 MPC5200 based board.
It requires three patches for the Fujitsu MB862xx driver.

Anatolij Gustschin (1):
  video: mb862xx: add option CONFIG_VIDEO_MB862xx_ACCEL for 32bpp mode

Wolfgang Grandegger (3):
  video: mb862xx: improve board-specific Lime configuration
  video: mb862xx: add option VIDEO_FB_16BPP_WORD_SWAP for IPEK01
  mpc52xx: add support for the IPEK01 board

 MAINTAINERS                 |    2 +
 MAKEALL                     |    1 +
 Makefile                    |    3 +
 board/ipek01/Makefile       |   50 ++++++
 board/ipek01/config.mk      |   30 +++
 board/ipek01/ipek01.c       |  282 +++++++++++++++++++++++++++++
 board/lwmon5/lwmon5.c       |    7 -
 board/socrates/socrates.c   |   46 +----
 drivers/video/cfb_console.c |    4 +-
 drivers/video/mb862xx.c     |   50 +++++-
 include/configs/ipek01.h    |  408 +++++++++++++++++++++++++++++++++++++++++++
 include/configs/lwmon5.h    |   12 +-
 include/configs/socrates.h  |    7 +
 include/mb862xx.h           |    5 +
 14 files changed, 852 insertions(+), 55 deletions(-)
 create mode 100644 board/ipek01/Makefile
 create mode 100644 board/ipek01/config.mk
 create mode 100644 board/ipek01/ipek01.c
 create mode 100644 include/configs/ipek01.h

[U-Boot] [PATCH 0/4] *** SUBJECT HERE ***

[Wolfgang Grandegegr]

From: Wolfgang Grandegger <wg@denx.de>

*** BLURB HERE ***

Anatolij Gustschin (1):
  video: mb862xx: add option CONFIG_VIDEO_MB862xx_ACCEL for 32bpp mode

Wolfgang Grandegger (3):
  video: mb862xx: improve board-specific Lime configuration
  video: mb862xx: add option VIDEO_FB_16BPP_WORD_SWAP for IPEK01
  mpc52xx: add support for the IPEK01 board

 MAINTAINERS                 |    2 +
 MAKEALL                     |    1 +
 Makefile                    |    3 +
 board/ipek01/Makefile       |   50 ++++++
 board/ipek01/config.mk      |   30 +++
 board/ipek01/ipek01.c       |  282 +++++++++++++++++++++++++++++
 board/lwmon5/lwmon5.c       |    7 -
 board/socrates/socrates.c   |   46 +----
 drivers/video/cfb_console.c |    4 +-
 drivers/video/mb862xx.c     |   50 +++++-
 include/configs/ipek01.h    |  408 +++++++++++++++++++++++++++++++++++++++++++
 include/configs/lwmon5.h    |   12 +-
 include/configs/socrates.h  |    7 +
 include/mb862xx.h           |    5 +
 14 files changed, 852 insertions(+), 55 deletions(-)
 create mode 100644 board/ipek01/Makefile
 create mode 100644 board/ipek01/config.mk
 create mode 100644 board/ipek01/ipek01.c
 create mode 100644 include/configs/ipek01.h

[U-Boot] [PATCH 1/4] video: mb862xx: improve board-specific Lime configuration

[Wolfgang Grandegegr]

From: Wolfgang Grandegger <wg@denx.de>

To avoid board-specific code accessing the mb862xx registers directly,
the public function mb862xx_probe() has been introduced. Furthermore,
the "Change of Clock Frequency" and "Set Memory I/F Mode" registers
are now defined by CONFIG_SYS_MB862xx_CCF and CONFIG_SYS_MB862xx__MMR,
respectively. The BSPs for the socrates and lwmon5 boards have been
adapted accordingly.

Signed-off-by: Wolfgang Grandegger <wg@denx.de>
---
 board/lwmon5/lwmon5.c      |    7 ------
 board/socrates/socrates.c  |   46 ++++++-------------------------------------
 drivers/video/mb862xx.c    |   34 +++++++++++++++++++++++++++++++-
 include/configs/lwmon5.h   |   10 +++-----
 include/configs/socrates.h |    5 ++++
 include/mb862xx.h          |    5 ++++
 6 files changed, 54 insertions(+), 53 deletions(-)

diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index ef7f2e8..d36ea04 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -532,13 +532,6 @@ unsigned int board_video_init (void)
 	udelay(500);
 	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
 
-	/* Lime memory clock adjusted to 100MHz */
-	out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_LIME_CLOCK_100MHZ);
-	/* Wait untill time expired. Because of requirements in lime manual */
-	udelay(300);
-	/* Write lime controller memory parameters */
-	out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
-
 	mb862xx.winSizeX = 640;
 	mb862xx.winSizeY = 480;
 	mb862xx.gdfBytesPP = 2;
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 51d66d5..9183c15 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -268,17 +268,6 @@ ft_board_setup(void *blob, bd_t *bd)
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 
-#define CONFIG_SYS_LIME_SRST		((CONFIG_SYS_LIME_BASE) + 0x01FC002C)
-#define CONFIG_SYS_LIME_CCF		((CONFIG_SYS_LIME_BASE) + 0x01FC0038)
-#define CONFIG_SYS_LIME_MMR		((CONFIG_SYS_LIME_BASE) + 0x01FCFFFC)
-/* Lime clock frequency */
-#define CONFIG_SYS_LIME_CLK_100MHZ	0x00000
-#define CONFIG_SYS_LIME_CLK_133MHZ	0x10000
-/* SDRAM parameter */
-#define CONFIG_SYS_LIME_MMR_VALUE	0x4157BA63
-
-#define DISPLAY_WIDTH		800
-#define DISPLAY_HEIGHT		480
 #define DEFAULT_BRIGHTNESS	25
 #define BACKLIGHT_ENABLE	(1 << 31)
 
@@ -308,14 +297,12 @@ const gdc_regs *board_get_regs (void)
 	return init_regs;
 }
 
-#define CONFIG_SYS_LIME_CID		((CONFIG_SYS_LIME_BASE) + 0x01FC00F0)
-#define CONFIG_SYS_LIME_REV		((CONFIG_SYS_LIME_BASE) + 0x01FF8084)
 int lime_probe(void)
 {
 	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	uint cfg_br2;
 	uint cfg_or2;
-	uint reg;
+	int type;
 
 	cfg_br2 = memctl->br2;
 	cfg_or2 = memctl->or2;
@@ -325,21 +312,15 @@ int lime_probe(void)
 	memctl->or2 = 0xfc000410;
 	memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
 
-	/* Try to access GDC ID/Revision registers */
-	reg = in_be32((void *)CONFIG_SYS_LIME_CID);
-	reg = in_be32((void *)CONFIG_SYS_LIME_CID);
-	if (reg == 0x303) {
-		reg = in_be32((void *)CONFIG_SYS_LIME_REV);
-		reg = in_be32((void *)CONFIG_SYS_LIME_REV);
-		reg = ((reg & ~0xff) == 0x20050100) ? 1 : 0;
-	} else
-		reg = 0;
+	/* Get controller type */
+	type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
 
 	/* Restore previous CS2 configuration */
 	memctl->br2 = 0;
 	memctl->or2 = cfg_or2;
 	memctl->br2 = cfg_br2;
-	return reg;
+
+	return (type == MB862XX_TYPE_LIME) ? 1 : 0;
 }
 
 /* Returns Lime base address */
@@ -348,21 +329,8 @@ unsigned int board_video_init (void)
 	if (!lime_probe())
 		return 0;
 
-	/*
-	 * Reset Lime controller
-	 */
-	out_be32((void *)CONFIG_SYS_LIME_SRST, 0x1);
-	udelay(200);
-
-	/* Set Lime clock to 133MHz */
-	out_be32((void *)CONFIG_SYS_LIME_CCF, CONFIG_SYS_LIME_CLK_133MHZ);
-	/* Delay required */
-	udelay(300);
-	/* Set memory parameters */
-	out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
-
-	mb862xx.winSizeX = DISPLAY_WIDTH;
-	mb862xx.winSizeY = DISPLAY_HEIGHT;
+	mb862xx.winSizeX = 800;
+	mb862xx.winSizeY = 480;
 	mb862xx.gdfIndex = GDF_15BIT_555RGB;
 	mb862xx.gdfBytesPP = 2;
 
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
index a8676cc..bb212a8 100644
--- a/drivers/video/mb862xx.c
+++ b/drivers/video/mb862xx.c
@@ -340,6 +340,30 @@ unsigned int card_init (void)
 }
 #endif
 
+
+#if !defined(CONFIG_VIDEO_CORALP)
+int mb862xx_probe(unsigned int addr)
+{
+	GraphicDevice *dev = &mb862xx;
+	unsigned int reg;
+
+	dev->frameAdrs = addr;
+	dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
+
+	/* Try to access GDC ID/Revision registers */
+	reg = HOST_RD_REG (GC_CID);
+	reg = HOST_RD_REG (GC_CID);
+	if (reg == 0x303) {
+		reg = DE_RD_REG(GC_REV);
+		reg = DE_RD_REG(GC_REV);
+		if ((reg & ~0xff) == 0x20050100)
+			return MB862XX_TYPE_LIME;
+	}
+
+	return 0;
+}
+#endif
+
 void *video_hw_init (void)
 {
 	GraphicDevice *dev = &mb862xx;
@@ -359,8 +383,16 @@ void *video_hw_init (void)
 	if ((dev->frameAdrs = board_video_init ()) == 0) {
 		puts ("Controller not found!\n");
 		return NULL;
-	} else
+	} else {
 		puts ("Lime\n");
+
+		/* Set Change of Clock Frequency Register */
+		HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
+		/* Delay required */
+		udelay(300);
+		/* Set Memory I/F Mode Register) */
+		HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
+	}
 #endif
 
 	de_init ();
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 777a4d6..67434f5 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -495,8 +495,6 @@
 /*-----------------------------------------------------------------------
  * Graphics (Fujitsu Lime)
  *----------------------------------------------------------------------*/
-/* SDRAM Clock frequency adjustment register */
-#define CONFIG_SYS_LIME_SDRAM_CLOCK	0xC1FC0038
 /* Lime Clock frequency is to set 100MHz */
 #define CONFIG_SYS_LIME_CLOCK_100MHZ	0x00000
 #if 0
@@ -504,15 +502,15 @@
 #define CONFIG_SYS_LIME_CLOCK_133MHZ	0x10000
 #endif
 
-/* SDRAM Parameter register */
-#define CONFIG_SYS_LIME_MMR		0xC1FCFFFC
 /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
    and pixel flare on display when 133MHz was configured. According to
    SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
-#define CONFIG_SYS_LIME_MMR_VALUE	0x414FB7F3
+#define CONFIG_SYS_MB862xx_MMR	0x414FB7F3
+#define CONFIG_SYS_MB862xx_CCF	CONFIG_SYS_LIME_CLOCK_133MHZ
 #else
-#define CONFIG_SYS_LIME_MMR_VALUE	0x414FB7F2
+#define CONFIG_SYS_MB862xx_MMR	0x414FB7F2
+#define CONFIG_SYS_MB862xx_CCF	CONFIG_SYS_LIME_CLOCK_100MHZ
 #endif
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 35feed0..3321aa2 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -210,6 +210,11 @@
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
 
+/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
+#define CONFIG_SYS_MB862xx_CCF		0x10000
+/* SDRAM parameter */
+#define CONFIG_SYS_MB862xx_MMR		0x4157BA63
+
 /* Serial Port */
 
 #define CONFIG_CONS_INDEX     1
diff --git a/include/mb862xx.h b/include/mb862xx.h
index 43f01e7..009da03 100644
--- a/include/mb862xx.h
+++ b/include/mb862xx.h
@@ -32,6 +32,8 @@
 #define PCI_DEVICE_ID_CORAL_P	0x2019
 #define PCI_DEVICE_ID_CORAL_PA	0x201E
 
+#define MB862XX_TYPE_LIME	0x1
+
 #define GC_HOST_BASE		0x01fc0000
 #define GC_DISP_BASE		0x01fd0000
 #define GC_DRAW_BASE		0x01ff0000
@@ -39,6 +41,7 @@
 /* Host interface registers */
 #define GC_SRST			0x0000002c
 #define GC_CCF			0x00000038
+#define GC_CID			0x000000f0
 #define GC_MMR			0x0000fffc
 
 /*
@@ -99,6 +102,7 @@
 #define GC_FC			0x00000480
 #define GC_BC			0x00000484
 #define GC_FIFO			0x000004a0
+#define GC_REV			0x00008084
 #define GC_GEO_FIFO		0x00008400
 
 typedef struct {
@@ -106,6 +110,7 @@ typedef struct {
 	unsigned int value;
 } gdc_regs;
 
+int mb862xx_probe(unsigned int addr);
 const gdc_regs *board_get_regs (void);
 unsigned int board_video_init (void);
 void board_backlight_switch(int);
-- 
1.6.2.5

[U-Boot] [PATCH 2/4] video: mb862xx: add option CONFIG_VIDEO_MB862xx_ACCEL for 32bpp mode

[Wolfgang Grandegegr]

From: Anatolij Gustschin <agust@denx.de>

The new IPEK01 board can use the 32 bpp mode for the Lime graphics
controller. For this mode, video accelaration does not work. This patch
makes the accelaration configurable via CONFIG_VIDEO_MB862xx_ACCEL,
which is enabled for the lwmon5 and the socrates board for backward
compatibility.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
---
 drivers/video/cfb_console.c |    2 ++
 drivers/video/mb862xx.c     |   16 +++++++++++++++-
 include/configs/lwmon5.h    |    1 +
 include/configs/socrates.h  |    1 +
 4 files changed, 19 insertions(+), 1 deletions(-)

diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index fbc4df9..0df321c 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -146,9 +146,11 @@ CONFIG_VIDEO_HW_CURSOR:	     - Uses the hardware cursor capability of the
 #ifdef CONFIG_VIDEO_CORALP
 #define VIDEO_FB_LITTLE_ENDIAN
 #endif
+#ifdef CONFIG_VIDEO_MB862xx_ACCEL
 #define VIDEO_HW_RECTFILL
 #define VIDEO_HW_BITBLT
 #endif
+#endif
 
 /*****************************************************************************/
 /* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc	     */
diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c
index bb212a8..edf34aa 100644
--- a/drivers/video/mb862xx.c
+++ b/drivers/video/mb862xx.c
@@ -89,6 +89,7 @@ unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
 				       (GC_DISP_BASE | GC_L0PAL0) + \
 				       ((idx) << 2)), (val))
 
+#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
 static void gdc_sw_reset (void)
 {
 	GraphicDevice *dev = &mb862xx;
@@ -129,6 +130,7 @@ static void de_wait_slots (int slots)
 			break;
 		}
 }
+#endif
 
 #if !defined(CONFIG_VIDEO_CORALP)
 static void board_disp_init (void)
@@ -144,11 +146,13 @@ static void board_disp_init (void)
 #endif
 
 /*
- * Init drawing engine
+ * Init drawing engine if accel enabled.
+ * Also clears visible framebuffer.
  */
 static void de_init (void)
 {
 	GraphicDevice *dev = &mb862xx;
+#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
 	int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
 
 	dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
@@ -174,6 +178,14 @@ static void de_init (void)
 	DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
 	/* sync with SW access to framebuffer */
 	de_wait ();
+#else
+	unsigned int i, *p;
+
+	i = dev->winSizeX * dev->winSizeY;
+	p = (unsigned int *)dev->frameAdrs;
+	while (i--)
+		*p++ = 0;
+#endif
 }
 
 #if defined(CONFIG_VIDEO_CORALP)
@@ -421,6 +433,7 @@ void video_set_lut (unsigned int index, unsigned char r,
 	L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
 }
 
+#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
 /*
  * Drawing engine Fill and BitBlt screen region
  */
@@ -462,3 +475,4 @@ void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
 	DE_WR_FIFO ((height << 16) | width);
 	de_wait (); /* sync */
 }
+#endif
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 67434f5..927b80f 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -344,6 +344,7 @@
 /* Video console */
 #define CONFIG_VIDEO
 #define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_CONSOLE_EXTRA_INFO
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 3321aa2..59a4b28 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -198,6 +198,7 @@
 
 #define CONFIG_VIDEO
 #define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
-- 
1.6.2.5

[U-Boot] [PATCH 3/4] video: mb862xx: add option VIDEO_FB_16BPP_WORD_SWAP for IPEK01

[Wolfgang Grandegegr]

From: Wolfgang Grandegger <wg@denx.de>

In 16 bpp mode, the new IPEK01 board only requires swapping of D16 words
for D32 accesses due to the diffferent connecting to the GDC bus. This
patch introduces the configuration option VIDEO_FB_16BPP_WORD_SWAP,
which should be set for all board using the mb862xx in 16 bpp mode. For
the IPEK01, VIDEO_FB_16BPP_PIXEL_SWAP should not be set.

Signed-off-by: Wolfgang Grandegger <wg@denx.de>
---
 drivers/video/cfb_console.c |    2 +-
 include/configs/lwmon5.h    |    1 +
 include/configs/socrates.h  |    1 +
 3 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 0df321c..16d6689 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -321,7 +321,7 @@ void	console_cursor (int state);
 #else
 #define SWAP16(x)	 (x)
 #define SWAP32(x)	 (x)
-#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
+#if defined(VIDEO_FB_16BPP_WORD_SWAP)
 #define SHORTSWAP32(x)	 ( ((x) >> 16) | ((x) << 16) )
 #else
 #define SHORTSWAP32(x)	 (x)
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 927b80f..011dd5c 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -349,6 +349,7 @@
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_CONSOLE_EXTRA_INFO
 #define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
 
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_VIDEO_SW_CURSOR
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 59a4b28..3632b84 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -204,6 +204,7 @@
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_CONSOLE_EXTRA_INFO
 #define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 #define CONFIG_VIDEO_SW_CURSOR
-- 
1.6.2.5

[U-Boot] [PATCH 4/4] mpc52xx: add support for the IPEK01 board

[Wolfgang Grandegegr]

From: Wolfgang Grandegger <wg@denx.de>

This patch adds support for the board IPEK01 based on the MPC5200.
The Futjitsu Lime graphics controller is configured in 16 bpp mode.

Signed-off-by: Wolfgang Grandegger <wg@denx.de>
---
 MAINTAINERS              |    2 +
 MAKEALL                  |    1 +
 Makefile                 |    3 +
 board/ipek01/Makefile    |   50 ++++++
 board/ipek01/config.mk   |   30 ++++
 board/ipek01/ipek01.c    |  282 ++++++++++++++++++++++++++++++++
 include/configs/ipek01.h |  408 ++++++++++++++++++++++++++++++++++++++++++++++
 7 files changed, 776 insertions(+), 0 deletions(-)
 create mode 100644 board/ipek01/Makefile
 create mode 100644 board/ipek01/config.mk
 create mode 100644 board/ipek01/ipek01.c
 create mode 100644 include/configs/ipek01.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 2297651..15d80c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -201,6 +201,8 @@ Frank Gottschling <fgottschling@eltec.de>
 
 Wolfgang Grandegger <wg@denx.de>
 
+	ipek01		MPC5200
+
 	CCM		MPC855
 
 	PN62		MPC8240
diff --git a/MAKEALL b/MAKEALL
index 07d2414..4cac417 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -63,6 +63,7 @@ LIST_5xxx="		\
 	icecube_5100	\
 	icecube_5200	\
 	inka4x0		\
+	ipek01		\
 	lite5200b	\
 	mcc200		\
 	mecp5200	\
diff --git a/Makefile b/Makefile
index bed9469..e4cde64 100644
--- a/Makefile
+++ b/Makefile
@@ -606,6 +606,9 @@ jupiter_config:	unconfig
 inka4x0_config:	unconfig
 	@$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
 
+ipek01_config: unconfig
+	@$(MKCONFIG) -a ipek01 ppc mpc5xxx ipek01
+
 lite5200b_config	\
 lite5200b_PM_config	\
 lite5200b_LOWBOOT_config:	unconfig
diff --git a/board/ipek01/Makefile b/board/ipek01/Makefile
new file mode 100644
index 0000000..ddfd2ef
--- /dev/null
+++ b/board/ipek01/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ipek01/config.mk b/board/ipek01/config.mk
new file mode 100644
index 0000000..c8ecb29
--- /dev/null
+++ b/board/ipek01/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2003-2004
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# IPEK01 board
+#
+
+TEXT_BASE = 0xfc000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c
new file mode 100644
index 0000000..463a81b
--- /dev/null
+++ b/board/ipek01/ipek01.c
@@ -0,0 +1,282 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
+ *
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * (C) Copyright 2009
+ * Wolfgang Grandegger, DENX Software Engineering, wg at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <mb862xx.h>
+#include <video_fb.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_OF_LIBFDT
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
+/* mt46v16m16-75 */
+#ifdef CONFIG_MPC5200_DDR
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+#else
+#error SDRAM is not supported on this board
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start (int hi_addr)
+{
+	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
+
+	/* precharge all banks */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+	/* set mode register: extended mode */
+	out_be32 (&sdram->mode, SDRAM_EMODE);
+
+	/* set mode register: reset DLL */
+	out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000);
+
+	/* precharge all banks */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+	/* auto refresh */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
+
+	/* set mode register */
+	out_be32 (&sdram->mode, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
+}
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+
+phys_size_t initdram (int board_type)
+{
+	struct mpc5xxx_mmap_ctl *mmap_ctl =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM;
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32 (&mmap_ctl->sdram0, 0x0000001e);	/* 2G at 0x0 */
+	out_be32 (&mmap_ctl->sdram1, 0x00000000);	/* disabled */
+
+	/* setup config registers */
+	out_be32 (&sdram->config1, SDRAM_CONFIG1);
+	out_be32 (&sdram->config2, SDRAM_CONFIG2);
+
+	/* set tap delay */
+	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start (0);
+	test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start (1);
+	test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start (0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0)
+		out_be32 (&mmap_ctl->sdram0,
+			  0x13 + __builtin_ffs (dramsize >> 20) - 1);
+	else
+		out_be32 (&mmap_ctl->sdram1, 0);	/* disabled */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	out_be32 (&sdram->sdelay, 0x04);
+
+	return dramsize + dramsize2;
+}
+
+int checkboard (void)
+{
+	puts ("Board: IPEK01 \n");
+	return 0;
+}
+
+void flash_preinit (void)
+{
+	struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
+
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	clrbits_be32 (&lpb->cs0_cfg, 0x1);	/* clear RO */
+}
+
+void flash_afterinit (ulong start, ulong size)
+{
+	struct mpc5xxx_mmap_ctl *mmap_ctl =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+
+#if defined(CONFIG_BOOT_ROM)
+	/* adjust mapping */
+	out_be32 (&mmap_ctl->cs1_start, START_REG (start));
+	out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
+#else
+	/* adjust mapping */
+	out_be32 (&mmap_ctl->boot_start, START_REG (start));
+	out_be32 (&mmap_ctl->cs0_start, START_REG (start));
+	out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
+	out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
+#endif
+}
+
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+int misc_init_r (void)
+{
+	/* adjust flash start */
+	gd->bd->bi_flashstart = flash_info[0].start[0];
+	return (0);
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init (struct pci_controller *);
+
+void pci_init_board (void)
+{
+	pci_mpc5xxx_init (&hose);
+}
+#endif
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup (void *blob, bd_t * bd)
+{
+	ft_cpu_setup (blob, bd);
+	fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+int board_eth_init(bd_t *bis)
+{
+        cpu_eth_init(bis); /* Built in FEC comes first */
+        return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_VIDEO
+extern GraphicDevice mb862xx;
+
+static const gdc_regs init_regs[] = {
+	{0x0100, 0x00000900},
+	{0x0020, 0x80190257},
+	{0x0024, 0x00000000},
+	{0x0028, 0x00000000},
+	{0x002c, 0x00000000},
+	{0x0110, 0x00000000},
+	{0x0114, 0x00000000},
+	{0x0118, 0x02570320},
+	{0x0004, 0x041f0000},
+	{0x0008, 0x031f031f},
+	{0x000c, 0x067f0347},
+	{0x0010, 0x02780000},
+	{0x0014, 0x0257025c},
+	{0x0018, 0x00000000},
+	{0x001c, 0x02570320},
+	{0x0100, 0x80010900},
+	{0x0, 0x0}
+};
+
+const gdc_regs *board_get_regs (void)
+{
+	return init_regs;
+}
+
+/* Returns Lime base address */
+unsigned int board_video_init (void)
+{
+	if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
+		return 0;
+
+	mb862xx.winSizeX = 800;
+	mb862xx.winSizeY = 600;
+	mb862xx.gdfIndex = GDF_15BIT_555RGB;
+	mb862xx.gdfBytesPP = 2;
+
+	return CONFIG_SYS_LIME_BASE;
+}
+
+#if defined(CONFIG_CONSOLE_EXTRA_INFO)
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	if (line_number == 1)
+		strcpy (info, " Board: IPEK01");
+	else
+		info[0] = '\0';
+}
+#endif
+#endif /* CONFIG_VIDEO */
diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
new file mode 100644
index 0000000..d9028fa
--- /dev/null
+++ b/include/configs/ipek01.h
@@ -0,0 +1,408 @@
+/*
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * (C) Copyright 2009
+ * Wolfgang Grandegger, DENX Software Engineering, wg at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC5200
+#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPX5200		1	/* ... on MPX5200 board */
+#define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM */
+#define CONFIG_IPEK01           	/* Motherboard is ipek01 */
+
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
+
+#define CONFIG_MISC_INIT_R
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+#define CONFIG_SYS_CACHELINE_SIZE	32 /* For MPC5xxx CPUs */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5  /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_BAUDRATE		115200	/* ... at 9600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+
+/*
+ * Video configuration for LIME GDC
+ */
+#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(2 << 20)	/* decompressed img */
+/* Lime clock frequency */
+#define CONFIG_SYS_MB862xx_CCF	0x90000	/* geo 166MHz other 133MHz */
+/* SDRAM parameter */
+#define CONFIG_SYS_MB862xx_MMR	0x41c767e3
+#endif
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI		1
+#define CONFIG_PCI_PNP		1
+#define CONFIG_PCI_SCAN_SHOW	1
+
+#define CONFIG_PCI_MEM_BUS	0x40000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x50000000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0x01000000
+
+#define CONFIG_NET_MULTI	1
+#define CONFIG_MII		1
+#define CONFIG_EEPRO100		1
+#define CONFIG_SYS_RX_ETH_BUFFER	8  /* use 8 rx buffer on eepro100  */
+
+/* Partitions */
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_OHCI_BE_CONTROLLER
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		MPC5XXX_USB
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"mpc5200"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP		/* BMP support */
+#endif
+#define CONFIG_CMD_DATE		/* support for RTC, date/time...*/
+#define CONFIG_CMD_DHCP		/* DHCP Support */
+#define CONFIG_CMD_FAT		/* FAT support */
+#define CONFIG_CMD_I2C		/* I2C serial bus support */
+#define CONFIG_CMD_IDE		/* IDE harddisk support */
+#define CONFIG_CMD_IRQ		/* irqinfo */
+#define CONFIG_CMD_MII		/* MII support */
+#define CONFIG_CMD_PCI		/* pciinfo */
+#define CONFIG_CMD_USB		/* USB Support */
+
+#define CONFIG_SYS_LOWBOOT	1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyPSC0\0"						\
+	"hostname=ipek01\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consoledev},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdtaddr}\0"			\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0"	\
+	"net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};"  \
+		"run nfsargs addip addtty;"    				\
+		 "bootm ${loadaddr} - ${fdtaddr}\0"			\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=ipek01/uImage\0"					\
+	"load=tftp 100000 ipek01/u-boot.bin\0"				\
+	"update=protect off FC000000 +60000; era FC000000 +60000; "	\
+		"cp.b 100000 FC000000 ${filesize}\0"   			\
+	"upd=run load;run update\0"					\
+	"fdtaddr=800000\0"						\
+	"loadaddr=400000\0"						\
+	"fdtfile=ipek01/ipek01.dtb\0"					\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 	/* for 133MHz */
+/* PCI clock must be 33, because board will not boot */
+#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2	/* for 66MHz */
+
+/*
+ * Open firmware flat tree support
+ */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+
+#define OF_CPU			"PowerPC,5200 at 0"
+#define OF_SOC			"soc5200 at f0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CONFIG_SYS_I2C_MODULE	2	/* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED	100000	/* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR		0x51
+
+#define CONFIG_SYS_FLASH_BASE		0xFC000000
+#define CONFIG_SYS_FLASH_SIZE		0x01000000
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+					 CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1    /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256  /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_PROTECTION  /* "Real" (hardware) sectors protection */
+
+/* use CFI flash driver */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SIZE			0x10000
+#define CONFIG_ENV_SECT_SIZE		0x20000
+#define CONFIG_ENV_OVERWRITE		1
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR			0xf0000000
+#define CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
+#define	CONFIG_SYS_SRAM_BASE		0xF1000000
+#define	CONFIG_SYS_SRAM_SIZE		0x00200000
+#define	CONFIG_SYS_LIME_BASE		0xE4000000
+#define	CONFIG_SYS_LIME_SIZE		0x04000000
+#define	CONFIG_SYS_FPGA_BASE		0xC0000000
+#define	CONFIG_SYS_FPGA_SIZE		0x10000000
+#define	CONFIG_SYS_MPEG_BASE		0xe2000000
+#define	CONFIG_SYS_MPEG_SIZE		0x01000000
+#define CONFIG_SYS_CF_BASE		0xe1000000
+#define CONFIG_SYS_CF_SIZE		0x01000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
+/* End of used area in DPRAM */
+#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
+
+
+
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#   define CONFIG_SYS_RAMBOOT		1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN	(384 << 10)  /* Reserve 384 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN	(4 << 20)    /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)    /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC		1
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR			0x00
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG	0x1d556624
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+#endif
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+
+#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1...15 MB in DRAM */
+
+#define CONFIG_SYS_LOAD_ADDR		0x100000 /* default load address */
+
+#define CONFIG_SYS_HZ			1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL		HID0_ICE
+#else
+#define CONFIG_SYS_HID0_INIT		0
+#define CONFIG_SYS_HID0_FINAL		0
+#endif
+
+#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_START		CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_CS1_SIZE		CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_CS3_START		CONFIG_SYS_LIME_BASE
+#define CONFIG_SYS_CS3_SIZE		CONFIG_SYS_LIME_SIZE
+#define	CONFIG_SYS_CS6_START		CONFIG_SYS_FPGA_BASE
+#define	CONFIG_SYS_CS6_SIZE		CONFIG_SYS_FPGA_SIZE
+#define	CONFIG_SYS_CS5_START		CONFIG_SYS_CF_BASE
+#define	CONFIG_SYS_CS5_SIZE		CONFIG_SYS_CF_SIZE
+#define	CONFIG_SYS_CS7_START		CONFIG_SYS_MPEG_BASE
+#define	CONFIG_SYS_CS7_SIZE		CONFIG_SYS_MPEG_SIZE
+
+#ifdef CONFIG_SYS_PCISPEED_66
+#define CONFIG_SYS_BOOTCS_CFG		0x0006F900
+#define CONFIG_SYS_CS1_CFG		0x0004FB00
+#define CONFIG_SYS_CS2_CFG		0x0006F900
+#else
+#define CONFIG_SYS_BOOTCS_CFG		0x0002F900
+#define CONFIG_SYS_CS1_CFG		0x0001FB00
+#define CONFIG_SYS_CS2_CFG		0x0002F90C
+#endif
+
+/*
+ * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
+ * waitstates, writeswap and readswap enabled
+ */
+#define CONFIG_SYS_CS3_CFG		0x00FFFB0C
+#define	CONFIG_SYS_CS6_CFG		0x00FFFB0C
+#define	CONFIG_SYS_CS7_CFG		0x4040751C
+
+#define CONFIG_SYS_CS_BURST		0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE		0x33330000
+
+#define CONFIG_SYS_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK		0x0001BBBB
+#define CONFIG_USB_CONFIG		0x00005000
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1 /* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE	2 /* max. 2 drives per IDE bus */
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses */
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers */
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#endif /* __CONFIG_H */
-- 
1.6.2.5

[U-Boot] [PATCH 4/4] mpc52xx: add support for the IPEK01 board

[Wolfgang Grandegegr]

[U-Boot] [PATCH 0/4] *** SUBJECT HERE ***

[Wolfgang Denk]

Dear Wolfgang Grandegegr,

In message <1256208516-10637-2-git-send-email-wg@grandegger.com> you wrote:
> From: Wolfgang Grandegger <wg@denx.de>
> 
> *** BLURB HERE ***

Heh :-)

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Do not follow where the path may lead....go instead where there is no
path and leave a trail.

[U-Boot] [PATCH 0/4] *** SUBJECT HERE ***

[Wolfgang Grandegger]

Wolfgang Denk wrote:
> Dear Wolfgang Grandegegr,
> 
> In message <1256208516-10637-2-git-send-email-wg@grandegger.com> you wrote:
>> From: Wolfgang Grandegger <wg@denx.de>
>>
>> *** BLURB HERE ***
> 
> Heh :-)

"git send-email" obviously has sent the emacs backup file
"0000-cover-letter.patch~" in my patch directory as well :-(. What's
worse is that I mis-spelled my second name. Sorry for the noise.

Wolfgang.

[U-Boot] [PATCH 4/4] mpc52xx: add support for the IPEK01 board

[Wolfgang Grandegger]

Hi,

there was a simple script fine in the patch directory as well, causing
"git send-email" to compose and send a crap mail using wired addresses.
Sorry again for the noise. Will remember next time.

Wolfgang.