[U-Boot] [PATCH 1/5] 8xxx: Add 'ecc' command

[U-Boot] [PATCH 1/5] 8xxx: Add 'ecc' command

[Peter Tyser]

Add a new 'ecc' command to interact with the 85xx and 86xx DDR ECC
registers.  The 'ecc' command can inject data/ECC errors to simulate
errors and provides an 'info' subcommand which displays ECC error
information such as failure address, read vs expected data/ECC,
physical signal which failed, single-bit error count, and multiple bit
error occurrence.  An example of the 'ecc info' command follows:

WARNING: ECC error in DDR Controller 0
        Addr:   0x0_01001000
        Data:   0x00000001_00000000     ECC:    0x00
        Expect: 0x00000000_00000000     ECC:    0x00
        Net:    DATA32
        Syndrome: 0xce
        Single-Bit errors: 0x40
        Attrib: 0x30112001
        Detect: 0x80000004 (MME, SBE)

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
---
This code was tested on a 8572, 8640, and P2020.  A board with a
32-bit data bus was not tested however.

 cpu/mpc8xxx/ddr/Makefile     |    2 +
 cpu/mpc8xxx/ddr/ecc.c        |  371 ++++++++++++++++++++++++++++++++++++++++++
 include/asm-ppc/immap_85xx.h |    4 +
 include/asm-ppc/immap_86xx.h |    3 +
 4 files changed, 380 insertions(+), 0 deletions(-)
 create mode 100644 cpu/mpc8xxx/ddr/ecc.c

diff --git a/cpu/mpc8xxx/ddr/Makefile b/cpu/mpc8xxx/ddr/Makefile
index cb7f856..f073779 100644
--- a/cpu/mpc8xxx/ddr/Makefile
+++ b/cpu/mpc8xxx/ddr/Makefile
@@ -22,6 +22,8 @@ COBJS-$(CONFIG_FSL_DDR3)	+= main.o util.o ctrl_regs.o options.o \
 				   lc_common_dimm_params.o
 COBJS-$(CONFIG_FSL_DDR3)	+= ddr3_dimm_params.o
 
+COBJS-$(CONFIG_DDR_ECC_CMD)	+= ecc.o
+
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
diff --git a/cpu/mpc8xxx/ddr/ecc.c b/cpu/mpc8xxx/ddr/ecc.c
new file mode 100644
index 0000000..bc80d7c
--- /dev/null
+++ b/cpu/mpc8xxx/ddr/ecc.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright 2009 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#if defined(CONFIG_MPC85xx)
+#include <mpc85xx.h>
+#elif defined(CONFIG_MPC86xx)
+#include <mpc86xx.h>
+#endif
+
+/* Provide a common define for DDR addresses on 85xx/86xx */
+#if defined(CONFIG_MPC85xx)
+#define MPC8xxx_DDR_ADDR	CONFIG_SYS_MPC85xx_DDR_ADDR
+#define MPC8xxx_DDR2_ADDR	CONFIG_SYS_MPC85xx_DDR2_ADDR
+#elif defined(CONFIG_MPC86xx)
+#define MPC8xxx_DDR_ADDR	CONFIG_SYS_MPC86xx_DDR_ADDR
+#define MPC8xxx_DDR2_ADDR	CONFIG_SYS_MPC86xx_DDR2_ADDR
+#else
+#error "ECC not supported on this platform"
+#endif
+
+/*
+ * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
+ * MPC8572 User's Manual.  Each line represents a syndrome bit column as a
+ * 64-bit value, but split into an upper and lower 32-bit chunk.  The labels
+ * below correspond to Freescale's manuals.
+ */
+static unsigned int ecc_table[16] = {
+	/* MSB           LSB */
+	/* [0:31]    [32:63] */
+	0xf00fe11e, 0xc33c0ff7,	/* Syndrome bit 7 */
+	0x00ff00ff, 0x00fff0ff,
+	0x0f0f0f0f, 0x0f0fff00,
+	0x11113333, 0x7777000f,
+	0x22224444, 0x8888222f,
+	0x44448888, 0xffff4441,
+	0x8888ffff, 0x11118882,
+	0xffff1111, 0x22221114,	/* Syndrome bit 0 */
+};
+
+/*
+ * Calculate the correct ECC value for a 64-bit integer specified by high:low
+ */
+static uint8_t calculate_ecc(uint32_t high, uint32_t low)
+{
+	uint32_t mask_low;
+	uint32_t mask_high;
+	int bit_cnt;
+	uint8_t ecc = 0;
+	int i;
+	int j;
+
+	for (i = 0; i < 8; i++) {
+		mask_high = ecc_table[i * 2];
+		mask_low = ecc_table[i * 2 + 1];
+		bit_cnt = 0;
+
+		for (j = 0; j < 32; j++) {
+			if ((mask_high >> j) & 1)
+				bit_cnt ^= (high >> j) & 1;
+			if ((mask_low >> j) & 1)
+				bit_cnt ^= (low >> j) & 1;
+		}
+
+		ecc |= bit_cnt << i;
+	}
+
+	return ecc;
+}
+
+/*
+ * Create the syndrome code which is generated if the data line specified by
+ * 'bit' failed.  Eg generate the 8-bit codes seen in Table 8-55 in the MPC8641
+ * User's Manual and 9-61 in the MPC8572 User's Manual.
+ */
+static uint8_t syndrome_from_bit(unsigned int bit) {
+	int i;
+	uint8_t syndrome = 0;
+
+	/*
+	 * Cycle through the upper or lower 32-bit portion of each value in
+	 * ecc_table depending on if 'bit' is in the upper or lower half of
+	 * 64-bit data.
+	 */
+	for (i = bit < 32; i < 16; i += 2)
+		syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
+
+	return syndrome;
+}
+
+/*
+ * Decode data and ecc syndrome to determine what went wrong
+ * Note: This can only decode single-bit errors
+ */
+static void ecc_decode(uint32_t data_hi, uint32_t data_lo, uint32_t ecc)
+{
+	int i;
+	int bad_data_bit = -1;
+	int bad_ecc_bit = -1;
+	uint8_t syndrome;
+
+	/*
+	 * Calculate the ECC of the captured data and XOR it with the captured
+	 * ECC to find an ECC syndrome value
+	 */
+	syndrome = calculate_ecc(data_hi, data_lo) ^ ecc;
+
+	/* Check if a data line is stuck... */
+	for (i = 0; i < 64; i++) {
+		if (syndrome == syndrome_from_bit(i)) {
+			/*
+			 * Save absolute position for printing out later.
+			 * Note that we are recording the bit failure address
+			 * with respect to the DRAM chips, not the CPU.  For
+			 * example, if the least significant data bit fails,
+			 * we print out that DATA0 failed, not DATA63 which is
+			 * how the CPU pinout is labeled.
+			 */
+			bad_data_bit = i;
+			break;
+		}
+	}
+
+	/* If data is correct, check ECC bits for errors... */
+	if (bad_data_bit == -1) {
+		for (i = 0; i < 8; i++) {
+			/*
+			 * Note that we are recording the bit failure address
+			 * with respect to the DRAM chips, not the CPU.  For
+			 * example, if the least significant ECC bit fails,
+			 * we print out that ECC0 failed, not ECC7 which is
+			 * how the CPU pinout is labeled.  See Table 9-62 in
+			 * the MPC8572 user's manual for additional details.
+			 */
+			if ((syndrome >> i) & 0x1) {
+				bad_ecc_bit = i;
+				break;
+			}
+		}
+	}
+
+	/* Print expected data */
+	if (bad_data_bit != -1) {
+		data_hi ^= 1 << (bad_data_bit - 32),
+		data_lo ^= 1 << bad_data_bit;
+	}
+	printf("\tExpect:\t0x%08x_%08x", data_hi, data_lo);
+
+	/* Print expected ECC code */
+	if (bad_ecc_bit != -1)
+		ecc ^= (1 << bad_ecc_bit) & 0xff;
+	printf("\tECC:\t0x%02x\n", ecc);
+
+	/* Print data or ECC net which caused ECC error */
+	if (bad_ecc_bit != -1)
+		printf("\tNet:\tECC%d\n", bad_ecc_bit);
+	else
+		printf("\tNet:\tDATA%d\n", bad_data_bit);
+
+	printf("\tSyndrome: 0x%x\n", syndrome);
+}
+
+int ecc_count(void)
+{
+	int count = 0;
+	int i;
+	volatile ccsr_ddr_t* ddr[] = {
+		(void*)MPC8xxx_DDR_ADDR,
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+		(void*)MPC8xxx_DDR2_ADDR,
+#endif
+	};
+
+	for (i = 0; i < ARRAY_SIZE(ddr); i++) {
+		/* Add up single-bit errors */
+		count += in_be32(&ddr[i]->err_sbe) & 0xff;
+
+		/* Add 1 for a multiple-bit error */
+		if (in_be32(&ddr[i]->err_detect) & 0x8)
+			count++;
+	}
+
+	return count;
+}
+
+void ecc_info(void)
+{
+	int controller;
+	uint32_t data_hi;
+	uint32_t data_lo;
+	uint32_t ecc;
+	uint32_t err_detect;
+	uint32_t sbe;
+	uint32_t attributes;
+	uint32_t address;
+	uint32_t ext_address;
+	volatile ccsr_ddr_t* ddr[] = {
+		(void*)MPC8xxx_DDR_ADDR,
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+		(void*)MPC8xxx_DDR2_ADDR,
+#endif
+	};
+
+	for (controller = 0;
+	     controller < CONFIG_NUM_DDR_CONTROLLERS;
+	     controller ++) {
+		/* Check for a single or multiple-bit ECC error */
+		sbe = in_be32(&ddr[controller]->err_sbe) & 0xff;
+		err_detect = in_be32(&ddr[controller]->err_detect);
+		if (!sbe && !(err_detect & 0x8))
+			continue;
+
+		/* Read in the rest of the ECC error info */
+		data_hi = in_be32(&ddr[controller]->capture_data_hi);
+		data_lo = in_be32(&ddr[controller]->capture_data_lo),
+		ecc = in_be32(&ddr[controller]->capture_ecc) & 0xff;
+		attributes = in_be32(&ddr[controller]->capture_attributes);
+		address = in_be32(&ddr[controller]->capture_address);
+		ext_address = in_be32(&ddr[controller]->capture_ext_address) & 0xf;
+
+		printf("\nWARNING: ECC error in DDR Controller %d\n", controller);
+		printf("\tAddr:\t0x%01x_%08x\n", ext_address, address);
+		printf("\tData:\t0x%08x_%08x\tECC:\t0x%02x\n",
+			data_hi, data_lo, ecc);
+
+		if (err_detect & 0x8) {
+			printf("ERROR: Multiple-bit errors!!!\n");
+		} else if (sbe) {
+			/* Analyze which data or ecc line is the culprit. */
+			ecc_decode(data_hi, data_lo, ecc);
+		}
+
+		printf("\tSingle-Bit errors: 0x%02x\n", sbe);
+		printf("\tAttrib:\t0x%08x\n", attributes);
+		printf("\tDetect:\t0x%08x", err_detect);
+		if(err_detect)
+			printf(" (");
+		if(err_detect & 0x80000000)
+			printf("MME, ");
+		if(err_detect & 0x100)
+			printf("APE, ");
+		if(err_detect & 0x80)
+			printf("ACE, ");
+		if(err_detect & 0x8)
+			printf("MBE, ");
+		if(err_detect & 0x4)
+			printf("SBE, ");
+		if(err_detect & 0x1)
+			printf("MSE, ");
+		if(err_detect)
+			printf("\b\b)\n");
+
+		printf("\n");
+
+		/* Clear ECC error info and count */
+		out_be32(&ddr[controller]->err_detect,
+			in_be32(&ddr[controller]->err_detect));
+		out_be32(&ddr[controller]->err_sbe,
+			in_be32(&ddr[controller]->err_sbe) & ~0xff);
+	}
+}
+
+static int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	static uint controller = 0;
+	uint32_t ecc_mask = 0;
+	uint32_t mask;
+	int count;
+	volatile ccsr_ddr_t* ddr[] = {
+		(void*)MPC8xxx_DDR_ADDR,
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+		(void*)MPC8xxx_DDR2_ADDR,
+#endif
+	};
+
+	if (argc == 2) {
+		if (argv[1][0] == 'i') {
+			/* 'ecc info' */
+			count = ecc_count();
+			if (count) {
+				ecc_info();
+				return count;
+			}
+
+			printf("No ECC errors have occurred\n");
+
+			return 0;
+		} else if (argv[1][0] == 'c') {
+			/* 'ecc ctrl' */
+			printf("Active controller: %d\n", controller);
+			return 0;
+		}
+	} else if (argc == 3) {
+		if (argv[1][0] == 'c') {
+			/* 'ecc ctrl num' */
+			controller = simple_strtoul(argv[2], NULL, 16);
+			if (controller > (CONFIG_NUM_DDR_CONTROLLERS - 1)) {
+				printf("Invalid controller number\n");
+				controller = 0;
+				return 1;
+			}
+			return 0;
+		} else if ((argv[1][0] == 'i') && (argv[2][0] == 'o')) {
+			/* 'ecc inject off' */
+			out_be32(&ddr[controller]->ecc_err_inject, 0);
+			out_be32(&ddr[controller]->data_err_inject_lo, 0);
+			out_be32(&ddr[controller]->data_err_inject_hi, 0);
+			return 0;
+		}
+	} else if (argc == 4) {
+		/* 'ecc inject <high|low|ecc> mask'  */
+		mask = simple_strtoul(argv[3], NULL, 16);
+		switch (argv[2][0]) {
+		case 'h':
+			out_be32(&ddr[controller]->data_err_inject_hi, mask);
+			break;
+		case 'l':
+			out_be32(&ddr[controller]->data_err_inject_lo, mask);
+			break;
+		case 'e':
+			ecc_mask = mask & ECC_ERR_INJECT_EEIM;
+			break;
+		default:
+			cmd_usage(cmdtp);
+			return 1;
+		}
+
+		/* Enable error injection */
+		out_be32(&ddr[controller]->ecc_err_inject,
+			ecc_mask | ECC_ERR_INJECT_EIEN);
+		return 0;
+	}
+
+	cmd_usage(cmdtp);
+	return 1;
+}
+
+U_BOOT_CMD(ecc, 5, 0, do_ecc,
+	"support for DDR ECC features",
+	"info - print ECC information\n"
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+	"ecc ctrl [num]\n"
+	"\t-Set active controller to 'num', or display active controller\n"
+#endif
+	"ecc inject high <mask>\n"
+	"ecc inject low <mask>\n"
+	"ecc inject ecc <mask>\n"
+	"\t- XOR 'mask' with high/low data or ECC\n"
+	"ecc inject off\n"
+	"\t- disable error injection\n"
+);
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 4194295..b283986 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -167,6 +167,10 @@ typedef struct ccsr_ddr {
 	u32	data_err_inject_hi;	/* Data Path Err Injection Mask High */
 	u32	data_err_inject_lo;	/* Data Path Err Injection Mask Low */
 	u32	ecc_err_inject;		/* Data Path Err Injection Mask ECC */
+#define ECC_ERR_INJECT_APIEN	0x00010000	/* Address Parity Injection */
+#define ECC_ERR_INJECT_EMB	0x00000200	/* ECC Mirror Byte */
+#define ECC_ERR_INJECT_EIEN	0x00000100	/* Error Injection Enable */
+#define ECC_ERR_INJECT_EEIM	0x000000ff	/* ECC Erroe Injection Enable */
 	u8	res9[20];
 	u32	capture_data_hi;	/* Data Path Read Capture High */
 	u32	capture_data_lo;	/* Data Path Read Capture Low */
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index fdfc654..384912f 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -135,6 +135,9 @@ typedef struct ccsr_ddr {
 	uint	data_err_inject_hi;	/* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
 	uint	data_err_inject_lo;	/* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
 	uint	ecc_err_inject;		/* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
+#define ECC_ERR_INJECT_EMB	0x00000200	/* ECC Mirror Byte */
+#define ECC_ERR_INJECT_EIEN	0x00000100	/* Error Injection Enable */
+#define ECC_ERR_INJECT_EEIM	0x000000ff	/* ECC Erroe Injection Enable */
 	char	res12[20];
 	uint	capture_data_hi;	/* 0x2e20 - DDR Memory Data Path Read Capture High */
 	uint	capture_data_lo;	/* 0x2e24 - DDR Memory Data Path Read Capture Low */
-- 
1.6.2.1

[U-Boot] [PATCH 2/5] Add check for ECC errors during SDRAM POST and mtest

[Peter Tyser]

Add a CONFIG_CHECK_ECC_ERRORS define which causes the SDRAM POST and
mtest command to check for ECC errors during execution.

The 85xx and 86xx architectures currently support enabling
CONFIG_CHECK_ECC_ERRORS.  Other architectures/boards can use it if they
implement an ecc_count() and ecc_info() function.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
 common/cmd_mem.c         |   10 ++++++++++
 cpu/mpc8xxx/ddr/Makefile |    2 +-
 cpu/mpc8xxx/ddr/ecc.c    |    4 ++++
 include/common.h         |    6 ++++++
 post/drivers/memory.c    |    5 +++++
 5 files changed, 26 insertions(+), 1 deletions(-)

diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index a34b342..efedf79 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -691,6 +691,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		__FUNCTION__, __LINE__, start, end);
 
 	for (;;) {
+#ifdef CONFIG_CHECK_ECC_ERRORS
+		if (ecc_count())
+			ecc_info();
+#endif
+
 		if (ctrlc()) {
 			putc ('\n');
 			return 1;
@@ -917,6 +922,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #else /* The original, quickie test */
 	incr = 1;
 	for (;;) {
+#ifdef CONFIG_CHECK_ECC_ERRORS
+		if (ecc_count())
+			ecc_info();
+#endif
+
 		if (ctrlc()) {
 			putc ('\n');
 			return 1;
diff --git a/cpu/mpc8xxx/ddr/Makefile b/cpu/mpc8xxx/ddr/Makefile
index f073779..935d72a 100644
--- a/cpu/mpc8xxx/ddr/Makefile
+++ b/cpu/mpc8xxx/ddr/Makefile
@@ -22,7 +22,7 @@ COBJS-$(CONFIG_FSL_DDR3)	+= main.o util.o ctrl_regs.o options.o \
 				   lc_common_dimm_params.o
 COBJS-$(CONFIG_FSL_DDR3)	+= ddr3_dimm_params.o
 
-COBJS-$(CONFIG_DDR_ECC_CMD)	+= ecc.o
+COBJS-$(CONFIG_DDR_ECC)		+= ecc.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/cpu/mpc8xxx/ddr/ecc.c b/cpu/mpc8xxx/ddr/ecc.c
index bc80d7c..9db5cef 100644
--- a/cpu/mpc8xxx/ddr/ecc.c
+++ b/cpu/mpc8xxx/ddr/ecc.c
@@ -21,6 +21,7 @@
  */
 
 #include <common.h>
+#if (defined(CONFIG_DDR_ECC_CMD) || defined(CONFIG_CHECK_ECC_ERRORS))
 #include <asm/io.h>
 #if defined(CONFIG_MPC85xx)
 #include <mpc85xx.h>
@@ -279,7 +280,9 @@ void ecc_info(void)
 			in_be32(&ddr[controller]->err_sbe) & ~0xff);
 	}
 }
+#endif /* CONFIG_DDR_ECC_CMD || CONFIG_CHECK_ECC_ERRORS */
 
+#ifdef CONFIG_DDR_ECC_CMD
 static int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	static uint controller = 0;
@@ -369,3 +372,4 @@ U_BOOT_CMD(ecc, 5, 0, do_ecc,
 	"ecc inject off\n"
 	"\t- disable error injection\n"
 );
+#endif /* CONFIG_DDR_ECC_CMD */
diff --git a/include/common.h b/include/common.h
index 7df9afa..b9e0fb1 100644
--- a/include/common.h
+++ b/include/common.h
@@ -556,6 +556,12 @@ int	prt_8260_rsr  (void);
 int	prt_83xx_rsr  (void);
 #endif
 
+/* $(CPU)/ecc.c */
+#ifdef CONFIG_CHECK_ECC_ERRORS
+void ecc_info(void);
+int ecc_count(void);
+#endif
+
 /* $(CPU)/interrupts.c */
 int	interrupt_init	   (void);
 void	timer_interrupt	   (struct pt_regs *);
diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index 0062360..b8bbac5 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c
@@ -477,6 +477,11 @@ int memory_post_test (int flags)
 		}
 	}
 
+#ifdef CONFIG_CHECK_ECC_ERRORS
+	if (ecc_count())
+		printf("WARNING: %d ECC errors detected!!\n", ecc_count());
+#endif
+
 	return ret;
 }
 
-- 
1.6.2.1

[U-Boot] [PATCH 3/5] xes: Enable the 'ecc' command

[Peter Tyser]

Enable the 'ecc' command for XES's 85xx and 86xx boards.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
 include/configs/XPEDITE5170.h |    1 +
 include/configs/XPEDITE5200.h |    1 +
 include/configs/XPEDITE5370.h |    1 +
 3 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index 1a810e4..f7615db 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -62,6 +62,7 @@
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
 #define CONFIG_DDR_ECC
+#define CONFIG_DDR_ECC_CMD
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index 3f73780..bc28b61 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -59,6 +59,7 @@
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
 #define CONFIG_DDR_ECC
+#define CONFIG_DDR_ECC_CMD
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 26b798b..e24d1d3 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -63,6 +63,7 @@
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
 #define CONFIG_DDR_ECC
+#define CONFIG_DDR_ECC_CMD
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000 /* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-- 
1.6.2.1

[U-Boot] [PATCH 3/5] xes: Enable the 'ecc' command

[Wolfgang Denk]

Dear Kumar,

In message <1256258353-25589-3-git-send-email-ptyser@xes-inc.com> Peter Tyser wrote:
> Enable the 'ecc' command for XES's 85xx and 86xx boards.

What's the state of these three patches:

[PATCH 3/5] xes: Enable the 'ecc' command
[PATCH 4/5] xes: Enable memory POST
[PATCH 5/5] xes: Enable ECC error checks during SDRAM POST and mtest


See also

http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/70205/focus=70203
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/70205/focus=70204
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/70205/focus=70202


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Imagination is more important than knowledge.      -- Albert Einstein

[U-Boot] [PATCH 3/5] xes: Enable the 'ecc' command

[Peter Tyser]

On Mon, 2009-11-23 at 23:35 +0100, Wolfgang Denk wrote:
> Dear Kumar,
> 
> In message <1256258353-25589-3-git-send-email-ptyser@xes-inc.com> Peter Tyser wrote:
> > Enable the 'ecc' command for XES's 85xx and 86xx boards.
> 
> What's the state of these three patches:
> 
> [PATCH 3/5] xes: Enable the 'ecc' command
> [PATCH 4/5] xes: Enable memory POST
> [PATCH 5/5] xes: Enable ECC error checks during SDRAM POST and mtest
> 
> 
> See also
> 
> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/70205/focus=70203
> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/70205/focus=70204
> http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/70205/focus=70202

This series was resubmitted as v2 here:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/71317/focus=71323

There was some debate about the changes to the 83xx boards, but the
conversation died off.  The patches are still OK in my opinion.  If
others have suggestions I'd be happy to resubmit, otherwise hopefully
they get picked up as is.

Best,
Peter

[U-Boot] [PATCH 4/5] xes: Enable memory POST

[Peter Tyser]

Note that SPRG4 is used to store U-Boot's post 'word'.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
 board/xes/common/Makefile        |    1 +
 board/xes/common/fsl_8xxx_post.c |   36 ++++++++++++++++++++++++++++++++++++
 include/configs/XPEDITE5170.h    |    1 +
 include/configs/XPEDITE5200.h    |    1 +
 include/configs/XPEDITE5370.h    |    1 +
 5 files changed, 40 insertions(+), 0 deletions(-)
 create mode 100644 board/xes/common/fsl_8xxx_post.c

diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile
index d022831..b6297ed 100644
--- a/board/xes/common/Makefile
+++ b/board/xes/common/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_FSL_PCI_INIT)	+= fsl_8xxx_pci.o
 COBJS-$(CONFIG_MPC8572)		+= fsl_8xxx_clk.o
 COBJS-$(CONFIG_MPC86xx)		+= fsl_8xxx_clk.o
 COBJS-$(CONFIG_FSL_DDR2)	+= fsl_8xxx_ddr.o
+COBJS-$(CONFIG_HAS_POST)	+= fsl_8xxx_post.o
 COBJS-$(CONFIG_NAND_ACTL)	+= actl_nand.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
diff --git a/board/xes/common/fsl_8xxx_post.c b/board/xes/common/fsl_8xxx_post.c
new file mode 100644
index 0000000..179f970
--- /dev/null
+++ b/board/xes/common/fsl_8xxx_post.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2008 Extreme Engineering Solutions, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+int post_hotkeys_pressed(void) {
+	return 0;
+}
+
+void post_word_store(ulong a) {
+	mtspr(SPRG4, a);
+}
+
+ulong post_word_load(void) {
+	return mfspr(SPRG4);
+}
diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index f7615db..6967754 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -107,6 +107,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY)
 
 /*
  * Memory map
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index bc28b61..ca333b7 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -90,6 +90,7 @@
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY)
 
 /*
  * Memory map
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index e24d1d3..4a4b48f 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -101,6 +101,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_ALT_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		0x20000000
+#define CONFIG_POST			(CONFIG_SYS_POST_MEMORY)
 
 /*
  * Memory map
-- 
1.6.2.1

[U-Boot] [PATCH 5/5] xes: Enable ECC error checks during SDRAM POST and mtest

[Peter Tyser]

Enable ECC error checking on XES's 85xx and 86xx boards.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
 include/configs/XPEDITE5170.h |    1 +
 include/configs/XPEDITE5200.h |    1 +
 include/configs/XPEDITE5370.h |    1 +
 3 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h
index 6967754..2778c04 100644
--- a/include/configs/XPEDITE5170.h
+++ b/include/configs/XPEDITE5170.h
@@ -108,6 +108,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		0x20000000
 #define CONFIG_POST			(CONFIG_SYS_POST_MEMORY)
+#define CONFIG_CHECK_ECC_ERRORS		/* Check ECC count during POST/mtest */
 
 /*
  * Memory map
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index ca333b7..993b011 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -91,6 +91,7 @@
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		0x20000000
 #define CONFIG_POST			(CONFIG_SYS_POST_MEMORY)
+#define CONFIG_CHECK_ECC_ERRORS		/* Check ECC count during POST/mtest */
 
 /*
  * Memory map
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index 4a4b48f..c374605 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -102,6 +102,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_MEMTEST_START	0x10000000
 #define CONFIG_SYS_MEMTEST_END		0x20000000
 #define CONFIG_POST			(CONFIG_SYS_POST_MEMORY)
+#define CONFIG_CHECK_ECC_ERRORS		/* Check ECC count during POST/mtest */
 
 /*
  * Memory map
-- 
1.6.2.1

[U-Boot] [PATCH 1/5] 8xxx: Add 'ecc' command

[Kumar Gala]

On Oct 22, 2009, at 7:39 PM, Peter Tyser wrote:

> Add a new 'ecc' command to interact with the 85xx and 86xx DDR ECC
> registers.  The 'ecc' command can inject data/ECC errors to simulate
> errors and provides an 'info' subcommand which displays ECC error
> information such as failure address, read vs expected data/ECC,
> physical signal which failed, single-bit error count, and multiple bit
> error occurrence.  An example of the 'ecc info' command follows:
>
> WARNING: ECC error in DDR Controller 0
>        Addr:   0x0_01001000
>        Data:   0x00000001_00000000     ECC:    0x00
>        Expect: 0x00000000_00000000     ECC:    0x00
>        Net:    DATA32
>        Syndrome: 0xce
>        Single-Bit errors: 0x40
>        Attrib: 0x30112001
>        Detect: 0x80000004 (MME, SBE)
>
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
> ---
> This code was tested on a 8572, 8640, and P2020.  A board with a
> 32-bit data bus was not tested however.
>
> cpu/mpc8xxx/ddr/Makefile     |    2 +
> cpu/mpc8xxx/ddr/ecc.c        |  371 +++++++++++++++++++++++++++++++++ 
> +++++++++
> include/asm-ppc/immap_85xx.h |    4 +
> include/asm-ppc/immap_86xx.h |    3 +
> 4 files changed, 380 insertions(+), 0 deletions(-)
> create mode 100644 cpu/mpc8xxx/ddr/ecc.c
>
> diff --git a/cpu/mpc8xxx/ddr/Makefile b/cpu/mpc8xxx/ddr/Makefile
> index cb7f856..f073779 100644
> --- a/cpu/mpc8xxx/ddr/Makefile
> +++ b/cpu/mpc8xxx/ddr/Makefile
> @@ -22,6 +22,8 @@ COBJS-$(CONFIG_FSL_DDR3)	+= main.o util.o  
> ctrl_regs.o options.o \
> 				   lc_common_dimm_params.o
> COBJS-$(CONFIG_FSL_DDR3)	+= ddr3_dimm_params.o
>
> +COBJS-$(CONFIG_DDR_ECC_CMD)	+= ecc.o

Should this be CONFIG_FSL_DDR_ECC_CMD ?

> +
> SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
> OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

[U-Boot] [PATCH 1/5] 8xxx: Add 'ecc' command

[Peter Tyser]

Kumar Gala wrote:
> 
> On Oct 22, 2009, at 7:39 PM, Peter Tyser wrote:
> 
>> Add a new 'ecc' command to interact with the 85xx and 86xx DDR ECC
>> registers.  The 'ecc' command can inject data/ECC errors to simulate
>> errors and provides an 'info' subcommand which displays ECC error
>> information such as failure address, read vs expected data/ECC,
>> physical signal which failed, single-bit error count, and multiple bit
>> error occurrence.  An example of the 'ecc info' command follows:
>>
>> WARNING: ECC error in DDR Controller 0
>>        Addr:   0x0_01001000
>>        Data:   0x00000001_00000000     ECC:    0x00
>>        Expect: 0x00000000_00000000     ECC:    0x00
>>        Net:    DATA32
>>        Syndrome: 0xce
>>        Single-Bit errors: 0x40
>>        Attrib: 0x30112001
>>        Detect: 0x80000004 (MME, SBE)
>>
>> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
>> Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
>> ---
>> This code was tested on a 8572, 8640, and P2020.  A board with a
>> 32-bit data bus was not tested however.
>>
>> cpu/mpc8xxx/ddr/Makefile     |    2 +
>> cpu/mpc8xxx/ddr/ecc.c        |  371 
>> ++++++++++++++++++++++++++++++++++++++++++
>> include/asm-ppc/immap_85xx.h |    4 +
>> include/asm-ppc/immap_86xx.h |    3 +
>> 4 files changed, 380 insertions(+), 0 deletions(-)
>> create mode 100644 cpu/mpc8xxx/ddr/ecc.c
>>
>> diff --git a/cpu/mpc8xxx/ddr/Makefile b/cpu/mpc8xxx/ddr/Makefile
>> index cb7f856..f073779 100644
>> --- a/cpu/mpc8xxx/ddr/Makefile
>> +++ b/cpu/mpc8xxx/ddr/Makefile
>> @@ -22,6 +22,8 @@ COBJS-$(CONFIG_FSL_DDR3)    += main.o util.o 
>> ctrl_regs.o options.o \
>>                    lc_common_dimm_params.o
>> COBJS-$(CONFIG_FSL_DDR3)    += ddr3_dimm_params.o
>>
>> +COBJS-$(CONFIG_DDR_ECC_CMD)    += ecc.o
> 
> Should this be CONFIG_FSL_DDR_ECC_CMD ?

I leaned towards CONFIG_DDR_ECC_CMD to prevent polluting the CONFIG_ 
namespace.  We could add a new CONFIG_FSL_DDR_ECC_CMD, 
CONFIG_AVR32_DDR_ECC_CMD, etc, but I think (CONFIG_MPC85xx + 
CONFIG_DDR_ECC_CMD), (CONFIG_AVR32 + CONFIG_DDR_ECC_CMD), etc 
accomplishes the same thing, but only adds 1 new CONFIG_DDR_ECC_CMD 
config option.  Doesn't really matter to me either way though...

Peter

[U-Boot] [PATCH 1/5] 8xxx: Add 'ecc' command

[Wolfgang Denk]

Dear Peter Tyser,

In message <1256258353-25589-1-git-send-email-ptyser@xes-inc.com> you wrote:
> Add a new 'ecc' command to interact with the 85xx and 86xx DDR ECC
> registers.  The 'ecc' command can inject data/ECC errors to simulate
> errors and provides an 'info' subcommand which displays ECC error
> information such as failure address, read vs expected data/ECC,
> physical signal which failed, single-bit error count, and multiple bit
> error occurrence.  An example of the 'ecc info' command follows:

We already have similar commands for other architectures, see for
example cpu/mpc83xx/ecc.c

I'm not sure if it's possible to use a common implementation, but I
would like to ask you to check if this is possible.

In any case I ask that we use a common user interface for both
implementations. It makes no sense that the same command name behaves
differently on different boards (even from the same vendor).

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"...one of the main causes of the fall of the Roman Empire was  that,
lacking  zero,  they had no way to indicate successful termination of
their C programs."                                     - Robert Firth

[U-Boot] [PATCH 1/5] 8xxx: Add 'ecc' command

[Peter Tyser]

Hi Wolfgang,

> In message <1256258353-25589-1-git-send-email-ptyser@xes-inc.com> you wrote:
>> Add a new 'ecc' command to interact with the 85xx and 86xx DDR ECC
>> registers.  The 'ecc' command can inject data/ECC errors to simulate
>> errors and provides an 'info' subcommand which displays ECC error
>> information such as failure address, read vs expected data/ECC,
>> physical signal which failed, single-bit error count, and multiple bit
>> error occurrence.  An example of the 'ecc info' command follows:
> 
> We already have similar commands for other architectures, see for
> example cpu/mpc83xx/ecc.c
> 
> I'm not sure if it's possible to use a common implementation, but I
> would like to ask you to check if this is possible.

83xx, 85xx, and 86xx could all share an implementation I believe. I 
didn't integrate the 83xx in this patch because it seemed to have a 
different "goal" than the patch I submitted.  The 83xx implementation 
supported a high degree of tweaking registers which I personally find 
unnecessary for general use.  I think that if someone wants that level 
of control, they could just modify the registers directly since they 
have to have the 83xx user's manual handy anyway.

The implementation I submitted has limited, common features and much 
better error reporting.  The error reporting is the feature that would 
be used 98% of the time, not the tweaking of registers.  I'd be happy to 
include the 83xx implementation in this patch, but I'd vote to strip out 
most of the current 83xx features - ie basically remove the 83xx ecc 
code and replace it with the  85/86xx implementation I submitted.  Would 
83xx people be OK with this?  Or have any suggestions on what the 
combined implementation should look like?

> In any case I ask that we use a common user interface for both
> implementations. It makes no sense that the same command name behaves
> differently on different boards (even from the same vendor).

I see your point.  As far as a common implementation, what did you have 
in mind?  Are you referring to only consolidating the 83xx/85xx/86xx 
implementations?  I'm fine with that, but don't think you could expand 
the "common interface" much past them as ECC reporting/injection 
features vary greatly from architecture to architecture.

Best,
Peter

[U-Boot] [PATCH 1/5] 8xxx: Add 'ecc' command

[Wolfgang Denk]

Dear Peter,

In message <4AE371E7.3000209@xes-inc.com> you wrote:
> 
> 83xx, 85xx, and 86xx could all share an implementation I believe. I 
> didn't integrate the 83xx in this patch because it seemed to have a 
> different "goal" than the patch I submitted.  The 83xx implementation 
> supported a high degree of tweaking registers which I personally find 
> unnecessary for general use.  I think that if someone wants that level 
> of control, they could just modify the registers directly since they 
> have to have the 83xx user's manual handy anyway.

Agreed.

> The implementation I submitted has limited, common features and much 
> better error reporting.  The error reporting is the feature that would 
> be used 98% of the time, not the tweaking of registers.  I'd be happy to 
> include the 83xx implementation in this patch, but I'd vote to strip out 
> most of the current 83xx features - ie basically remove the 83xx ecc 
> code and replace it with the  85/86xx implementation I submitted.  Would 
> 83xx people be OK with this?  Or have any suggestions on what the 
> combined implementation should look like?

I have yet to see a user who actually uses the existing code on 83xx,
so as far as I am concerned I'll be fine with the common, simpler
code.

> I see your point.  As far as a common implementation, what did you have 
> in mind?  Are you referring to only consolidating the 83xx/85xx/86xx 
> implementations?  I'm fine with that, but don't think you could expand 
> the "common interface" much past them as ECC reporting/injection 
> features vary greatly from architecture to architecture.

So far, this only affexts 8xxx, and having consistent code ther eis
good enough for me now. We may want to check this again when other
architectures raise their concerns and formulate their needs, but this
is then.

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Of all the things I've lost, I miss my mind the most.

[U-Boot] [PATCH 1/5] 8xxx: Add 'ecc' command

[Peter Tyser]

> In message <4AE371E7.3000209@xes-inc.com> you wrote:
>> 83xx, 85xx, and 86xx could all share an implementation I believe. I 
>> didn't integrate the 83xx in this patch because it seemed to have a 
>> different "goal" than the patch I submitted.  The 83xx implementation 
>> supported a high degree of tweaking registers which I personally find 
>> unnecessary for general use.  I think that if someone wants that level 
>> of control, they could just modify the registers directly since they 
>> have to have the 83xx user's manual handy anyway.
> 
> Agreed.
> 
>> The implementation I submitted has limited, common features and much 
>> better error reporting.  The error reporting is the feature that would 
>> be used 98% of the time, not the tweaking of registers.  I'd be happy to 
>> include the 83xx implementation in this patch, but I'd vote to strip out 
>> most of the current 83xx features - ie basically remove the 83xx ecc 
>> code and replace it with the  85/86xx implementation I submitted.  Would 
>> 83xx people be OK with this?  Or have any suggestions on what the 
>> combined implementation should look like?
> 
> I have yet to see a user who actually uses the existing code on 83xx,
> so as far as I am concerned I'll be fine with the common, simpler
> code.
> 
>> I see your point.  As far as a common implementation, what did you have 
>> in mind?  Are you referring to only consolidating the 83xx/85xx/86xx 
>> implementations?  I'm fine with that, but don't think you could expand 
>> the "common interface" much past them as ECC reporting/injection 
>> features vary greatly from architecture to architecture.
> 
> So far, this only affexts 8xxx, and having consistent code ther eis
> good enough for me now. We may want to check this again when other
> architectures raise their concerns and formulate their needs, but this
> is then.

Sounds good.  I'll rework and resubmit.

Best,
Peter