[U-Boot] [PATCH] samsung: move DRAM parameters

["\"Seunghyeon Rhee (이승현)\"" <seunghyeon@lpmtec.com>]

Move the definitions of DRAM parameters from SoC description
(s3c6400.h) to board description (smdk6400.h). DRAM parameters
are rather board-specific than SoC specific. According to the
current source, one may have to change the definitions in
s3c6400.h in addition to creating the new board description
whenever he wants to add support for a new board based on
s3c6400. I don't think this meets the U-Boot policy of
separating SoC description and board description.
There will be no observable changes in operation. It's just
to make it easier to add support for new boards.

Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
---
 include/configs/smdk6400.h |   21 +++++++++++++++++++++
 include/s3c6400.h          |   21 ---------------------
 2 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index f6e1221..a2b46fd 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -309,4 +309,25 @@
 # error "usb_ohci.c is currently broken with MMU enabled."
 #endif
 
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define DMC1_MEM_CFG	0x80010012	/* Chip1, Burst4, Row/Column bit */
+#define DMC1_MEM_CFG2	0xB45
+#define DMC1_CHIP0_CFG	0x150F8		/* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
+#define DMC_DDR_32_CFG	0x0 		/* 32bit, DDR */
+
+/* Memory Parameters */
+/* DDR Parameters */
+#define DDR_tREFRESH		7800	/* ns */
+#define DDR_tRAS		45	/* ns (min: 45ns)*/
+#define DDR_tRC 		68	/* ns (min: 67.5ns)*/
+#define DDR_tRCD		23	/* ns (min: 22.5ns)*/
+#define DDR_tRFC		80	/* ns (min: 80ns)*/
+#define DDR_tRP 		23	/* ns (min: 22.5ns)*/
+#define DDR_tRRD		15	/* ns (min: 15ns)*/
+#define DDR_tWR 		15	/* ns (min: 15ns)*/
+#define DDR_tXSR		120	/* ns (min: 120ns)*/
+#define DDR_CASL		3	/* CAS Latency 3 */
+
 #endif	/* __CONFIG_H */
diff --git a/include/s3c6400.h b/include/s3c6400.h
index e527c08..34d0d15 100644
--- a/include/s3c6400.h
+++ b/include/s3c6400.h
@@ -814,27 +814,6 @@
 #endif
 
 
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define DMC1_MEM_CFG	0x80010012	/* Chip1, Burst4, Row/Column bit */
-#define DMC1_MEM_CFG2	0xB45
-#define DMC1_CHIP0_CFG	0x150F8		/* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
-#define DMC_DDR_32_CFG	0x0 		/* 32bit, DDR */
-
-/* Memory Parameters */
-/* DDR Parameters */
-#define DDR_tREFRESH		7800	/* ns */
-#define DDR_tRAS		45	/* ns (min: 45ns)*/
-#define DDR_tRC 		68	/* ns (min: 67.5ns)*/
-#define DDR_tRCD		23	/* ns (min: 22.5ns)*/
-#define DDR_tRFC		80	/* ns (min: 80ns)*/
-#define DDR_tRP 		23	/* ns (min: 22.5ns)*/
-#define DDR_tRRD		15	/* ns (min: 15ns)*/
-#define DDR_tWR 		15	/* ns (min: 15ns)*/
-#define DDR_tXSR		120	/* ns (min: 120ns)*/
-#define DDR_CASL		3	/* CAS Latency 3 */
-
 /*
  * mDDR memory configuration
  */
-- 
1.6.2.5


-- 
Seunghyeon Rhee, Ph.D. / Director
LPM Technology Inc.
T +82-70-8255-6007  F +82-2-6442-6462
M +82-10-2790-0657