[U-Boot] [PATCH] Initial support for Orion5x SoC and EDMini board

* [U-Boot] [PATCH] Initial support for Orion5x SoC and EDMini board
@ 2009-11-14  1:01 Albert Aribaud
  2009-11-14  2:21 ` Tom
  2009-11-14  6:29 ` Prafulla Wadaskar
  0 siblings, 2 replies; 6+ messages in thread
From: Albert Aribaud @ 2009-11-14  1:01 UTC (permalink / raw)
  To: u-boot

This patch adds initial u-boot support for the Marvell orion5x
SoC and the LAcie ED Mini V2 board--support is limited to serial,
flash and environment. Further support will be added as devices
common with kirkwood are made useable across SoCs.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
---
 Makefile                               |    3 +
 board/Marvell/edminiv2/Makefile        |   51 +++++
 board/Marvell/edminiv2/config.mk       |   25 +++
 board/Marvell/edminiv2/edminiv2.c      |  165 ++++++++++++++++
 board/Marvell/edminiv2/edminiv2.h      |   39 ++++
 cpu/arm926ejs/orion5x/Makefile         |   52 +++++
 cpu/arm926ejs/orion5x/cpu.c            |  339 ++++++++++++++++++++++++++++++++
 cpu/arm926ejs/orion5x/dram.c           |   61 ++++++
 cpu/arm926ejs/orion5x/mpp.c            |   88 ++++++++
 cpu/arm926ejs/orion5x/timer.c          |  171 ++++++++++++++++
 drivers/serial/serial.c                |    3 +
 include/asm-arm/arch-orion5x/88f5182.h |   40 ++++
 include/asm-arm/arch-orion5x/cpu.h     |  213 ++++++++++++++++++++
 include/asm-arm/arch-orion5x/gpio.h    |   53 +++++
 include/asm-arm/arch-orion5x/mpp.h     |  122 ++++++++++++
 include/asm-arm/arch-orion5x/orion5x.h |   67 +++++++
 include/configs/edminiv2.h             |  158 +++++++++++++++
 17 files changed, 1650 insertions(+), 0 deletions(-)
 create mode 100644 board/Marvell/edminiv2/Makefile
 create mode 100644 board/Marvell/edminiv2/config.mk
 create mode 100644 board/Marvell/edminiv2/edminiv2.c
 create mode 100644 board/Marvell/edminiv2/edminiv2.h
 create mode 100644 cpu/arm926ejs/orion5x/Makefile
 create mode 100644 cpu/arm926ejs/orion5x/cpu.c
 create mode 100644 cpu/arm926ejs/orion5x/dram.c
 create mode 100644 cpu/arm926ejs/orion5x/mpp.c
 create mode 100644 cpu/arm926ejs/orion5x/timer.c
 create mode 100644 include/asm-arm/arch-orion5x/88f5182.h
 create mode 100644 include/asm-arm/arch-orion5x/cpu.h
 create mode 100644 include/asm-arm/arch-orion5x/gpio.h
 create mode 100644 include/asm-arm/arch-orion5x/mpp.h
 create mode 100644 include/asm-arm/arch-orion5x/orion5x.h
 create mode 100644 include/configs/edminiv2.h

diff --git a/Makefile b/Makefile
index bcb3fe9..60f9140 100644
--- a/Makefile
+++ b/Makefile
@@ -2951,6 +2951,9 @@ davinci_dm365evm_config :	unconfig
 davinci_dm6467evm_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci
 
+edminiv2_config: unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell orion5x
+
 imx27lite_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
 
diff --git a/board/Marvell/edminiv2/Makefile b/board/Marvell/edminiv2/Makefile
new file mode 100644
index 0000000..2e6d305
--- /dev/null
+++ b/board/Marvell/edminiv2/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= edminiv2.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/edminiv2/config.mk b/board/Marvell/edminiv2/config.mk
new file mode 100644
index 0000000..a4ea769
--- /dev/null
+++ b/board/Marvell/edminiv2/config.mk
@@ -0,0 +1,25 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x00600000
diff --git a/board/Marvell/edminiv2/edminiv2.c b/board/Marvell/edminiv2/edminiv2.c
new file mode 100644
index 0000000..f23de0e
--- /dev/null
+++ b/board/Marvell/edminiv2/edminiv2.c
@@ -0,0 +1,165 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/orion5x.h>
+#include <asm/arch/mpp.h>
+#include "edminiv2.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+{
+	int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
+	int sect;
+
+	if (base != CONFIG_SYS_FLASH_BASE)
+		return 0;
+
+	info->size = 0;
+	info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	for (sect=0; sect<CONFIG_SYS_MAX_FLASH_SECT; sect++) {
+		info->start[sect] = base+info->size;
+		info->size += sectsz[sect];
+	}
+	info->flash_id			= 0x01000000;
+	info->portwidth = FLASH_CFI_8BIT;
+	info->chipwidth = FLASH_CFI_BY8;
+	info->buffer_size = 32;
+	info->erase_blk_tout = 16384;
+	info->write_tout = 2;
+	info->buffer_write_tout = 5;
+	info->vendor = CFI_CMDSET_AMD_LEGACY;
+	info->cmd_reset= 0xF0;
+	info->interface= FLASH_CFI_X8;
+	info->legacy_unlock = 0;
+	info->manufacturer_id = 0xC2;
+	info->device_id = 0xBA;
+	info->device_id2= 0;
+
+	info->ext_addr = 0;
+	info->cfi_version = 0x3133;
+	info->cfi_offset = 0x0000;
+	info->addr_unlock1 = 0x00000555;
+	info->addr_unlock2 = 0x000002AA;
+	info->name = "MX29LV400CB";
+
+	return 1;
+}
+#endif				/* CONFIG_SYS_FLASH_CFI */
+
+int board_init(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	orion5x_config_gpio(EDMINIV2_OE_VAL_LOW, EDMINIV2_OE_LOW);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 edminiv2_mpp_config[] = {
+		MPP0_GPIO,
+		MPP1_GPIO,
+		MPP2_GPIO,
+		MPP3_GPIO,
+		MPP4_GPIO,
+		MPP5_GPIO,
+		MPP6_GPIO,
+		MPP7_GPIO,
+		MPP8_GPIO,
+		MPP9_GPIO,
+		MPP10_GPIO,
+		MPP11_GPIO,
+		MPP12_SATA0_PRESENTn,
+		MPP13_SATA1_PRESENTn,
+		MPP14_SATA0_ACTn,
+		MPP15_SATA1_ACTn,
+		MPP16_GPIO,
+		MPP17_GPIO,
+		MPP18_GPIO,
+		MPP19_GPIO,
+		0
+	};
+	orion5x_mpp_conf(edminiv2_mpp_config);
+
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = orion5x_sdram_bar(0) + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
+		gd->bd->bi_dram[i].size = orion5x_sdram_bs(i);
+	}
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__FUNCTION__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/edminiv2/edminiv2.h b/board/Marvell/edminiv2/edminiv2.h
new file mode 100644
index 0000000..77a108e
--- /dev/null
+++ b/board/Marvell/edminiv2/edminiv2.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __EDMINIV2_H
+#define __EDMINIV2_H
+
+#define EDMINIV2_OE_LOW		(~(0))
+#define EDMINIV2_OE_VAL_LOW		(1 << 29)	/* USB_PWEN low */
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __EDMINIV2_H */
diff --git a/cpu/arm926ejs/orion5x/Makefile b/cpu/arm926ejs/orion5x/Makefile
new file mode 100644
index 0000000..4b506a7
--- /dev/null
+++ b/cpu/arm926ejs/orion5x/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2009 Albert ARIBAUD <albrt.aribaud@free.fr>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS-y	= dram.o
+COBJS-y	+= cpu.o
+COBJS-y	+= mpp.o
+COBJS-y	+= timer.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm926ejs/orion5x/cpu.c b/cpu/arm926ejs/orion5x/cpu.c
new file mode 100644
index 0000000..50ca724
--- /dev/null
+++ b/cpu/arm926ejs/orion5x/cpu.c
@@ -0,0 +1,339 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/cache.h>
+#include <u-boot/md5.h>
+#include <asm/arch/orion5x.h>
+#include <hush.h>
+
+#define BUFLEN	16
+
+void reset_cpu(unsigned long ignored)
+{
+	struct orion5x_cpu_registers *cpureg =
+	    (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
+
+	writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
+		&cpureg->rstoutn_mask);
+	writel(readl(&cpureg->sys_soft_rst) | 1,
+		&cpureg->sys_soft_rst);
+	while (1) ;
+}
+
+/*
+ * Window Size
+ * Used with the Base register to set the address window size and location.
+ * Must be programmed from LSB to MSB as sequence of ones followed by
+ * sequence of zeros. The number of ones specifies the size of the window in
+ * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
+ * NOTE: A value of 0x0 specifies 64-KByte size.
+ */
+unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
+{
+	int i;
+	unsigned int j = 0;
+	u32 val = sizeval >> 1;
+
+	for (i = 0; val > 0x10000; i++) {
+		j |= (1 << i);
+		val = val >> 1;
+	}
+	return (0x0000ffff & j);
+}
+
+/*
+ * orion5x_config_adr_windows - Configure address Windows
+ *
+ * There are 8 address windows supported by Orion5x Soc to addess different
+ * devices. Each window can be configured for size, BAR and remap addr
+ * Below configuration is standard for most of the cases
+ *
+ * If remap function not used, remap_lo must be set as base
+ *
+ * Reference Documentation:
+ * Mbus-L to Mbus Bridge Registers Configuration.
+ * (Sec 25.1 and 25.3 of Datasheet)
+ */
+int orion5x_config_adr_windows(void)
+{
+	struct orion5x_win_registers *winregs =
+		(struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
+
+	/* Window 0: PCIE MEM address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM, ORION5X_TARGET_PCIE,
+		ORION5X_ATTR_PCIE_MEM, ORION5X_WIN_ENABLE), &winregs[0].ctrl);
+	writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base);
+	writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
+	writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
+
+	/* Window 1: PCIE IO address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO, ORION5X_TARGET_PCIE,
+		ORION5X_ATTR_PCIE_IO, ORION5X_WIN_ENABLE), &winregs[1].ctrl);
+	writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base);
+	writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
+	writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
+
+	/* Window 2: PCI MEM address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM, ORION5X_TARGET_PCI,
+		ORION5X_ATTR_PCI_MEM, ORION5X_WIN_ENABLE), &winregs[2].ctrl);
+	writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base);
+
+	/* Window 3: PCI IO address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO, ORION5X_TARGET_PCI,
+		ORION5X_ATTR_PCI_IO, ORION5X_WIN_ENABLE), &winregs[3].ctrl);
+	writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base);
+
+	/* Window 4: DEV_CS0 address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0, ORION5X_TARGET_DEVICE,
+		ORION5X_ATTR_DEV_CS0, ORION5X_WIN_ENABLE), &winregs[4].ctrl);
+	writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base);
+
+	/* Window 5: DEV_CS1 address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1, ORION5X_TARGET_DEVICE,
+		ORION5X_ATTR_DEV_CS1, ORION5X_WIN_ENABLE), &winregs[5].ctrl);
+	writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base);
+
+	/* Window 6: DEV_CS2 address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2, ORION5X_TARGET_DEVICE,
+		ORION5X_ATTR_DEV_CS2, ORION5X_WIN_ENABLE), &winregs[6].ctrl);
+	writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base);
+
+	/* Window 7: BOOT Memory address space */
+	writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM, ORION5X_TARGET_DEVICE,
+		ORION5X_ATTR_BOOTROM, ORION5X_WIN_ENABLE), &winregs[7].ctrl);
+	writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base);
+
+	return 0;
+}
+
+/*
+ * orion5x_config_gpio - GPIO configuration
+ */
+void orion5x_config_gpio(u32 gpp_oe_val, u32 gpp_oe)
+{
+	struct orion5x_gpio_registers *gpioreg =
+		(struct orion5x_gpio_registers *)ORION5X_GPIO_BASE;
+
+	/* Init GPIOS to default values as per board requirement */
+	writel(gpp_oe_val, &gpioreg->dout);
+	writel(gpp_oe, &gpioreg->oe);
+}
+
+/*
+ * orion5x_config_mpp - Multi-Purpose Pins Functionality configuration
+ *
+ * Each MPP can be configured to different functionality through
+ * MPP control register, ref (sec 6.1 of Orion5x h/w specification)
+ *
+ * There are maximum 64 Multi-Pourpose Pins on Orion5x
+ * Each MPP functionality can be configuration by a 4bit value
+ * of MPP control reg, the value and associated functionality depends
+ * upon used SoC varient
+ */
+int orion5x_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23)
+{
+	u32 *mppreg = (u32 *) ORION5X_MPP_BASE;
+
+	/* program mpp registers */
+	writel(mpp0_7, &mppreg[0]);
+	writel(mpp8_15, &mppreg[1]);
+	writel(mpp16_23, &mppreg[2]);
+	return 0;
+}
+
+/* Orion5x identification is done through PCIE space.
+ * As long as there is no Orion5x support for PCIE,
+ * We'll define the ID and revision PCIE registers
+ * here.
+ */
+#define PCIE_DEV_ID_OFF         (ORION5X_REG_PCIE_BASE + 0x0000)
+#define PCIE_DEV_REV_OFF        (ORION5X_REG_PCIE_BASE + 0x0008)
+u32 orion5x_device_id(void)
+{
+	return readl(PCIE_DEV_ID_OFF) >> 16;
+}
+
+u32 orion5x_device_rev(void)
+{
+	return readl(PCIE_DEV_REV_OFF) & 0xff;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+
+int print_cpuinfo(void)
+{
+	char dev_str[] = "0x0000";
+	char *dev_name = dev_str;
+	char rev_str[] = "0x00";
+	char *rev_name = rev_str;
+
+	u32 dev = orion5x_device_id();
+	u32 rev = orion5x_device_rev();
+
+	if (dev == MV88F5181_DEV_ID) {
+		dev_name = "MV88F5181";
+		if (rev == MV88F5181_REV_B1) {
+			rev_name = "B1";
+		} else if (rev == MV88F5181L_REV_A1) {
+			dev_name = "MV88F5181L";
+			rev_name = "A1";
+		} else if (rev == MV88F5181L_REV_A0) {
+			dev_name = "MV88F5181L";
+			rev_name = "A0";
+		} else {
+			sprintf(rev_str,"0x%02x", rev);
+		}
+	} else if (dev == MV88F5182_DEV_ID) {
+		dev_name = "MV88F5182";
+		if (rev == MV88F5182_REV_A2) {
+			rev_name = "A2";
+		} else {
+			sprintf(rev_str,"0x%02x", rev);
+		}
+	} else if (dev == MV88F5281_DEV_ID) {
+		dev_name = "MV88F5281";
+		if (rev == MV88F5281_REV_D2) {
+			rev_name = "D2";
+		} else if (rev == MV88F5281_REV_D1) {
+			rev_name = "D1";
+		} else if (rev == MV88F5281_REV_D0) {
+			rev_name = "D0";
+		} else {
+			sprintf(rev_str,"0x%02x", rev);
+		}
+	} else if (dev == MV88F6183_DEV_ID) {
+		dev_name = "MV88F6183";
+		if (rev == MV88F6183_REV_B0) {
+			rev_name = "B0";
+		} else {
+			sprintf(rev_str,"0x%02x", rev);
+		}
+	} else {
+		sprintf(dev_str,"0x%04x", rev);
+		sprintf(rev_str,"0x%02x", rev);
+	}
+
+	printf("SoC:   Orion5x %s-%s\n", dev_name, rev_name);
+
+	return 0;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+	struct orion5x_cpu_registers *cpureg =
+		(struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
+
+	/* Linux expects` the internal registers to be at 0xf1000000 */
+	writel(ORION5X_REGS_PHY_BASE, ORION5X_OFFSET_REG);
+
+	/* Enable and invalidate L2 cache in write through mode */
+	writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
+	invalidate_l2_cache();
+
+	orion5x_config_adr_windows();
+
+#ifdef CONFIG_ORION5X_RGMII_PAD_1V8
+	/*
+	 * Configures the I/O voltage of the pads connected to Egigabit
+	 * Ethernet interface to 1.8V
+	 * By defult it is set to 3.3V
+	 */
+	reg = readl(ORION5X_REG_MPP_OUT_DRV_REG);
+	reg |= (1 << 7);
+	writel(reg, ORION5X_REG_MPP_OUT_DRV_REG);
+#endif
+#ifdef CONFIG_ORION5X_EGIGA_INIT
+	/*
+	 * Set egiga port0/1 in normal functional mode
+	 * This is required becasue on Orion5x by default ports are in reset mode
+	 * OS egiga driver may not have provision to set them in normal mode
+	 * and if u-boot is build without network support, network may fail@OS level
+	 */
+	reg = readl(ORION5XGBE_PORT_SERIAL_CONTROL1_REG(0));
+	reg &= ~(1 << 4);	/* Clear PortReset Bit */
+	writel(reg, (ORION5XGBE_PORT_SERIAL_CONTROL1_REG(0)));
+	reg = readl(ORION5XGBE_PORT_SERIAL_CONTROL1_REG(1));
+	reg &= ~(1 << 4);	/* Clear PortReset Bit */
+	writel(reg, (ORION5XGBE_PORT_SERIAL_CONTROL1_REG(1)));
+#endif
+#ifdef CONFIG_ORION5X_PCIE_INIT
+	/*
+	 * Enable PCI Express Port0
+	 */
+	reg = readl(&cpureg->ctrl_stat);
+	reg |= (1 << 0);	/* Set PEX0En Bit */
+	writel(reg, &cpureg->ctrl_stat);
+#endif
+	return 0;
+}
+#endif /* CONFIG_ARCH_CPU_INIT */
+
+/*
+ * SOC specific misc init
+ */
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+	volatile u32 temp;
+
+	/*CPU streaming & write allocate */
+	temp = readfr_extra_feature_reg();
+	temp &= ~(1 << 28);	/* disable wr alloc */
+	writefr_extra_feature_reg(temp);
+
+	temp = readfr_extra_feature_reg();
+	temp &= ~(1 << 29);	/* streaming disabled */
+	writefr_extra_feature_reg(temp);
+
+	/* L2Cache settings */
+	temp = readfr_extra_feature_reg();
+	/* Disable L2C pre fetch - Set bit 24 */
+	temp |= (1 << 24);
+	/* enable L2C - Set bit 22 */
+	temp |= (1 << 22);
+	writefr_extra_feature_reg(temp);
+
+	icache_enable();
+	/* Change reset vector to address 0x0 */
+	temp = get_cr();
+	set_cr(temp & ~CR_V);
+
+	return 0;
+}
+#endif /* CONFIG_ARCH_MISC_INIT */
+
+#ifdef CONFIG_ORION5X_EGIGA
+int cpu_eth_init(bd_t *bis)
+{
+	orion5x_egiga_initialize(bis);
+	return 0;
+}
+#endif
diff --git a/cpu/arm926ejs/orion5x/dram.c b/cpu/arm926ejs/orion5x/dram.c
new file mode 100644
index 0000000..69aec26
--- /dev/null
+++ b/cpu/arm926ejs/orion5x/dram.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <config.h>
+#include <asm/arch/orion5x.h>
+
+#define ORION5X_REG_CPUCS_WIN_BAR(x)		(ORION5X_REGISTER(0x1500) + (x * 0x08))
+#define ORION5X_REG_CPUCS_WIN_SZ(x)		(ORION5X_REGISTER(0x1504) + (x * 0x08))
+/*
+ * orion5x_sdram_bar - reads SDRAM Base Address Register
+ */
+u32 orion5x_sdram_bar(enum memory_bank bank)
+{
+	u32 result = 0;
+	u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank));
+
+	if ((!enable) || (bank > BANK3))
+		return 0;
+
+	result = readl(ORION5X_REG_CPUCS_WIN_BAR(bank));
+	return result;
+}
+
+/*
+ * orion5x_sdram_bs - reads SDRAM Bank size
+ */
+u32 orion5x_sdram_bs(enum memory_bank bank)
+{
+	u32 result = 0;
+	u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank));
+
+	if ((!enable) || (bank > BANK3))
+		return 0;
+	result = 0xff000000 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank));
+	result += 0x01000000;
+	return result;
+}
diff --git a/cpu/arm926ejs/orion5x/mpp.c b/cpu/arm926ejs/orion5x/mpp.c
new file mode 100644
index 0000000..1b1e7fa
--- /dev/null
+++ b/cpu/arm926ejs/orion5x/mpp.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support
+ *
+ * arch/arm/mach-orion5x/mpp.c
+ *
+ * MPP functions for Marvell Kirorion5xood SoCs
+ * Referenced from Linux kernel source
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <common.h>
+#include <asm/arch/orion5x.h>
+#include <asm/arch/mpp.h>
+
+static u32 orion5x_variant(void)
+{
+        switch (orion5x_device_id()) {
+		case MV88F5181_DEV_ID:
+			return 0;
+		case MV88F5182_DEV_ID:
+			return MPP_F5182_MASK;
+		case MV88F5281_DEV_ID:
+			return MPP_F5281_MASK;
+		case MV88F6183_DEV_ID:
+			return 0;
+		default:
+	                debug("MPP setup: unknown Orion5x variant\n");
+	                return 0;
+	}
+}
+
+#define MPP_CTRL(i)	(ORION5X_MPP_BASE + (i* 4))
+#define MPP_NR_REGS	(1 + MPP_MAX/8)
+
+void orion5x_mpp_conf(u32 *mpp_list)
+{
+	u32 mpp_ctrl[MPP_NR_REGS];
+	unsigned int variant_mask;
+	int i;
+
+	variant_mask = orion5x_variant();
+	if (!variant_mask)
+		return;
+
+	debug( "initial MPP regs:");
+	for (i = 0; i < MPP_NR_REGS; i++) {
+		mpp_ctrl[i] = readl(MPP_CTRL(i));
+		debug(" %08x", mpp_ctrl[i]);
+	}
+	debug("\n");
+
+
+	while (*mpp_list) {
+		unsigned int num = MPP_NUM(*mpp_list);
+		unsigned int sel = MPP_SEL(*mpp_list);
+		int shift;
+
+		if (num > MPP_MAX) {
+			debug("orion5x_mpp_conf: invalid MPP "
+					"number (%u)\n", num);
+			continue;
+		}
+		if (!(*mpp_list & variant_mask)) {
+			debug("orion5x_mpp_conf: requested MPP%u config "
+				"unavailable on this hardware\n", num);
+			continue;
+		}
+
+		shift = (num & 7) << 2;
+		mpp_ctrl[num / 8] &= ~(0xf << shift);
+		mpp_ctrl[num / 8] |= sel << shift;
+
+		mpp_list++;
+	}
+
+	debug("  final MPP regs:");
+	for (i = 0; i < MPP_NR_REGS; i++) {
+		writel(mpp_ctrl[i], MPP_CTRL(i));
+		debug(" %08x", mpp_ctrl[i]);
+	}
+	debug("\n");
+
+}
diff --git a/cpu/arm926ejs/orion5x/timer.c b/cpu/arm926ejs/orion5x/timer.c
new file mode 100644
index 0000000..80fee75
--- /dev/null
+++ b/cpu/arm926ejs/orion5x/timer.c
@@ -0,0 +1,171 @@
+/*
+  * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * Copyright (C) Marvell International Ltd. and its affiliates
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/orion5x.h>
+
+#define UBOOT_CNTR	0	/* counter to use for uboot timer */
+
+/* Timer reload and current value registers */
+struct orion5x_tmr_val {
+	u32 reload;	/* Timer reload reg */
+	u32 val;	/* Timer value reg */
+};
+
+/* Timer registers */
+struct orion5x_tmr_registers {
+	u32 ctrl;	/* Timer control reg */
+	u32 pad[3];
+	struct orion5x_tmr_val tmr[2];
+	u32 wdt_reload;
+	u32 wdt_val;
+};
+
+struct orion5x_tmr_registers *orion5x_tmr_regs = (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
+
+/*
+ * ARM Timers Registers Map
+ */
+#define CNTMR_CTRL_REG			&orion5x_tmr_regs->ctrl
+#define CNTMR_RELOAD_REG(tmrnum)	&orion5x_tmr_regs->tmr[tmrnum].reload
+#define CNTMR_VAL_REG(tmrnum)		&orion5x_tmr_regs->tmr[tmrnum].val
+
+/*
+ * ARM Timers Control Register
+ * CPU_TIMERS_CTRL_REG (CTCR)
+ */
+#define CTCR_ARM_TIMER_EN_OFFS(cntr)	(cntr * 2)
+#define CTCR_ARM_TIMER_EN_MASK(cntr)	(1 << CTCR_ARM_TIMER_EN_OFFS)
+#define CTCR_ARM_TIMER_EN(cntr)		(1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+#define CTCR_ARM_TIMER_DIS(cntr)	(0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
+
+#define CTCR_ARM_TIMER_AUTO_OFFS(cntr)	((cntr * 2) + 1)
+#define CTCR_ARM_TIMER_AUTO_MASK(cntr)	(1 << 1)
+#define CTCR_ARM_TIMER_AUTO_EN(cntr)	(1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+#define CTCR_ARM_TIMER_AUTO_DIS(cntr)	(0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
+
+/*
+ * ARM Timer\Watchdog Reload Register
+ * CNTMR_RELOAD_REG (TRR)
+ */
+#define TRG_ARM_TIMER_REL_OFFS		0
+#define TRG_ARM_TIMER_REL_MASK		0xffffffff
+
+/*
+ * ARM Timer\Watchdog Register
+ * CNTMR_VAL_REG (TVRG)
+ */
+#define TVR_ARM_TIMER_OFFS		0
+#define TVR_ARM_TIMER_MASK		0xffffffff
+#define TVR_ARM_TIMER_MAX		0xffffffff
+#define TIMER_LOAD_VAL 			0xffffffff
+
+#define READ_TIMER			(readl(CNTMR_VAL_REG(UBOOT_CNTR)) /	\
+					 (CONFIG_SYS_TCLK / 1000))
+
+static ulong timestamp;
+static ulong lastdec;
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER;
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec +
+			(TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+void udelay(unsigned long usec)
+{
+	uint current;
+	ulong delayticks;
+
+	current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
+	delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
+
+	if (current < delayticks) {
+		delayticks -= current;
+		while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
+		while ((TIMER_LOAD_VAL - delayticks) <
+			readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
+	} else {
+		while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
+			(current - delayticks)) ;
+	}
+}
+
+/*
+ * init the counter
+ */
+int timer_init(void)
+{
+	unsigned int cntmrctrl;
+
+	/* load value into timer */
+	writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
+	writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
+
+	/* enable timer in auto reload mode */
+	cntmrctrl = readl(CNTMR_CTRL_REG);
+	cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
+	cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
+	writel(cntmrctrl, CNTMR_CTRL_REG);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index dd5f332..18686a2 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -30,6 +30,9 @@
 #ifdef CONFIG_KIRKWOOD
 #include <asm/arch/kirkwood.h>
 #endif
+#ifdef CONFIG_ORION5X
+#include <asm/arch/orion5x.h>
+#endif
 
 #if defined (CONFIG_SERIAL_MULTI)
 #include <serial.h>
diff --git a/include/asm-arm/arch-orion5x/88f5182.h b/include/asm-arm/arch-orion5x/88f5182.h
new file mode 100644
index 0000000..1dfdb24
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/88f5182.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood 88F6182 support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Feroceon CPU core 88F5182 SOC.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_88F5182_H
+#define _CONFIG_88F5182_H
+
+/* SOC specific definations */
+#define F88F5182_REGS_PHYS_BASE		0xf1000000
+#define ORION5X_REGS_PHY_BASE		F88F5182_REGS_PHYS_BASE
+
+/* TCLK Core Clock defination */
+#define CONFIG_SYS_TCLK			166000000 /* 166MHz */
+
+#endif /* _CONFIG_88F5182_H */
diff --git a/include/asm-arm/arch-orion5x/cpu.h b/include/asm-arm/arch-orion5x/cpu.h
new file mode 100644
index 0000000..7078d2e
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/cpu.h
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirorion5x_ood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ORION5X_CPU_H
+#define _ORION5X_CPU_H
+
+#include <asm/system.h>
+
+#ifndef __ASSEMBLY__
+
+#define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
+			| (attr << 8) | (orion5x_winctrl_calcsize(size) << 16))
+
+#define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x)	\
+		((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c)
+
+#define ORION5X_REG_DEVICE_ID		(ORION5X_MPP_BASE + 0x34)
+#define ORION5X_REG_SYSRST_CNT		(ORION5X_MPP_BASE + 0x50)
+#define SYSRST_CNT_1SEC_VAL		(25*1000000)
+#define ORION5X_REG_MPP_OUT_DRV_REG		(ORION5X_MPP_BASE + 0xE0)
+
+enum memory_bank {
+	BANK0,
+	BANK1,
+	BANK2,
+	BANK3
+};
+
+enum orion5x_cpu_winen {
+	ORION5X_WIN_DISABLE,
+	ORION5X_WIN_ENABLE
+};
+
+enum orion5x_cpu_target {
+	ORION5X_TARGET_DRAM = 0,
+	ORION5X_TARGET_DEVICE = 1,
+	ORION5X_TARGET_PCI = 3,
+	ORION5X_TARGET_PCIE = 4,
+	ORION5X_TARGET_SASRAM = 9
+};
+
+enum orion5x_cpu_attrib {
+	ORION5X_ATTR_DRAM_CS0 = 0x0e,
+	ORION5X_ATTR_DRAM_CS1 = 0x0d,
+	ORION5X_ATTR_DRAM_CS2 = 0x0b,
+	ORION5X_ATTR_DRAM_CS3 = 0x07,
+	ORION5X_ATTR_PCI_MEM = 0x59,
+	ORION5X_ATTR_PCI_IO = 0x51,
+	ORION5X_ATTR_PCIE_MEM = 0x59,
+	ORION5X_ATTR_PCIE_IO = 0x51,
+	ORION5X_ATTR_SASRAM = 0x00,
+	ORION5X_ATTR_DEV_CS0 = 0x1e,
+	ORION5X_ATTR_DEV_CS1 = 0x1d,
+	ORION5X_ATTR_DEV_CS2 = 0x1b,
+	ORION5X_ATTR_BOOTROM = 0x0f
+};
+
+/*
+ * Default Device Address MAP BAR values
+ */
+#define ORION5X_DEFADR_PCIE_MEM	0x90000000
+#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO	0x90000000
+#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI	0
+#define ORION5X_DEFSZ_PCIE_MEM	(128*1024*1024)
+
+#define ORION5X_DEFADR_PCIE_IO	0xf0000000
+#define ORION5X_DEFADR_PCIE_IO_REMAP_LO	0x90000000
+#define ORION5X_DEFADR_PCIE_IO_REMAP_HI	0
+#define ORION5X_DEFSZ_PCIE_IO	(64*1024)
+
+#define ORION5X_DEFADR_PCI_MEM	0x98000000
+#define ORION5X_DEFSZ_PCI_MEM	(128*1024*1024)
+
+#define ORION5X_DEFADR_PCI_IO	0xf0100000
+#define ORION5X_DEFSZ_PCI_IO	(64*1024)
+
+#define ORION5X_DEFADR_DEV_CS0	0xfa000000
+#define ORION5X_DEFSZ_DEV_CS0	(2*1024*1024)
+
+#define ORION5X_DEFADR_DEV_CS1	0xf8000000
+#define ORION5X_DEFSZ_DEV_CS1	(32*1024*1024)
+
+#define ORION5X_DEFADR_DEV_CS2	0xfa800000
+#define ORION5X_DEFSZ_DEV_CS2	(1*1024*1024)
+
+#define ORION5X_DEFADR_BOOTROM	0xFFF80000
+#define ORION5X_DEFSZ_BOOTROM	(512*1024)
+
+/* Constants for known devices and revisions
+ *
+ */
+
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
+#define MV88F5181_DEV_ID        0x5181
+#define MV88F5181_REV_B1        3
+#define MV88F5181L_REV_A0       8
+#define MV88F5181L_REV_A1       9
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID        0x5182
+#define MV88F5182_REV_A2        2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID        0x5281
+#define MV88F5281_REV_D0        4
+#define MV88F5281_REV_D1        5
+#define MV88F5281_REV_D2        6
+/* Orion-1-90 (88F6183) */
+#define MV88F6183_DEV_ID        0x6183
+#define MV88F6183_REV_B0        3
+
+/*
+ * read feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline unsigned int readfr_extra_feature_reg(void)
+{
+	unsigned int val;
+	asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
+			(val)::"cc");
+	return val;
+}
+
+/*
+ * write feroceon/sheeva core extra feature register
+ * using co-proc instruction
+ */
+static inline void writefr_extra_feature_reg(unsigned int val)
+{
+	asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
+			(val):"cc");
+	isb();
+}
+
+/*
+ * MBus-L to Mbus Bridge Registers
+ * Ref: Datasheet sec:A.3
+ */
+struct orion5x_win_registers {
+	u32 ctrl;
+	u32 base;
+	u32 remap_lo;
+	u32 remap_hi;
+};
+
+/*
+ * CPU control and status Registers
+ * Ref: Datasheet sec:A.3.2
+ */
+struct orion5x_cpu_registers {
+	u32 config;	/*0x20100 */
+	u32 ctrl_stat;	/*0x20104 */
+	u32 rstoutn_mask; /* 0x20108 */
+	u32 sys_soft_rst; /* 0x2010C */
+	u32 ahb_mbus_cause_irq; /* 0x20110 */
+	u32 ahb_mbus_mask_irq; /* 0x20114 */
+	u32 pad1[2];
+	u32 ftdll_config; /* 0x20120 */
+	u32 pad2;
+	u32 l2_cfg;	/* 0x20128 */
+};
+
+/*
+ * GPIO Registers
+ * Ref: Datasheet sec:A.19
+ */
+struct orion5x_gpio_registers {
+	u32 dout;
+	u32 oe;
+	u32 blink_en;
+	u32 din_pol;
+	u32 din;
+	u32 irq_cause;
+	u32 irq_mask;
+	u32 irq_level;
+};
+
+/*
+ * functions
+ */
+void reset_cpu(unsigned long ignored);
+u32 orion5x_device_id(void);
+u32 orion5x_device_rev(void);
+unsigned int orion5x_sdram_bar(enum memory_bank bank);
+unsigned int orion5x_sdram_bs(enum memory_bank bank);
+int orion5x_config_adr_windows(void);
+void orion5x_config_gpio(unsigned int gpp_oe_val, unsigned int gpp_oe);
+int orion5x_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, unsigned int mpp16_23);
+unsigned int orion5x_winctrl_calcsize(unsigned int sizeval);
+#endif /* __ASSEMBLY__ */
+#endif /* _ORION5X_CPU_H */
diff --git a/include/asm-arm/arch-orion5x/gpio.h b/include/asm-arm/arch-orion5x/gpio.h
new file mode 100644
index 0000000..40fe2e0
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/gpio.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on arch/asm-arm/mach-kirkwood/include/mach/gpio.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
+ * Removed kernel level irq handling. Took some macros from kernel to
+ * allow build.
+ *
+ * Dieter Kiermaier dk-arm-linux at gmx.de
+ */
+
+#ifndef __ORION5X_GPIO_H
+#define __ORION5X_GPIO_H
+
+/* got from kernel include/linux/bitops.h */
+#define BITS_PER_BYTE 8
+#define BITS_TO_LONGS(nr)	DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+
+#define GPIO_MAX		50
+#define GPIO_OFF(pin)		(((pin) >> 5) ? 0x0040 : 0x0000)
+#define GPIO_OUT(pin)		(ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
+#define GPIO_IO_CONF(pin)	(ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
+#define GPIO_BLINK_EN(pin)	(ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
+#define GPIO_IN_POL(pin)	(ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
+#define GPIO_DATA_IN(pin)	(ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
+#define GPIO_EDGE_CAUSE(pin)	(ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
+#define GPIO_EDGE_MASK(pin)	(ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
+#define GPIO_LEVEL_MASK(pin)	(ORION5X_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
+
+/*
+ * Kirorion5xood-specific GPIO API
+ */
+
+void orion5x_gpio_set_valid(unsigned pin, int mode);
+int orion5x_gpio_is_valid(unsigned pin, int mode);
+int orion5x_gpio_direction_input(unsigned pin);
+int orion5x_gpio_direction_output(unsigned pin, int value);
+int orion5x_gpio_get_value(unsigned pin);
+void orion5x_gpio_set_value(unsigned pin, int value);
+void orion5x_gpio_set_blink(unsigned pin, int blink);
+void orion5x_gpio_set_unused(unsigned pin);
+
+#define GPIO_INPUT_OK		(1 << 0)
+#define GPIO_OUTPUT_OK		(1 << 1)
+
+#endif
diff --git a/include/asm-arm/arch-orion5x/mpp.h b/include/asm-arm/arch-orion5x/mpp.h
new file mode 100644
index 0000000..a03eb8e
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/mpp.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * Copyright 2009: Marvell Technology Group Ltd.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ORION5X_MPP_H
+#define __ORION5X_MPP_H
+
+#define MPP(_num, _sel, _in, _out, _F5182, _F5281) ( \
+	/* MPP number */		((_num) & 0xff) | \
+	/* MPP select value */		(((_sel) & 0xf) << 8) | \
+	/* may be input signal */	((!!(_in)) << 12) | \
+	/* may be output signal */	((!!(_out)) << 13) | \
+	/* available on F5182 */	((!!(_F5182)) << 14) | \
+	/* available on F5281 */	((!!(_F5182)) << 15))
+
+#define MPP_NUM(x)	((x) & 0xff)
+#define MPP_SEL(x)	(((x) >> 8) & 0xf)
+
+					/*   num sel  i  o  5182 5281 */
+
+#define MPP_INPUT_MASK			MPP(  0, 0x0, 1, 0, 0,   0    )
+#define MPP_OUTPUT_MASK			MPP(  0, 0x0, 0, 1, 0,   0    )
+
+#define MPP_F5182_MASK			MPP(  0, 0x0, 0, 0, 1,   0    )
+#define MPP_F5281_MASK			MPP(  0, 0x0, 0, 0, 0,   1    )
+
+#define MPP0_PEX_RST_OUTn		MPP(  0, 0x0, 0, 1, 1,   1    )
+#define MPP0_PCI_REQ2n			MPP(  0, 0x2, 1, 0, 1,   1    )
+#define MPP0_GPIO			MPP(  0, 0x3, 1, 1, 1,   1    )
+
+#define MPP1_GPIO			MPP(  1, 0x0, 1, 1, 1,   1    )
+#define MPP1_PCI_GNT2n			MPP(  1, 0x2, 0, 1, 1,   1    )
+
+#define MPP2_GPIO			MPP(  2, 0x0, 1, 1, 1,   1    )
+#define MPP2_PCI_REQ3n			MPP(  2, 0x2, 1, 0, 1,   1    )
+#define MPP2_PMEn			MPP(  2, 0x3, 0, 1, 1,   1    )
+
+#define MPP3_GPIO			MPP(  3, 0x0, 1, 1, 1,   1    )
+#define MPP3_PCI_GNT3nO			MPP(  3, 0x2, 0, 1, 1,   1    )
+
+#define MPP4_GPIO			MPP(  4, 0x0, 1, 1, 1,   1    )
+#define MPP4_PCI_REQ4n			MPP(  4, 0x2, 1, 0, 1,   1    )
+#define MPP4_BOOT_NAND_FLASH_REn	MPP(  4, 0x4, 0, 0, 1,   1    )
+#define MPP4_SATA0_PRESENTn		MPP(  4, 0x5, 0, 1, 1,   0    )
+
+#define MPP5_GPIO			MPP(  5, 0x0, 1, 1, 1,   1    )
+#define MPP5_PCI_GNT4n			MPP(  5, 0x2, 0, 1, 1,   1    )
+#define MPP5_BOOT_NAND_FLASH_WEn	MPP(  5, 0x4, 0, 0, 1,   1    )
+#define MPP5_SATA1_PRESENTn		MPP(  5, 0x5, 0, 1, 1,   0    )
+
+#define MPP6_GPIO			MPP(  6, 0x0, 1, 1, 1,   1    )
+#define MPP6_PCI_REQ5n			MPP(  6, 0x2, 1, 0, 1,   1    )
+#define MPP6_NAND_FLASH_RE0n		MPP(  6, 0x4, 0, 0, 1,   1    )
+#define MPP6_SATA0_ACTn			MPP(  6, 0x5, 0, 1, 1,   0    )
+
+#define MPP7_GPIO			MPP(  7, 0x0, 1, 1, 1,   1    )
+#define MPP7_PCI_GNT5n			MPP(  7, 0x2, 0, 1, 1,   1    )
+#define MPP7_NAND_FLASH_WE0n		MPP(  7, 0x4, 0, 0, 1,   1    )
+#define MPP7_SATA1_ACTn			MPP(  7, 0x5, 0, 1, 1,   0    )
+
+#define MPP8_GPIO			MPP(  8, 0x0, 1, 1, 1,   1    )
+#define MPP8_GE_COL			MPP(  8, 0x1, 1, 0, 1,   1    )
+
+#define MPP9_GPIO			MPP(  9, 0x0, 1, 1, 1,   1    )
+#define MPP9_GE_RXERR			MPP(  9, 0x1, 1, 0, 1,   1    )
+
+#define MPP10_GPIO			MPP( 10, 0x0, 1, 1, 1,   1    )
+#define MPP10_GE_CRS			MPP( 10, 0x1, 1, 0, 1,   1    )
+
+#define MPP11_GPIO			MPP( 11, 0x0, 1, 1, 1,   1    )
+#define MPP11_GE_TXERR			MPP( 11, 0x1, 0, 1, 1,   1    )
+
+#define MPP12_GPIO			MPP( 12, 0x0, 1, 1, 1,   1    )
+#define MPP12_GE_TXD4			MPP( 12, 0x1, 0, 1, 1,   1    )
+#define MPP12_NAND_FLASH_RE1n		MPP( 12, 0x4, 1, 1, 1,   1    )
+#define MPP12_SATA0_PRESENTn		MPP( 12, 0x5, 0, 1, 1,   0    )
+
+#define MPP13_GPIO			MPP( 13, 0x0, 1, 1, 1,   1    )
+#define MPP13_GE_TXD5			MPP( 13, 0x1, 0, 1, 1,   1    )
+#define MPP13_NAND_FLASH_WE1n		MPP( 13, 0x4, 0, 1, 1,   1    )
+#define MPP13_SATA1_PRESENTn		MPP( 13, 0x5, 0, 1, 1,   0    )
+
+#define MPP14_GPIO			MPP( 14, 0x0, 1, 1, 1,   1    )
+#define MPP14_GE_TXD6			MPP( 14, 0x1, 0, 1, 1,   1    )
+#define MPP14_NAND_FLASH_RE2n		MPP( 14, 0x4, 1, 1, 1,   1    )
+#define MPP14_SATA0_ACTn		MPP( 14, 0x5, 0, 1, 1,   0    )
+
+#define MPP15_GPIO			MPP( 15, 0x0, 1, 1, 1,   1    )
+#define MPP15_GE_TXD7			MPP( 15, 0x1, 0, 1, 1,   1    )
+#define MPP15_NAND_FLASH_WE2n		MPP( 15, 0x4, 0, 1, 1,   1    )
+#define MPP15_SATA1_ACTn		MPP( 15, 0x5, 0, 1, 1,   0    )
+
+#define MPP16_UART1_RXD			MPP( 16, 0x0, 1, 0, 1,   1    )
+#define MPP16_GE_RXD4			MPP( 16, 0x1, 1, 0, 1,   1    )
+#define MPP16_BOOT_NAND_FLASH_REn	MPP( 16, 0x4, 0, 0, 1,   1    )
+#define MPP16_GPIO			MPP( 16, 0x5, 1, 1, 1,   0    )
+
+#define MPP17_UART1_TXD			MPP( 17, 0x0, 0, 1, 1,   1    )
+#define MPP17_GE_RXD5			MPP( 17, 0x1, 1, 0, 1,   1    )
+#define MPP17_BOOT_NAND_FLASH_WEn	MPP( 17, 0x4, 0, 0, 1,   1    )
+#define MPP17_GPIO			MPP( 17, 0x5, 1, 1, 1,   0    )
+
+#define MPP18_UART1_CTSn		MPP( 18, 0x0, 1, 0, 1,   1    )
+#define MPP18_GE_RXD6			MPP( 18, 0x1, 1, 0, 1,   1    )
+#define MPP18_GPIO			MPP( 18, 0x5, 1, 1, 1,   0    )
+
+#define MPP19_UART1_RTSn		MPP( 19, 0x0, 0, 1, 1,   1    )
+#define MPP19_GE_RXD7			MPP( 19, 0x1, 1, 0, 1,   1    )
+#define MPP19_GPIO			MPP( 19, 0x5, 1, 1, 1,   0    )
+
+#define MPP_MAX				19
+
+void orion5x_mpp_conf(unsigned int *mpp_list);
+
+#endif
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
new file mode 100644
index 0000000..76cb927
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/orion5x.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * Header file for Marvell's Orion SoC with Feroceon CPU core.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_ORION5X_H
+#define _ASM_ARCH_ORION5X_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif /* __ASSEMBLY__ */
+
+#if defined (CONFIG_FEROCEON)
+#include <asm/arch/cpu.h>
+
+/* SOC specific definations */
+#define INTREG_BASE				0xd0000000
+#define ORION5X_REGISTER(x)			(ORION5X_REGS_PHY_BASE + x)
+#define ORION5X_OFFSET_REG			(INTREG_BASE + 0x20080)
+
+/* Documented registers */
+#define ORION5X_TWSI_BASE			(ORION5X_REGISTER(0x11000))
+#define ORION5X_UART0_BASE			(ORION5X_REGISTER(0x12000))
+#define ORION5X_UART1_BASE			(ORION5X_REGISTER(0x12100))
+#define ORION5X_MPP_BASE			(ORION5X_REGISTER(0x10000))
+#define ORION5X_GPIO_BASE			(ORION5X_REGISTER(0x10100))
+#define ORION5X_CPU_WIN_BASE			(ORION5X_REGISTER(0x20000))
+#define ORION5X_CPU_REG_BASE			(ORION5X_REGISTER(0x20100))
+#define ORION5X_TIMER_BASE			(ORION5X_REGISTER(0x20300))
+#define ORION5X_REG_PCI_BASE			(ORION5X_REGISTER(0x30000))
+#define ORION5X_REG_PCIE_BASE			(ORION5X_REGISTER(0x40000))
+#define ORION5X_USB20_PORT0_BASE		(ORION5X_REGISTER(0x50000))
+#define ORION5X_USB20_PORT1_BASE		(ORION5X_REGISTER(0xA0000))
+#define ORION5X_EGIGA_BASE			(ORION5X_REGISTER(0x72000))
+
+#if defined (CONFIG_88F5182)
+#include <asm/arch/88f5182.h>
+#else
+#error "SOC Name not defined"
+#endif
+#endif /* CONFIG_FEROCEON */
+#endif /* _ASM_ARCH_ORION5X_H */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
new file mode 100644
index 0000000..a8036dd
--- /dev/null
+++ b/include/configs/edminiv2.h
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_EDMINIV2_H
+#define _CONFIG_EDMINIV2_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	" Lacie ED Mini V2"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL		1
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+#define CONFIG_FEROCEON		1	/* CPU Core subversion */
+#define CONFIG_ORION5X		1	/* SOC Family Name */
+#define CONFIG_88F5182		1	/* SOC Name */
+#define CONFIG_MACH_EDMINIV2	1	/* Machine type */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * CLKs configurations
+ */
+#define CONFIG_SYS_HZ		1000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		ORION5X_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/*Console on UART0 */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
+					  115200,230400, 460800, 921600 }
+/*
+ * FLASH configuration
+ */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_WIDTH      FLASH_CFI_8BIT
+#define CONFIG_FLASH_CFI_LEGACY
+
+//#define CONFIG_SYS_FLASH_LEGACY_512Kx8
+#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks       */
+#define CONFIG_SYS_MAX_FLASH_SECT       11      /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BASE           0xfff80000
+#define CONFIG_SYS_FLASH_SECTSZ {16384,8192,8192,32768,65536,65536,65536,65536,65536,65536,65536}
+
+/* auto boot */
+#define CONFIG_BOOTDELAY	3	/* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */
+
+#define	CONFIG_SYS_PROMPT	"Marvell>> "	/* Command Prompt */
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
+#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
+		+sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print Buff */
+/*
+ * Commands configuration
+ */
+/*
+ * Disabling many default commands for staggered bring-up
+ */
+#if 0
+#include <config_cmd_default.h>
+#else
+#define CONFIG_CMD_BDI          /* bdinfo                       */
+#define CONFIG_CMD_CONSOLE      /* coninfo                      */
+#define CONFIG_CMD_ECHO         /* echo arguments               */
+#define CONFIG_CMD_EDITENV      /* editenv                      */
+#define CONFIG_CMD_IMI          /* iminfo                       */
+#define CONFIG_CMD_ITEST        /* Integer (and string) test    */
+#define CONFIG_CMD_FLASH        /* flinfo, erase, protect       */
+#define CONFIG_CMD_IMLS         /* List all found images        */
+#define CONFIG_CMD_LOADB        /* loadb                        */
+#define CONFIG_CMD_LOADS        /* loads                        */
+#define CONFIG_CMD_MEMORY       /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC         /* Misc functions like sleep etc*/
+#define CONFIG_CMD_RUN          /* run command in env variable  */
+#define CONFIG_CMD_SAVEENV      /* saveenv                      */
+#define CONFIG_CMD_SOURCE       /* "source" command support     */
+#endif
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_ENV
+
+/*
+ *  Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SECT_SIZE		0x2000	/* 16K */
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		0x4000	/* env starts here */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
+#define CONFIG_ARCH_CPU_INIT	/* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT	/* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO	/* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS	4
+#define CONFIG_STACKSIZE	0x00100000	/* regular stack- 1M */
+#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
+#define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+
+#endif /* _CONFIG_EDMINIV2_H */
-- 
1.6.4.4

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