From: Scott Wood <scottwood@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] NAND: DaVinci: Update 4 bit ECC correction
Date: Tue, 01 Dec 2009 17:21:33 -0600 [thread overview]
Message-ID: <4B15A4FD.6000609@freescale.com> (raw)
In-Reply-To: <0554BEF07D437848AF01B9C9B5F0BC5D945E4806@dlee01.ent.ti.com>
Paulraj, Sandeep wrote:
>> Is it possible that there could be a race, whereby the hardware finishes
>> before you read NANDFSR for the first time, and thus you never see it be
>> greater than 3?
>
> There are other check conditions after this check condition in the driver.
> If we never see the concetned value greater than 3, that actually
> means that ECC calculation has finished or not required at all
> because there were no errors
And this patch will respond to that by hanging, waiting for a value
greater than 3.
-Scott
prev parent reply other threads:[~2009-12-01 23:21 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-12-01 22:24 [U-Boot] [PATCH] NAND: DaVinci: Update 4 bit ECC correction s-paulraj at ti.com
2009-12-01 22:53 ` Scott Wood
2009-12-01 23:08 ` Paulraj, Sandeep
2009-12-01 23:21 ` Scott Wood [this message]
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