From mboxrd@z Thu Jan 1 00:00:00 1970 From: Scott Wood Date: Tue, 01 Dec 2009 17:21:33 -0600 Subject: [U-Boot] [PATCH] NAND: DaVinci: Update 4 bit ECC correction In-Reply-To: <0554BEF07D437848AF01B9C9B5F0BC5D945E4806@dlee01.ent.ti.com> References: <1259706299-10213-1-git-send-email-s-paulraj@ti.com> <20091201225303.GA19467@loki.buserror.net> <0554BEF07D437848AF01B9C9B5F0BC5D945E4806@dlee01.ent.ti.com> Message-ID: <4B15A4FD.6000609@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Paulraj, Sandeep wrote: >> Is it possible that there could be a race, whereby the hardware finishes >> before you read NANDFSR for the first time, and thus you never see it be >> greater than 3? > > There are other check conditions after this check condition in the driver. > If we never see the concetned value greater than 3, that actually > means that ECC calculation has finished or not required at all > because there were no errors And this patch will respond to that by hanging, waiting for a value greater than 3. -Scott