[U-Boot] [PATCH 1/5] fdt: add fdt_del_node_by_path() API

[U-Boot] [PATCH 1/5] fdt: add fdt_del_node_by_path() API

[Li Yang]

For removing node easily by path or alias.

Signed-off-by: Li Yang <leoli@freescale.com>
---
 common/fdt_support.c  |   10 ++++++++++
 include/fdt_support.h |    1 +
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/common/fdt_support.c b/common/fdt_support.c
index f89a3ee..8f1186e 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -757,3 +757,13 @@ int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size)
 	return -1;
 }
 #endif
+
+int fdt_del_node_by_path(void *fdt, const char *path)
+{
+	int off = fdt_path_offset(fdt, path);
+
+	if (off >= 0)
+		return fdt_del_node(fdt, off);
+	else
+		return off;
+}
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 0a9dd0d..d0705d1 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -80,6 +80,7 @@ void set_working_fdt_addr(void *addr);
 int fdt_resize(void *blob);
 
 int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
+int fdt_del_node_by_path(void *fdt, const char *path);
 
 #endif /* ifdef CONFIG_OF_LIBFDT */
 #endif /* ifndef __FDT_SUPPORT_H */
-- 
1.6.4

[U-Boot] [PATCH 2/5] fsl_law: add SRIO2 target id and law_size_bits() macro

[Li Yang]

Signed-off-by: Li Yang <leoli@freescale.com>
---
 include/asm-ppc/fsl_law.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h
index 31bb754..34c56a2 100644
--- a/include/asm-ppc/fsl_law.h
+++ b/include/asm-ppc/fsl_law.h
@@ -46,6 +46,8 @@ enum law_size {
 	LAW_SIZE_32G,
 };
 
+#define law_size_bits(sz)	(__ilog2_u64(sz) - 1)
+
 #ifdef CONFIG_FSL_CORENET
 enum law_trgt_if {
 	LAW_TRGT_IF_PCIE_1 = 0x00,
@@ -78,6 +80,7 @@ enum law_trgt_if {
 	LAW_TRGT_IF_CCSR = 0x08,
 	LAW_TRGT_IF_DDR_INTRLV = 0x0b,
 	LAW_TRGT_IF_RIO = 0x0c,
+	LAW_TRGT_IF_RIO_2 = 0x0d,
 	LAW_TRGT_IF_DDR = 0x0f,
 	LAW_TRGT_IF_DDR_2 = 0x16,	/* 2nd controller */
 };
-- 
1.6.4

[U-Boot] [PATCH 3/5] 85xx: add common serdes ports configuration code

[Li Yang]

Add common board configuration code which uses serdes
configuration information gotten from common fsl_serdes
APIs to initialize peripheral ports like PCIE, SGMII and
SRIO.  Disable unused block when not configured.

Also update device trees to remove unused nodes to
prevent these devices/buses being initialized in kernel.

Signed-off-by: Li Yang <leoli@freescale.com>
---
 cpu/mpc85xx/Makefile         |    1 +
 cpu/mpc85xx/cpu_init.c       |   14 ++--
 cpu/mpc85xx/serdes.c         |  217 ++++++++++++++++++++++++++++++++++++++++++
 include/asm-ppc/fsl_serdes.h |   50 ++++++++++
 4 files changed, 275 insertions(+), 7 deletions(-)
 create mode 100644 cpu/mpc85xx/serdes.c

diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index 56de7eb..018ebc9 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -62,6 +62,7 @@ COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
 COBJS-$(CONFIG_PCI)	+= pci.o
 COBJS-$(CONFIG_QE)	+= qe_io.o
 COBJS-$(CONFIG_CPM2)	+= serial_scc.o
+COBJS-$(CONFIG_FSL_SERDES)	+= serdes.o
 
 COBJS	= $(COBJS-y)
 COBJS	+= cpu.o
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 0041a60..05133d3 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -33,14 +33,11 @@
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
 #include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_MPC8536
-extern void fsl_serdes_init(void);
-#endif
-
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -237,9 +234,7 @@ void cpu_init_f (void)
 	/* Config QE ioports */
 	config_qe_ioports();
 #endif
-#if defined(CONFIG_MPC8536)
-	fsl_serdes_init();
-#endif
+
 #if defined(CONFIG_FSL_DMA)
 	dma_init();
 #endif
@@ -374,6 +369,11 @@ int cpu_init_r(void)
 	qe_reset();
 #endif
 
+	/* XXX: remove MPC8536 eventually */
+#if defined(CONFIG_FSL_SERDES) || defined(CONFIG_MPC8536)
+	fsl_serdes_init();
+#endif
+
 #if defined(CONFIG_MP)
 	setup_mp();
 #endif
diff --git a/cpu/mpc85xx/serdes.c b/cpu/mpc85xx/serdes.c
new file mode 100644
index 0000000..87ec221
--- /dev/null
+++ b/cpu/mpc85xx/serdes.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_pci.h>
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+void mpc85xx_serdes_board_init(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct fsl_pci_info pci_info[3];
+	u32 devdisr, host_agent;
+	int first_free_busno = 0;
+	int num = 0;
+	int rio = 0;
+
+	int pcie_ep;
+
+	devdisr = in_be32(&gur->devdisr);
+	host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
+
+	debug("   mpc85xx_serdes_board_init: devdisr=%x, host_agent=%x\n",
+			devdisr, host_agent);
+
+	if (is_serdes_configured(SGMII_TSEC1))
+		puts("    eTSEC1 is in sgmii mode.\n");
+	if (is_serdes_configured(SGMII_TSEC2))
+		puts("    eTSEC2 is in sgmii mode.\n");
+	if (is_serdes_configured(SGMII_TSEC3))
+		puts("    eTSEC3 is in sgmii mode.\n");
+
+	puts("\n");
+#ifdef CONFIG_PCIE1
+	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
+
+	if (is_serdes_configured(PCIE1) && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+		set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS,
+				law_size_bits(CONFIG_SYS_PCIE1_MEM_SIZE),
+				LAW_TRGT_IF_PCIE_1);
+		set_next_law(CONFIG_SYS_PCIE1_IO_PHYS,
+				law_size_bits(CONFIG_SYS_PCIE1_IO_SIZE),
+				LAW_TRGT_IF_PCIE_1);
+
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		printf("    PCIE1 used as %s (base addr %lx)\n",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie1_hose, first_free_busno);
+	} else {
+		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
+		printf("    PCIE1: disabled\n");
+	}
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE2
+	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
+
+	if (is_serdes_configured(PCIE2) && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
+		set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS,
+				law_size_bits(CONFIG_SYS_PCIE2_MEM_SIZE),
+				LAW_TRGT_IF_PCIE_2);
+		set_next_law(CONFIG_SYS_PCIE2_IO_PHYS,
+				law_size_bits(CONFIG_SYS_PCIE2_IO_SIZE),
+				LAW_TRGT_IF_PCIE_2);
+
+		SET_STD_PCIE_INFO(pci_info[num], 2);
+		printf("    PCIE2 used as %s (base addr %lx)\n",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie2_hose, first_free_busno);
+
+	} else {
+		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2);
+		printf("    PCIE2: disabled\n");
+	}
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
+#endif
+
+#ifdef CONFIG_PCIE3
+	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
+
+	if (is_serdes_configured(PCIE3) && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS,
+				law_size_bits(CONFIG_SYS_PCIE3_MEM_SIZE),
+				LAW_TRGT_IF_PCIE_3);
+		set_next_law(CONFIG_SYS_PCIE3_IO_PHYS,
+				law_size_bits(CONFIG_SYS_PCIE3_IO_SIZE),
+				LAW_TRGT_IF_PCIE_3);
+
+		SET_STD_PCIE_INFO(pci_info[num], 3);
+		printf("    PCIE3 used as %s (base addr %lx)\n",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+					&pcie3_hose, first_free_busno);
+	} else {
+		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3);
+		printf("    PCIE3: disabled\n");
+	}
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
+#endif
+
+#ifdef CONFIG_SRIO
+	if (is_serdes_configured(SRIO1) && !(devdisr & MPC85xx_DEVDISR_SRIO)){
+		set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
+				law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
+				LAW_TRGT_IF_RIO);
+
+		rio = 1;
+		printf("    SRIO1 enabled\n");
+	} else {
+		printf("    SRIO1: disabled\n");
+	}
+
+	if (is_serdes_configured(SRIO2) && !(devdisr & MPC85xx_DEVDISR_SRIO)){
+		set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
+				law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
+				LAW_TRGT_IF_RIO_2);
+
+		printf("    SRIO2 enabled\n");
+	} else {
+		printf("    SRIO2: disabled\n");
+		if (rio == 0)
+			setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO);
+
+	}
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO); /* disable */
+#endif
+}
+
+void ft_mpc85xx_serdes_board_setup(void *blob)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 devdisr = in_be32(&gur->devdisr);
+
+#ifdef CONFIG_PCIE1
+	if (devdisr & MPC85xx_DEVDISR_PCIE)
+		fdt_del_node_by_path(blob, PCIE1_ALIAS_NAME);
+	else
+		ft_fsl_pci_setup(blob, PCIE1_ALIAS_NAME, &pcie1_hose);
+#else
+	fdt_del_node_by_path(blob, PCIE1_ALIAS_NAME);
+#endif
+#ifdef CONFIG_PCIE2
+	if (devdisr & MPC85xx_DEVDISR_PCIE2)
+		fdt_del_node_by_path(blob, PCIE2_ALIAS_NAME);
+	else
+		ft_fsl_pci_setup(blob, PCIE2_ALIAS_NAME, &pcie2_hose);
+#else
+	fdt_del_node_by_path(blob, PCIE2_ALIAS_NAME);
+#endif
+#ifdef CONFIG_PCIE3
+	if (devdisr & MPC85xx_DEVDISR_PCIE3)
+		fdt_del_node_by_path(blob, PCIE3_ALIAS_NAME);
+	else
+		ft_fsl_pci_setup(blob, PCIE3_ALIAS_NAME, &pcie3_hose);
+#else
+	fdt_del_node_by_path(blob, PCIE3_ALIAS_NAME);
+#endif
+#ifdef CONFIG_SRIO
+	if (devdisr & MPC85xx_DEVDISR_SRIO) {
+		fdt_del_node_by_path(blob, SRIO1_ALIAS_NAME);
+		fdt_del_node_by_path(blob, SRIO2_ALIAS_NAME);
+	} else {
+		if (!is_serdes_configured(SRIO1))
+			fdt_del_node_by_path(blob, SRIO1_ALIAS_NAME);
+		if (!is_serdes_configured(SRIO2))
+			fdt_del_node_by_path(blob, SRIO2_ALIAS_NAME);
+	}
+#else
+	fdt_del_node_by_path(blob, SRIO1_ALIAS_NAME);
+	fdt_del_node_by_path(blob, SRIO2_ALIAS_NAME);
+#endif
+}
diff --git a/include/asm-ppc/fsl_serdes.h b/include/asm-ppc/fsl_serdes.h
index 6da4b6f..b75d736 100644
--- a/include/asm-ppc/fsl_serdes.h
+++ b/include/asm-ppc/fsl_serdes.h
@@ -3,6 +3,7 @@
 
 #include <config.h>
 
+#ifdef CONFIG_MPC83xx
 #define FSL_SERDES_CLK_100		(0 << 28)
 #define FSL_SERDES_CLK_125		(1 << 28)
 #define FSL_SERDES_CLK_150		(3 << 28)
@@ -17,5 +18,54 @@ extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
 #else
 static void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) {}
 #endif /* CONFIG_FSL_SERDES */
+#endif /* CONFIG_MPC83xx */
+
+#ifdef CONFIG_MPC85xx
+enum srds_prtcl {
+	NONE = 0,
+	PCIE1,
+	PCIE2,
+	PCIE3,
+	SRIO1,
+	SRIO2,
+	SGMII_TSEC1,
+	SGMII_TSEC2,
+	SGMII_TSEC3,
+};
+
+#if defined(CONFIG_MPC8548)
+#define PCIE1_ALIAS_NAME	"pci2"
+#elif defined(CONFIG_MPC8536)
+#define PCIE1_ALIAS_NAME	"pci3"
+#define PCIE2_ALIAS_NAME	"pci2"
+#define PCIE3_ALIAS_NAME	"pci1"
+#else
+#define PCIE1_ALIAS_NAME	"pci2"
+#define PCIE2_ALIAS_NAME	"pci1"
+#define PCIE3_ALIAS_NAME	"pci0"
+#endif
+
+#define SRIO1_ALIAS_NAME	"rio0"
+#define SRIO2_ALIAS_NAME	"rio1"
+
+extern void mpc85xx_serdes_board_init(void);
+extern void ft_mpc85xx_serdes_board_setup(void *blob);
+
+#ifdef CONFIG_FSL_SERDES
+extern void fsl_serdes_init(void);
+extern int is_serdes_configured(enum srds_prtcl prtcl);
+#else
+
+/* XXX: MPC8536 should eventually use CONFIG_FSL_SERDES */
+#ifndef CONFIG_MPC8536
+void fsl_serdes_init(void) {}
+#endif
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+	return 1;
+}
+#endif /* CONFIG_FSL_SERDES */
+#endif /* CONFIG_MPC85xx */
 
 #endif /* __FSL_SERDES_H */
-- 
1.6.4

[U-Boot] [PATCH 4/5] p2020: add serdes status code complying to fsl_serdes APIs

[Li Yang]

Signed-off-by: Li Yang <leoli@freescale.com>
---
 cpu/mpc85xx/Makefile       |    1 +
 cpu/mpc85xx/p2020_serdes.c |   89 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 90 insertions(+), 0 deletions(-)
 create mode 100644 cpu/mpc85xx/p2020_serdes.c

diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index 018ebc9..457a45f 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -63,6 +63,7 @@ COBJS-$(CONFIG_PCI)	+= pci.o
 COBJS-$(CONFIG_QE)	+= qe_io.o
 COBJS-$(CONFIG_CPM2)	+= serial_scc.o
 COBJS-$(CONFIG_FSL_SERDES)	+= serdes.o
+COBJS-$(CONFIG_P2020)	+= p2020_serdes.o
 
 COBJS	= $(COBJS-y)
 COBJS	+= cpu.o
diff --git a/cpu/mpc85xx/p2020_serdes.c b/cpu/mpc85xx/p2020_serdes.c
new file mode 100644
index 0000000..f52d744
--- /dev/null
+++ b/cpu/mpc85xx/p2020_serdes.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS_MAX_LANES		4
+
+static int serdes_cfg;
+static int serdes_prtcl_map = 0;
+
+u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+	[0] = {PCIE1, NONE, NONE, NONE},
+	[1] = {NONE, NONE, NONE, NONE},
+	[2] = {PCIE1, PCIE2, PCIE3, PCIE3},
+	[4] = {PCIE1, PCIE1, PCIE3, PCIE3},
+	[6] = {PCIE1, PCIE1, PCIE1, PCIE1},
+	[7] = {SRIO2, SRIO1, NONE, NONE},
+	[8] = {SRIO2, SRIO2, SRIO2, SRIO2},
+	[9] = {SRIO2, SRIO2, SRIO2, SRIO2},
+	[10] = {SRIO2, SRIO2, SRIO2, SRIO2},
+	[11] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3},
+	[12] = {SRIO2, SRIO1, SGMII_TSEC2, SGMII_TSEC3},
+	[13] = {PCIE1, SRIO1, SGMII_TSEC2, SGMII_TSEC3},
+	[14] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
+	[15] = {PCIE1, PCIE1, SGMII_TSEC2, SGMII_TSEC3},
+};
+
+static const char *serdes_prtcl_str[] = {
+	[NONE] = "NA",
+	[PCIE1] = "PCIE1",
+	[PCIE2] = "PCIE2",
+	[PCIE3] = "PCIE3",
+	[SRIO1] = "SRIO1",
+	[SRIO2] = "SRIO2",
+	[SGMII_TSEC2] = "SGMII_TSEC2",
+	[SGMII_TSEC3] = "SGMII_TSEC3",
+};
+
+static enum srds_prtcl serdes_get_prtcl(int lane)
+{
+	return serdes_cfg_tbl[serdes_cfg][lane];
+}
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+	return (1 << prtcl) & serdes_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int lane;
+	int i;
+	enum srds_prtcl lane_prtcl;
+
+	serdes_cfg = (in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	debug("Using SERDES configuration 0x%x, lane settings:\n",
+			serdes_cfg);
+
+	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+		lane_prtcl = serdes_get_prtcl(lane);
+
+		serdes_prtcl_map |= (1 << lane_prtcl);
+		debug("%s ", serdes_prtcl_str[lane_prtcl]);
+	}
+	debug("\n");
+}
-- 
1.6.4

[U-Boot] [PATCH 5/5] p2020ds: use common code to initialize serdes ports

[Li Yang]

Setting up LAWs, PCIE, SRIO, SGMII intelligently
based on the power-on serdes configuration.

Signed-off-by: Li Yang <leoli@freescale.com>
---
 board/freescale/p2020ds/law.c     |    6 --
 board/freescale/p2020ds/p2020ds.c |  126 ++-----------------------------------
 include/configs/P2020DS.h         |   21 ++++++
 3 files changed, 27 insertions(+), 126 deletions(-)

diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c
index 28ed2ed..c90c9ae 100644
--- a/board/freescale/p2020ds/law.c
+++ b/board/freescale/p2020ds/law.c
@@ -29,12 +29,6 @@
 
 struct law_entry law_table[] = {
 	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
 };
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index e38c014..64db0c1 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -27,7 +27,6 @@
 #include <asm/mmu.h>
 #include <asm/cache.h>
 #include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
 #include <asm/fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <miiphy.h>
@@ -37,6 +36,7 @@
 #include <asm/fsl_law.h>
 #include <asm/mp.h>
 #include <netdev.h>
+#include <asm/fsl_serdes.h>
 
 #include "../common/pixis.h"
 #include "../common/sgmii_riser.h"
@@ -180,120 +180,10 @@ phys_size_t fixed_sdram(void)
 
 #endif
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
-
 #ifdef CONFIG_PCI
 void pci_init_board(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[3];
-	u32 devdisr, pordevsr, io_sel, host_agent;
-	int first_free_busno = 0;
-	int num = 0;
-
-	int pcie_ep, pcie_configured;
-
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-	host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
-
-	debug("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
-			devdisr, io_sel, host_agent);
-
-	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
-		printf("    eTSEC2 is in sgmii mode.\n");
-	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
-		printf("    eTSEC3 is in sgmii mode.\n");
-
-	puts("\n");
-#ifdef CONFIG_PCIE2
-	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
-	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
-		SET_STD_PCIE_INFO(pci_info[num], 2);
-		printf("    PCIE2 connected to ULI as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
-				pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie2_hose, first_free_busno);
-
-		/*
-		 * The workaround doesn't work on p2020 because the location
-		 * we try and read isn't valid on p2020, fix this later
-		 */
-#if 0
-		/*
-		 * Activate ULI1575 legacy chip by performing a fake
-		 * memory access.  Needed to make ULI RTC work.
-		 * Device 1d has the first on-board memory BAR.
-		 */
-
-		pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
-				PCI_BASE_ADDRESS_1, &temp32);
-		if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
-			void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
-							temp32, 4, 0);
-			debug(" uli1575 read to %p\n", p);
-			in_be32(p);
-		}
-#endif
-	} else {
-		printf("    PCIE2: disabled\n");
-	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE3
-	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
-	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
-		SET_STD_PCIE_INFO(pci_info[num], 3);
-		printf("    PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
-				pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie3_hose, first_free_busno);
-	} else {
-		printf("    PCIE3: disabled\n");
-	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
-	pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
-	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		printf("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
-				pcie_ep ? "End Point" : "Root Complex",
-				pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("    PCIE1: disabled\n");
-	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
+	mpc85xx_serdes_board_init();
 }
 #endif
 
@@ -523,6 +413,8 @@ int board_eth_init(bd_t *bis)
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 devdisr = in_be32(&gur->devdisr);
 	phys_addr_t base;
 	phys_size_t size;
 
@@ -533,14 +425,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
-#ifdef CONFIG_PCIE3
-	ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
-#endif
-#ifdef CONFIG_PCIE2
-	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE1
-	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#ifdef CONFIG_FSL_SERDES
+	ft_mpc85xx_serdes_board_setup(blob);
 #endif
 #ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_fdt_fixup(blob);
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index b48c199..406afc7 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -39,6 +39,7 @@
 #define CONFIG_P2020DS		1
 #define CONFIG_MP		1	/* support multiple processors */
 
+#define CONFIG_FSL_SERDES	1	/* Use common serdes init code */
 #define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
@@ -519,6 +520,26 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
 #endif
 
+#define CONFIG_SRIO
+
+/* SRIO1 uses the same window as PCIE2 mem window */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
+
+/* SRIO2 uses the same window as PCIE1 mem window */
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x20000000	/* 512M */
+
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
 
-- 
1.6.4

[U-Boot] [PATCH 2/5] fsl_law: add SRIO2 target id and law_size_bits() macro

[Kumar Gala]

On Dec 10, 2009, at 1:41 AM, Li Yang wrote:

> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> include/asm-ppc/fsl_law.h |    3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)

applied to 85xx next

- k

[U-Boot] [PATCH 1/5] fdt: add fdt_del_node_by_path() API

[Kumar Gala]

On Dec 10, 2009, at 1:41 AM, Li Yang wrote:

> For removing node easily by path or alias.
> 
> Signed-off-by: Li Yang <leoli@freescale.com>
> ---
> common/fdt_support.c  |   10 ++++++++++
> include/fdt_support.h |    1 +
> 2 files changed, 11 insertions(+), 0 deletions(-)

Jerry,

If you can ack this I'll handling pulling this in via the 85xx tree.

- k

[U-Boot] [PATCH 1/5] fdt: add fdt_del_node_by_path() API

[Jerry Van Baren]

Kumar Gala wrote:
> On Dec 10, 2009, at 1:41 AM, Li Yang wrote:
> 
>> For removing node easily by path or alias.
>>
>> Signed-off-by: Li Yang <leoli@freescale.com>
>> ---
>> common/fdt_support.c  |   10 ++++++++++
>> include/fdt_support.h |    1 +
>> 2 files changed, 11 insertions(+), 0 deletions(-)
> 
> Jerry,
> 
> If you can ack this I'll handling pulling this in via the 85xx tree.
> 
> - k

Acked-by: Gerald Van Baren <vanbaren@cideas.com>

Thanks,
gvb