[U-Boot] CFI not detecting S29 flash device on 405gp board

[U-Boot] CFI not detecting S29 flash device on 405gp board

[ayman at austin.rr.com]

I've got a custom board that was based on the walnut.  I have a 2+ year old
version of u-boot working on it, but we are trying to go to the newer version
to match our newer hardware.  The hardware is a 405gpr to spansion s29jl064.
I found another board using the same flash for some hints.  Here are parts of
the config.  I did not modify amcc-common.h  (The debug and more info are below).

#define CONFIG_SYS_FLASH_BASE           0xFF800000

#define FLASH_BASE0_PRELIM      CONFIG_SYS_FLASH_BASE   /* FLASH bank #0                */
#define FLASH_BASE1_PRELIM      0               /* FLASH bank #1                */

#define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
#define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */

#undef  CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO    /* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_ERASE_TOUT    (3 * 1000)
#define CONFIG_SYS_FLASH_WRITE_TOUT    (3 * 1000)
#define CONFIG_SYS_FLASH_LOCK_TOUT     (3 * 1000)
#define CONFIG_SYS_FLASH_UNLOCK_TOUT   (3 * 1000)
#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP


#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
#define CONFIG_SYS_MAX_FLASH_SECT       150     /* max number of sectors on one chip    */
#define CONFIG_SYS_FLASH_CFI_WDITH      FLASH_CFI_8BIT

/* Memory Bank 0 (Flash Bank 0) initialization                                  */
#define CONFIG_SYS_EBC_PB0AP            0x03015400
#define CONFIG_SYS_EBC_PB0CR            0xFF878000  /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit  */

#if 0
#define CONFIG_SYS_EBC_PB1AP            0x02815480
#define CONFIG_SYS_EBC_PB1CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */

#define CONFIG_SYS_EBC_PB2AP            0x03011380
#define CONFIG_SYS_EBC_PB2CR            0xC00FC000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit  */

#define CONFIG_SYS_EBC_PB3AP            0x01815280
#define CONFIG_SYS_EBC_PB3CR            0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */

#define CONFIG_SYS_EBC_PB7AP            0x01815280
#define CONFIG_SYS_EBC_PB7CR            0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
#endif

/*-----------------------------------------------------------------------
 * External peripheral base address
 *-----------------------------------------------------------------------
 */
#define CONFIG_KEY_REG_BASE_ADDR        0xF0100000
#define CONFIG_IR_REG_BASE_ADDR 0xF0200000
#define CONFIG_FPGA_REG_BASE_ADDR       0xF0300000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area
 */
#define CONFIG_SYS_INIT_DCACHE_CS       3       /* use cs # 4 for data cache memory    */

#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* inside of SDRAM                     */
#define CONFIG_SYS_INIT_RAM_END 0x2000  /* End of used area in RAM             */
#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 */
#define SPD_EEPROM_ADDRESS      0x50

#undef CONFIG_IDE_LED
#undef CONFIG_IDE_RESET
#undef CONFIG_HW_WATCHDOG



The walnut doesn't use the generic CFI driver, but I saw no reason that I could
not, so I enabled it.  With that and debug on, I get the output below.  It can't
seem to read the MFR Id.  I confirmed that I can read it with the BDI after I do
a reset halt.  If I do a reset run, then halt, I *cannot* read the flash Id.  It
makes me think that the PB0AP or CR are wrong, but viewing them on the BDI, they
are identical.  I

Here is the cmd I use to read the mfr id and the output (correct)
Core#0>mmb 0xFF800aaa 0xaa; mmb 0xFF800555 0x55; mmb 0xFF800aaa 0x90; mdb 0xFF800000 1
ff800000 : 0x01     1  .

With DEBUG enabled, I get the following output ....


U-Boot 2008.10 (Dec 30 2009 - 16:20:32)

CPU:   AMCC PowerPC 405GPr Rev. B at 266.667 MHz (PLB=133, OPB=66, EBC=33 MHz)
       Internal PCI arbiter disabled, PCI sync clock at 33 MHz
       16 kB I-Cache 16 kB D-Cache
Board: TanoEngine - AMCC PPC405GPr
I2C:   ready
DRAM:  64 MB
FLASH: flash detect cfi
fwc addr ff800000 cmd f0 f0 8bit x 8 bit
fwc addr ff800000 cmd ff ff 8bit x 8 bit
fwc addr ff800055 cmd 98 98 8bit x 8 bit
is= cmd 51(Q) addr ff800010 is= ff 51
fwc addr ff800555 cmd 98 98 8bit x 8 bit
is= cmd 51(Q) addr ff800010 is= ff 51
fwc addr ff800000 cmd f0 f0f0 16bit x 8 bit
fwc addr ff800000 cmd ff ffff 16bit x 8 bit
fwc addr ff8000aa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff800020 is= ffff 5151
fwc addr ff800aaa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff800020 is= ffff 5151
fwc addr ff800000 cmd f0 00f0 16bit x 16 bit
fwc addr ff800000 cmd ff 00ff 16bit x 16 bit
fwc addr ff8000aa cmd 98 0098 16bit x 16 bit
is= cmd 51(Q) addr ff800020 is= ffff 0051
fwc addr ff800aaa cmd 98 0098 16bit x 16 bit
is= cmd 51(Q) addr ff800020 is= ffff 0051
fwc addr ff800000 cmd f0 f0f0f0f0 32bit x 8 bit
fwc addr ff800000 cmd ff ffffffff 32bit x 8 bit
fwc addr ff800154 cmd 98 98989898 32bit x 8 bit
is= cmd 51(Q) addr ff800040 is= ffffffff 51515151
fwc addr ff801554 cmd 98 98989898 32bit x 8 bit
is= cmd 51(Q) addr ff800040 is= ffffffff 51515151
fwc addr ff800000 cmd f0 00f000f0 32bit x 16 bit
fwc addr ff800000 cmd ff 00ff00ff 32bit x 16 bit
fwc addr ff800154 cmd 98 00980098 32bit x 16 bit
is= cmd 51(Q) addr ff800040 is= ffffffff 00510051
fwc addr ff801554 cmd 98 00980098 32bit x 16 bit
is= cmd 51(Q) addr ff800040 is= ffffffff 00510051
fwc addr ff800000 cmd f0 000000f0 32bit x 32 bit
fwc addr ff800000 cmd ff 000000ff 32bit x 32 bit
fwc addr ff800154 cmd 98 00000098 32bit x 32 bit
is= cmd 51(Q) addr ff800040 is= ffffffff 00000051
fwc addr ff801554 cmd 98 00000098 32bit x 32 bit
is= cmd 51(Q) addr ff800040 is= ffffffff 00000051
fwrite addr ff800000 cmd f0 f0f0f0f0f0f0f0f0 64 bit x 8 bit
fwrite addr ff800000 cmd ff ffffffffffffffff 64 bit x 8 bit
fwrite addr ff8002a8 cmd 98 9898989898989898 64 bit x 8 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 5151515151515151
fwrite addr ff802aa8 cmd 98 9898989898989898 64 bit x 8 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 5151515151515151
fwrite addr ff800000 cmd f0 00f000f000f000f0 64 bit x 16 bit
fwrite addr ff800000 cmd ff 00ff00ff00ff00ff 64 bit x 16 bit
fwrite addr ff8002a8 cmd 98 0098009800980098 64 bit x 16 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 0051005100510051
fwrite addr ff802aa8 cmd 98 0098009800980098 64 bit x 16 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 0051005100510051
fwrite addr ff800000 cmd f0 000000f0000000f0 64 bit x 32 bit
fwrite addr ff800000 cmd ff 000000ff000000ff 64 bit x 32 bit
fwrite addr ff8002a8 cmd 98 0000009800000098 64 bit x 32 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 0000005100000051
fwrite addr ff802aa8 cmd 98 0000009800000098 64 bit x 32 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 0000005100000051
fwrite addr ff800000 cmd f0 00000000000000f0 64 bit x 64 bit
fwrite addr ff800000 cmd ff 00000000000000ff 64 bit x 64 bit
fwrite addr ff8002a8 cmd 98 0000000000000098 64 bit x 64 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 0000000000000051
fwrite addr ff802aa8 cmd 98 0000000000000098 64 bit x 64 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 0000000000000051
not found
## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB
*** failed ***
### ERROR ### Please RESET the board ###

Thanks,
Ayman

[U-Boot] CFI not detecting S29 flash device on 405gp board

[ame]

Some additional information and a small amount of success.

I was finally able to get the part identified correctly 
using the CFI code.  However, ONLY when I use gdb+bdi 
2000.  So if I just use "reset run" on the bdi then it 
will fail with the log in my previous email.  If I use
"reset halt", then using gdb tell it to continue (no 
breakpoints or anything), then it is correctly identified.
Without the bdi attached it does not work either (fails
in the same way as case #1).

I don't know what the difference is but obviously there 
is something about using continue that makes it work. I
put a large delay (several hundred ms) before the flash 
reset, but it did not seem to matter.

I also tried a patch that was posted for moving the reset
command into the board specific files to handle the case
of flashes that go south when they get certain resets.
I only implemented the AMD reset, but again, no diff.

Thanks
Ayman

[U-Boot] CFI not detecting S29 flash device on 405gp board

[Jerry Van Baren]

Hi Ayman,

ame wrote:
> Some additional information and a small amount of success.
> 
> I was finally able to get the part identified correctly 
> using the CFI code.  However, ONLY when I use gdb+bdi 
> 2000.  So if I just use "reset run" on the bdi then it 
> will fail with the log in my previous email.  If I use
> "reset halt", then using gdb tell it to continue (no 
> breakpoints or anything), then it is correctly identified.
> Without the bdi attached it does not work either (fails
> in the same way as case #1).
> 
> I don't know what the difference is but obviously there 
> is something about using continue that makes it work. I
> put a large delay (several hundred ms) before the flash 
> reset, but it did not seem to matter.

Your BDI-2000 config has some initialization in it which is configuring 
something in your hardware to make the flash interface work.  Reset run 
does not do the BDI-2000 config script.  Reset halt does.

Perhaps you have chip select configuration in your BDI-2000 initialization?

Start removing configuration items from your BDI-2000 config.  When it 
breaks, the last thing that you removed will be it. ;-)

> I also tried a patch that was posted for moving the reset
> command into the board specific files to handle the case
> of flashes that go south when they get certain resets.
> I only implemented the AMD reset, but again, no diff.

Your hardware is not being initialized properly by your u-boot 
initialization code, but it is by your BDI-2000 config.  It is not a CFI 
/ S29 flash issue, it is a basic hardware initialization issue.

> Thanks
> Ayman

Best regards,
gvb

[U-Boot] CFI not detecting S29 flash device on 405gp board

[ame]

On Wed, Dec 30, 2009 at 04:38:44PM -0600, ayman at austin.rr.com wrote:
> I've got a custom board that was based on the walnut.  I have a 2+ year old
> version of u-boot working on it, but we are trying to go to the newer version
> to match our newer hardware.  The hardware is a 405gpr to spansion s29jl064.
> I found another board using the same flash for some hints.  Here are parts of
> the config.  I did not modify amcc-common.h  (The debug and more info are below).

<snip>

> is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 0000005100000051
> fwrite addr ff800000 cmd f0 00000000000000f0 64 bit x 64 bit
> fwrite addr ff800000 cmd ff 00000000000000ff 64 bit x 64 bit
> fwrite addr ff8002a8 cmd 98 0000000000000098 64 bit x 64 bit
> is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 0000000000000051
> fwrite addr ff802aa8 cmd 98 0000000000000098 64 bit x 64 bit
> is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 0000000000000051
> not found
> ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB
> *** failed ***
> ### ERROR ### Please RESET the board ###

I had another reply (that I seem to be missing), but the clue was in the BDI
working when I did reset halt, then attach via gdb, then continue.  In this
case, it would work.  When I did a reset run it did not.  As it turns out some
registers were setup in the bdi config that were not getting done properly by
the init code.  By just eliminating them a couple at a time, I was able to
find the problem register.  Thanks for all your help.

Ayman