[U-Boot] [PATCH v3 00/11] SPEAr : Adding support for SPEAr SoCs

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* [U-Boot] [PATCH v3 00/11] SPEAr : Adding support for SPEAr SoCs
@ 2010-01-08 13:48 Vipin KUMAR
  2010-01-08 13:48 ` [U-Boot] [PATCH v3 01/11] SPEAr : Adding README.spear in doc Vipin KUMAR
  0 siblings, 1 reply; 13+ messages in thread
From: Vipin KUMAR @ 2010-01-08 13:48 UTC (permalink / raw)
  To: u-boot

The patch set contains the review feedbacks recieved on PATCH v2
The patch set has been recreated to make sure that the dependencies
do not exist. i.e all subpatches depend only on preceeding subpatches

Also removed build error which came with BUILD_DIR option

Chekckpatch error removed

Vipin (11):
  SPEAr : Adding README.spear in doc
  SPEAr : Adding basic support for SPEAr600
  SPEAr : Adding basic support for SPEAr300
  SPEAr : Adding basic support for SPEAr310
  SPEAr : Adding basic support for SPEAr320
  SPEAr : i2c driver support addded
  SPEAr : Support for HW macid read/write from i2c memory
  SPEAr : Support for serial memory interface driver and serial NOR
    flash
  SPEAr : Support for nand driver
  SPEAr : Support for usbd driver and usbtty support
  SPEAr : Support for cfi driver and parallel NOR flash

 MAKEALL                                        |    4 +
 Makefile                                       |    6 +
 board/spear/common/Makefile                    |   54 ++
 board/spear/common/spr_lowlevel_init.S         |  197 +++++
 board/spear/common/spr_misc.c                  |  297 +++++++
 board/spear/spear300/Makefile                  |   51 ++
 board/spear/spear300/config.mk                 |   39 +
 board/spear/spear300/spear300.c                |   57 ++
 board/spear/spear310/Makefile                  |   51 ++
 board/spear/spear310/config.mk                 |   44 +
 board/spear/spear310/spear310.c                |   58 ++
 board/spear/spear320/Makefile                  |   51 ++
 board/spear/spear320/config.mk                 |   44 +
 board/spear/spear320/spear320.c                |   58 ++
 board/spear/spear600/Makefile                  |   51 ++
 board/spear/spear600/config.mk                 |   39 +
 board/spear/spear600/spear600.c                |   53 ++
 cpu/arm926ejs/spear/Makefile                   |   52 ++
 cpu/arm926ejs/spear/reset.c                    |   53 ++
 cpu/arm926ejs/spear/timer.c                    |  150 ++++
 doc/README.spear                               |   53 ++
 drivers/i2c/Makefile                           |    1 +
 drivers/i2c/spr_i2c.c                          |  340 ++++++++
 drivers/mtd/Makefile                           |    1 +
 drivers/mtd/nand/Makefile                      |    1 +
 drivers/mtd/nand/spr_nand.c                    |  123 +++
 drivers/mtd/spr_smi.c                          |  530 +++++++++++++
 drivers/serial/usbtty.h                        |    2 +
 drivers/usb/gadget/Makefile                    |    1 +
 drivers/usb/gadget/spr_udc.c                   | 1004 ++++++++++++++++++++++++
 include/asm-arm/arch-spear/spr_defs.h          |   38 +
 include/asm-arm/arch-spear/spr_emi.h           |   54 ++
 include/asm-arm/arch-spear/spr_gpt.h           |   83 ++
 include/asm-arm/arch-spear/spr_i2c.h           |  146 ++++
 include/asm-arm/arch-spear/spr_misc.h          |  130 +++
 include/asm-arm/arch-spear/spr_nand.h          |   57 ++
 include/asm-arm/arch-spear/spr_smi.h           |  117 +++
 include/asm-arm/arch-spear/spr_syscntl.h       |   38 +
 include/asm-arm/arch-spear/spr_xloader_table.h |   67 ++
 include/configs/spear.h                        |  363 +++++++++
 include/usb/spr_udc.h                          |  227 ++++++
 41 files changed, 4785 insertions(+), 0 deletions(-)
 create mode 100644 board/spear/common/Makefile
 create mode 100755 board/spear/common/spr_lowlevel_init.S
 create mode 100755 board/spear/common/spr_misc.c
 create mode 100755 board/spear/spear300/Makefile
 create mode 100755 board/spear/spear300/config.mk
 create mode 100755 board/spear/spear300/spear300.c
 create mode 100755 board/spear/spear310/Makefile
 create mode 100755 board/spear/spear310/config.mk
 create mode 100755 board/spear/spear310/spear310.c
 create mode 100755 board/spear/spear320/Makefile
 create mode 100755 board/spear/spear320/config.mk
 create mode 100755 board/spear/spear320/spear320.c
 create mode 100755 board/spear/spear600/Makefile
 create mode 100755 board/spear/spear600/config.mk
 create mode 100755 board/spear/spear600/spear600.c
 create mode 100755 cpu/arm926ejs/spear/Makefile
 create mode 100755 cpu/arm926ejs/spear/reset.c
 create mode 100755 cpu/arm926ejs/spear/timer.c
 create mode 100644 doc/README.spear
 mode change 100644 => 100755 drivers/i2c/Makefile
 create mode 100755 drivers/i2c/spr_i2c.c
 mode change 100644 => 100755 drivers/mtd/Makefile
 create mode 100755 drivers/mtd/nand/spr_nand.c
 create mode 100755 drivers/mtd/spr_smi.c
 mode change 100644 => 100755 drivers/serial/usbtty.h
 mode change 100644 => 100755 drivers/usb/gadget/Makefile
 create mode 100755 drivers/usb/gadget/spr_udc.c
 create mode 100644 include/asm-arm/arch-spear/spr_defs.h
 create mode 100644 include/asm-arm/arch-spear/spr_emi.h
 create mode 100755 include/asm-arm/arch-spear/spr_gpt.h
 create mode 100755 include/asm-arm/arch-spear/spr_i2c.h
 create mode 100644 include/asm-arm/arch-spear/spr_misc.h
 create mode 100644 include/asm-arm/arch-spear/spr_nand.h
 create mode 100755 include/asm-arm/arch-spear/spr_smi.h
 create mode 100644 include/asm-arm/arch-spear/spr_syscntl.h
 create mode 100755 include/asm-arm/arch-spear/spr_xloader_table.h
 create mode 100755 include/configs/spear.h
 create mode 100755 include/usb/spr_udc.h

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [U-Boot] [PATCH v3 01/11] SPEAr : Adding README.spear in doc
  2010-01-08 13:48 [U-Boot] [PATCH v3 00/11] SPEAr : Adding support for SPEAr SoCs Vipin KUMAR
@ 2010-01-08 13:48 ` Vipin KUMAR
  2010-01-08 13:48   ` [U-Boot] [PATCH v3 02/11] SPEAr : Adding basic support for SPEAr600 Vipin KUMAR
  0 siblings, 1 reply; 13+ messages in thread
From: Vipin KUMAR @ 2010-01-08 13:48 UTC (permalink / raw)
  To: u-boot


Signed-off-by: Vipin <vipin.kumar@st.com>
---
 doc/README.spear |   53 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 53 insertions(+), 0 deletions(-)
 create mode 100644 doc/README.spear

diff --git a/doc/README.spear b/doc/README.spear
new file mode 100644
index 0000000..db90a7b
--- /dev/null
+++ b/doc/README.spear
@@ -0,0 +1,53 @@
+
+SPEAr (Structured Processor Enhanced Architecture).
+
+SPEAr600 is also known as SPEArPlus and SPEAr300 is also known as SPEArBasic
+
+The SPEAr SoC family also embeds a customizable logic that could be programmed
+one-time by a customer at silicon mask level (i.e. not at runtime!).
+We are now adding the support in u-boot for two SoC: SPEAr600 and SPEAr3xx.
+Pls note that SPEAr300/310/320 differs only for the default customization.
+
+All 4 SoCs share common peripherals.
+
+1. ARM926ejs core based (sp600 has two cores, the 2nd handled only in Linux)
+2. FastEthernet (sp600 has Gbit version, but same controller - GMAC)
+3. USB Host
+4. USB Device
+5. NAND controller (FSMC)
+6. Serial NOR ctrl
+7. I2C
+8. SPI
+9. CLCD
+10. others ..
+
+sp600 is not customized by default.
+sp3xx are differently customized...
+sp300 is more oriented to TELECOM/video (it has tdm, i2s, ITU i/f support)
+sp310 for networking (a part GMAC in fixed part, it has 5 MACB ctrls in
+custom)
+sp320 for industrial (SPP ctrl, CAN ctrl, 2 MACBs, ...)
+
+Everything is supported in Linux.
+u-boot is not currently supporting all peripeharls (just a few).
+
+More description can be found on Internet, for example here:
+
+http://embedded-system.net/spear-basic-customizable-arm-based-soc-stmicroelectronics.html
+
+Build options
+	make spear600_config
+	make spear300_config
+	make spear310_config
+	make spear320_config
+
+Further options
+	make ENV=NAND (supported by all 4 SoCs)
+	- This option generates a uboot image that saves environment inn NAND
+
+	make CONSOLE=USB (supported by all 4 SoCs)
+ 	- This option generates a uboot image for using usbdevice as a tty i/f
+
+	make FLASH=PNOR (supported by SPEAr310 and SPEAr320)
+	- This option generates a uboot image that supports emi controller for
+	CFI compliant parallel NOR flash
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [U-Boot] [PATCH v3 02/11] SPEAr : Adding basic support for SPEAr600
  2010-01-08 13:48 ` [U-Boot] [PATCH v3 01/11] SPEAr : Adding README.spear in doc Vipin KUMAR
@ 2010-01-08 13:48   ` Vipin KUMAR
  2010-01-08 13:48     ` [U-Boot] [PATCH v3 03/11] SPEAr : Adding basic support for SPEAr300 Vipin KUMAR
  0 siblings, 1 reply; 13+ messages in thread
From: Vipin KUMAR @ 2010-01-08 13:48 UTC (permalink / raw)
  To: u-boot


Signed-off-by: Vipin <vipin.kumar@st.com>
---
 MAKEALL                                        |    1 +
 Makefile                                       |    3 +
 board/spear/common/Makefile                    |   54 +++++++
 board/spear/common/spr_lowlevel_init.S         |  197 ++++++++++++++++++++++++
 board/spear/common/spr_misc.c                  |  163 ++++++++++++++++++++
 board/spear/spear600/Makefile                  |   51 ++++++
 board/spear/spear600/config.mk                 |   28 ++++
 board/spear/spear600/spear600.c                |   31 ++++
 cpu/arm926ejs/spear/Makefile                   |   52 ++++++
 cpu/arm926ejs/spear/reset.c                    |   53 +++++++
 cpu/arm926ejs/spear/timer.c                    |  150 ++++++++++++++++++
 include/asm-arm/arch-spear/spr_defs.h          |   38 +++++
 include/asm-arm/arch-spear/spr_gpt.h           |   83 ++++++++++
 include/asm-arm/arch-spear/spr_misc.h          |  130 ++++++++++++++++
 include/asm-arm/arch-spear/spr_syscntl.h       |   38 +++++
 include/asm-arm/arch-spear/spr_xloader_table.h |   67 ++++++++
 include/configs/spear.h                        |  149 ++++++++++++++++++
 17 files changed, 1288 insertions(+), 0 deletions(-)
 create mode 100644 board/spear/common/Makefile
 create mode 100755 board/spear/common/spr_lowlevel_init.S
 create mode 100755 board/spear/common/spr_misc.c
 create mode 100755 board/spear/spear600/Makefile
 create mode 100755 board/spear/spear600/config.mk
 create mode 100755 board/spear/spear600/spear600.c
 create mode 100755 cpu/arm926ejs/spear/Makefile
 create mode 100755 cpu/arm926ejs/spear/reset.c
 create mode 100755 cpu/arm926ejs/spear/timer.c
 create mode 100644 include/asm-arm/arch-spear/spr_defs.h
 create mode 100755 include/asm-arm/arch-spear/spr_gpt.h
 create mode 100644 include/asm-arm/arch-spear/spr_misc.h
 create mode 100644 include/asm-arm/arch-spear/spr_syscntl.h
 create mode 100755 include/asm-arm/arch-spear/spr_xloader_table.h
 create mode 100755 include/configs/spear.h

diff --git a/MAKEALL b/MAKEALL
index ab1bb6f..8eb39e5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -572,6 +572,7 @@ LIST_ARM9="			\
 	sheevaplug		\
 	smdk2400		\
 	smdk2410		\
+	spear600		\
 	trab			\
 	VCMA9			\
 	versatile		\
diff --git a/Makefile b/Makefile
index ed6156f..47f0d23 100644
--- a/Makefile
+++ b/Makefile
@@ -3023,6 +3023,9 @@ smdk2400_config	:	unconfig
 smdk2410_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0
 
+spear600_config :	unconfig
+	@$(MKCONFIG) -n $@ -t $(@:_config=) spear arm arm926ejs $(@:_config=) spear spear
+
 SX1_stdout_serial_config \
 SX1_config:		unconfig
 	@mkdir -p $(obj)include
diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile
new file mode 100644
index 0000000..4f8959f
--- /dev/null
+++ b/board/spear/common/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)board/$(VENDOR)/common)
+endif
+
+LIB	= $(obj)lib$(VENDOR).a
+
+COBJS	:= spr_misc.o
+SOBJS	:= spr_lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/spear/common/spr_lowlevel_init.S b/board/spear/common/spr_lowlevel_init.S
new file mode 100755
index 0000000..64db45c
--- /dev/null
+++ b/board/spear/common/spr_lowlevel_init.S
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2006
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+/*
+ * platform specific initializations are already done in Xloader
+ * Initializations already done include
+ * DDR, PLLs, IP's clock enable and reset release etc
+ */
+.globl lowlevel_init
+lowlevel_init:
+	/* By default, U-Boot switches CPU to low-vector */
+	/* Revert this as we work in high vector even in U-Boot */
+	mrc	p15, 0, r0, c1, c0, 0
+	orr	r0, r0, #0x00002000
+	mcr	p15, 0, r0, c1, c0, 0
+	mov	pc, lr
+
+/* ;void setfreq(unsigned int device, unsigned int frequency) */
+.global setfreq
+setfreq:
+	stmfd 	sp!,{r14}
+	stmfd 	sp!,{r0-r12}
+
+	mov  	r8,sp
+	ldr 	sp,SRAM_STACK_V
+
+	/* ;Saving the function arguements for later use */
+	mov  	r4,r0
+	mov  	r5,r1
+
+	/* ;Putting DDR into self refresh */
+	ldr 	r0,DDR_07_V
+	ldr	r1,[r0]
+	ldr	r2,DDR_ACTIVE_V
+	bic	r1, r1, r2
+	str	r1,[r0]
+	ldr 	r0,DDR_57_V
+	ldr	r1,[r0]
+	ldr	r2,CYCLES_MASK_V
+	bic	r1, r1, r2
+	ldr	r2,REFRESH_CYCLES_V
+	orr	r1, r1, r2, lsl #16
+	str	r1,[r0]
+	ldr 	r0,DDR_07_V
+	ldr	r1,[r0]
+	ldr	r2,SREFRESH_MASK_V
+	orr	r1, r1, r2
+	str	r1,[r0]
+
+	b	1f
+	.align 5
+1:
+	/* ;Delay to ensure self refresh mode */
+	ldr  	r0,SREFRESH_DELAY_V
+1:
+	sub  	r0,r0,#1
+	cmp  	r0,#0
+	bne  	1b
+
+	/* ;Putting system in slow mode */
+	ldr  	r0,SCCTRL_V
+	mov  	r1,#2
+	str  	r1,[r0]
+
+	/* ;Changing PLL(1/2) frequency */
+	mov  	r0,r4
+	mov  	r1,r5
+
+	cmp  	r4,#0
+	beq  	1f
+
+	/* ;Change PLL2 (DDR frequency) */
+	ldr  	r6,PLL2_FREQ_V
+	ldr  	r7,PLL2_CNTL_V
+	b    	2f
+
+1:
+	/* ;Change PLL1 (CPU frequency) */
+	ldr  	r6,PLL1_FREQ_V
+	ldr  	r7,PLL1_CNTL_V
+
+2:
+	mov  	r0,r6
+	ldr  	r1,[r0]
+	ldr  	r2,PLLFREQ_MASK_V
+	bic  	r1,r1,r2
+	mov  	r2,r5,lsr#1
+	orr  	r1,r1,r2,lsl#24
+	str  	r1,[r0]
+
+	mov  	r0,r7
+	ldr  	r1,P1C0A_V
+	str  	r1,[r0]
+	/* ;ldr  r0,r7 */
+	ldr  	r1,P1C0E_V
+	str  	r1,[r0]
+	/* ;ldr  r0,r7 */
+	ldr  	r1,P1C06_V
+	str  	r1,[r0]
+	/* ;ldr  r0,r7 */
+	ldr  	r1,P1C0E_V
+	str  	r1,[r0]
+
+1:
+	ldr  	r1,[r0]
+	and  	r1,r1,#1
+	cmp  	r1,#0
+	beq  	1b
+
+	/* ;Putting system back to normal mode */
+	ldr  	r0,SCCTRL_V
+	mov  	r1,#4
+	str  	r1,[r0]
+
+	/* ;Putting DDR back to normal */
+	ldr 	r0,DDR_07_V
+	ldr	r1,[R0]
+	ldr	r2,SREFRESH_MASK_V
+	bic	r1, r1, r2
+	str	r1,[r0]
+	ldr	r2,DDR_ACTIVE_V
+	orr	r1, r1, r2
+	str	r1,[r0]
+
+	/* ;Delay to ensure self refresh mode */
+	ldr  	r0,SREFRESH_DELAY_V
+1:
+	sub  	r0,r0,#1
+	cmp  	r0,#0
+	bne  	1b
+
+	mov  	sp,r8
+	/* ;Resuming back to code */
+	ldmia 	sp!,{r0-r12}
+	ldmia 	sp!,{pc}
+
+SCCTRL_V:
+	.word 0xfca00000
+PLL1_FREQ_V:
+	.word 0xfca8000C
+PLL1_CNTL_V:
+	.word 0xfca80008
+PLL2_FREQ_V:
+	.word 0xfca80018
+PLL2_CNTL_V:
+	.word 0xfca80014
+PLLFREQ_MASK_V:
+	.word 0xff000000
+P1C0A_V:
+	.word 0x1C0A
+P1C0E_V:
+	.word 0x1C0E
+P1C06_V:
+	.word 0x1C06
+
+SREFRESH_DELAY_V:
+	.word 0x9999
+SRAM_STACK_V:
+	.word 0xD2800600
+DDR_07_V:
+	.word 0xfc60001c
+DDR_ACTIVE_V:
+	.word 0x01000000
+DDR_57_V:
+	.word 0xfc6000e4
+CYCLES_MASK_V:
+	.word 0xffff0000
+REFRESH_CYCLES_V:
+	.word 0xf0f0
+SREFRESH_MASK_V:
+	.word 0x00010000
+
+.global setfreq_sz
+setfreq_sz:
+	.word setfreq_sz - setfreq
diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
new file mode 100755
index 0000000..3fbeba7
--- /dev/null
+++ b/board/spear/common/spr_misc.c
@@ -0,0 +1,163 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <net.h>
+#include <asm/io.h>
+#include <asm/arch/spr_xloader_table.h>
+#include <asm/arch/spr_defs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+static struct chip_data chip_data;
+
+int dram_init(void)
+{
+	struct xloader_table *xloader_tb =
+	    (struct xloader_table *)XLOADER_TABLE_ADDRESS;
+	struct xloader_table_1_1 *table_1_1;
+	struct xloader_table_1_2 *table_1_2;
+	struct chip_data *chip = &chip_data;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1,
+					       PHYS_SDRAM_1_MAXSIZE);
+
+	if (XLOADER_TABLE_VERSION_1_1 == xloader_tb->table_version) {
+		table_1_1 = &xloader_tb->table.table_1_1;
+		chip->dramfreq = table_1_1->ddrfreq;
+		chip->dramtype = table_1_1->ddrtype;
+
+	} else if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) {
+		table_1_2 = &xloader_tb->table.table_1_2;
+		chip->dramfreq = table_1_2->ddrfreq;
+		chip->dramtype = table_1_2->ddrtype;
+	} else {
+		chip->dramfreq = -1;
+	}
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	setenv("verify", "n");
+	return 0;
+}
+
+int spear_board_init(ulong mach_type)
+{
+	struct xloader_table *xloader_tb =
+	    (struct xloader_table *)XLOADER_TABLE_ADDRESS;
+	struct xloader_table_1_2 *table_1_2;
+	struct chip_data *chip = &chip_data;
+
+	gd->bd->bi_arch_number = mach_type;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR;
+
+	/* CPU is initialized to work at 333MHz in Xloader */
+	chip->cpufreq = 333;
+
+	if (XLOADER_TABLE_VERSION_1_2 == xloader_tb->table_version) {
+		table_1_2 = &xloader_tb->table.table_1_2;
+		memcpy(chip->version, table_1_2->version,
+		       sizeof(chip->version));
+	}
+
+	return 0;
+}
+
+#define CPU 0
+#define DDR 1
+
+int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	void (*sram_setfreq) (unsigned int, unsigned int);
+	struct chip_data *chip = &chip_data;
+	unsigned int frequency;
+
+	if ((argc > 3) || (argc < 2)) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	if ((!strcmp(argv[1], "cpufreq")) || (!strcmp(argv[1], "ddrfreq"))) {
+
+		frequency = simple_strtoul(argv[2], NULL, 0);
+
+		if (frequency > 333) {
+			printf("Frequency is limited to 333MHz\n");
+			return 1;
+		}
+
+		sram_setfreq = memcpy((void *)0xD2801000, setfreq, setfreq_sz);
+
+		if (!strcmp(argv[1], "cpufreq")) {
+			sram_setfreq(CPU, frequency);
+			printf("CPU frequency changed to %u\n", frequency);
+
+			chip->cpufreq = frequency;
+		} else {
+			sram_setfreq(DDR, frequency);
+			printf("DDR frequency changed to %u\n", frequency);
+
+			chip->dramfreq = frequency;
+		}
+
+		return 0;
+	} else if (!strcmp(argv[1], "display")) {
+
+		if (chip->cpufreq == -1)
+			printf("CPU Freq    = Not Known\n");
+		else
+			printf("CPU Freq    = %d MHz\n", chip->cpufreq);
+
+		if (chip->dramfreq == -1)
+			printf("DDR Freq    = Not Known\n");
+		else
+			printf("DDR Freq    = %d MHz\n", chip->dramfreq);
+
+		if (chip->dramtype == DDRMOBILE)
+			printf("DDR Type    = MOBILE\n");
+		else if (chip->dramtype == DDR2)
+			printf("DDR Type    = DDR2\n");
+		else
+			printf("DDR Type    = Not Known\n");
+
+		printf("Xloader Rev = %s\n", chip->version);
+
+		return 0;
+	}
+
+	cmd_usage(cmdtp);
+	return 1;
+}
+
+U_BOOT_CMD(chip_config, 3, 1, do_chip_config,
+	   "configure chip",
+	   "ethaddr XX:XX:XX:XX:XX:XX\n"
+	   "chip_config cpufreq/ddrfreq frequency\n"
+	   "chip_config display");
diff --git a/board/spear/spear600/Makefile b/board/spear/spear600/Makefile
new file mode 100755
index 0000000..1978002
--- /dev/null
+++ b/board/spear/spear600/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= spear600.o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk
new file mode 100755
index 0000000..0bbb40f
--- /dev/null
+++ b/board/spear/spear600/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2009
+# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#########################################################################
+
+TEXT_BASE = 0x00700000
+
+ALL += $(obj)u-boot.img
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
new file mode 100755
index 0000000..8984358
--- /dev/null
+++ b/board/spear/spear600/spear600.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+
+int board_init(void)
+{
+	return spear_board_init(MACH_TYPE_SPEAR600);
+}
diff --git a/cpu/arm926ejs/spear/Makefile b/cpu/arm926ejs/spear/Makefile
new file mode 100755
index 0000000..bf8dfa8
--- /dev/null
+++ b/cpu/arm926ejs/spear/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	:= reset.o \
+	   timer.o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm926ejs/spear/reset.c b/cpu/arm926ejs/spear/reset.c
new file mode 100755
index 0000000..4df46a9
--- /dev/null
+++ b/cpu/arm926ejs/spear/reset.c
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/spr_syscntl.h>
+
+void reset_cpu(ulong ignored)
+{
+	struct syscntl_regs *syscntl_regs_p =
+	    (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
+
+	printf("System is going to reboot ...\n");
+
+	/*
+	 * This 1 second delay will allow the above message
+	 * to be printed before reset
+	 */
+	udelay((1000 * 1000));
+
+	/* Going into slow mode before resetting SOC */
+	writel(0x02, &syscntl_regs_p->scctrl);
+
+	/*
+	 * Writing any value to the system status register will
+	 * reset the SoC
+	 */
+	writel(0x00, &syscntl_regs_p->scsysstat);
+
+	/* system will restart */
+	while (1)
+		;
+}
diff --git a/cpu/arm926ejs/spear/timer.c b/cpu/arm926ejs/spear/timer.c
new file mode 100755
index 0000000..2a265fb
--- /dev/null
+++ b/cpu/arm926ejs/spear/timer.c
@@ -0,0 +1,150 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/spr_gpt.h>
+#include <asm/arch/spr_misc.h>
+
+#define GPT_RESOLUTION	(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
+#define READ_TIMER()	(readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
+
+static struct gpt_regs *const gpt_regs_p =
+    (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
+
+static struct misc_regs *const misc_regs_p =
+    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init(void)
+{
+	u32 synth;
+
+	/* Prescaler setting */
+#if defined(CONFIG_SPEAR3XX)
+	writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg);
+	synth = MISC_GPT4SYNTH;
+#elif defined(CONFIG_SPEAR600)
+	writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
+	synth = MISC_GPT3SYNTH;
+#endif
+
+	writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
+	       &misc_regs_p->periph_clk_cfg);
+
+	/* disable timers */
+	writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
+
+	/* load value for free running */
+	writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
+
+	/* auto reload, start timer */
+	writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
+
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return (get_timer_masked() / GPT_RESOLUTION) - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong tmo;
+	ulong start = get_timer_masked();
+	ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
+	ulong rndoff;
+
+	rndoff = (usec % 10) ? 1 : 0;
+
+	/* tenudelcnt timer tick gives 10 microsecconds delay */
+	tmo = ((usec / 10) + rndoff) * tenudelcnt;
+
+	while ((ulong) (get_timer_masked() - start) < tmo)
+		;
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	lastdec = READ_TIMER();
+	timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER();
+
+	if (now >= lastdec) {
+		/* normal mode */
+		timestamp += now - lastdec;
+	} else {
+		/* we have an overflow ... */
+		timestamp += now + GPT_FREE_RUNNING - lastdec;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void udelay_masked(unsigned long usec)
+{
+	return udelay(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/include/asm-arm/arch-spear/spr_defs.h b/include/asm-arm/arch-spear/spr_defs.h
new file mode 100644
index 0000000..9dde54a
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_defs.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPR_DEFS_H__
+#define __SPR_DEFS_H__
+
+extern int spear_board_init(ulong);
+extern void setfreq(unsigned int, unsigned int);
+extern unsigned int setfreq_sz;
+
+struct chip_data {
+	int cpufreq;
+	int dramfreq;
+	int dramtype;
+	uchar version[32];
+};
+
+#endif
diff --git a/include/asm-arm/arch-spear/spr_gpt.h b/include/asm-arm/arch-spear/spr_gpt.h
new file mode 100755
index 0000000..8e62391
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_gpt.h
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPR_GPT_H
+#define _SPR_GPT_H
+
+struct gpt_regs {
+	u8 reserved[0x80];
+	u32 control;
+	u32 status;
+	u32 compare;
+	u32 count;
+	u32 capture_re;
+	u32 capture_fe;
+};
+
+/*
+ * TIMER_CONTROL register settings
+ */
+
+#define GPT_PRESCALER_MASK		0x000F
+#define GPT_PRESCALER_1			0x0000
+#define GPT_PRESCALER_2 		0x0001
+#define GPT_PRESCALER_4 		0x0002
+#define GPT_PRESCALER_8 		0x0003
+#define GPT_PRESCALER_16		0x0004
+#define GPT_PRESCALER_32		0x0005
+#define GPT_PRESCALER_64		0x0006
+#define GPT_PRESCALER_128		0x0007
+#define GPT_PRESCALER_256		0x0008
+
+#define GPT_MODE_SINGLE_SHOT		0x0010
+#define GPT_MODE_AUTO_RELOAD		0x0000
+
+#define GPT_ENABLE          		0x0020
+
+#define GPT_CAPT_MODE_MASK  		0x00C0
+#define GPT_CAPT_MODE_NONE  		0x0000
+#define GPT_CAPT_MODE_RE    		0x0040
+#define GPT_CAPT_MODE_FE    		0x0080
+#define GPT_CAPT_MODE_BOTH  		0x00C0
+
+#define GPT_INT_MATCH       		0x0100
+
+#define GPT_INT_FE          		0x0200
+
+#define GPT_INT_RE          		0x0400
+
+/*
+ * TIMER_STATUS register settings
+ */
+
+#define GPT_STS_MATCH			0x0001
+#define GPT_STS_FE			0x0002
+#define GPT_STS_RE			0x0004
+
+/*
+ * TIMER_COMPARE register settings
+ */
+
+#define GPT_FREE_RUNNING		0xFFFF
+
+#endif
diff --git a/include/asm-arm/arch-spear/spr_misc.h b/include/asm-arm/arch-spear/spr_misc.h
new file mode 100644
index 0000000..8b96d9b
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_misc.h
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPR_MISC_H
+#define _SPR_MISC_H
+
+struct misc_regs {
+	u32 auto_cfg_reg;	/* 0x0 */
+	u32 armdbg_ctr_reg;	/* 0x4 */
+	u32 pll1_cntl;		/* 0x8 */
+	u32 pll1_frq;		/* 0xc */
+	u32 pll1_mod;		/* 0x10 */
+	u32 pll2_cntl;		/* 0x14 */
+	u32 pll2_frq;		/* 0x18 */
+	u32 pll2_mod;		/* 0x1C */
+	u32 pll_ctr_reg;	/* 0x20 */
+	u32 amba_clk_cfg;	/* 0x24 */
+	u32 periph_clk_cfg;	/* 0x28 */
+	u32 periph1_clken;	/* 0x2C */
+	u32 periph2_clken;	/* 0x30 */
+	u32 ras_clken;		/* 0x34 */
+	u32 periph1_rst;	/* 0x38 */
+	u32 periph2_rst;	/* 0x3C */
+	u32 ras_rst;		/* 0x40 */
+	u32 prsc1_clk_cfg;	/* 0x44 */
+	u32 prsc2_clk_cfg;	/* 0x48 */
+	u32 prsc3_clk_cfg;	/* 0x4C */
+	u32 amem_cfg_ctrl;	/* 0x50 */
+	u32 port_cfg_ctrl;	/* 0x54 */
+	u32 reserved_1;		/* 0x58 */
+	u32 clcd_synth_clk;	/* 0x5C */
+	u32 irda_synth_clk;	/* 0x60 */
+	u32 uart_synth_clk;	/* 0x64 */
+	u32 gmac_synth_clk;	/* 0x68 */
+	u32 ras_synth1_clk;	/* 0x6C */
+	u32 ras_synth2_clk;	/* 0x70 */
+	u32 ras_synth3_clk;	/* 0x74 */
+	u32 ras_synth4_clk;	/* 0x78 */
+	u32 arb_icm_ml1;	/* 0x7C */
+	u32 arb_icm_ml2;	/* 0x80 */
+	u32 arb_icm_ml3;	/* 0x84 */
+	u32 arb_icm_ml4;	/* 0x88 */
+	u32 arb_icm_ml5;	/* 0x8C */
+	u32 arb_icm_ml6;	/* 0x90 */
+	u32 arb_icm_ml7;	/* 0x94 */
+	u32 arb_icm_ml8;	/* 0x98 */
+	u32 arb_icm_ml9;	/* 0x9C */
+	u32 dma_src_sel;	/* 0xA0 */
+	u32 uphy_ctr_reg;	/* 0xA4 */
+	u32 gmac_ctr_reg;	/* 0xA8 */
+	u32 port_bridge_ctrl;	/* 0xAC */
+	u32 reserved_2[4];	/* 0xB0--0xBC */
+	u32 prc1_ilck_ctrl_reg;	/* 0xC0 */
+	u32 prc2_ilck_ctrl_reg;	/* 0xC4 */
+	u32 prc3_ilck_ctrl_reg;	/* 0xC8 */
+	u32 prc4_ilck_ctrl_reg;	/* 0xCC */
+	u32 prc1_intr_ctrl_reg;	/* 0xD0 */
+	u32 prc2_intr_ctrl_reg;	/* 0xD4 */
+	u32 prc3_intr_ctrl_reg;	/* 0xD8 */
+	u32 prc4_intr_ctrl_reg;	/* 0xDC */
+	u32 powerdown_cfg_reg;	/* 0xE0 */
+	u32 ddr_1v8_compensation;	/* 0xE4  */
+	u32 ddr_2v5_compensation;	/* 0xE8 */
+	u32 core_3v3_compensation;	/* 0xEC */
+	u32 ddr_pad;		/* 0xF0 */
+	u32 bist1_ctr_reg;	/* 0xF4 */
+	u32 bist2_ctr_reg;	/* 0xF8 */
+	u32 bist3_ctr_reg;	/* 0xFC */
+	u32 bist4_ctr_reg;	/* 0x100 */
+	u32 bist5_ctr_reg;	/* 0x104 */
+	u32 bist1_rslt_reg;	/* 0x108 */
+	u32 bist2_rslt_reg;	/* 0x10C */
+	u32 bist3_rslt_reg;	/* 0x110 */
+	u32 bist4_rslt_reg;	/* 0x114 */
+	u32 bist5_rslt_reg;	/* 0x118 */
+	u32 syst_error_reg;	/* 0x11C */
+	u32 reserved_3[0x1FB8];	/* 0x120--0x7FFC */
+	u32 ras_gpp1_in;	/* 0x8000 */
+	u32 ras_gpp2_in;	/* 0x8004 */
+	u32 ras_gpp1_out;	/* 0x8008 */
+	u32 ras_gpp2_out;	/* 0x800C */
+};
+
+/* AUTO_CFG_REG value */
+#define MISC_SOCCFGMSK                  0x0000003F
+#define MISC_SOCCFG30                   0x0000000C
+#define MISC_SOCCFG31                   0x0000000D
+#define MISC_NANDDIS			0x00020000
+
+/* PERIPH_CLK_CFG value */
+#define MISC_GPT3SYNTH			0x00000400
+#define MISC_GPT4SYNTH			0x00000800
+
+/* PRSC_CLK_CFG value */
+/*
+ * Fout = Fin / (2^(N+1) * (M + 1))
+ */
+#define MISC_PRSC_N_1			0x00001000
+#define MISC_PRSC_M_9			0x00000009
+#define MISC_PRSC_N_4			0x00004000
+#define MISC_PRSC_M_399			0x0000018F
+#define MISC_PRSC_N_6			0x00006000
+#define MISC_PRSC_M_2593		0x00000A21
+#define MISC_PRSC_M_124			0x0000007C
+#define MISC_PRSC_CFG			(MISC_PRSC_N_1 | MISC_PRSC_M_9)
+
+/* PERIPH1_CLKEN, PERIPH1_RST value */
+#define MISC_USBDENB			0x01000000
+
+#endif
diff --git a/include/asm-arm/arch-spear/spr_syscntl.h b/include/asm-arm/arch-spear/spr_syscntl.h
new file mode 100644
index 0000000..3c92f09
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_syscntl.h
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2009
+ * Ryan CHEN, ST Micoelectronics, ryan.chen at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+struct syscntl_regs {
+	u32 scctrl;
+	u32 scsysstat;
+	u32 scimctrl;
+	u32 scimsysstat;
+	u32 scxtalctrl;
+	u32 scpllctrl;
+	u32 scpllfctrl;
+	u32 scperctrl0;
+	u32 scperctrl1;
+	u32 scperen;
+	u32 scperdis;
+	const u32 scperclken;
+	const u32 scperstat;
+};
diff --git a/include/asm-arm/arch-spear/spr_xloader_table.h b/include/asm-arm/arch-spear/spr_xloader_table.h
new file mode 100755
index 0000000..3eac235
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_xloader_table.h
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SPR_XLOADER_TABLE_H
+#define _SPR_XLOADER_TABLE_H
+
+#define XLOADER_TABLE_VERSION_1_1 	2
+#define XLOADER_TABLE_VERSION_1_2 	3
+
+#define XLOADER_TABLE_ADDRESS 0xD2801FF0
+
+#define DDRMOBILE	1
+#define DDR2 		2
+
+#define REV_BA		1
+#define REV_AA		2
+#define REV_AB		3
+
+struct xloader_table_1_1 {
+	unsigned short ddrfreq;
+	unsigned char ddrsize;
+	unsigned char ddrtype;
+
+	unsigned char soc_rev;
+} __attribute__ ((packed));
+
+struct xloader_table_1_2 {
+	unsigned const char *version;
+
+	unsigned short ddrfreq;
+	unsigned char ddrsize;
+	unsigned char ddrtype;
+
+	unsigned char soc_rev;
+} __attribute__ ((packed));
+
+union table_contents {
+	struct xloader_table_1_1 table_1_1;
+	struct xloader_table_1_2 table_1_2;
+};
+
+struct xloader_table {
+	unsigned char table_version;
+	union table_contents table;
+} __attribute__ ((packed));
+
+#endif
diff --git a/include/configs/spear.h b/include/configs/spear.h
new file mode 100755
index 0000000..7c74290
--- /dev/null
+++ b/include/configs/spear.h
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SPEAR600				1
+
+/*
+ * Serial Configuration (PL011)
+ */
+#define CONFIG_PL011_SERIAL
+#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
+#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1 }
+#define CONFIG_CONS_INDEX			0
+#define CONFIG_BAUDRATE				115200
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
+						57600, 115200 }
+#define CONFIG_SYS_SERIAL0			0xD0000000
+#define CONFIG_SYS_SERIAL1			0xD0080000
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/*
+ * Platform specific defines (SPEAr)
+ */
+#define CONFIG_SPEAR_SYSCNTLBASE		(0xFCA00000)
+#define CONFIG_SPEAR_TIMERBASE			(0xFC800000)
+#define CONFIG_SPEAR_MISCBASE			(0xFCA80000)
+
+#define CONFIG_SYS_HZ				(1000)
+#define CONFIG_SYS_HZ_CLOCK			(8300000)
+
+/*
+ * FLASH Configuration
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS		2
+#define CONFIG_SYS_FLASH_BASE			(0xF8000000)
+#define CONFIG_SYS_CS1_FLASH_BASE		(0xF9000000)
+#define CONFIG_SYS_FLASH_BANK_SIZE		(0x01000000)
+#define CONFIG_SYS_FLASH_ADDR_BASE		{CONFIG_SYS_FLASH_BASE, \
+						CONFIG_SYS_CS1_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT		128
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO		1
+#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)
+
+/*
+ * NAND FLASH Configuration
+ */
+#define CONFIG_NAND_SPEAR			1
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE		1
+
+/*
+ * Command support defines
+ */
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVES
+
+/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/*
+ * Default Environment Varible definitions
+ */
+#define CONFIG_BOOTDELAY			1
+#define CONFIG_BOOTARGS_NFS			"root=/dev/nfs ip=dhcp " \
+						"console=ttyS0 init=/bin/sh"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_ENV_IS_NOWHERE			1
+#define CONFIG_ENV_SIZE				0x02000
+#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
+#define CONFIG_CMDLINE_TAG			1
+#define CONFIG_SETUP_MEMORY_TAGS		1
+#define CONFIG_MISC_INIT_R			1
+#define CONFIG_ZERO_BOOTDELAY_CHECK		1
+#define CONFIG_AUTOBOOT_KEYED			1
+#define CONFIG_AUTOBOOT_STOP_STR		" "
+#define CONFIG_AUTOBOOT_PROMPT			\
+		"Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
+
+#define CONFIG_SYS_MEMTEST_START		0x00800000
+#define CONFIG_SYS_MEMTEST_END			0x04000000
+#define CONFIG_SYS_MALLOC_LEN			(1024*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE		128
+#define CONFIG_IDENT_STRING			"-SPEAr"
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT			"u-boot> "
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_CBSIZE			256
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
+						sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LOAD_ADDR			0x00800000
+#define CONFIG_SYS_CONSOLE_INFO_QUIET		1
+#define CONFIG_SYS_64BIT_VSPRINTF		1
+
+/*
+ * Stack sizes
+ */
+#define CONFIG_STACKSIZE			(128*1024)
+
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ			(4*1024)
+#define CONFIG_STACKSIZE_FIQ			(4*1024)
+#endif
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS			1
+#define PHYS_SDRAM_1				0x00000000
+#define PHYS_SDRAM_1_MAXSIZE			0x40000000
+
+#endif  /* __CONFIG_H */
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [U-Boot] [PATCH v3 03/11] SPEAr : Adding basic support for SPEAr300
  2010-01-08 13:48   ` [U-Boot] [PATCH v3 02/11] SPEAr : Adding basic support for SPEAr600 Vipin KUMAR
@ 2010-01-08 13:48     ` Vipin KUMAR
  2010-01-08 13:49       ` [U-Boot] [PATCH v3 04/11] SPEAr : Adding basic support for SPEAr310 Vipin KUMAR
  0 siblings, 1 reply; 13+ messages in thread
From: Vipin KUMAR @ 2010-01-08 13:48 UTC (permalink / raw)
  To: u-boot


Signed-off-by: Vipin <vipin.kumar@st.com>
---
 MAKEALL                         |    1 +
 Makefile                        |    1 +
 board/spear/spear300/Makefile   |   51 +++++++++++++++++++++++++++++++++++++++
 board/spear/spear300/config.mk  |   28 +++++++++++++++++++++
 board/spear/spear300/spear300.c |   31 +++++++++++++++++++++++
 include/configs/spear.h         |   17 ++++++++++--
 6 files changed, 126 insertions(+), 3 deletions(-)
 create mode 100755 board/spear/spear300/Makefile
 create mode 100755 board/spear/spear300/config.mk
 create mode 100755 board/spear/spear300/spear300.c

diff --git a/MAKEALL b/MAKEALL
index 8eb39e5..b39a77d 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -572,6 +572,7 @@ LIST_ARM9="			\
 	sheevaplug		\
 	smdk2400		\
 	smdk2410		\
+	spear300		\
 	spear600		\
 	trab			\
 	VCMA9			\
diff --git a/Makefile b/Makefile
index 47f0d23..499314f 100644
--- a/Makefile
+++ b/Makefile
@@ -3023,6 +3023,7 @@ smdk2400_config	:	unconfig
 smdk2410_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0
 
+spear300_config \
 spear600_config :	unconfig
 	@$(MKCONFIG) -n $@ -t $(@:_config=) spear arm arm926ejs $(@:_config=) spear spear
 
diff --git a/board/spear/spear300/Makefile b/board/spear/spear300/Makefile
new file mode 100755
index 0000000..b5168ff
--- /dev/null
+++ b/board/spear/spear300/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= spear300.o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/spear/spear300/config.mk b/board/spear/spear300/config.mk
new file mode 100755
index 0000000..0bbb40f
--- /dev/null
+++ b/board/spear/spear300/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2009
+# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#########################################################################
+
+TEXT_BASE = 0x00700000
+
+ALL += $(obj)u-boot.img
diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c
new file mode 100755
index 0000000..137f7b3
--- /dev/null
+++ b/board/spear/spear300/spear300.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+
+int board_init(void)
+{
+	return spear_board_init(MACH_TYPE_SPEAR300);
+}
diff --git a/include/configs/spear.h b/include/configs/spear.h
index 7c74290..f5a2471 100755
--- a/include/configs/spear.h
+++ b/include/configs/spear.h
@@ -28,21 +28,32 @@
  * High Level Configuration Options
  * (easy to change)
  */
+#if defined(CONFIG_MK_spear600)
 #define CONFIG_SPEAR600				1
+#elif defined(CONFIG_MK_spear300)
+#define CONFIG_SPEAR3XX				1
+#define CONFIG_SPEAR300				1
+#endif
 
 /*
  * Serial Configuration (PL011)
  */
 #define CONFIG_PL011_SERIAL
 #define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
-#define CONFIG_PL01x_PORTS			{ (void *)CONFIG_SYS_SERIAL0, \
+#define CONFIG_SYS_SERIAL0			0xD0000000
+
+#if defined(CONFIG_SPEAR600)
+#define CONFIG_SYS_SERIAL1			0xD0080000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
 						(void *)CONFIG_SYS_SERIAL1 }
+#elif defined(CONFIG_SPEAR300)
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0}
+#endif
+
 #define CONFIG_CONS_INDEX			0
 #define CONFIG_BAUDRATE				115200
 #define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
 						57600, 115200 }
-#define CONFIG_SYS_SERIAL0			0xD0000000
-#define CONFIG_SYS_SERIAL1			0xD0080000
 
 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [U-Boot] [PATCH v3 04/11] SPEAr : Adding basic support for SPEAr310
  2010-01-08 13:48     ` [U-Boot] [PATCH v3 03/11] SPEAr : Adding basic support for SPEAr300 Vipin KUMAR
@ 2010-01-08 13:49       ` Vipin KUMAR
  2010-01-08 13:49         ` [U-Boot] [PATCH v3 05/11] SPEAr : Adding basic support for SPEAr320 Vipin KUMAR
  0 siblings, 1 reply; 13+ messages in thread
From: Vipin KUMAR @ 2010-01-08 13:49 UTC (permalink / raw)
  To: u-boot


Signed-off-by: Vipin <vipin.kumar@st.com>
---
 MAKEALL                         |    1 +
 Makefile                        |    1 +
 board/spear/spear310/Makefile   |   51 +++++++++++++++++++++++++++++++++++++++
 board/spear/spear310/config.mk  |   28 +++++++++++++++++++++
 board/spear/spear310/spear310.c |   32 ++++++++++++++++++++++++
 include/configs/spear.h         |   33 ++++++++++++++++++++----
 6 files changed, 140 insertions(+), 6 deletions(-)
 create mode 100755 board/spear/spear310/Makefile
 create mode 100755 board/spear/spear310/config.mk
 create mode 100755 board/spear/spear310/spear310.c

diff --git a/MAKEALL b/MAKEALL
index b39a77d..6a2f66c 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -573,6 +573,7 @@ LIST_ARM9="			\
 	smdk2400		\
 	smdk2410		\
 	spear300		\
+	spear310		\
 	spear600		\
 	trab			\
 	VCMA9			\
diff --git a/Makefile b/Makefile
index 499314f..2bee80a 100644
--- a/Makefile
+++ b/Makefile
@@ -3024,6 +3024,7 @@ smdk2410_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0
 
 spear300_config \
+spear310_config \
 spear600_config :	unconfig
 	@$(MKCONFIG) -n $@ -t $(@:_config=) spear arm arm926ejs $(@:_config=) spear spear
 
diff --git a/board/spear/spear310/Makefile b/board/spear/spear310/Makefile
new file mode 100755
index 0000000..e67e941
--- /dev/null
+++ b/board/spear/spear310/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= spear310.o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/spear/spear310/config.mk b/board/spear/spear310/config.mk
new file mode 100755
index 0000000..0bbb40f
--- /dev/null
+++ b/board/spear/spear310/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2009
+# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#########################################################################
+
+TEXT_BASE = 0x00700000
+
+ALL += $(obj)u-boot.img
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
new file mode 100755
index 0000000..86c3e96
--- /dev/null
+++ b/board/spear/spear310/spear310.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2009
+ * Ryan Chen, ST Micoelectronics, ryan.chen at st.com.
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+
+int board_init(void)
+{
+	return spear_board_init(MACH_TYPE_SPEAR300);
+}
diff --git a/include/configs/spear.h b/include/configs/spear.h
index f5a2471..0a9bbe7 100755
--- a/include/configs/spear.h
+++ b/include/configs/spear.h
@@ -33,6 +33,9 @@
 #elif defined(CONFIG_MK_spear300)
 #define CONFIG_SPEAR3XX				1
 #define CONFIG_SPEAR300				1
+#elif defined(CONFIG_MK_spear310)
+#define CONFIG_SPEAR3XX				1
+#define CONFIG_SPEAR310				1
 #endif
 
 /*
@@ -41,6 +44,12 @@
 #define CONFIG_PL011_SERIAL
 #define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
 #define CONFIG_SYS_SERIAL0			0xD0000000
+#define CONFIG_CONS_INDEX			0
+#define CONFIG_BAUDRATE				115200
+#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
+						57600, 115200 }
+
+#define CONFIG_SYS_LOADS_BAUD_CHANGE
 
 #if defined(CONFIG_SPEAR600)
 #define CONFIG_SYS_SERIAL1			0xD0080000
@@ -48,14 +57,26 @@
 						(void *)CONFIG_SYS_SERIAL1 }
 #elif defined(CONFIG_SPEAR300)
 #define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0}
-#endif
 
-#define CONFIG_CONS_INDEX			0
-#define CONFIG_BAUDRATE				115200
-#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
-						57600, 115200 }
+#elif defined(CONFIG_SPEAR310)
 
-#define CONFIG_SYS_LOADS_BAUD_CHANGE
+#if (CONFIG_CONS_INDEX)
+#undef  CONFIG_PL011_CLOCK
+#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
+#endif
+
+#define CONFIG_SYS_SERIAL1			0xB2000000
+#define CONFIG_SYS_SERIAL2			0xB2080000
+#define CONFIG_SYS_SERIAL3			0xB2100000
+#define CONFIG_SYS_SERIAL4			0xB2180000
+#define CONFIG_SYS_SERIAL5			0xB2200000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1, \
+						(void *)CONFIG_SYS_SERIAL2, \
+						(void *)CONFIG_SYS_SERIAL3, \
+						(void *)CONFIG_SYS_SERIAL4, \
+						(void *)CONFIG_SYS_SERIAL5 }
+#endif
 
 /*
  * Platform specific defines (SPEAr)
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [U-Boot] [PATCH v3 05/11] SPEAr : Adding basic support for SPEAr320
  2010-01-08 13:49       ` [U-Boot] [PATCH v3 04/11] SPEAr : Adding basic support for SPEAr310 Vipin KUMAR
@ 2010-01-08 13:49         ` Vipin KUMAR
  2010-01-08 13:49           ` [U-Boot] [PATCH v3 06/11] SPEAr : i2c driver support addded Vipin KUMAR
  0 siblings, 1 reply; 13+ messages in thread
From: Vipin KUMAR @ 2010-01-08 13:49 UTC (permalink / raw)
  To: u-boot


Signed-off-by: Vipin <vipin.kumar@st.com>
---
 MAKEALL                         |    1 +
 Makefile                        |    1 +
 board/spear/spear320/Makefile   |   51 +++++++++++++++++++++++++++++++++++++++
 board/spear/spear320/config.mk  |   28 +++++++++++++++++++++
 board/spear/spear320/spear320.c |   32 ++++++++++++++++++++++++
 include/configs/spear.h         |   15 +++++++++++
 6 files changed, 128 insertions(+), 0 deletions(-)
 create mode 100755 board/spear/spear320/Makefile
 create mode 100755 board/spear/spear320/config.mk
 create mode 100755 board/spear/spear320/spear320.c

diff --git a/MAKEALL b/MAKEALL
index 6a2f66c..a76ab8f 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -574,6 +574,7 @@ LIST_ARM9="			\
 	smdk2410		\
 	spear300		\
 	spear310		\
+	spear320		\
 	spear600		\
 	trab			\
 	VCMA9			\
diff --git a/Makefile b/Makefile
index 2bee80a..bf28331 100644
--- a/Makefile
+++ b/Makefile
@@ -3025,6 +3025,7 @@ smdk2410_config	:	unconfig
 
 spear300_config \
 spear310_config \
+spear320_config \
 spear600_config :	unconfig
 	@$(MKCONFIG) -n $@ -t $(@:_config=) spear arm arm926ejs $(@:_config=) spear spear
 
diff --git a/board/spear/spear320/Makefile b/board/spear/spear320/Makefile
new file mode 100755
index 0000000..1b80586
--- /dev/null
+++ b/board/spear/spear320/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= spear320.o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk
new file mode 100755
index 0000000..0bbb40f
--- /dev/null
+++ b/board/spear/spear320/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2009
+# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#########################################################################
+
+TEXT_BASE = 0x00700000
+
+ALL += $(obj)u-boot.img
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
new file mode 100755
index 0000000..86c3e96
--- /dev/null
+++ b/board/spear/spear320/spear320.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2009
+ * Ryan Chen, ST Micoelectronics, ryan.chen at st.com.
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/spr_defs.h>
+#include <asm/arch/spr_misc.h>
+
+int board_init(void)
+{
+	return spear_board_init(MACH_TYPE_SPEAR300);
+}
diff --git a/include/configs/spear.h b/include/configs/spear.h
index 0a9bbe7..9c4cab3 100755
--- a/include/configs/spear.h
+++ b/include/configs/spear.h
@@ -36,6 +36,9 @@
 #elif defined(CONFIG_MK_spear310)
 #define CONFIG_SPEAR3XX				1
 #define CONFIG_SPEAR310				1
+#elif defined(CONFIG_MK_spear320)
+#define CONFIG_SPEAR3XX				1
+#define CONFIG_SPEAR320				1
 #endif
 
 /*
@@ -76,6 +79,18 @@
 						(void *)CONFIG_SYS_SERIAL3, \
 						(void *)CONFIG_SYS_SERIAL4, \
 						(void *)CONFIG_SYS_SERIAL5 }
+#elif defined(CONFIG_SPEAR320)
+
+#if (CONFIG_CONS_INDEX)
+#undef  CONFIG_PL011_CLOCK
+#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
+#endif
+
+#define CONFIG_SYS_SERIAL1			0xA3000000
+#define CONFIG_SYS_SERIAL2			0xA4000000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1, \
+						(void *)CONFIG_SYS_SERIAL2 }
 #endif
 
 /*
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [U-Boot] [PATCH v3 06/11] SPEAr : i2c driver support addded
  2010-01-08 13:49         ` [U-Boot] [PATCH v3 05/11] SPEAr : Adding basic support for SPEAr320 Vipin KUMAR
@ 2010-01-08 13:49           ` Vipin KUMAR
  2010-01-08 13:49             ` [U-Boot] [PATCH v3 07/11] SPEAr : Support for HW macid read/write from i2c memory Vipin KUMAR
  2010-01-11  9:44             ` [U-Boot] [PATCH v3 06/11] SPEAr : i2c driver support addded Heiko Schocher
  0 siblings, 2 replies; 13+ messages in thread
From: Vipin KUMAR @ 2010-01-08 13:49 UTC (permalink / raw)
  To: u-boot


Signed-off-by: Vipin <vipin.kumar@st.com>
---
 drivers/i2c/Makefile                 |    1 +
 drivers/i2c/spr_i2c.c                |  340 ++++++++++++++++++++++++++++++++++
 include/asm-arm/arch-spear/spr_i2c.h |  146 +++++++++++++++
 include/configs/spear.h              |   11 +
 4 files changed, 498 insertions(+), 0 deletions(-)
 mode change 100644 => 100755 drivers/i2c/Makefile
 create mode 100755 drivers/i2c/spr_i2c.c
 create mode 100755 include/asm-arm/arch-spear/spr_i2c.h

diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
old mode 100644
new mode 100755
index b860e89..29bda85
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -37,6 +37,7 @@ COBJS-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
 COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
 COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o
 COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o
+COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
 COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
 
 COBJS	:= $(COBJS-y)
diff --git a/drivers/i2c/spr_i2c.c b/drivers/i2c/spr_i2c.c
new file mode 100755
index 0000000..497ca47
--- /dev/null
+++ b/drivers/i2c/spr_i2c.c
@@ -0,0 +1,340 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/spr_i2c.h>
+
+static struct i2c_regs *const i2c_regs_p =
+    (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
+
+/*
+ * set_speed - Set the i2c speed mode (standard, high, fast)
+ * @i2c_spd:	required i2c speed mode
+ *
+ * Set the i2c speed mode (standard, high, fast)
+ */
+static void set_speed(int i2c_spd)
+{
+	unsigned int cntl;
+	unsigned int hcnt, lcnt;
+	unsigned int high, low;
+
+	cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK));
+
+	switch (i2c_spd) {
+	case IC_SPEED_MODE_MAX:
+		cntl |= IC_CON_SPD_HS;
+		high = MIN_HS_SCL_HIGHTIME;
+		low = MIN_HS_SCL_LOWTIME;
+		break;
+
+	case IC_SPEED_MODE_STANDARD:
+		cntl |= IC_CON_SPD_SS;
+		high = MIN_SS_SCL_HIGHTIME;
+		low = MIN_SS_SCL_LOWTIME;
+		break;
+
+	case IC_SPEED_MODE_FAST:
+	default:
+		cntl |= IC_CON_SPD_FS;
+		high = MIN_FS_SCL_HIGHTIME;
+		low = MIN_FS_SCL_LOWTIME;
+		break;
+	}
+
+	writel(cntl, &i2c_regs_p->ic_con);
+
+	hcnt = (IC_CLK * high) / NANO_TO_MICRO;
+	writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt);
+
+	lcnt = (IC_CLK * low) / NANO_TO_MICRO;
+	writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt);
+}
+
+/*
+ * i2c_set_bus_speed - Set the i2c speed
+ * @speed:	required i2c speed
+ *
+ * Set the i2c speed.
+ */
+void i2c_set_bus_speed(int speed)
+{
+	if (speed >= I2C_MAX_SPEED) {
+		set_speed(IC_SPEED_MODE_MAX);
+
+	} else if (speed >= I2C_FAST_SPEED) {
+		set_speed(IC_SPEED_MODE_FAST);
+
+	} else {
+		set_speed(IC_SPEED_MODE_STANDARD);
+	}
+}
+
+/*
+ * i2c_get_bus_speed - Gets the i2c speed
+ *
+ * Gets the i2c speed.
+ */
+int i2c_get_bus_speed(void)
+{
+	u32 cntl;
+
+	cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK);
+
+	if (cntl == IC_CON_SPD_HS) {
+		return I2C_MAX_SPEED;
+
+	} else if (cntl == IC_CON_SPD_FS) {
+		return I2C_FAST_SPEED;
+
+	} else if (cntl == IC_CON_SPD_SS) {
+		return I2C_STANDARD_SPEED;
+	}
+
+	return 0;
+}
+
+/*
+ * i2c_init - Init function
+ * @speed:	required i2c speed
+ * @slaveadd:	slave address for the spear device
+ *
+ * Initialization function.
+ */
+void i2c_init(int speed, int slaveadd)
+{
+	unsigned int enbl;
+
+	/* Disable i2c */
+	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl &= ~IC_ENABLE_0B;
+	writel(enbl, &i2c_regs_p->ic_enable);
+
+	writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con);
+	writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl);
+	writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl);
+	i2c_set_bus_speed(speed);
+	writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask);
+	writel(slaveadd, &i2c_regs_p->ic_sar);
+
+	/* Enable i2c */
+	enbl = readl(&i2c_regs_p->ic_enable);
+	enbl |= IC_ENABLE_0B;
+	writel(enbl, &i2c_regs_p->ic_enable);
+}
+
+/*
+ * i2c_setaddress - Sets the target slave address
+ * @i2c_addr:	target i2c address
+ *
+ * Sets the target slave address.
+ */
+static void i2c_setaddress(unsigned int i2c_addr)
+{
+	writel(i2c_addr, &i2c_regs_p->ic_tar);
+}
+
+/*
+ * i2c_flush_rxfifo - Flushes the i2c RX FIFO
+ *
+ * Flushes the i2c RX FIFO
+ */
+static void i2c_flush_rxfifo(void)
+{
+	while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE)
+		readl(&i2c_regs_p->ic_cmd_data);
+}
+
+/*
+ * i2c_wait_for_bb - Waits for bus busy
+ *
+ * Waits for bus busy
+ */
+static int i2c_wait_for_bb(void)
+{
+	unsigned long start_time_bb = get_timer(0);
+
+	while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) ||
+	       !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) {
+
+		/* Evaluate timeout */
+		if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
+			return 1;
+	}
+
+	return 0;
+}
+
+/* check parameters for i2c_read and i2c_write */
+static int check_params(uint addr, int alen, uchar *buffer, int len)
+{
+	if (buffer == NULL) {
+		printf("Buffer is invalid\n");
+		return 1;
+	}
+
+	if (alen > 1) {
+		printf("addr len %d not supported\n", alen);
+		return 1;
+	}
+
+	if (addr + len > 256) {
+		printf("address out of range\n");
+		return 1;
+	}
+
+	return 0;
+}
+
+static int i2c_xfer_init(uchar chip, uint addr)
+{
+	if (i2c_wait_for_bb()) {
+		printf("Timed out waiting for bus\n");
+		return 1;
+	}
+
+	i2c_setaddress(chip);
+	writel(addr, &i2c_regs_p->ic_cmd_data);
+
+	return 0;
+}
+
+static int i2c_xfer_finish(void)
+{
+	ulong start_stop_det = get_timer(0);
+
+	while (1) {
+		if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) {
+			readl(&i2c_regs_p->ic_clr_stop_det);
+			break;
+		} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
+			break;
+		}
+	}
+
+	if (i2c_wait_for_bb()) {
+		printf("Timed out waiting for bus\n");
+		return 1;
+	}
+
+	i2c_flush_rxfifo();
+
+	/* Wait for read/write operation to complete on actual memory */
+	udelay(10000);
+
+	return 0;
+}
+
+/*
+ * i2c_read - Read from i2c memory
+ * @chip:	target i2c address
+ * @addr:	address to read from
+ * @alen:
+ * @buffer:	buffer for read data
+ * @len:	no of bytes to be read
+ *
+ * Read from i2c memory.
+ */
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	unsigned long start_time_rx;
+
+	if (check_params(addr, alen, buffer, len)) {
+		return 1;
+	}
+
+	if (i2c_xfer_init(chip, addr)) {
+		return 1;
+	}
+
+	start_time_rx = get_timer(0);
+	while (len) {
+		writel(IC_CMD, &i2c_regs_p->ic_cmd_data);
+
+		if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) {
+			*buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data);
+			len--;
+			start_time_rx = get_timer(0);
+
+		} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
+				printf("Timed out. i2c read Failed\n");
+				return 1;
+		}
+	}
+
+	return i2c_xfer_finish();
+}
+
+/*
+ * i2c_write - Write to i2c memory
+ * @chip:	target i2c address
+ * @addr:	address to read from
+ * @alen:
+ * @buffer:	buffer for read data
+ * @len:	no of bytes to be read
+ *
+ * Write to i2c memory.
+ */
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+	int nb = len;
+	unsigned long start_time_tx;
+
+	if (check_params(addr, alen, buffer, len)) {
+		return 1;
+	}
+
+	if (i2c_xfer_init(chip, addr)) {
+		return 1;
+	}
+
+	start_time_tx = get_timer(0);
+	while (len) {
+		if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) {
+			writel(*buffer, &i2c_regs_p->ic_cmd_data);
+			buffer++;
+			len--;
+			start_time_tx = get_timer(0);
+
+		} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
+				printf("Timed out. i2c write Failed\n");
+				return 1;
+		}
+	}
+
+	return i2c_xfer_finish();
+}
+
+/*
+ * i2c_probe - Probe the i2c chip
+ */
+int i2c_probe(uchar chip)
+{
+	u32 tmp;
+
+	/*
+	 * Try to read the first location of the chip.
+	 */
+	return i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
+}
diff --git a/include/asm-arm/arch-spear/spr_i2c.h b/include/asm-arm/arch-spear/spr_i2c.h
new file mode 100755
index 0000000..7521ebc
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_i2c.h
@@ -0,0 +1,146 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPR_I2C_H_
+#define __SPR_I2C_H_
+
+struct i2c_regs {
+	u32 ic_con;
+	u32 ic_tar;
+	u32 ic_sar;
+	u32 ic_hs_maddr;
+	u32 ic_cmd_data;
+	u32 ic_ss_scl_hcnt;
+	u32 ic_ss_scl_lcnt;
+	u32 ic_fs_scl_hcnt;
+	u32 ic_fs_scl_lcnt;
+	u32 ic_hs_scl_hcnt;
+	u32 ic_hs_scl_lcnt;
+	u32 ic_intr_stat;
+	u32 ic_intr_mask;
+	u32 ic_raw_intr_stat;
+	u32 ic_rx_tl;
+	u32 ic_tx_tl;
+	u32 ic_clr_intr;
+	u32 ic_clr_rx_under;
+	u32 ic_clr_rx_over;
+	u32 ic_clr_tx_over;
+	u32 ic_clr_rd_req;
+	u32 ic_clr_tx_abrt;
+	u32 ic_clr_rx_done;
+	u32 ic_clr_activity;
+	u32 ic_clr_stop_det;
+	u32 ic_clr_start_det;
+	u32 ic_clr_gen_call;
+	u32 ic_enable;
+	u32 ic_status;
+	u32 ic_txflr;
+	u32 ix_rxflr;
+	u32 reserved_1;
+	u32 ic_tx_abrt_source;
+};
+
+#define IC_CLK			166
+#define NANO_TO_MICRO		1000
+
+/* High and low times in different speed modes (in ns) */
+#define MIN_SS_SCL_HIGHTIME	4000
+#define MIN_SS_SCL_LOWTIME	5000
+#define MIN_FS_SCL_HIGHTIME	800
+#define MIN_FS_SCL_LOWTIME	1700
+#define MIN_HS_SCL_HIGHTIME	60
+#define MIN_HS_SCL_LOWTIME	160
+
+/* Worst case timeout for 1 byte is kept as 2ms */
+#define I2C_BYTE_TO		(CONFIG_SYS_HZ/500)
+#define I2C_STOPDET_TO		(CONFIG_SYS_HZ/500)
+#define I2C_BYTE_TO_BB		(I2C_BYTE_TO * 16)
+
+/* i2c control register definitions */
+#define IC_CON_SD		0x0040
+#define IC_CON_RE		0x0020
+#define IC_CON_10BITADDRMASTER	0x0010
+#define IC_CON_10BITADDR_SLAVE	0x0008
+#define IC_CON_SPD_MSK		0x0006
+#define IC_CON_SPD_SS		0x0002
+#define IC_CON_SPD_FS		0x0004
+#define IC_CON_SPD_HS		0x0006
+#define IC_CON_MM		0x0001
+
+/* i2c target address register definitions */
+#define TAR_ADDR		0x0050
+
+/* i2c slave address register definitions */
+#define IC_SLAVE_ADDR		0x0002
+
+/* i2c data buffer and command register definitions */
+#define IC_CMD			0x0100
+
+/* i2c interrupt status register definitions */
+#define IC_GEN_CALL		0x0800
+#define IC_START_DET		0x0400
+#define IC_STOP_DET		0x0200
+#define IC_ACTIVITY		0x0100
+#define IC_RX_DONE		0x0080
+#define IC_TX_ABRT		0x0040
+#define IC_RD_REQ		0x0020
+#define IC_TX_EMPTY		0x0010
+#define IC_TX_OVER		0x0008
+#define IC_RX_FULL		0x0004
+#define IC_RX_OVER 		0x0002
+#define IC_RX_UNDER		0x0001
+
+/* fifo threshold register definitions */
+#define IC_TL0			0x00
+#define IC_TL1			0x01
+#define IC_TL2			0x02
+#define IC_TL3			0x03
+#define IC_TL4			0x04
+#define IC_TL5			0x05
+#define IC_TL6			0x06
+#define IC_TL7			0x07
+#define IC_RX_TL		IC_TL0
+#define IC_TX_TL		IC_TL0
+
+/* i2c enable register definitions */
+#define IC_ENABLE_0B		0x0001
+
+/* i2c status register  definitions */
+#define IC_STATUS_SA		0x0040
+#define IC_STATUS_MA		0x0020
+#define IC_STATUS_RFF		0x0010
+#define IC_STATUS_RFNE		0x0008
+#define IC_STATUS_TFE		0x0004
+#define IC_STATUS_TFNF		0x0002
+#define IC_STATUS_ACT		0x0001
+
+/* Speed Selection */
+#define IC_SPEED_MODE_STANDARD	1
+#define IC_SPEED_MODE_FAST	2
+#define IC_SPEED_MODE_MAX	3
+
+#define I2C_MAX_SPEED		3400000
+#define I2C_FAST_SPEED		400000
+#define I2C_STANDARD_SPEED	100000
+
+#endif /* __SPR_I2C_H_ */
diff --git a/include/configs/spear.h b/include/configs/spear.h
index 9c4cab3..4a6458d 100755
--- a/include/configs/spear.h
+++ b/include/configs/spear.h
@@ -42,6 +42,14 @@
 #endif
 
 /*
+ * I2C driver configuration
+ */
+#define CONFIG_HARD_I2C
+#define CONFIG_SPEAR_I2C
+#define CONFIG_SYS_I2C_SPEED			400000
+#define CONFIG_SYS_I2C_SLAVE			0x02
+
+/*
  * Serial Configuration (PL011)
  */
 #define CONFIG_PL011_SERIAL
@@ -100,6 +108,8 @@
 #define CONFIG_SPEAR_TIMERBASE			(0xFC800000)
 #define CONFIG_SPEAR_MISCBASE			(0xFCA80000)
 
+#define CONFIG_SYS_I2C_BASE			(0xD0200000)
+
 #define CONFIG_SYS_HZ				(1000)
 #define CONFIG_SYS_HZ_CLOCK			(8300000)
 
@@ -128,6 +138,7 @@
 /*
  * Command support defines
  */
+#define CONFIG_CMD_I2C
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_RUN
 #define CONFIG_CMD_SAVES
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [U-Boot] [PATCH v3 07/11] SPEAr : Support for HW macid read/write from i2c memory
  2010-01-08 13:49           ` [U-Boot] [PATCH v3 06/11] SPEAr : i2c driver support addded Vipin KUMAR
@ 2010-01-08 13:49             ` Vipin KUMAR
  2010-01-08 13:49               ` [U-Boot] [PATCH v3 08/11] SPEAr : Support for serial memory interface driver and serial NOR flash Vipin KUMAR
  2010-01-11  9:44             ` [U-Boot] [PATCH v3 06/11] SPEAr : i2c driver support addded Heiko Schocher
  1 sibling, 1 reply; 13+ messages in thread
From: Vipin KUMAR @ 2010-01-08 13:49 UTC (permalink / raw)
  To: u-boot


Signed-off-by: Vipin <vipin.kumar@st.com>
---
 board/spear/common/spr_misc.c |   70 ++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 69 insertions(+), 1 deletions(-)

diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
index 3fbeba7..c4e3a1a 100755
--- a/board/spear/common/spr_misc.c
+++ b/board/spear/common/spr_misc.c
@@ -62,6 +62,13 @@ int dram_init(void)
 
 int misc_init_r(void)
 {
+#if defined(CONFIG_CMD_NET)
+	uchar mac_id[6];
+
+	if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id)) {
+		eth_setenv_enetaddr("ethaddr", mac_id);
+	}
+#endif
 	setenv("verify", "n");
 	return 0;
 }
@@ -90,6 +97,46 @@ int spear_board_init(ulong mach_type)
 	return 0;
 }
 
+static int i2c_read_mac(uchar *buffer)
+{
+	u8 buf[2];
+
+	i2c_read(0x50, 0x0, 1, buf, 2);
+
+	/* Check if mac in i2c memory is valid */
+	if ((buf[0] == 0x55) && (buf[1] == 0xAA)) {
+		/* Valid mac address is saved in i2c eeprom */
+		i2c_read(0x50, 0x2, 1, buffer, 6);
+		return 0;
+	}
+
+	return -1;
+}
+
+static int write_mac(uchar *mac)
+{
+	unsigned char buf[2];
+
+	buf[0] = 0x55;
+	buf[1] = 0xAA;
+	i2c_write(0x50, 0x0, 1, buf, 2);
+
+	buf[0] = 0x44;
+	buf[1] = 0x66;
+
+	i2c_read(0x50, 0x0, 1, buf, 2);
+
+	/* check if valid MAC address is saved in I2C EEPROM or not? */
+	if ((buf[0] == 0x55) && (buf[1] == 0xAA)) {
+		i2c_write(0x50, 0x2, 1, mac, 6);
+		puts("I2C EEPROM written with mac address \n");
+		return 0;
+	}
+
+	puts("I2C EEPROM writing failed \n");
+	return -1;
+}
+
 #define CPU 0
 #define DDR 1
 
@@ -97,7 +144,10 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	void (*sram_setfreq) (unsigned int, unsigned int);
 	struct chip_data *chip = &chip_data;
-	unsigned int frequency;
+	unsigned char mac[6];
+	unsigned int reg, frequency;
+	char *s, *e;
+	char i2c_mac[20];
 
 	if ((argc > 3) || (argc < 2)) {
 		cmd_usage(cmdtp);
@@ -128,6 +178,17 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		}
 
 		return 0;
+	} else if (!strcmp(argv[1], "ethaddr")) {
+
+		s = argv[2];
+		for (reg = 0; reg < 6; ++reg) {
+			mac[reg] = s ? simple_strtoul(s, &e, 16) : 0;
+			if (s)
+				s = (*e) ? e + 1 : e;
+		}
+		write_mac(mac);
+
+		return 0;
 	} else if (!strcmp(argv[1], "display")) {
 
 		if (chip->cpufreq == -1)
@@ -147,6 +208,13 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 		else
 			printf("DDR Type    = Not Known\n");
 
+		if (!i2c_read_mac(mac)) {
+			sprintf(i2c_mac, "%pM", mac);
+			printf("Ethaddr (from i2c mem) = %s\n", i2c_mac);
+		} else {
+			printf("Ethaddr (from i2c mem) = Not set\n");
+		}
+
 		printf("Xloader Rev = %s\n", chip->version);
 
 		return 0;
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [U-Boot] [PATCH v3 08/11] SPEAr : Support for serial memory interface driver and serial NOR flash
  2010-01-08 13:49             ` [U-Boot] [PATCH v3 07/11] SPEAr : Support for HW macid read/write from i2c memory Vipin KUMAR
@ 2010-01-08 13:49               ` Vipin KUMAR
  2010-01-08 13:49                 ` [U-Boot] [PATCH v3 09/11] SPEAr : Support for nand driver Vipin KUMAR
  0 siblings, 1 reply; 13+ messages in thread
From: Vipin KUMAR @ 2010-01-08 13:49 UTC (permalink / raw)
  To: u-boot


Signed-off-by: Vipin <vipin.kumar@st.com>
---
 drivers/mtd/Makefile                 |    1 +
 drivers/mtd/spr_smi.c                |  530 ++++++++++++++++++++++++++++++++++
 include/asm-arm/arch-spear/spr_smi.h |  117 ++++++++
 include/configs/spear.h              |   35 ++-
 4 files changed, 681 insertions(+), 2 deletions(-)
 mode change 100644 => 100755 drivers/mtd/Makefile
 create mode 100755 drivers/mtd/spr_smi.c
 create mode 100755 include/asm-arm/arch-spear/spr_smi.h

diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
old mode 100644
new mode 100755
index 754d648..cbf6f15
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
 COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o
 COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
 COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o
+COBJS-$(CONFIG_SPEARSMI) += spr_smi.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/spr_smi.c
new file mode 100755
index 0000000..cb07e71
--- /dev/null
+++ b/drivers/mtd/spr_smi.c
@@ -0,0 +1,530 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <flash.h>
+#include <linux/err.h>
+
+#include <asm/io.h>
+#include <asm/arch/spr_smi.h>
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+
+static struct smi_regs *const smicntl =
+    (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
+static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_ADDR_BASE;
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+#define ST_M25Pxx_ID		0x00002020
+
+static struct flash_dev flash_ids[] = {
+	{0x10, 64 * 1024, 2},
+	{0x11, 128 * 1024, 4},
+	{0x12, 256 * 1024, 4},
+	{0x13, 512 * 1024, 8},
+	{0x14, 1 * 1024 * 1024, 16},
+	{0x15, 2 * 1024 * 1024, 32},
+	{0x16, 4 * 1024 * 1024, 64},
+	{0x17, 8 * 1024 * 1024, 128},
+	{0x18, 16 * 1024 * 1024, 64},
+	{0x00,}
+};
+
+/*
+ * smi_wait_xfer_finish - Wait until TFF is set in status register
+ * @timeout:	 timeout in milliseconds
+ *
+ * Wait until TFF is set in status register
+ */
+static inline void smi_wait_xfer_finish(int timeout)
+{
+	while (timeout--) {
+		if (readl(&smicntl->smi_sr) & TFF)
+			break;
+		udelay(1000);
+	}
+}
+
+/*
+ * smi_read_id - Read flash id
+ * @info:	 flash_info structure pointer
+ * @banknum:	 bank number
+ *
+ * Read the flash id present at bank #banknum
+ */
+static unsigned int smi_read_id(flash_info_t *info, int banknum)
+{
+	unsigned int value;
+
+	writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
+	writel(READ_ID, &smicntl->smi_tr);
+	writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3,
+	       &smicntl->smi_cr2);
+	smi_wait_xfer_finish(XFER_FINISH_TOUT);
+
+	value = (readl(&smicntl->smi_rr) & 0x00FFFFFF);
+
+	writel(readl(&smicntl->smi_sr) & ~(TFF), &smicntl->smi_sr);
+	writel(readl(&smicntl->smi_cr1) & ~(SW_MODE), &smicntl->smi_cr1);
+
+	return value;
+}
+
+/*
+ * flash_get_size - Detect the SMI flash by reading the ID.
+ * @base:	 Base address of the flash area bank #banknum
+ * @banknum:	 Bank number
+ *
+ * Detect the SMI flash by reading the ID. Initializes the flash_info structure
+ * with size, sector count etc.
+ */
+static ulong flash_get_size(ulong base, int banknum)
+{
+	flash_info_t *info = &flash_info[banknum];
+	struct flash_dev *dev;
+	unsigned int value;
+	unsigned int density;
+	int i;
+
+	value = smi_read_id(info, banknum);
+	density = (value >> 16) & 0xff;
+
+	for (i = 0, dev = &flash_ids[0]; dev->density != 0x0;
+	     i++, dev = &flash_ids[i]) {
+		if (dev->density == density) {
+			info->size = dev->size;
+			info->sector_count = dev->sector_count;
+			break;
+		}
+	}
+
+	if (0x0 == dev->density)
+		return 0;
+
+	info->flash_id = value & 0xffff;
+	info->start[0] = base;
+
+	return info->size;
+}
+
+/*
+ * smi_read_sr - Read status register of SMI
+ * @bank:	 bank number
+ *
+ * This routine will get the status register of the flash chip present at the
+ * given bank
+ */
+static int smi_read_sr(int bank)
+{
+	u32 ctrlreg1;
+
+	/* store the CTRL REG1 state */
+	ctrlreg1 = readl(&smicntl->smi_cr1);
+
+	/* Program SMI in HW Mode */
+	writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE),
+	       &smicntl->smi_cr1);
+
+	/* Performing a RSR instruction in HW mode */
+	writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2);
+
+	smi_wait_xfer_finish(XFER_FINISH_TOUT);
+
+	/* Restore the CTRL REG1 state */
+	writel(ctrlreg1, &smicntl->smi_cr1);
+
+	return readl(&smicntl->smi_sr);
+}
+
+/*
+ * smi_wait_till_ready - Wait till last operation is over.
+ * @bank:	 bank number shifted.
+ * @timeout:	 timeout in milliseconds.
+ *
+ * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0)
+ * The routine checks for #timeout loops, each at interval of 1 milli-second.
+ * If successful the routine returns 0.
+ */
+static int smi_wait_till_ready(int bank, int timeout)
+{
+	int count;
+	int sr;
+
+	/* One chip guarantees max 5 msec wait here after page writes,
+	   but potentially three seconds (!) after page erase. */
+	for (count = 0; count < timeout; count++) {
+
+		sr = smi_read_sr(bank);
+		if (sr < 0) {
+			break;
+		} else if (!(sr & WIP_BIT)) {
+			return 0;
+		}
+
+		/* Try again after 1m-sec */
+		udelay(1000);
+	}
+	printf("SMI controller is still in wait, timeout=%d\n", timeout);
+	return -EIO;
+}
+
+/*
+ * smi_write_enable - Enable the flash to do write operation
+ * @bank:	 bank number
+ *
+ * Set write enable latch with Write Enable command.
+ * Returns negative if error occurred.
+ */
+static inline int smi_write_enable(int bank)
+{
+	u32 ctrlreg1;
+	int timeout = WMODE_TOUT;
+
+	/* Store the CTRL REG1 state */
+	ctrlreg1 = readl(&smicntl->smi_cr1);
+
+	/* Program SMI in H/W Mode */
+	writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1);
+
+	/* Give the Flash, Write Enable command */
+	writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2);
+
+	smi_wait_xfer_finish(XFER_FINISH_TOUT);
+
+	/* Restore the CTRL REG1 state */
+	writel(ctrlreg1, &smicntl->smi_cr1);
+
+	while (timeout--) {
+		if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT)))
+			break;
+		udelay(1000);
+	}
+
+	return 0;
+}
+
+/*
+ * smi_init - SMI initialization routine
+ *
+ * SMI initialization routine. Sets SMI control register1.
+ */
+static void smi_init(void)
+{
+	/* Setting the fast mode values. SMI working@166/4 = 41.5 MHz */
+	writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
+	       &smicntl->smi_cr1);
+}
+
+/*
+ * smi_sector_erase - Erase flash sector
+ * @info:	 flash_info structure pointer
+ * @sector:	 sector number
+ *
+ * Set write enable latch with Write Enable command.
+ * Returns negative if error occurred.
+ */
+static int smi_sector_erase(flash_info_t *info, unsigned int sector)
+{
+	int bank;
+	unsigned int sect_add;
+	unsigned int instruction;
+
+	switch (info->start[0]) {
+	case SMIBANK0_BASE:
+		bank = BANK0;
+		break;
+	case SMIBANK1_BASE:
+		bank = BANK1;
+		break;
+	case SMIBANK2_BASE:
+		bank = BANK2;
+		break;
+	case SMIBANK3_BASE:
+		bank = BANK3;
+		break;
+	default:
+		return -1;
+	}
+
+	sect_add = sector * (info->size / info->sector_count);
+	instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE;
+
+	writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr);
+
+	if (info->flash_id == ST_M25Pxx_ID) {
+		/* Wait until finished previous write command. */
+		if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
+			return -EBUSY;
+
+		/* Send write enable, before erase commands. */
+		if (smi_write_enable(bank))
+			return -EIO;
+
+		/* Put SMI in SW mode */
+		writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1);
+
+		/* Send Sector Erase command in SW Mode */
+		writel(instruction, &smicntl->smi_tr);
+		writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4,
+		       &smicntl->smi_cr2);
+		smi_wait_xfer_finish(XFER_FINISH_TOUT);
+
+		if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT))
+			return -EBUSY;
+
+		/* Put SMI in HW mode */
+		writel(readl(&smicntl->smi_cr1) & ~(SW_MODE),
+		       &smicntl->smi_cr1);
+
+		return 0;
+	} else {
+		/* Put SMI in HW mode */
+		writel(readl(&smicntl->smi_cr1) & ~(SW_MODE),
+		       &smicntl->smi_cr1);
+		return -EINVAL;
+	}
+}
+
+/*
+ * smi_write - Write to SMI flash
+ * @src_addr:	 source buffer
+ * @dst_addr:	 destination buffer
+ * @length:	 length to write in words
+ * @bank:	 bank base address
+ *
+ * Write to SMI flash
+ */
+static int smi_write(unsigned int *src_addr, unsigned int *dst_addr,
+		     unsigned int length, ulong bank_addr)
+{
+	int banknum;
+	unsigned int WM;
+
+	switch (bank_addr) {
+	case SMIBANK0_BASE:
+		banknum = BANK0;
+		WM = WM0;
+		break;
+	case SMIBANK1_BASE:
+		banknum = BANK1;
+		WM = WM1;
+		break;
+	case SMIBANK2_BASE:
+		banknum = BANK2;
+		WM = WM2;
+		break;
+	case SMIBANK3_BASE:
+		banknum = BANK3;
+		WM = WM3;
+		break;
+	default:
+		return -1;
+	}
+
+	if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
+		return -EBUSY;
+
+	/* Set SMI in Hardware Mode */
+	writel(readl(&smicntl->smi_cr1) & ~(SW_MODE), &smicntl->smi_cr1);
+
+	if (smi_write_enable(banknum))
+		return -EIO;
+
+	/* Perform the write command */
+	while (length--) {
+		if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) {
+			if (smi_wait_till_ready(banknum,
+						CONFIG_SYS_FLASH_WRITE_TOUT))
+				return -EBUSY;
+
+			if (smi_write_enable(banknum))
+				return -EIO;
+		}
+
+		*dst_addr++ = *src_addr++;
+
+		if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2)))
+			return -EIO;
+	}
+
+	if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT))
+		return -EBUSY;
+
+	writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr);
+
+	return 0;
+}
+
+/*
+ * write_buff - Write to SMI flash
+ * @info:	 flash info structure
+ * @src:	 source buffer
+ * @dest_addr:	 destination buffer
+ * @length:	 length to write in words
+ *
+ * Write to SMI flash
+ */
+int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length)
+{
+	smi_write((unsigned int *)src, (unsigned int *)dest_addr,
+		  (length + 3) / 4, info->start[0]);
+	return 0;
+}
+
+/*
+ * flash_init - SMI flash initialization
+ *
+ * SMI flash initialization
+ */
+unsigned long flash_init(void)
+{
+	unsigned long size = 0;
+	int i, j;
+
+	smi_init();
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		size += flash_info[i].size = flash_get_size(bank_base[i], i);
+	}
+
+	for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) {
+		for (i = 1; i < flash_info[j].sector_count; i++)
+			flash_info[j].start[i] =
+			    flash_info[j].start[i - 1] +
+			    flash_info->size / flash_info->sector_count;
+
+	}
+
+	return size;
+}
+
+/*
+ * flash_print_info - Print SMI flash information
+ *
+ * Print SMI flash information
+ */
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+	if (info->flash_id == FLASH_UNKNOWN) {
+		puts("missing or unknown FLASH type\n");
+		return;
+	}
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	puts("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
+		int size;
+		int erased;
+		u32 *flash;
+
+		/*
+		 * Check if whole sector is erased
+		 */
+		size = (info->size) / (info->sector_count);
+		flash = (u32 *) info->start[i];
+		size = size / sizeof(int);
+
+		while ((size--) && (*flash++ == ~0))
+			;
+
+		size++;
+		if (size)
+			erased = 0;
+		else
+			erased = 1;
+
+		if ((i % 5) == 0)
+			printf("\n");
+
+		printf(" %08lX%s%s",
+		       info->start[i],
+		       erased ? " E" : "  ", info->protect[i] ? "RO " : "   ");
+#else
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i], info->protect[i] ? " (RO)  " : "     ");
+#endif
+	}
+	putc('\n');
+	return;
+}
+
+/*
+ * flash_erase - Erase SMI flash
+ *
+ * Erase SMI flash
+ */
+int flash_erase(flash_info_t *info, int s_first, int s_last)
+{
+	int rcode = 0;
+	int prot = 0;
+	flash_sect_t sect;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		puts("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		puts("- no sectors to erase\n");
+		return 1;
+	}
+
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n",
+		       prot);
+	} else {
+		putc('\n');
+	}
+
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {
+			switch (info->flash_id) {
+			case ST_M25Pxx_ID:
+				if (smi_sector_erase(info, sect))
+					rcode = 1;
+				else
+					putc('.');
+
+				break;
+
+			default:
+				printf("Unkown flash vendor 0x%x\n",
+				       (u32) info->flash_id);
+				break;
+			}
+		}
+	}
+	puts(" done\n");
+	return rcode;
+}
+#endif
diff --git a/include/asm-arm/arch-spear/spr_smi.h b/include/asm-arm/arch-spear/spr_smi.h
new file mode 100755
index 0000000..a42a874
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_smi.h
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef SPR_SMI_H
+#define SPR_SMI_H
+
+/* 0xF800.0000 . 0xFBFF.FFFF	64MB	SMI (Serial Flash Mem) */
+/* 0xFC00.0000 . 0xFC1F.FFFF	2MB	SMI (Serial Flash Reg.) */
+
+#define SMI_BASE 	  	CONFIG_SYS_SMI_BASE
+
+#define FLASH_START_ADDRESS	CONFIG_SYS_FLASH_BASE
+#define FLASH_BANK_SIZE         CONFIG_SYS_FLASH_BANK_SIZE
+
+#define SMIBANK0_BASE 		(FLASH_START_ADDRESS)
+#define SMIBANK1_BASE 		(SMIBANK0_BASE + FLASH_BANK_SIZE)
+#define SMIBANK2_BASE 		(SMIBANK1_BASE + FLASH_BANK_SIZE)
+#define SMIBANK3_BASE 		(SMIBANK2_BASE + FLASH_BANK_SIZE)
+
+#define BANK0 0
+#define BANK1 1
+#define BANK2 2
+#define BANK3 3
+
+struct smi_regs {
+	u32 smi_cr1;
+	u32 smi_cr2;
+	u32 smi_sr;
+	u32 smi_tr;
+	u32 smi_rr;
+};
+
+/* CONTROL REG 1 */
+#define BANK_EN       0x0000000F	/* enables all banks */
+#define DSEL_TIME     0x00000060	/* Deselect time 6+1 SMI_CK periods */
+#define PRESCAL5      0x00000500	/* AHB_CK prescaling value */
+#define PRESCALA      0x00000A00	/* AHB_CK prescaling value */
+#define PRESCAL3      0x00000300	/* AHB_CK prescaling value */
+#define PRESCAL4      0x00000400	/* AHB_CK prescaling value */
+#define SW_MODE       0x10000000	/* enables SW Mode */
+#define WB_MODE       0x20000000	/* Write Burst Mode */
+#define FAST_MODE     0x00008000	/* Fast Mode */
+#define HOLD1         0x00010000
+
+/* CONTROL REG 2 */
+#define RD_STATUS_REG 0x00000400	/* reads status reg */
+#define WE            0x00000800	/* Write Enable */
+#define BANK0_SEL     0x00000000	/* Select Banck0 */
+#define BANK1_SEL     0x00001000	/* Select Banck1 */
+#define BANK2_SEL     0x00002000	/* Select Banck2 */
+#define BANK3_SEL     0x00003000	/* Select Banck3 */
+#define BANKSEL_SHIFT 12
+#define SEND          0x00000080	/* Send data */
+#define TX_LEN_1      0x00000001	/* data length = 1 byte */
+#define TX_LEN_2      0x00000002	/* data length = 2 byte */
+#define TX_LEN_3      0x00000003	/* data length = 3 byte */
+#define TX_LEN_4      0x00000004	/* data length = 4 byte */
+#define RX_LEN_1      0x00000010	/* data length = 1 byte */
+#define RX_LEN_2      0x00000020	/* data length = 2 byte */
+#define RX_LEN_3      0x00000030	/* data length = 3 byte */
+#define RX_LEN_4      0x00000040	/* data length = 4 byte */
+#define TFIE          0x00000100	/* Transmission Flag Interrupt Enable */
+#define WCIE          0x00000200	/* Write Complete Interrupt Enable */
+
+/* STATUS_REG */
+#define INT_WCF_CLR   0xFFFFFDFF	/* clear: WCF clear */
+#define INT_TFF_CLR   0xFFFFFEFF	/* clear: TFF clear */
+#define WIP_BIT       0x00000001	/* WIP Bit of SPI SR on SMI SR */
+#define WEL_BIT       0x00000002	/* WEL Bit of SPI SR on SMI SR */
+#define RSR           0x00000005	/* Read Status regiser */
+#define TFF           0x00000100	/* Transfer Finished FLag */
+#define WCF           0x00000200	/* Transfer Finished FLag */
+#define ERF1          0x00000400	/* Error Flag 1 */
+#define ERF2          0x00000800	/* Error Flag 2 */
+#define WM0           0x00001000	/* WM Bank 0 */
+#define WM1           0x00002000	/* WM Bank 1 */
+#define WM2           0x00004000	/* WM Bank 2 */
+#define WM3           0x00008000	/* WM Bank 3 */
+#define WM_SHIFT      12
+
+/* TR REG */
+#define READ_ID       0x0000009F	/* Read Identification */
+#define BULK_ERASE    0x000000C7	/* BULK erase */
+#define SECTOR_ERASE  0x000000D8	/* SECTOR erase */
+#define WRITE_ENABLE  0x00000006	/* Wenable command to FLASH */
+
+struct flash_dev {
+	u32 density;
+	ulong size;
+	ushort sector_count;
+};
+
+#define SFLASH_PAGE_SIZE     0x100
+#define XFER_FINISH_TOUT 2
+#define WMODE_TOUT    2
+
+#endif
diff --git a/include/configs/spear.h b/include/configs/spear.h
index 4a6458d..5589df8 100755
--- a/include/configs/spear.h
+++ b/include/configs/spear.h
@@ -50,6 +50,11 @@
 #define CONFIG_SYS_I2C_SLAVE			0x02
 
 /*
+ * SMI driver configuration
+ */
+#define CONFIG_SPEARSMI
+
+/*
  * Serial Configuration (PL011)
  */
 #define CONFIG_PL011_SERIAL
@@ -104,6 +109,8 @@
 /*
  * Platform specific defines (SPEAr)
  */
+#define CONFIG_SYS_SMI_BASE			(0xFC000000)
+#define CONFIG_SYS_FLASH_BASE			(0xF8000000)
 #define CONFIG_SPEAR_SYSCNTLBASE		(0xFCA00000)
 #define CONFIG_SPEAR_TIMERBASE			(0xFC800000)
 #define CONFIG_SPEAR_MISCBASE			(0xFCA80000)
@@ -134,11 +141,14 @@
 #define CONFIG_NAND_SPEAR			1
 #define CONFIG_SYS_MAX_NAND_DEVICE		1
 #define CONFIG_MTD_NAND_VERIFY_WRITE		1
+=======
+>>>>>>> a15fb6e... SPEAr : Support for serial memory interface driver and serial NOR flash:include/configs/spear.h
 
 /*
  * Command support defines
  */
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_ENV
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_RUN
 #define CONFIG_CMD_SAVES
@@ -155,11 +165,32 @@
 #define CONFIG_BOOTARGS_NFS			"root=/dev/nfs ip=dhcp " \
 						"console=ttyS0 init=/bin/sh"
 
+#define CONFIG_ENV_OVERWRITE
+
 /*
- * Miscellaneous configurable options
+ * U-Boot Environment placing definitions.
  */
-#define CONFIG_ENV_IS_NOWHERE			1
+#define CONFIG_ENV_IS_IN_FLASH
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_SYS_MONITOR_LEN			0x00040000
+#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
+#define CONFIG_ENV_SECT_SIZE			0x10000
+#define CONFIG_ENV_ADDR				(CONFIG_SYS_MONITOR_BASE + \
+						CONFIG_SYS_MONITOR_LEN)
+
+#define CONFIG_BOOTARGS				"console=ttyS0 mem=128M " \
+						"root=/dev/mtdblock3 " \
+						"rootfstype=jffs2"
+#define CONFIG_BOOTCOMMAND			"bootm 0xf8050000"
+
+#endif
+
 #define CONFIG_ENV_SIZE				0x02000
+
+/*
+ * Miscellaneous configurable options
+ */
 #define CONFIG_BOOT_PARAMS_ADDR			0x00000100
 #define CONFIG_CMDLINE_TAG			1
 #define CONFIG_SETUP_MEMORY_TAGS		1
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [U-Boot] [PATCH v3 09/11] SPEAr : Support for nand driver
  2010-01-08 13:49               ` [U-Boot] [PATCH v3 08/11] SPEAr : Support for serial memory interface driver and serial NOR flash Vipin KUMAR
@ 2010-01-08 13:49                 ` Vipin KUMAR
  2010-01-08 13:49                   ` [U-Boot] [PATCH v3 10/11] SPEAr : Support for usbd driver and usbtty support Vipin KUMAR
  0 siblings, 1 reply; 13+ messages in thread
From: Vipin KUMAR @ 2010-01-08 13:49 UTC (permalink / raw)
  To: u-boot


Signed-off-by: Vipin <vipin.kumar@st.com>
---
 board/spear/spear300/config.mk        |    7 ++
 board/spear/spear300/spear300.c       |   26 +++++++
 board/spear/spear310/config.mk        |    7 ++
 board/spear/spear310/spear310.c       |   26 +++++++
 board/spear/spear320/config.mk        |    7 ++
 board/spear/spear320/spear320.c       |   26 +++++++
 board/spear/spear600/config.mk        |    7 ++
 board/spear/spear600/spear600.c       |   22 ++++++
 drivers/mtd/nand/Makefile             |    1 +
 drivers/mtd/nand/spr_nand.c           |  123 +++++++++++++++++++++++++++++++++
 include/asm-arm/arch-spear/spr_nand.h |   57 +++++++++++++++
 include/configs/spear.h               |   59 +++++++++++++---
 12 files changed, 357 insertions(+), 11 deletions(-)
 create mode 100755 drivers/mtd/nand/spr_nand.c
 create mode 100644 include/asm-arm/arch-spear/spr_nand.h

diff --git a/board/spear/spear300/config.mk b/board/spear/spear300/config.mk
index 0bbb40f..e597326 100755
--- a/board/spear/spear300/config.mk
+++ b/board/spear/spear300/config.mk
@@ -26,3 +26,10 @@
 TEXT_BASE = 0x00700000
 
 ALL += $(obj)u-boot.img
+
+# Environment variables in NAND
+ifeq ($(ENV),NAND)
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
+else
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
+endif
diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c
index 137f7b3..5fc5cdb 100755
--- a/board/spear/spear300/spear300.c
+++ b/board/spear/spear300/spear300.c
@@ -22,10 +22,36 @@
  */
 
 #include <common.h>
+#include <nand.h>
+#include <asm/io.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_nand.h>
 
 int board_init(void)
 {
 	return spear_board_init(MACH_TYPE_SPEAR300);
 }
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+int board_nand_init(struct nand_chip *nand)
+{
+	struct misc_regs *const misc_regs_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG30) ||
+	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG31)) {
+
+		return spear_nand_init(nand);
+	}
+
+	return -1;
+}
diff --git a/board/spear/spear310/config.mk b/board/spear/spear310/config.mk
index 0bbb40f..e597326 100755
--- a/board/spear/spear310/config.mk
+++ b/board/spear/spear310/config.mk
@@ -26,3 +26,10 @@
 TEXT_BASE = 0x00700000
 
 ALL += $(obj)u-boot.img
+
+# Environment variables in NAND
+ifeq ($(ENV),NAND)
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
+else
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
+endif
diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c
index 86c3e96..e4a91a8 100755
--- a/board/spear/spear310/spear310.c
+++ b/board/spear/spear310/spear310.c
@@ -23,10 +23,36 @@
  */
 
 #include <common.h>
+#include <nand.h>
+#include <asm/io.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_nand.h>
 
 int board_init(void)
 {
 	return spear_board_init(MACH_TYPE_SPEAR300);
 }
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+int board_nand_init(struct nand_chip *nand)
+{
+	struct misc_regs *const misc_regs_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG30) ||
+	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG31)) {
+
+		return spear_nand_init(nand);
+	}
+
+	return -1;
+}
diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk
index 0bbb40f..e597326 100755
--- a/board/spear/spear320/config.mk
+++ b/board/spear/spear320/config.mk
@@ -26,3 +26,10 @@
 TEXT_BASE = 0x00700000
 
 ALL += $(obj)u-boot.img
+
+# Environment variables in NAND
+ifeq ($(ENV),NAND)
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
+else
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
+endif
diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c
index 86c3e96..e4a91a8 100755
--- a/board/spear/spear320/spear320.c
+++ b/board/spear/spear320/spear320.c
@@ -23,10 +23,36 @@
  */
 
 #include <common.h>
+#include <nand.h>
+#include <asm/io.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_nand.h>
 
 int board_init(void)
 {
 	return spear_board_init(MACH_TYPE_SPEAR300);
 }
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+int board_nand_init(struct nand_chip *nand)
+{
+	struct misc_regs *const misc_regs_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG30) ||
+	    ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) ==
+	     MISC_SOCCFG31)) {
+
+		return spear_nand_init(nand);
+	}
+
+	return -1;
+}
diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk
index 0bbb40f..e597326 100755
--- a/board/spear/spear600/config.mk
+++ b/board/spear/spear600/config.mk
@@ -26,3 +26,10 @@
 TEXT_BASE = 0x00700000
 
 ALL += $(obj)u-boot.img
+
+# Environment variables in NAND
+ifeq ($(ENV),NAND)
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
+else
+PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
+endif
diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c
index 8984358..5f4a78a 100755
--- a/board/spear/spear600/spear600.c
+++ b/board/spear/spear600/spear600.c
@@ -22,10 +22,32 @@
  */
 
 #include <common.h>
+#include <nand.h>
+#include <asm/io.h>
 #include <asm/arch/spr_defs.h>
 #include <asm/arch/spr_misc.h>
+#include <asm/arch/spr_nand.h>
 
 int board_init(void)
 {
 	return spear_board_init(MACH_TYPE_SPEAR600);
 }
+
+/*
+ * board_nand_init - Board specific NAND initialization
+ * @nand:	mtd private chip structure
+ *
+ * Called by nand_init_chip to initialize the board specific functions
+ */
+
+int board_nand_init(struct nand_chip *nand)
+{
+	struct misc_regs *const misc_regs_p =
+	    (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
+
+	if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) {
+		return spear_nand_init(nand);
+	}
+
+	return -1;
+}
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 02449ee..28f27da 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
 COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
 COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
 COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
+COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o
 COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
 COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o
 endif
diff --git a/drivers/mtd/nand/spr_nand.c b/drivers/mtd/nand/spr_nand.c
new file mode 100755
index 0000000..fbf1b8f
--- /dev/null
+++ b/drivers/mtd/nand/spr_nand.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <asm/io.h>
+#include <asm/arch/spr_nand.h>
+
+static struct fsmc_regs *const fsmc_regs_p =
+    (struct fsmc_regs *)CONFIG_SPEAR_FSMCBASE;
+
+static struct nand_ecclayout spear_nand_ecclayout = {
+	.eccbytes = 24,
+	.eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
+		   66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
+	.oobfree = {
+		    {.offset = 8, .length = 8},
+		    {.offset = 24, .length = 8},
+		    {.offset = 40, .length = 8},
+		    {.offset = 56, .length = 8},
+		    {.offset = 72, .length = 8},
+		    {.offset = 88, .length = 8},
+		    {.offset = 104, .length = 8},
+		    {.offset = 120, .length = 8}
+		    }
+};
+
+static void spear_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	ulong IO_ADDR_W;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		IO_ADDR_W = (ulong)this->IO_ADDR_W;
+
+		IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE);
+		if (ctrl & NAND_CLE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_CLE;
+		if (ctrl & NAND_ALE)
+			IO_ADDR_W |= CONFIG_SYS_NAND_ALE;
+
+		if (ctrl & NAND_NCE) {
+			writel(readl(&fsmc_regs_p->genmemctrl_pc) |
+			       FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc);
+		} else {
+			writel(readl(&fsmc_regs_p->genmemctrl_pc) &
+			       ~FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc);
+		}
+		this->IO_ADDR_W = (void *)IO_ADDR_W;
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+static int spear_read_hwecc(struct mtd_info *mtd,
+			    const u_char *data, u_char ecc[3])
+{
+	u_int ecc_tmp;
+
+	/* read the h/w ECC */
+	ecc_tmp = readl(&fsmc_regs_p->genmemctrl_ecc);
+
+	ecc[0] = (u_char) (ecc_tmp & 0xFF);
+	ecc[1] = (u_char) ((ecc_tmp & 0xFF00) >> 8);
+	ecc[2] = (u_char) ((ecc_tmp & 0xFF0000) >> 16);
+
+	return 0;
+}
+
+void spear_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+	writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~0x80,
+	       &fsmc_regs_p->genmemctrl_pc);
+	writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~FSMC_ECCEN,
+	       &fsmc_regs_p->genmemctrl_pc);
+	writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_ECCEN,
+	       &fsmc_regs_p->genmemctrl_pc);
+}
+
+int spear_nand_init(struct nand_chip *nand)
+{
+	writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON,
+	       &fsmc_regs_p->genmemctrl_pc);
+	writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_TCLR_1 | FSMC_TAR_1,
+	       &fsmc_regs_p->genmemctrl_pc);
+	writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
+	       &fsmc_regs_p->genmemctrl_comm);
+	writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
+	       &fsmc_regs_p->genmemctrl_attrib);
+
+	nand->options = 0;
+	nand->ecc.mode = NAND_ECC_HW;
+	nand->ecc.layout = &spear_nand_ecclayout;
+	nand->ecc.size = 512;
+	nand->ecc.bytes = 3;
+	nand->ecc.calculate = spear_read_hwecc;
+	nand->ecc.hwctl = spear_enable_hwecc;
+	nand->ecc.correct = nand_correct_data;
+	nand->cmd_ctrl = spear_nand_hwcontrol;
+	return 0;
+}
diff --git a/include/asm-arm/arch-spear/spr_nand.h b/include/asm-arm/arch-spear/spr_nand.h
new file mode 100644
index 0000000..2b63dc7
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_nand.h
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPR_NAND_H__
+#define __SPR_NAND_H__
+
+struct fsmc_regs {
+	u32 reserved_1[0x10];
+	u32 genmemctrl_pc;
+	u32 reserved_2;
+	u32 genmemctrl_comm;
+	u32 genmemctrl_attrib;
+	u32 reserved_3;
+	u32 genmemctrl_ecc;
+};
+
+/* genmemctrl_pc register definitions */
+#define FSMC_RESET		(1 << 0)
+#define FSMC_WAITON		(1 << 1)
+#define FSMC_ENABLE		(1 << 2)
+#define FSMC_DEVTYPE_NAND	(1 << 3)
+#define FSMC_DEVWID_8		(0 << 4)
+#define FSMC_DEVWID_16		(1 << 4)
+#define FSMC_ECCEN		(1 << 6)
+#define FSMC_ECCPLEN_512	(0 << 7)
+#define FSMC_ECCPLEN_256	(1 << 7)
+#define FSMC_TCLR_1		(1 << 9)
+#define FSMC_TAR_1		(1 << 13)
+
+/* genmemctrl_comm register definitions */
+#define FSMC_TSET_0		(0 << 0)
+#define FSMC_TWAIT_6		(6 << 8)
+#define FSMC_THOLD_4		(4 << 16)
+#define FSMC_THIZ_1		(1 << 24)
+
+extern int spear_nand_init(struct nand_chip *nand);
+#endif
diff --git a/include/configs/spear.h b/include/configs/spear.h
index 5589df8..da10f61 100755
--- a/include/configs/spear.h
+++ b/include/configs/spear.h
@@ -115,7 +115,35 @@
 #define CONFIG_SPEAR_TIMERBASE			(0xFC800000)
 #define CONFIG_SPEAR_MISCBASE			(0xFCA80000)
 
+#define CONFIG_SYS_NAND_CLE			(1 << 16)
+#define CONFIG_SYS_NAND_ALE			(1 << 17)
+
+#if defined(CONFIG_SPEAR600)
 #define CONFIG_SYS_I2C_BASE			(0xD0200000)
+#define CONFIG_SPEAR_FSMCBASE			(0xD1800000)
+#define CONFIG_SYS_NAND_BASE			(0xD2000000)
+
+#elif defined(CONFIG_SPEAR300)
+#define CONFIG_SYS_I2C_BASE			(0xD0180000)
+#define CONFIG_SPEAR_FSMCBASE			(0x94000000)
+#define CONFIG_SYS_NAND_BASE			(0x80000000)
+
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_I2C_BASE			(0xD0180000)
+#define CONFIG_SPEAR_FSMCBASE			(0x44000000)
+#define CONFIG_SYS_NAND_BASE			(0x40000000)
+
+#undef CONFIG_SYS_NAND_CLE
+#undef CONFIG_SYS_NAND_ALE
+#define CONFIG_SYS_NAND_CLE			(1 << 17)
+#define CONFIG_SYS_NAND_ALE			(1 << 16)
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_I2C_BASE			(0xD0180000)
+#define CONFIG_SPEAR_FSMCBASE			(0x4C000000)
+#define CONFIG_SYS_NAND_BASE			(0x50000000)
+
+#endif
 
 #define CONFIG_SYS_HZ				(1000)
 #define CONFIG_SYS_HZ_CLOCK			(8300000)
@@ -141,13 +169,12 @@
 #define CONFIG_NAND_SPEAR			1
 #define CONFIG_SYS_MAX_NAND_DEVICE		1
 #define CONFIG_MTD_NAND_VERIFY_WRITE		1
-=======
->>>>>>> a15fb6e... SPEAr : Support for serial memory interface driver and serial NOR flash:include/configs/spear.h
 
 /*
  * Command support defines
  */
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_NAND
 #define CONFIG_CMD_ENV
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_RUN
@@ -162,30 +189,40 @@
  * Default Environment Varible definitions
  */
 #define CONFIG_BOOTDELAY			1
-#define CONFIG_BOOTARGS_NFS			"root=/dev/nfs ip=dhcp " \
-						"console=ttyS0 init=/bin/sh"
-
 #define CONFIG_ENV_OVERWRITE
 
 /*
  * U-Boot Environment placing definitions.
  */
-#define CONFIG_ENV_IS_IN_FLASH
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
+#if defined(CONFIG_ENV_IS_IN_FLASH)
 #define CONFIG_SYS_MONITOR_LEN			0x00040000
 #define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
 #define CONFIG_ENV_SECT_SIZE			0x10000
+#define CONFIG_FSMTDBLK				"/dev/mtdblock8 "
 #define CONFIG_ENV_ADDR				(CONFIG_SYS_MONITOR_BASE + \
 						CONFIG_SYS_MONITOR_LEN)
 
-#define CONFIG_BOOTARGS				"console=ttyS0 mem=128M " \
-						"root=/dev/mtdblock3 " \
-						"rootfstype=jffs2"
 #define CONFIG_BOOTCOMMAND			"bootm 0xf8050000"
 
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+
+#define CONFIG_ENV_OFFSET			0x60000
+#define CONFIG_ENV_SIZE				0x04000
+#define CONFIG_ENV_RANGE			0x10000
+#define CONFIG_FSMTDBLK				"/dev/mtdblock12 "
+
+#define CONFIG_BOOTCOMMAND			"nand read.jffs2 0x1600000 " \
+						"0x80000 0x4C0000; " \
+						"bootm 0x1600000"
+
 #endif
 
+#define CONFIG_BOOTARGS_NFS			"root=/dev/nfs ip=dhcp " \
+						"console=ttyS0 init=/bin/sh"
+#define CONFIG_BOOTARGS				"console=ttyS0 mem=128M "  \
+						"root="CONFIG_FSMTDBLK \
+						"rootfstype=jffs2"
+
 #define CONFIG_ENV_SIZE				0x02000
 
 /*
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [U-Boot] [PATCH v3 10/11] SPEAr : Support for usbd driver and usbtty support
  2010-01-08 13:49                 ` [U-Boot] [PATCH v3 09/11] SPEAr : Support for nand driver Vipin KUMAR
@ 2010-01-08 13:49                   ` Vipin KUMAR
  2010-01-08 13:49                     ` [U-Boot] [PATCH v3 11/11] SPEAr : Support for cfi driver and parallel NOR flash Vipin KUMAR
  0 siblings, 1 reply; 13+ messages in thread
From: Vipin KUMAR @ 2010-01-08 13:49 UTC (permalink / raw)
  To: u-boot


Signed-off-by: Vipin <vipin.kumar@st.com>
---
 board/spear/common/spr_misc.c  |    6 +
 board/spear/spear300/config.mk |    4 +
 board/spear/spear310/config.mk |    9 +
 board/spear/spear320/config.mk |    9 +
 board/spear/spear600/config.mk |    4 +
 drivers/serial/usbtty.h        |    2 +
 drivers/usb/gadget/Makefile    |    1 +
 drivers/usb/gadget/spr_udc.c   | 1004 ++++++++++++++++++++++++++++++++++++++++
 include/configs/spear.h        |   22 +
 include/usb/spr_udc.h          |  227 +++++++++
 10 files changed, 1288 insertions(+), 0 deletions(-)
 mode change 100644 => 100755 drivers/serial/usbtty.h
 mode change 100644 => 100755 drivers/usb/gadget/Makefile
 create mode 100755 drivers/usb/gadget/spr_udc.c
 create mode 100755 include/usb/spr_udc.h

diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
index c4e3a1a..391cec2 100755
--- a/board/spear/common/spr_misc.c
+++ b/board/spear/common/spr_misc.c
@@ -70,6 +70,12 @@ int misc_init_r(void)
 	}
 #endif
 	setenv("verify", "n");
+
+#if defined(CONFIG_SPEAR_USBTTY)
+	setenv("stdin", "usbtty");
+	setenv("stdout", "usbtty");
+	setenv("stderr", "usbtty");
+#endif
 	return 0;
 }
 
diff --git a/board/spear/spear300/config.mk b/board/spear/spear300/config.mk
index e597326..35646f2 100755
--- a/board/spear/spear300/config.mk
+++ b/board/spear/spear300/config.mk
@@ -33,3 +33,7 @@ PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
 else
 PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
 endif
+
+ifeq ($(CONSOLE),USB)
+PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
+endif
diff --git a/board/spear/spear310/config.mk b/board/spear/spear310/config.mk
index e597326..cba8436 100755
--- a/board/spear/spear310/config.mk
+++ b/board/spear/spear310/config.mk
@@ -33,3 +33,12 @@ PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
 else
 PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
 endif
+
+# Support parallel flash
+ifeq ($(FLASH),PNOR)
+PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR
+endif
+
+ifeq ($(CONSOLE),USB)
+PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
+endif
diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk
index e597326..cba8436 100755
--- a/board/spear/spear320/config.mk
+++ b/board/spear/spear320/config.mk
@@ -33,3 +33,12 @@ PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
 else
 PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
 endif
+
+# Support parallel flash
+ifeq ($(FLASH),PNOR)
+PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR
+endif
+
+ifeq ($(CONSOLE),USB)
+PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
+endif
diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk
index e597326..35646f2 100755
--- a/board/spear/spear600/config.mk
+++ b/board/spear/spear600/config.mk
@@ -33,3 +33,7 @@ PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
 else
 PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
 endif
+
+ifeq ($(CONSOLE),USB)
+PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY
+endif
diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h
old mode 100644
new mode 100755
index 6b6c4a1..a23169a
--- a/drivers/serial/usbtty.h
+++ b/drivers/serial/usbtty.h
@@ -33,6 +33,8 @@
 #include <usb/musb_udc.h>
 #elif defined(CONFIG_PXA27X)
 #include <usb/pxa27x_udc.h>
+#elif defined(CONFIG_SPEAR3XX) || defined(CONFIG_SPEAR600)
+#include <usb/spr_udc.h>
 #endif
 
 #include <version_autogenerated.h>
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
old mode 100644
new mode 100755
index 2a19b1e..1d7362d
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -32,6 +32,7 @@ COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o
 COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o
 COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o
 COBJS-$(CONFIG_PXA27X) += pxa27x_udc.o
+COBJS-$(CONFIG_SPEARUDC) += spr_udc.o
 endif
 
 COBJS	:= $(COBJS-y)
diff --git a/drivers/usb/gadget/spr_udc.c b/drivers/usb/gadget/spr_udc.c
new file mode 100755
index 0000000..1b5e484
--- /dev/null
+++ b/drivers/usb/gadget/spr_udc.c
@@ -0,0 +1,1004 @@
+/*
+ * Based on drivers/usb/gadget/omap1510_udc.c
+ * TI OMAP1510 USB bus interface driver
+ *
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include <usbdevice.h>
+#include "ep0.h"
+#include <usb/spr_udc.h>
+#include <asm/arch/spr_misc.h>
+
+#define UDC_INIT_MDELAY		     80	/* Device settle delay */
+
+/* Some kind of debugging output... */
+#ifndef DEBUG_SPRUSBTTY
+#define UDCDBG(str)
+#define UDCDBGA(fmt, args...)
+#else
+#define UDCDBG(str) serial_printf(str "\n")
+#define UDCDBGA(fmt, args...) serial_printf(fmt "\n", ##args)
+#endif
+
+static struct urb *ep0_urb;
+static struct usb_device_instance *udc_device;
+
+static struct plug_regs *const plug_regs_p =
+    (struct plug_regs * const)CONFIG_SYS_PLUG_BASE;
+static struct udc_regs *const udc_regs_p =
+    (struct udc_regs * const)CONFIG_SYS_USBD_BASE;
+static struct udc_endp_regs *const outep_regs_p =
+    &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->out_regs[0];
+static struct udc_endp_regs *const inep_regs_p =
+    &((struct udc_regs * const)CONFIG_SYS_USBD_BASE)->in_regs[0];
+
+/*
+ * udc_state_transition - Write the next packet to TxFIFO.
+ * @initial:	Initial state.
+ * @final:	Final state.
+ *
+ * Helper function to implement device state changes. The device states and
+ * the events that transition between them are:
+ *
+ *				STATE_ATTACHED
+ *				||	/\
+ *				\/	||
+ *	DEVICE_HUB_CONFIGURED			DEVICE_HUB_RESET
+ *				||	/\
+ *				\/	||
+ *				STATE_POWERED
+ *				||	/\
+ *				\/	||
+ *	DEVICE_RESET				DEVICE_POWER_INTERRUPTION
+ *				||	/\
+ *				\/	||
+ *				STATE_DEFAULT
+ *				||	/\
+ *				\/	||
+ *	DEVICE_ADDRESS_ASSIGNED			DEVICE_RESET
+ *				||	/\
+ *				\/	||
+ *				STATE_ADDRESSED
+ *				||	/\
+ *				\/	||
+ *	DEVICE_CONFIGURED			DEVICE_DE_CONFIGURED
+ *				||	/\
+ *				\/	||
+ *				STATE_CONFIGURED
+ *
+ * udc_state_transition transitions up (in the direction from STATE_ATTACHED
+ * to STATE_CONFIGURED) from the specified initial state to the specified final
+ * state, passing through each intermediate state on the way. If the initial
+ * state is at or above (i.e. nearer to STATE_CONFIGURED) the final state, then
+ * no state transitions will take place.
+ *
+ * udc_state_transition also transitions down (in the direction from
+ * STATE_CONFIGURED to STATE_ATTACHED) from the specified initial state to the
+ * specified final state, passing through each intermediate state on the way.
+ * If the initial state is at or below (i.e. nearer to STATE_ATTACHED) the final
+ * state, then no state transitions will take place.
+ *
+ * This function must only be called with interrupts disabled.
+ */
+static void udc_state_transition(usb_device_state_t initial,
+				 usb_device_state_t final)
+{
+	if (initial < final) {
+		switch (initial) {
+		case STATE_ATTACHED:
+			usbd_device_event_irq(udc_device,
+					      DEVICE_HUB_CONFIGURED, 0);
+			if (final == STATE_POWERED)
+				break;
+		case STATE_POWERED:
+			usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
+			if (final == STATE_DEFAULT)
+				break;
+		case STATE_DEFAULT:
+			usbd_device_event_irq(udc_device,
+					      DEVICE_ADDRESS_ASSIGNED, 0);
+			if (final == STATE_ADDRESSED)
+				break;
+		case STATE_ADDRESSED:
+			usbd_device_event_irq(udc_device, DEVICE_CONFIGURED, 0);
+		case STATE_CONFIGURED:
+			break;
+		default:
+			break;
+		}
+	} else if (initial > final) {
+		switch (initial) {
+		case STATE_CONFIGURED:
+			usbd_device_event_irq(udc_device,
+					      DEVICE_DE_CONFIGURED, 0);
+			if (final == STATE_ADDRESSED)
+				break;
+		case STATE_ADDRESSED:
+			usbd_device_event_irq(udc_device, DEVICE_RESET, 0);
+			if (final == STATE_DEFAULT)
+				break;
+		case STATE_DEFAULT:
+			usbd_device_event_irq(udc_device,
+					      DEVICE_POWER_INTERRUPTION, 0);
+			if (final == STATE_POWERED)
+				break;
+		case STATE_POWERED:
+			usbd_device_event_irq(udc_device, DEVICE_HUB_RESET, 0);
+		case STATE_ATTACHED:
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+/* Stall endpoint */
+static void udc_stall_ep(u32 ep_num)
+{
+	writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
+	       &inep_regs_p[ep_num].endp_cntl);
+
+	writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL,
+	       &outep_regs_p[ep_num].endp_cntl);
+}
+
+static void *get_fifo(int ep_num, int in)
+{
+	u32 *fifo_ptr = (u32 *)CONFIG_SYS_FIFO_BASE;
+
+	switch (ep_num) {
+	case 3:
+		fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn);
+		/* break intentionally left out */
+
+	case 1:
+		fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn);
+		/* break intentionally left out */
+
+	case 0:
+	default:
+		if (in) {
+			fifo_ptr +=
+			    readl(&outep_regs_p[2].endp_maxpacksize) >> 16;
+			/* break intentionally left out */
+		} else {
+			break;
+		}
+
+	case 2:
+		fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16;
+		/* break intentionally left out */
+	}
+
+	return (void *)fifo_ptr;
+}
+
+static short usbgetpckfromfifo(int epNum, u8 *bufp, u32 len)
+{
+	u8 *fifo_ptr = (u8 *)get_fifo(epNum, 0);
+	u32 i, nw, nb;
+	u32 *wrdp;
+	u8 *bytp;
+
+	if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY)
+		return -1;
+
+	nw = len / sizeof(u32);
+	nb = len % sizeof(u32);
+
+	wrdp = (u32 *)bufp;
+	for (i = 0; i < nw; i++) {
+		writel(readl(fifo_ptr), wrdp);
+		wrdp++;
+	}
+
+	bytp = (u8 *)wrdp;
+	for (i = 0; i < nb; i++) {
+		writeb(readb(fifo_ptr), bytp);
+		fifo_ptr++;
+		bytp++;
+	}
+	readl(&outep_regs_p[epNum].write_done);
+
+	return 0;
+}
+
+static void usbputpcktofifo(int epNum, u8 *bufp, u32 len)
+{
+	u32 i, nw, nb;
+	u32 *wrdp;
+	u8 *bytp;
+	u8 *fifo_ptr = get_fifo(epNum, 1);
+
+	nw = len / sizeof(int);
+	nb = len % sizeof(int);
+	wrdp = (u32 *)bufp;
+	for (i = 0; i < nw; i++) {
+		writel(*wrdp, fifo_ptr);
+		wrdp++;
+	}
+
+	bytp = (u8 *)wrdp;
+	for (i = 0; i < nb; i++) {
+		writeb(*bytp, fifo_ptr);
+		fifo_ptr++;
+		bytp++;
+	}
+}
+
+/*
+ * spear_write_noniso_tx_fifo - Write the next packet to TxFIFO.
+ * @endpoint:		Endpoint pointer.
+ *
+ * If the endpoint has an active tx_urb, then the next packet of data from the
+ * URB is written to the tx FIFO.  The total amount of data in the urb is given
+ * by urb->actual_length.  The maximum amount of data that can be sent in any
+ * one packet is given by endpoint->tx_packetSize.  The number of data bytes
+ * from this URB that have already been transmitted is given by endpoint->sent.
+ * endpoint->last is updated by this routine with the number of data bytes
+ * transmitted in this packet.
+ *
+ */
+static void spear_write_noniso_tx_fifo(struct usb_endpoint_instance
+				       *endpoint)
+{
+	struct urb *urb = endpoint->tx_urb;
+	int align;
+
+	if (urb) {
+		u32 last;
+
+		UDCDBGA("urb->buffer %p, buffer_length %d, actual_length %d",
+			urb->buffer, urb->buffer_length, urb->actual_length);
+
+		last = MIN(urb->actual_length - endpoint->sent,
+			   endpoint->tx_packetSize);
+
+		if (last) {
+			u8 *cp = urb->buffer + endpoint->sent;
+
+			/*
+			 * This ensures that USBD packet fifo is accessed
+			 * - through word aligned pointer or
+			 * - through non word aligned pointer but only
+			 *   with a max length to make the next packet
+			 *   word aligned
+			 */
+
+			align = ((ulong)cp % sizeof(int));
+			if (align)
+				last = MIN(last, sizeof(int) - align);
+
+			UDCDBGA("endpoint->sent %d, tx_packetSize %d, last %d",
+				endpoint->sent, endpoint->tx_packetSize, last);
+
+			usbputpcktofifo(endpoint->endpoint_address &
+					USB_ENDPOINT_NUMBER_MASK, cp, last);
+		}
+		endpoint->last = last;
+	}
+}
+
+/*
+ * Handle SETUP USB interrupt.
+ * This function implements TRM Figure 14-14.
+ */
+static void spear_udc_setup(struct usb_endpoint_instance *endpoint)
+{
+	u8 *datap = (u8 *)&ep0_urb->device_request;
+	int ep_addr = endpoint->endpoint_address;
+
+	UDCDBG("-> Entering device setup");
+	usbgetpckfromfifo(ep_addr, datap, 8);
+
+	/* Try to process setup packet */
+	if (ep0_recv_setup(ep0_urb)) {
+		/* Not a setup packet, stall next EP0 transaction */
+		udc_stall_ep(0);
+		UDCDBG("can't parse setup packet, still waiting for setup");
+		return;
+	}
+
+	/* Check direction */
+	if ((ep0_urb->device_request.bmRequestType & USB_REQ_DIRECTION_MASK)
+	    == USB_REQ_HOST2DEVICE) {
+		UDCDBG("control write on EP0");
+		if (le16_to_cpu(ep0_urb->device_request.wLength)) {
+			/* Stall this request */
+			UDCDBG("Stalling unsupported EP0 control write data "
+			       "stage.");
+			udc_stall_ep(0);
+		}
+	} else {
+
+		UDCDBG("control read on EP0");
+		/*
+		 * The ep0_recv_setup function has already placed our response
+		 * packet data in ep0_urb->buffer and the packet length in
+		 * ep0_urb->actual_length.
+		 */
+		endpoint->tx_urb = ep0_urb;
+		endpoint->sent = 0;
+		/*
+		 * Write packet data to the FIFO.  spear_write_noniso_tx_fifo
+		 * will update endpoint->last with the number of bytes written
+		 * to the FIFO.
+		 */
+		spear_write_noniso_tx_fifo(endpoint);
+
+		writel(0x0, &inep_regs_p[ep_addr].write_done);
+	}
+
+	udc_unset_nak(endpoint->endpoint_address);
+
+	UDCDBG("<- Leaving device setup");
+}
+
+/*
+ * Handle endpoint 0 RX interrupt
+ */
+static void spear_udc_ep0_rx(struct usb_endpoint_instance *endpoint)
+{
+	u8 dummy[64];
+
+	UDCDBG("RX on EP0");
+
+	/* Check direction */
+	if ((ep0_urb->device_request.bmRequestType
+	     & USB_REQ_DIRECTION_MASK) == USB_REQ_HOST2DEVICE) {
+		/*
+		 * This rx interrupt must be for a control write data
+		 * stage packet.
+		 *
+		 * We don't support control write data stages.
+		 * We should never end up here.
+		 */
+
+		UDCDBG("Stalling unexpected EP0 control write "
+		       "data stage packet");
+		udc_stall_ep(0);
+	} else {
+		/*
+		 * This rx interrupt must be for a control read status
+		 * stage packet.
+		 */
+		UDCDBG("ACK on EP0 control read status stage packet");
+		u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff;
+		usbgetpckfromfifo(0, dummy, len);
+	}
+}
+
+/*
+ * Handle endpoint 0 TX interrupt
+ */
+static void spear_udc_ep0_tx(struct usb_endpoint_instance *endpoint)
+{
+	struct usb_device_request *request = &ep0_urb->device_request;
+	int ep_addr;
+
+	UDCDBG("TX on EP0");
+
+	/* Check direction */
+	if ((request->bmRequestType & USB_REQ_DIRECTION_MASK) ==
+	    USB_REQ_HOST2DEVICE) {
+		/*
+		 * This tx interrupt must be for a control write status
+		 * stage packet.
+		 */
+		UDCDBG("ACK on EP0 control write status stage packet");
+	} else {
+		/*
+		 * This tx interrupt must be for a control read data
+		 * stage packet.
+		 */
+		int wLength = le16_to_cpu(request->wLength);
+
+		/*
+		 * Update our count of bytes sent so far in this
+		 * transfer.
+		 */
+		endpoint->sent += endpoint->last;
+
+		/*
+		 * We are finished with this transfer if we have sent
+		 * all of the bytes in our tx urb (urb->actual_length)
+		 * unless we need a zero-length terminating packet.  We
+		 * need a zero-length terminating packet if we returned
+		 * fewer bytes than were requested (wLength) by the host,
+		 * and the number of bytes we returned is an exact
+		 * multiple of the packet size endpoint->tx_packetSize.
+		 */
+		if ((endpoint->sent == ep0_urb->actual_length) &&
+		    ((ep0_urb->actual_length == wLength) ||
+		     (endpoint->last != endpoint->tx_packetSize))) {
+			/* Done with control read data stage. */
+			UDCDBG("control read data stage complete");
+		} else {
+			/*
+			 * We still have another packet of data to send
+			 * in this control read data stage or else we
+			 * need a zero-length terminating packet.
+			 */
+			UDCDBG("ACK control read data stage packet");
+			spear_write_noniso_tx_fifo(endpoint);
+
+			ep_addr = endpoint->endpoint_address;
+			writel(0x0, &inep_regs_p[ep_addr].write_done);
+		}
+	}
+}
+
+static struct usb_endpoint_instance *spear_find_ep(int ep)
+{
+	int i;
+
+	for (i = 0; i < udc_device->bus->max_endpoints; i++) {
+		if ((udc_device->bus->endpoint_array[i].endpoint_address &
+		     USB_ENDPOINT_NUMBER_MASK) == ep)
+			return &udc_device->bus->endpoint_array[i];
+	}
+	return NULL;
+}
+
+/*
+ * Handle RX transaction on non-ISO endpoint.
+ * The ep argument is a physical endpoint number for a non-ISO IN endpoint
+ * in the range 1 to 15.
+ */
+static void spear_udc_epn_rx(int ep)
+{
+	int nbytes = 0;
+	struct urb *urb;
+	struct usb_endpoint_instance *endpoint = spear_find_ep(ep);
+
+	if (endpoint) {
+		urb = endpoint->rcv_urb;
+
+		if (urb) {
+			u8 *cp = urb->buffer + urb->actual_length;
+
+			nbytes = (readl(&outep_regs_p[ep].endp_status) >> 11) &
+			    0xfff;
+			usbgetpckfromfifo(ep, cp, nbytes);
+			usbd_rcv_complete(endpoint, nbytes, 0);
+		}
+	}
+}
+
+/*
+ * Handle TX transaction on non-ISO endpoint.
+ * The ep argument is a physical endpoint number for a non-ISO IN endpoint
+ * in the range 16 to 30.
+ */
+static void spear_udc_epn_tx(int ep)
+{
+	struct usb_endpoint_instance *endpoint = spear_find_ep(ep);
+
+	/*
+	 * We need to transmit a terminating zero-length packet now if
+	 * we have sent all of the data in this URB and the transfer
+	 * size was an exact multiple of the packet size.
+	 */
+	if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
+		if (endpoint->last == endpoint->tx_packetSize) {
+			/* handle zero length packet here */
+			writel(0x0, &inep_regs_p[ep].write_done);
+		}
+		/* retire the data that was just sent */
+		usbd_tx_complete(endpoint);
+		/*
+		 * Check to see if we have more data ready to transmit
+		 * now.
+		 */
+		if (endpoint->tx_urb && endpoint->tx_urb->actual_length) {
+			/* write data to FIFO */
+			spear_write_noniso_tx_fifo(endpoint);
+			writel(0x0, &inep_regs_p[ep].write_done);
+
+		} else if (endpoint->tx_urb
+			   && (endpoint->tx_urb->actual_length == 0)) {
+			/* udc_set_nak(ep); */
+		}
+	}
+}
+
+/*
+ * Start of public functions.
+ */
+
+/* Called to start packet transmission. */
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint)
+{
+	udc_unset_nak(endpoint->endpoint_address & USB_ENDPOINT_NUMBER_MASK);
+	return 0;
+}
+
+/* Start to initialize h/w stuff */
+int udc_init(void)
+{
+	int i;
+	u32 plug_st;
+
+	udc_device = NULL;
+
+	UDCDBG("starting");
+
+	readl(&plug_regs_p->plug_pending);
+
+	udc_disconnect();
+
+	for (i = 0; i < UDC_INIT_MDELAY; i++)
+		udelay(1000);
+
+	plug_st = readl(&plug_regs_p->plug_state);
+	writel(plug_st | PLUG_STATUS_EN, &plug_regs_p->plug_state);
+
+	writel(~0x0, &udc_regs_p->endp_int);
+	writel(~0x0, &udc_regs_p->dev_int_mask);
+	writel(~0x0, &udc_regs_p->endp_int_mask);
+
+	writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW |
+	       /* Dev_Conf_SYNCFRAME | */
+	       DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf);
+
+	writel(0x0, &udc_regs_p->dev_cntl);
+
+	/* Clear all interrupts pending */
+	writel(DEV_INT_MSK, &udc_regs_p->dev_int);
+
+	return 0;
+}
+
+/*
+ * udc_setup_ep - setup endpoint
+ * Associate a physical endpoint with endpoint_instance
+ */
+void udc_setup_ep(struct usb_device_instance *device,
+		  u32 ep, struct usb_endpoint_instance *endpoint)
+{
+	UDCDBGA("setting up endpoint addr %x", endpoint->endpoint_address);
+	int ep_addr;
+	int ep_num, ep_type;
+	int packet_size;
+	int buffer_size;
+	int attributes;
+	char *tt;
+	u32 endp_intmask;
+
+	tt = getenv("usbtty");
+	if (!tt)
+		tt = "generic";
+
+	ep_addr = endpoint->endpoint_address;
+	ep_num = ep_addr & USB_ENDPOINT_NUMBER_MASK;
+
+	if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
+		/* IN endpoint */
+		packet_size = endpoint->tx_packetSize;
+		buffer_size = packet_size * 2;
+		attributes = endpoint->tx_attributes;
+	} else {
+		/* OUT endpoint */
+		packet_size = endpoint->rcv_packetSize;
+		buffer_size = packet_size * 2;
+		attributes = endpoint->rcv_attributes;
+	}
+
+	switch (attributes & USB_ENDPOINT_XFERTYPE_MASK) {
+	case USB_ENDPOINT_XFER_CONTROL:
+		ep_type = ENDP_EPTYPE_CNTL;
+		break;
+	case USB_ENDPOINT_XFER_BULK:
+	default:
+		ep_type = ENDP_EPTYPE_BULK;
+		break;
+	case USB_ENDPOINT_XFER_INT:
+		ep_type = ENDP_EPTYPE_INT;
+		break;
+	case USB_ENDPOINT_XFER_ISOC:
+		ep_type = ENDP_EPTYPE_ISO;
+		break;
+	}
+
+	struct udc_endp_regs *out_p = &outep_regs_p[ep_num];
+	struct udc_endp_regs *in_p = &inep_regs_p[ep_num];
+
+	if (!ep_addr) {
+		/* Setup endpoint 0 */
+		buffer_size = packet_size;
+
+		writel(readl(&in_p->endp_cntl) | ENDP_CNTL_CNAK,
+		       &in_p->endp_cntl);
+
+		writel(readl(&out_p->endp_cntl) | ENDP_CNTL_CNAK,
+		       &out_p->endp_cntl);
+
+		writel(ENDP_CNTL_CONTROL | ENDP_CNTL_FLUSH, &in_p->endp_cntl);
+
+		writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
+
+		writel(packet_size, &in_p->endp_maxpacksize);
+
+		writel(ENDP_CNTL_CONTROL | ENDP_CNTL_RRDY, &out_p->endp_cntl);
+
+		writel(packet_size | ((buffer_size / sizeof(int)) << 16),
+		       &out_p->endp_maxpacksize);
+
+		writel((packet_size << 19) | ENDP_EPTYPE_CNTL,
+		       &udc_regs_p->udc_endp_reg[ep_num]);
+
+	} else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
+		/* Setup the IN endpoint */
+		writel(0x0, &in_p->endp_status);
+		writel((ep_type << 4) | ENDP_CNTL_RRDY, &in_p->endp_cntl);
+		writel(buffer_size / sizeof(int), &in_p->endp_bsorfn);
+		writel(packet_size, &in_p->endp_maxpacksize);
+
+		if (!strcmp(tt, "cdc_acm")) {
+			if (ep_type == ENDP_EPTYPE_INT) {
+				/* Conf no. 1 Interface no. 0 */
+				writel((packet_size << 19) |
+				       ENDP_EPDIR_IN | (1 << 7) |
+				       (0 << 11) | (ep_type << 5) | ep_num,
+				       &udc_regs_p->udc_endp_reg[ep_num]);
+			} else {
+				/* Conf no. 1 Interface no. 1 */
+				writel((packet_size << 19) |
+				       ENDP_EPDIR_IN | (1 << 7) |
+				       (1 << 11) | (ep_type << 5) | ep_num,
+				       &udc_regs_p->udc_endp_reg[ep_num]);
+			}
+		} else {
+			/* Conf no. 1 Interface no. 0 */
+			writel((packet_size << 19) |
+			       ENDP_EPDIR_IN | (1 << 7) |
+			       (0 << 11) | (ep_type << 5) | ep_num,
+			       &udc_regs_p->udc_endp_reg[ep_num]);
+		}
+
+	} else {
+		/* Setup the OUT endpoint */
+		writel(0x0, &out_p->endp_status);
+		writel((ep_type << 4) | ENDP_CNTL_RRDY, &out_p->endp_cntl);
+		writel(packet_size | ((buffer_size / sizeof(int)) << 16),
+		       &out_p->endp_maxpacksize);
+
+		if (!strcmp(tt, "cdc_acm")) {
+			writel((packet_size << 19) |
+			       ENDP_EPDIR_OUT | (1 << 7) |
+			       (1 << 11) | (ep_type << 5) | ep_num,
+			       &udc_regs_p->udc_endp_reg[ep_num]);
+		} else {
+			writel((packet_size << 19) |
+			       ENDP_EPDIR_OUT | (1 << 7) |
+			       (0 << 11) | (ep_type << 5) | ep_num,
+			       &udc_regs_p->udc_endp_reg[ep_num]);
+		}
+
+	}
+
+	endp_intmask = readl(&udc_regs_p->endp_int_mask);
+	endp_intmask &= ~((1 << ep_num) | 0x10000 << ep_num);
+	writel(endp_intmask, &udc_regs_p->endp_int_mask);
+}
+
+/* Turn on the USB connection by enabling the pullup resistor */
+void udc_connect(void)
+{
+	u32 plug_st;
+
+	plug_st = readl(&plug_regs_p->plug_state);
+	plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
+	writel(plug_st, &plug_regs_p->plug_state);
+}
+
+/* Turn off the USB connection by disabling the pullup resistor */
+void udc_disconnect(void)
+{
+	u32 plug_st;
+
+	plug_st = readl(&plug_regs_p->plug_state);
+	plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE);
+	writel(plug_st, &plug_regs_p->plug_state);
+}
+
+/* Switch on the UDC */
+void udc_enable(struct usb_device_instance *device)
+{
+	UDCDBGA("enable device %p, status %d", device, device->status);
+
+	/* Save the device structure pointer */
+	udc_device = device;
+
+	/* Setup ep0 urb */
+	if (!ep0_urb) {
+		ep0_urb =
+		    usbd_alloc_urb(udc_device, udc_device->bus->endpoint_array);
+	} else {
+		serial_printf("udc_enable: ep0_urb already allocated %p\n",
+			      ep0_urb);
+	}
+
+	writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
+}
+
+/**
+ * udc_startup - allow udc code to do any additional startup
+ */
+void udc_startup_events(struct usb_device_instance *device)
+{
+	/* The DEVICE_INIT event puts the USB device in the state STATE_INIT. */
+	usbd_device_event_irq(device, DEVICE_INIT, 0);
+
+	/*
+	 * The DEVICE_CREATE event puts the USB device in the state
+	 * STATE_ATTACHED.
+	 */
+	usbd_device_event_irq(device, DEVICE_CREATE, 0);
+
+	/*
+	 * Some USB controller driver implementations signal
+	 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here.
+	 * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED,
+	 * and DEVICE_RESET causes a transition to the state STATE_DEFAULT.
+	 * The SPEAr USB client controller has the capability to detect when the
+	 * USB cable is connected to a powered USB bus, so we will defer the
+	 * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later.
+	 */
+
+	udc_enable(device);
+}
+
+/*
+ * Plug detection interrupt handling
+ */
+void spear_udc_plug_irq(void)
+{
+	if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) {
+		/*
+		 * USB cable attached
+		 * Turn off PHY reset bit (PLUG detect).
+		 * Switch PHY opmode to normal operation (PLUG detect).
+		 */
+		udc_connect();
+		writel(DEV_INT_SOF, &udc_regs_p->dev_int_mask);
+
+		UDCDBG("device attached and powered");
+		udc_state_transition(udc_device->device_state, STATE_POWERED);
+	} else {
+		/*
+		 * USB cable detached
+		 * Reset the PHY and switch the mode.
+		 */
+		udc_disconnect();
+		writel(~0x0, &udc_regs_p->dev_int_mask);
+
+		UDCDBG("device detached or unpowered");
+		udc_state_transition(udc_device->device_state, STATE_ATTACHED);
+	}
+}
+
+/*
+ * Device interrupt handling
+ */
+void spear_udc_dev_irq(void)
+{
+	if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) {
+		writel(~0x0, &udc_regs_p->endp_int_mask);
+
+		udc_connect();
+
+		writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH,
+		       &inep_regs_p[0].endp_cntl);
+
+		writel(DEV_INT_USBRESET, &udc_regs_p->dev_int);
+
+		UDCDBG("device reset in progess");
+		udc_state_transition(udc_device->device_state, STATE_DEFAULT);
+	}
+
+	/* Device Enumeration completed */
+	if (readl(&udc_regs_p->dev_int) & DEV_INT_ENUM) {
+		writel(DEV_INT_ENUM, &udc_regs_p->dev_int);
+
+		/* Endpoint interrupt enabled for Ctrl IN & Ctrl OUT */
+		writel(readl(&udc_regs_p->endp_int_mask) & ~0x10001,
+		       &udc_regs_p->endp_int_mask);
+
+		UDCDBG("default -> addressed");
+		udc_state_transition(udc_device->device_state, STATE_ADDRESSED);
+	}
+
+	/* The USB will be in SUSPEND in 3 ms */
+	if (readl(&udc_regs_p->dev_int) & DEV_INT_INACTIVE) {
+		writel(DEV_INT_INACTIVE, &udc_regs_p->dev_int);
+
+		UDCDBG("entering inactive state");
+		/* usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0); */
+	}
+
+	/* SetConfiguration command received */
+	if (readl(&udc_regs_p->dev_int) & DEV_INT_SETCFG) {
+		writel(DEV_INT_SETCFG, &udc_regs_p->dev_int);
+
+		UDCDBG("entering configured state");
+		udc_state_transition(udc_device->device_state,
+				     STATE_CONFIGURED);
+	}
+
+	/* SetInterface command received */
+	if (readl(&udc_regs_p->dev_int) & DEV_INT_SETINTF) {
+		writel(DEV_INT_SETINTF, &udc_regs_p->dev_int);
+	}
+
+	/* USB Suspend detected on cable */
+	if (readl(&udc_regs_p->dev_int) & DEV_INT_SUSPUSB) {
+		writel(DEV_INT_SUSPUSB, &udc_regs_p->dev_int);
+
+		UDCDBG("entering suspended state");
+		usbd_device_event_irq(udc_device, DEVICE_BUS_INACTIVE, 0);
+	}
+
+	/* USB Start-Of-Frame detected on cable */
+	if (readl(&udc_regs_p->dev_int) & DEV_INT_SOF) {
+		writel(DEV_INT_SOF, &udc_regs_p->dev_int);
+	}
+}
+
+/*
+ * Endpoint interrupt handling
+ */
+void spear_udc_endpoint_irq(void)
+{
+	while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) {
+
+		writel(ENDP0_INT_CTRLOUT, &udc_regs_p->endp_int);
+
+		if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK)
+		    == ENDP_STATUS_OUT_SETUP) {
+			spear_udc_setup(udc_device->bus->endpoint_array + 0);
+			writel(ENDP_STATUS_OUT_SETUP,
+			       &outep_regs_p[0].endp_status);
+
+		} else if ((readl(&outep_regs_p[0].endp_status) &
+			    ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
+			spear_udc_ep0_rx(udc_device->bus->endpoint_array + 0);
+			writel(ENDP_STATUS_OUT_DATA,
+			       &outep_regs_p[0].endp_status);
+
+		} else if ((readl(&outep_regs_p[0].endp_status) &
+			    ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
+			/* NONE received */
+		}
+
+		writel(0x0, &outep_regs_p[0].endp_status);
+	}
+
+	if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) {
+		spear_udc_ep0_tx(udc_device->bus->endpoint_array + 0);
+
+		writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status);
+		writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int);
+	}
+
+	while (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) {
+		u32 epnum = 0;
+		u32 ep_int = readl(&udc_regs_p->endp_int) &
+		    ENDP_INT_NONISOOUT_MSK;
+
+		ep_int >>= 16;
+		while (0x0 == (ep_int & 0x1)) {
+			ep_int >>= 1;
+			epnum++;
+		}
+
+		writel((1 << 16) << epnum, &udc_regs_p->endp_int);
+
+		if ((readl(&outep_regs_p[epnum].endp_status) &
+		     ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) {
+
+			spear_udc_epn_rx(epnum);
+			writel(ENDP_STATUS_OUT_DATA,
+			       &outep_regs_p[epnum].endp_status);
+		} else if ((readl(&outep_regs_p[epnum].endp_status) &
+			    ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_NONE) {
+			writel(0x0, &outep_regs_p[epnum].endp_status);
+		}
+	}
+
+	if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOIN_MSK) {
+		u32 epnum = 0;
+		u32 ep_int = readl(&udc_regs_p->endp_int) &
+		    ENDP_INT_NONISOIN_MSK;
+
+		while (0x0 == (ep_int & 0x1)) {
+			ep_int >>= 1;
+			epnum++;
+		}
+
+		if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) {
+			writel(ENDP_STATUS_IN,
+			       &outep_regs_p[epnum].endp_status);
+			spear_udc_epn_tx(epnum);
+
+			writel(ENDP_STATUS_IN,
+			       &outep_regs_p[epnum].endp_status);
+		}
+
+		writel((1 << epnum), &udc_regs_p->endp_int);
+	}
+}
+
+/*
+ * UDC interrupts
+ */
+void udc_irq(void)
+{
+	/*
+	 * Loop while we have interrupts.
+	 * If we don't do this, the input chain
+	 * polling delay is likely to miss
+	 * host requests.
+	 */
+	while (readl(&plug_regs_p->plug_pending))
+		spear_udc_plug_irq();
+
+	while (readl(&udc_regs_p->dev_int))
+		spear_udc_dev_irq();
+
+	if (readl(&udc_regs_p->endp_int))
+		spear_udc_endpoint_irq();
+}
+
+/* Flow control */
+void udc_set_nak(int epid)
+{
+	writel(readl(&inep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
+	       &inep_regs_p[epid].endp_cntl);
+
+	writel(readl(&outep_regs_p[epid].endp_cntl) | ENDP_CNTL_SNAK,
+	       &outep_regs_p[epid].endp_cntl);
+}
+
+void udc_unset_nak(int epid)
+{
+	u32 val;
+
+	val = readl(&inep_regs_p[epid].endp_cntl);
+	val &= ~ENDP_CNTL_SNAK;
+	val |= ENDP_CNTL_CNAK;
+	writel(val, &inep_regs_p[epid].endp_cntl);
+
+	val = readl(&outep_regs_p[epid].endp_cntl);
+	val &= ~ENDP_CNTL_SNAK;
+	val |= ENDP_CNTL_CNAK;
+	writel(val, &outep_regs_p[epid].endp_cntl);
+}
+
+/*******************************************************************
+ * SLAVE MODE ::
+ * Routines to acces RX/TX FIFOs directly.
+ *******************************************************************/
diff --git a/include/configs/spear.h b/include/configs/spear.h
index da10f61..4e0a3dc 100755
--- a/include/configs/spear.h
+++ b/include/configs/spear.h
@@ -42,6 +42,18 @@
 #endif
 
 /*
+ * USBD driver configuration
+ */
+#define CONFIG_SPEARUDC
+#define CONFIG_USB_DEVICE
+#define CONFIG_USB_TTY
+
+#define CONFIG_USBD_PRODUCT_NAME		"SPEAr SoC"
+#define CONFIG_USBD_MANUFACTURER		"ST Microelectronics"
+
+#define CONFIG_EXTRA_ENV_USBTTY			"usbtty=cdc_acm\0"
+
+/*
  * I2C driver configuration
  */
 #define CONFIG_HARD_I2C
@@ -109,6 +121,9 @@
 /*
  * Platform specific defines (SPEAr)
  */
+#define CONFIG_SYS_USBD_BASE			(0xE1100000)
+#define CONFIG_SYS_PLUG_BASE			(0xE1200000)
+#define CONFIG_SYS_FIFO_BASE			(0xE1000800)
 #define CONFIG_SYS_SMI_BASE			(0xFC000000)
 #define CONFIG_SYS_FLASH_BASE			(0xF8000000)
 #define CONFIG_SPEAR_SYSCNTLBASE		(0xFCA00000)
@@ -188,7 +203,12 @@
 /*
  * Default Environment Varible definitions
  */
+#if defined(CONFIG_SPEAR_USBTTY)
+#define CONFIG_BOOTDELAY			-1
+#else
 #define CONFIG_BOOTDELAY			1
+#endif
+
 #define CONFIG_ENV_OVERWRITE
 
 /*
@@ -255,6 +275,8 @@
 #define CONFIG_SYS_CONSOLE_INFO_QUIET		1
 #define CONFIG_SYS_64BIT_VSPRINTF		1
 
+#define CONFIG_EXTRA_ENV_SETTINGS		CONFIG_EXTRA_ENV_USBTTY
+
 /*
  * Stack sizes
  */
diff --git a/include/usb/spr_udc.h b/include/usb/spr_udc.h
new file mode 100755
index 0000000..191c439
--- /dev/null
+++ b/include/usb/spr_udc.h
@@ -0,0 +1,227 @@
+/*
+ * (C) Copyright 2009
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPR_UDC_H
+#define __SPR_UDC_H
+
+/*****************************************************************************
+ * Defines for  USBD
+ *
+ * The udc_ahb controller has three AHB slaves:
+ *
+ * 1.  THe UDC registers
+ * 2.  The plug detect
+ * 3.  The RX/TX FIFO
+ *****************************************************************************/
+
+#define MAX_ENDPOINTS		16
+
+struct udc_endp_regs {
+	u32 endp_cntl;
+	u32 endp_status;
+	u32 endp_bsorfn;
+	u32 endp_maxpacksize;
+	u32 reserved_1;
+	u32 endp_desc_point;
+	u32 reserved_2;
+	u32 write_done;
+};
+
+/* Endpoint Control Register definitions */
+
+#define  ENDP_CNTL_STALL		0x00000001
+#define  ENDP_CNTL_FLUSH		0x00000002
+#define  ENDP_CNTL_SNOOP		0x00000004
+#define  ENDP_CNTL_POLL			0x00000008
+#define  ENDP_CNTL_CONTROL		0x00000000
+#define  ENDP_CNTL_ISO			0x00000010
+#define  ENDP_CNTL_BULK			0x00000020
+#define  ENDP_CNTL_INT			0x00000030
+#define  ENDP_CNTL_NAK			0x00000040
+#define  ENDP_CNTL_SNAK			0x00000080
+#define  ENDP_CNTL_CNAK			0x00000100
+#define  ENDP_CNTL_RRDY			0x00000200
+
+/* Endpoint Satus Register definitions */
+
+#define  ENDP_STATUS_PIDMSK		0x0000000f
+#define  ENDP_STATUS_OUTMSK		0x00000030
+#define  ENDP_STATUS_OUT_NONE		0x00000000
+#define  ENDP_STATUS_OUT_DATA		0x00000010
+#define  ENDP_STATUS_OUT_SETUP		0x00000020
+#define  ENDP_STATUS_IN			0x00000040
+#define  ENDP_STATUS_BUFFNAV		0x00000080
+#define  ENDP_STATUS_FATERR		0x00000100
+#define  ENDP_STATUS_HOSTBUSERR		0x00000200
+#define  ENDP_STATUS_TDC		0x00000400
+#define  ENDP_STATUS_RXPKTMSK		0x003ff800
+
+struct udc_regs {
+	struct udc_endp_regs in_regs[MAX_ENDPOINTS];
+	struct udc_endp_regs out_regs[MAX_ENDPOINTS];
+	u32 dev_conf;
+	u32 dev_cntl;
+	u32 dev_stat;
+	u32 dev_int;
+	u32 dev_int_mask;
+	u32 endp_int;
+	u32 endp_int_mask;
+	u32 reserved_3[0x39];
+	u32 reserved_4;		/* offset 0x500 */
+	u32 udc_endp_reg[MAX_ENDPOINTS];
+};
+
+/* Device Configuration Register definitions */
+
+#define  DEV_CONF_HS_SPEED		0x00000000
+#define  DEV_CONF_LS_SPEED		0x00000002
+#define  DEV_CONF_FS_SPEED		0x00000003
+#define  DEV_CONF_REMWAKEUP		0x00000004
+#define  DEV_CONF_SELFPOW		0x00000008
+#define  DEV_CONF_SYNCFRAME		0x00000010
+#define  DEV_CONF_PHYINT_8		0x00000020
+#define  DEV_CONF_PHYINT_16		0x00000000
+#define  DEV_CONF_UTMI_BIDIR		0x00000040
+#define  DEV_CONF_STATUS_STALL		0x00000080
+
+/* Device Control Register definitions */
+
+#define  DEV_CNTL_RESUME		0x00000001
+#define  DEV_CNTL_TFFLUSH		0x00000002
+#define  DEV_CNTL_RXDMAEN		0x00000004
+#define  DEV_CNTL_TXDMAEN		0x00000008
+#define  DEV_CNTL_DESCRUPD		0x00000010
+#define  DEV_CNTL_BIGEND		0x00000020
+#define  DEV_CNTL_BUFFILL		0x00000040
+#define  DEV_CNTL_TSHLDEN		0x00000080
+#define  DEV_CNTL_BURSTEN		0x00000100
+#define  DEV_CNTL_DMAMODE		0x00000200
+#define  DEV_CNTL_SOFTDISCONNECT	0x00000400
+#define  DEV_CNTL_SCALEDOWN		0x00000800
+#define  DEV_CNTL_BURSTLENU		0x00010000
+#define  DEV_CNTL_BURSTLENMSK		0x00ff0000
+#define  DEV_CNTL_TSHLDLENU		0x01000000
+#define  DEV_CNTL_TSHLDLENMSK		0xff000000
+
+/* Device Status Register definitions */
+
+#define  DEV_STAT_CFG			0x0000000f
+#define  DEV_STAT_INTF			0x000000f0
+#define  DEV_STAT_ALT			0x00000f00
+#define  DEV_STAT_SUSP			0x00001000
+#define  DEV_STAT_ENUM			0x00006000
+#define  DEV_STAT_ENUM_SPEED_HS		0x00000000
+#define  DEV_STAT_ENUM_SPEED_FS		0x00002000
+#define  DEV_STAT_ENUM_SPEED_LS		0x00004000
+#define  DEV_STAT_RXFIFO_EMPTY		0x00008000
+#define  DEV_STAT_PHY_ERR		0x00010000
+#define  DEV_STAT_TS			0xf0000000
+
+/* Device Interrupt Register definitions */
+
+#define  DEV_INT_MSK			0x0000007f
+#define  DEV_INT_SETCFG			0x00000001
+#define  DEV_INT_SETINTF		0x00000002
+#define  DEV_INT_INACTIVE		0x00000004
+#define  DEV_INT_USBRESET		0x00000008
+#define  DEV_INT_SUSPUSB		0x00000010
+#define  DEV_INT_SOF			0x00000020
+#define  DEV_INT_ENUM			0x00000040
+
+/* Endpoint Interrupt Register definitions */
+
+#define  ENDP0_INT_CTRLIN		0x00000001
+#define  ENDP1_INT_BULKIN		0x00000002
+#define  ENDP_INT_NONISOIN_MSK		0x0000AAAA
+#define  ENDP2_INT_BULKIN		0x00000004
+#define  ENDP0_INT_CTRLOUT		0x00010000
+#define  ENDP1_INT_BULKOUT		0x00020000
+#define  ENDP2_INT_BULKOUT		0x00040000
+#define  ENDP_INT_NONISOOUT_MSK		0x55540000
+
+/* Endpoint Register definitions */
+#define  ENDP_EPDIR_OUT			0x00000000
+#define  ENDP_EPDIR_IN			0x00000010
+#define  ENDP_EPTYPE_CNTL		0x0
+#define  ENDP_EPTYPE_ISO		0x1
+#define  ENDP_EPTYPE_BULK		0x2
+#define  ENDP_EPTYPE_INT		0x3
+
+/*
+ * Defines for Plug Detect
+ */
+
+struct plug_regs {
+	u32 plug_state;
+	u32 plug_pending;
+};
+
+/* Plug State Register definitions */
+#define  PLUG_STATUS_EN			0x1
+#define  PLUG_STATUS_ATTACHED		0x2
+#define  PLUG_STATUS_PHY_RESET		0x4
+#define  PLUG_STATUS_PHY_MODE		0x8
+
+/*
+ * Defines for UDC FIFO (Slave Mode)
+ */
+struct udcfifo_regs {
+	u32 *fifo_p;
+};
+
+/*
+ * USBTTY definitions
+ */
+#define  EP0_MAX_PACKET_SIZE        64
+#define  UDC_INT_ENDPOINT           1
+#define  UDC_INT_PACKET_SIZE        64
+#define  UDC_OUT_ENDPOINT           2
+#define  UDC_BULK_PACKET_SIZE       64
+#define  UDC_IN_ENDPOINT            3
+#define  UDC_OUT_PACKET_SIZE        64
+#define  UDC_IN_PACKET_SIZE         64
+
+/*
+ * Function declarations
+ */
+
+void udc_irq(void);
+
+void udc_set_nak(int epid);
+void udc_unset_nak(int epid);
+
+int udc_endpoint_write(struct usb_endpoint_instance *endpoint);
+
+int udc_init(void);
+
+void udc_enable(struct usb_device_instance *device);
+void udc_disable(void);
+
+void udc_connect(void);
+void udc_disconnect(void);
+
+void udc_startup_events(struct usb_device_instance *device);
+void udc_setup_ep(struct usb_device_instance *device, unsigned int ep,
+		  struct usb_endpoint_instance *endpoint);
+
+#endif /* __SPR_UDC_H */
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [U-Boot] [PATCH v3 11/11] SPEAr : Support for cfi driver and parallel NOR flash
  2010-01-08 13:49                   ` [U-Boot] [PATCH v3 10/11] SPEAr : Support for usbd driver and usbtty support Vipin KUMAR
@ 2010-01-08 13:49                     ` Vipin KUMAR
  0 siblings, 0 replies; 13+ messages in thread
From: Vipin KUMAR @ 2010-01-08 13:49 UTC (permalink / raw)
  To: u-boot


Signed-off-by: Vipin <vipin.kumar@st.com>
---
 board/spear/common/spr_misc.c        |   60 +++++++++++++++++++++++++
 include/asm-arm/arch-spear/spr_emi.h |   54 ++++++++++++++++++++++
 include/configs/spear.h              |   82 ++++++++++++++++++++++++++++++---
 3 files changed, 188 insertions(+), 8 deletions(-)
 create mode 100644 include/asm-arm/arch-spear/spr_emi.h

diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c
index 391cec2..8153123 100755
--- a/board/spear/common/spr_misc.c
+++ b/board/spear/common/spr_misc.c
@@ -26,6 +26,7 @@
 #include <i2c.h>
 #include <net.h>
 #include <asm/io.h>
+#include <asm/arch/spr_emi.h>
 #include <asm/arch/spr_xloader_table.h>
 #include <asm/arch/spr_defs.h>
 
@@ -79,6 +80,62 @@ int misc_init_r(void)
 	return 0;
 }
 
+#ifdef CONFIG_SPEAR_EMI
+struct cust_emi_para {
+	unsigned int tap;
+	unsigned int tsdp;
+	unsigned int tdpw;
+	unsigned int tdpr;
+	unsigned int tdcs;
+	unsigned int control;
+};
+
+/* EMI timing setting of m28w640hc of linux kernel */
+const struct cust_emi_para emi_timing_m28w640hc = {
+	.tap = 0x10,
+	.tsdp = 0x05,
+	.tdpw = 0x0a,
+	.tdpr = 0x0a,
+	.tdcs = 0x05,
+};
+
+/* EMI timing setting of bootrom */
+const struct cust_emi_para emi_timing_bootrom = {
+	.tap = 0xf,
+	.tsdp = 0x0,
+	.tdpw = 0xff,
+	.tdpr = 0x111,
+	.tdcs = 0x02,
+};
+
+void spear_emi_init(void)
+{
+	const struct cust_emi_para *p = &emi_timing_m28w640hc;
+	struct emi_regs *emi_regs_p = (struct emi_regs *)CONFIG_SPEAR_EMIBASE;
+	unsigned int cs;
+	unsigned int val, tmp;
+
+	val = readl(CONFIG_SPEAR_RASBASE);
+
+	if (val & EMI_ACKMSK)
+		tmp = 0x3f;
+	else
+		tmp = 0x0;
+
+	writel(tmp, &emi_regs_p->ack);
+
+	for (cs = 0; cs < CONFIG_SYS_MAX_FLASH_BANKS; cs++) {
+		writel(p->tap, &emi_regs_p->bank_regs[cs].tap);
+		writel(p->tsdp, &emi_regs_p->bank_regs[cs].tsdp);
+		writel(p->tdpw, &emi_regs_p->bank_regs[cs].tdpw);
+		writel(p->tdpr, &emi_regs_p->bank_regs[cs].tdpr);
+		writel(p->tdcs, &emi_regs_p->bank_regs[cs].tdcs);
+		writel(EMI_CNTL_ENBBYTERW | ((val & 0x18) >> 3),
+		       &emi_regs_p->bank_regs[cs].control);
+	}
+}
+#endif
+
 int spear_board_init(ulong mach_type)
 {
 	struct xloader_table *xloader_tb =
@@ -100,6 +157,9 @@ int spear_board_init(ulong mach_type)
 		       sizeof(chip->version));
 	}
 
+#ifdef CONFIG_SPEAR_EMI
+	spear_emi_init();
+#endif
 	return 0;
 }
 
diff --git a/include/asm-arm/arch-spear/spr_emi.h b/include/asm-arm/arch-spear/spr_emi.h
new file mode 100644
index 0000000..c1f1c2a
--- /dev/null
+++ b/include/asm-arm/arch-spear/spr_emi.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2009
+ * Ryan CHEN, ST Micoelectronics, ryan.chen at st.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SPEAR_EMI_H__
+#define __SPEAR_EMI_H__
+
+#ifdef CONFIG_SPEAR_EMI
+
+struct emi_bank_regs {
+	u32 tap;
+	u32 tsdp;
+	u32 tdpw;
+	u32 tdpr;
+	u32 tdcs;
+	u32 control;
+};
+
+struct emi_regs {
+	struct emi_bank_regs bank_regs[CONFIG_SYS_MAX_FLASH_BANKS];
+	u32 tout;
+	u32 ack;
+	u32 irq;
+};
+
+#define EMI_ACKMSK		0x40
+
+/* control register definitions */
+#define EMI_CNTL_ENBBYTEW	(1 << 2)
+#define EMI_CNTL_ENBBYTER	(1 << 3)
+#define EMI_CNTL_ENBBYTERW	(EMI_CNTL_ENBBYTER | EMI_CNTL_ENBBYTEW)
+
+#endif
+
+#endif
diff --git a/include/configs/spear.h b/include/configs/spear.h
index 4e0a3dc..78c035f 100755
--- a/include/configs/spear.h
+++ b/include/configs/spear.h
@@ -64,7 +64,11 @@
 /*
  * SMI driver configuration
  */
-#define CONFIG_SPEARSMI
+#if defined(CONFIG_FLASH_PNOR)
+#define CONFIG_SPEAR_EMI			1
+#else
+#define CONFIG_SPEARSMI				1
+#endif
 
 /*
  * Serial Configuration (PL011)
@@ -125,7 +129,6 @@
 #define CONFIG_SYS_PLUG_BASE			(0xE1200000)
 #define CONFIG_SYS_FIFO_BASE			(0xE1000800)
 #define CONFIG_SYS_SMI_BASE			(0xFC000000)
-#define CONFIG_SYS_FLASH_BASE			(0xF8000000)
 #define CONFIG_SPEAR_SYSCNTLBASE		(0xFCA00000)
 #define CONFIG_SPEAR_TIMERBASE			(0xFC800000)
 #define CONFIG_SPEAR_MISCBASE			(0xFCA80000)
@@ -153,11 +156,17 @@
 #define CONFIG_SYS_NAND_CLE			(1 << 17)
 #define CONFIG_SYS_NAND_ALE			(1 << 16)
 
+#define CONFIG_SPEAR_EMIBASE			(0x4F000000)
+#define CONFIG_SPEAR_RASBASE			(0xB4000000)
+
 #elif defined(CONFIG_SPEAR320)
 #define CONFIG_SYS_I2C_BASE			(0xD0180000)
 #define CONFIG_SPEAR_FSMCBASE			(0x4C000000)
 #define CONFIG_SYS_NAND_BASE			(0x50000000)
 
+#define CONFIG_SPEAR_EMIBASE			(0x40000000)
+#define CONFIG_SPEAR_RASBASE			(0xB3000000)
+
 #endif
 
 #define CONFIG_SYS_HZ				(1000)
@@ -166,6 +175,8 @@
 /*
  * FLASH Configuration
  */
+#if defined(CONFIG_SPEARSMI)
+
 #define CONFIG_SYS_MAX_FLASH_BANKS		2
 #define CONFIG_SYS_FLASH_BASE			(0xF8000000)
 #define CONFIG_SYS_CS1_FLASH_BASE		(0xF9000000)
@@ -178,6 +189,44 @@
 #define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
 #define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)
 
+#elif defined(CONFIG_SPEAR_EMI)
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#if defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_FLASH_BASE			0x50000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0x60000000
+#define CONFIG_SYS_CS2_FLASH_BASE		0x70000000
+#define CONFIG_SYS_CS3_FLASH_BASE		0x80000000
+#define CONFIG_SYS_CS4_FLASH_BASE		0x90000000
+#define CONFIG_SYS_CS5_FLASH_BASE		0xA0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
+						CONFIG_SYS_CS1_FLASH_BASE, \
+						CONFIG_SYS_CS2_FLASH_BASE, \
+						CONFIG_SYS_CS3_FLASH_BASE, \
+						CONFIG_SYS_CS4_FLASH_BASE, \
+						CONFIG_SYS_CS5_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS		6
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_FLASH_BASE			0x44000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0x45000000
+#define CONFIG_SYS_CS2_FLASH_BASE		0x46000000
+#define CONFIG_SYS_CS3_FLASH_BASE		0x47000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
+						CONFIG_SYS_CS1_FLASH_BASE, \
+						CONFIG_SYS_CS2_FLASH_BASE, \
+						CONFIG_SYS_CS3_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS		4
+
+#endif
+
+#define CONFIG_SYS_MAX_FLASH_SECT		(127 + 8)
+#define CONFIG_SYS_FLASH_QUIET_TEST		1
+
+#endif
+
 /*
  * NAND FLASH Configuration
  */
@@ -215,26 +264,43 @@
  * U-Boot Environment placing definitions.
  */
 #if defined(CONFIG_ENV_IS_IN_FLASH)
+#ifdef CONFIG_SPEARSMI
+/*
+ * Environment is in serial NOR flash
+ */
 #define CONFIG_SYS_MONITOR_LEN			0x00040000
-#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
-#define CONFIG_ENV_SECT_SIZE			0x10000
+#define CONFIG_ENV_SECT_SIZE			0x00010000
 #define CONFIG_FSMTDBLK				"/dev/mtdblock8 "
-#define CONFIG_ENV_ADDR				(CONFIG_SYS_MONITOR_BASE + \
-						CONFIG_SYS_MONITOR_LEN)
 
 #define CONFIG_BOOTCOMMAND			"bootm 0xf8050000"
 
+#elif defined(CONFIG_SPEAR_EMI)
+/*
+ * Environment is in parallel NOR flash
+ */
+#define CONFIG_SYS_MONITOR_LEN			0x00060000
+#define CONFIG_ENV_SECT_SIZE			0x00020000
+#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "
+
+#define CONFIG_BOOTCOMMAND			"cp.b 0x50080000 0x1600000 " \
+						"0x4C0000; bootm 0x1600000"
+#endif
+
+#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_FLASH_BASE
+#define CONFIG_ENV_ADDR				(CONFIG_SYS_MONITOR_BASE + \
+						CONFIG_SYS_MONITOR_LEN)
 #elif defined(CONFIG_ENV_IS_IN_NAND)
+/*
+ * Environment is in NAND
+ */
 
 #define CONFIG_ENV_OFFSET			0x60000
-#define CONFIG_ENV_SIZE				0x04000
 #define CONFIG_ENV_RANGE			0x10000
 #define CONFIG_FSMTDBLK				"/dev/mtdblock12 "
 
 #define CONFIG_BOOTCOMMAND			"nand read.jffs2 0x1600000 " \
 						"0x80000 0x4C0000; " \
 						"bootm 0x1600000"
-
 #endif
 
 #define CONFIG_BOOTARGS_NFS			"root=/dev/nfs ip=dhcp " \
-- 
1.6.0.2

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [U-Boot] [PATCH v3 06/11] SPEAr : i2c driver support addded
  2010-01-08 13:49           ` [U-Boot] [PATCH v3 06/11] SPEAr : i2c driver support addded Vipin KUMAR
  2010-01-08 13:49             ` [U-Boot] [PATCH v3 07/11] SPEAr : Support for HW macid read/write from i2c memory Vipin KUMAR
@ 2010-01-11  9:44             ` Heiko Schocher
  1 sibling, 0 replies; 13+ messages in thread
From: Heiko Schocher @ 2010-01-11  9:44 UTC (permalink / raw)
  To: u-boot

Hello Vipin,

Vipin KUMAR wrote:
> Signed-off-by: Vipin <vipin.kumar@st.com>
> ---
>  drivers/i2c/Makefile                 |    1 +
>  drivers/i2c/spr_i2c.c                |  340 ++++++++++++++++++++++++++++++++++
>  include/asm-arm/arch-spear/spr_i2c.h |  146 +++++++++++++++
>  include/configs/spear.h              |   11 +
>  4 files changed, 498 insertions(+), 0 deletions(-)
>  mode change 100644 => 100755 drivers/i2c/Makefile
>  create mode 100755 drivers/i2c/spr_i2c.c
>  create mode 100755 include/asm-arm/arch-spear/spr_i2c.h
> 
[...]
> diff --git a/drivers/i2c/spr_i2c.c b/drivers/i2c/spr_i2c.c
> new file mode 100755
> index 0000000..497ca47
> --- /dev/null
> +++ b/drivers/i2c/spr_i2c.c
[...]
> +/*
> + * i2c_set_bus_speed - Set the i2c speed
> + * @speed:	required i2c speed
> + *
> + * Set the i2c speed.
> + */
> +void i2c_set_bus_speed(int speed)
> +{
> +	if (speed >= I2C_MAX_SPEED) {
> +		set_speed(IC_SPEED_MODE_MAX);

No brackets for single statement, please,

> +

blank line not needed here.

> +	} else if (speed >= I2C_FAST_SPEED) {
> +		set_speed(IC_SPEED_MODE_FAST);
> +

same as above.

> +	} else {
> +		set_speed(IC_SPEED_MODE_STANDARD);
> +	}
> +}
> +
> +/*
> + * i2c_get_bus_speed - Gets the i2c speed
> + *
> + * Gets the i2c speed.
> + */
> +int i2c_get_bus_speed(void)
> +{
> +	u32 cntl;
> +
> +	cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK);
> +
> +	if (cntl == IC_CON_SPD_HS) {
> +		return I2C_MAX_SPEED;
> +

here too, please fix globally.

[...]

If you fix this small Coding Style issues, you get my:

Acked-by: Heiko Schocher<hs@denx.de>

thanks!

bye
Heiko
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, other threads:[~2010-01-11  9:44 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-01-08 13:48 [U-Boot] [PATCH v3 00/11] SPEAr : Adding support for SPEAr SoCs Vipin KUMAR
2010-01-08 13:48 ` [U-Boot] [PATCH v3 01/11] SPEAr : Adding README.spear in doc Vipin KUMAR
2010-01-08 13:48   ` [U-Boot] [PATCH v3 02/11] SPEAr : Adding basic support for SPEAr600 Vipin KUMAR
2010-01-08 13:48     ` [U-Boot] [PATCH v3 03/11] SPEAr : Adding basic support for SPEAr300 Vipin KUMAR
2010-01-08 13:49       ` [U-Boot] [PATCH v3 04/11] SPEAr : Adding basic support for SPEAr310 Vipin KUMAR
2010-01-08 13:49         ` [U-Boot] [PATCH v3 05/11] SPEAr : Adding basic support for SPEAr320 Vipin KUMAR
2010-01-08 13:49           ` [U-Boot] [PATCH v3 06/11] SPEAr : i2c driver support addded Vipin KUMAR
2010-01-08 13:49             ` [U-Boot] [PATCH v3 07/11] SPEAr : Support for HW macid read/write from i2c memory Vipin KUMAR
2010-01-08 13:49               ` [U-Boot] [PATCH v3 08/11] SPEAr : Support for serial memory interface driver and serial NOR flash Vipin KUMAR
2010-01-08 13:49                 ` [U-Boot] [PATCH v3 09/11] SPEAr : Support for nand driver Vipin KUMAR
2010-01-08 13:49                   ` [U-Boot] [PATCH v3 10/11] SPEAr : Support for usbd driver and usbtty support Vipin KUMAR
2010-01-08 13:49                     ` [U-Boot] [PATCH v3 11/11] SPEAr : Support for cfi driver and parallel NOR flash Vipin KUMAR
2010-01-11  9:44             ` [U-Boot] [PATCH v3 06/11] SPEAr : i2c driver support addded Heiko Schocher

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