From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerry Van Baren Date: Tue, 19 Jan 2010 08:58:27 -0500 Subject: [U-Boot] U-boot running on DDR fails to detect the CFI compliant flash In-Reply-To: <201001191449.27687.sr@denx.de> References: <201001180945.57013.sr@denx.de> <201001191449.27687.sr@denx.de> Message-ID: <4B55BA83.4050505@ge.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Stefan Roese wrote: > On Tuesday 19 January 2010 07:24:10 prakash bedge wrote: >> I have tried the code in the URL link you have provided. But still I am >> facing the same problem. I am getting the error in "flash_detect_cfi" as >> flash not found. It fails at initial stage at read CFI query command. >> The code you have provided is for M29W128GL.(Numonix). Will this work for >> M29W128GH (STMIcrotronics)? > > Frankly, I don't know. You need to check the datasheets, to see if there are > some differences. > >> I believe Uboot support M29W128GH flash. I am using this flash chip in 16 x >> 8 bit mode. >> The URL I provided is available under the thread: >> "[U-Boot] Query: Does Uboot support CFI flash driver forM29W128GH". >> Can there be an endianness issue, as I am running uboot from SDRAM and in >> Big endian mode? > > No, I don't think that this is an endian issue. All PPC4xx platforms are doing > it the same way. This must be a different problem. > > Did you check that the NOR chip is really selected (chip select signal etc on > the FLASH chip via oscilloscope)? Are the addresses correct for the query > (etc) commands? > > Cheers, > Stefan IIRC, Prakash added debug print statements that showed the "Q" of the "QRY" being read, but did not show anything more. As a result, it was impossible to tell why the CFI detect was not working. What I find is *VERY* helpful when trying to understand flash control issues is to *manually* do the QRY write sequence (see your flash data sheet) by using memory write/read commands from the u-boot command prompt. This way I can quickly try different byte widths, lanes, etc. for the writes and see the full QRY response from the memory. Usually the problem is a simple misunderstanding of how the chip is configured or the hardware is wired (beware of hardware designers doing "endian fixes"). Good luck, gvb