[U-Boot] [PATCH] OMAP3EVM: Added NAND support

[U-Boot] [PATCH] OMAP3EVM: Added NAND support

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

User can now choose between NAND and ONENAND support in omap3_evm.h

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 include/configs/omap3_evm.h |   27 ++++++++++++++++++++++++++-
 1 files changed, 26 insertions(+), 1 deletions(-)

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index a5514ae..3434306 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -110,7 +110,8 @@

 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+/*#define CONFIG_CMD_ONENAND*/	/* ONENAND support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING

@@ -141,6 +142,7 @@
 							/* to access */
 							/* nand at CS0 */

+
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
 							/* NAND devices */
 #define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
@@ -268,7 +270,13 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND		1
+#elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_ENV_IS_IN_ONENAND	1
+#endif
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

@@ -300,6 +308,23 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif

+
+#define WRITE_NAND_COMMAND(d, adr)\
+			writel(d, &nand_cs_base->nand_cmd)
+#define WRITE_NAND_ADDRESS(d, adr)\
+			writel(d, &nand_cs_base->nand_adr)
+#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
+#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
+
+/* Other NAND Access APIs */
+#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
+			while (0)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+#define NAND_WAIT_READY(nand)	udelay(10)
+
 /*----------------------------------------------------------------------------
  * SMSC9115 Ethernet from SMSC9118 family
  *----------------------------------------------------------------------------
--
1.6.2.4

[U-Boot] [PATCH] OMAP3EVM: Added NAND support

[Dirk Behme]

hvaibhav at ti.com wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> User can now choose between NAND and ONENAND support in omap3_evm.h
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
>  include/configs/omap3_evm.h |   27 ++++++++++++++++++++++++++-
>  1 files changed, 26 insertions(+), 1 deletions(-)
> 
> diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
> index a5514ae..3434306 100644
> --- a/include/configs/omap3_evm.h
> +++ b/include/configs/omap3_evm.h
> @@ -110,7 +110,8 @@
> 
>  #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
>  #define CONFIG_CMD_MMC		/* MMC support			*/
> -#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
> +/*#define CONFIG_CMD_ONENAND*/	/* ONENAND support		*/
> +#define CONFIG_CMD_NAND		/* NAND support			*/

Is it okay to switch the default from ONENAND to NAND here?

>  #define CONFIG_CMD_DHCP
>  #define CONFIG_CMD_PING
> 
> @@ -141,6 +142,7 @@
>  							/* to access */
>  							/* nand at CS0 */
> 
> +

?

>  #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
>  							/* NAND devices */
>  #define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
> @@ -268,7 +270,13 @@
>  #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
>  #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
> 
> +#if defined(CONFIG_CMD_NAND)
> +#define CONFIG_NAND_OMAP_GPMC
> +#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
> +#define CONFIG_ENV_IS_IN_NAND		1
> +#elif defined(CONFIG_CMD_ONENAND)
>  #define CONFIG_ENV_IS_IN_ONENAND	1
> +#endif
>  #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
>  #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
> 
> @@ -300,6 +308,23 @@ extern unsigned int boot_flash_sec;
>  extern unsigned int boot_flash_type;
>  #endif
> 
> +
> +#define WRITE_NAND_COMMAND(d, adr)\
> +			writel(d, &nand_cs_base->nand_cmd)
> +#define WRITE_NAND_ADDRESS(d, adr)\
> +			writel(d, &nand_cs_base->nand_adr)
> +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
> +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
> +
> +/* Other NAND Access APIs */
> +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
> +			while (0)
> +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
> +			while (0)
> +#define NAND_DISABLE_CE(nand)
> +#define NAND_ENABLE_CE(nand)
> +#define NAND_WAIT_READY(nand)	udelay(10)

Would encapsulating this with

#if defined(CONFIG_CMD_NAND)

#endif

make sense here?

Best regards

Dirk

[U-Boot] [PATCH] OMAP3EVM: Added NAND support

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Dirk Behme [mailto:dirk.behme at googlemail.com]
> Sent: Wednesday, November 18, 2009 1:01 PM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH] OMAP3EVM: Added NAND support
> 
> hvaibhav at ti.com wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > User can now choose between NAND and ONENAND support in
> omap3_evm.h
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > ---
> >  include/configs/omap3_evm.h |   27 ++++++++++++++++++++++++++-
> >  1 files changed, 26 insertions(+), 1 deletions(-)
> >
> > diff --git a/include/configs/omap3_evm.h
> b/include/configs/omap3_evm.h
> > index a5514ae..3434306 100644
> > --- a/include/configs/omap3_evm.h
> > +++ b/include/configs/omap3_evm.h
> > @@ -110,7 +110,8 @@
> >
> >  #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
> >  #define CONFIG_CMD_MMC		/* MMC support			*/
> > -#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
> > +/*#define CONFIG_CMD_ONENAND*/	/* ONENAND support		*/
> > +#define CONFIG_CMD_NAND		/* NAND support			*/
> 
> Is it okay to switch the default from ONENAND to NAND here?
> 
[Hiremath, Vaibhav] Most EVM's which I have seen comes with NAND support, so I have chosen NAND as a default.  And anyway here user can select ONENAND also.

Do you see any issues with moving NAND as a default?

> >  #define CONFIG_CMD_DHCP
> >  #define CONFIG_CMD_PING
> >
> > @@ -141,6 +142,7 @@
> >  							/* to access */
> >  							/* nand at CS0 */
> >
> > +
> 
> ?
> 
> >  #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number
> of */
> >  							/* NAND devices */
> >  #define CONFIG_SYS_64BIT_VSPRINTF		/* needed for
> nand_util.c */
> > @@ -268,7 +270,13 @@
> >  #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
> >  #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
> >
> > +#if defined(CONFIG_CMD_NAND)
> > +#define CONFIG_NAND_OMAP_GPMC
> > +#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
> > +#define CONFIG_ENV_IS_IN_NAND		1
> > +#elif defined(CONFIG_CMD_ONENAND)
> >  #define CONFIG_ENV_IS_IN_ONENAND	1
> > +#endif
> >  #define ONENAND_ENV_OFFSET		0x260000 /* environment starts
> here */
> >  #define SMNAND_ENV_OFFSET		0x260000 /* environment starts
> here */
> >
> > @@ -300,6 +308,23 @@ extern unsigned int boot_flash_sec;
> >  extern unsigned int boot_flash_type;
> >  #endif
> >
> > +
> > +#define WRITE_NAND_COMMAND(d, adr)\
> > +			writel(d, &nand_cs_base->nand_cmd)
> > +#define WRITE_NAND_ADDRESS(d, adr)\
> > +			writel(d, &nand_cs_base->nand_adr)
> > +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
> > +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
> > +
> > +/* Other NAND Access APIs */
> > +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |=
> GPMC_CONFIG_WP; } \
> > +			while (0)
> > +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &=
> ~GPMC_CONFIG_WP; } \
> > +			while (0)
> > +#define NAND_DISABLE_CE(nand)
> > +#define NAND_ENABLE_CE(nand)
> > +#define NAND_WAIT_READY(nand)	udelay(10)
> 
> Would encapsulating this with
> 
> #if defined(CONFIG_CMD_NAND)
> 
> #endif
> 
> make sense here?
> 
[Hiremath, Vaibhav] Opps. Sorry, by mistake I have sent old patch, sending you the cleaned one.

Thanks,
Vaibhav
> Best regards
> 
> Dirk

[U-Boot] [PATCH] OMAP3EVM: Added NAND support

[Nishanth Menon]

On Wed, Nov 18, 2009 at 12:58 AM,  <hvaibhav@ti.com> wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
>
> User can now choose between NAND and ONENAND support in omap3_evm.h
>
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
> ?include/configs/omap3_evm.h | ? 27 ++++++++++++++++++++++++++-
> ?1 files changed, 26 insertions(+), 1 deletions(-)
>
> diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
> index a5514ae..3434306 100644
> --- a/include/configs/omap3_evm.h
> +++ b/include/configs/omap3_evm.h
> @@ -110,7 +110,8 @@
>
> ?#define CONFIG_CMD_I2C ? ? ? ? /* I2C serial bus support ? ? ? */
> ?#define CONFIG_CMD_MMC ? ? ? ? /* MMC support ? ? ? ? ? ? ? ? ?*/
> -#define CONFIG_CMD_ONENAND ? ? /* ONENAND support ? ? ? ? ? ? ?*/
> +/*#define CONFIG_CMD_ONENAND*/ /* ONENAND support ? ? ? ? ? ? ?*/
do you wish to use #undef instead of commented code? also adding a
comment on top saying this is an option might help..

This patch opens up a chain for me: how do we have the same build of
u-boot boot accross nand, onenand, mmc  type devices?
current  u-boot looks constrainted in that respect.

> +#define CONFIG_CMD_NAND ? ? ? ? ? ? ? ?/* NAND support ? ? ? ? ? ? ? ? */
> ?#define CONFIG_CMD_DHCP
> ?#define CONFIG_CMD_PING
>
> @@ -141,6 +142,7 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?/* to access */
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?/* nand at CS0 */
>
> +
> ?#define CONFIG_SYS_MAX_NAND_DEVICE ? ? 1 ? ? ? ? ? ? ? /* Max number of */
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?/* NAND devices */
> ?#define CONFIG_SYS_64BIT_VSPRINTF ? ? ? ? ? ? ?/* needed for nand_util.c */
> @@ -268,7 +270,13 @@
> ?#define CONFIG_SYS_MONITOR_BASE ? ? ? ? ? ? ? ?CONFIG_SYS_FLASH_BASE
> ?#define CONFIG_SYS_ONENAND_BASE ? ? ? ? ? ? ? ?ONENAND_MAP
>
> +#if defined(CONFIG_CMD_NAND)
> +#define CONFIG_NAND_OMAP_GPMC
> +#define GPMC_NAND_ECC_LP_x16_LAYOUT ? ?1
> +#define CONFIG_ENV_IS_IN_NAND ? ? ? ? ?1
> +#elif defined(CONFIG_CMD_ONENAND)
> ?#define CONFIG_ENV_IS_IN_ONENAND ? ? ? 1
> +#endif

what if a user decided to enable NAND and ONENAND?

> ?#define ONENAND_ENV_OFFSET ? ? ? ? ? ? 0x260000 /* environment starts here */
> ?#define SMNAND_ENV_OFFSET ? ? ? ? ? ? ?0x260000 /* environment starts here */
>
> @@ -300,6 +308,23 @@ extern unsigned int boot_flash_sec;
> ?extern unsigned int boot_flash_type;
> ?#endif
>
> +
> +#define WRITE_NAND_COMMAND(d, adr)\
> + ? ? ? ? ? ? ? ? ? ? ? writel(d, &nand_cs_base->nand_cmd)
writel? i thought u had 16 bit nand device.

> +#define WRITE_NAND_ADDRESS(d, adr)\
> + ? ? ? ? ? ? ? ? ? ? ? writel(d, &nand_cs_base->nand_adr)
> +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
> +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
readl?? should'nt you be using readw?

Why these functions? does'nt mtd layer handle this? look at beagle ->
it does not use that..

> +
> +/* Other NAND Access APIs */
> +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
> + ? ? ? ? ? ? ? ? ? ? ? while (0)
> +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
> + ? ? ? ? ? ? ? ? ? ? ? while (0)
> +#define NAND_DISABLE_CE(nand)
> +#define NAND_ENABLE_CE(nand)
> +#define NAND_WAIT_READY(nand) ?udelay(10)
> +
are these really needed?

> ?/*----------------------------------------------------------------------------
> ?* SMSC9115 Ethernet from SMSC9118 family
> ?*----------------------------------------------------------------------------
> --
> 1.6.2.4
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>

[U-Boot] [PATCH] OMAP3EVM: Added NAND support

[Scott Wood]

Nishanth Menon wrote:
>> +
>> +#define WRITE_NAND_COMMAND(d, adr)\
>> +                       writel(d, &nand_cs_base->nand_cmd)
> writel? i thought u had 16 bit nand device.
> 
>> +#define WRITE_NAND_ADDRESS(d, adr)\
>> +                       writel(d, &nand_cs_base->nand_adr)
>> +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
>> +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
> readl?? should'nt you be using readw?
> 
> Why these functions? does'nt mtd layer handle this? look at beagle ->
> it does not use that..
> 
>> +
>> +/* Other NAND Access APIs */
>> +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
>> +                       while (0)
>> +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
>> +                       while (0)
>> +#define NAND_DISABLE_CE(nand)
>> +#define NAND_ENABLE_CE(nand)
>> +#define NAND_WAIT_READY(nand)  udelay(10)
>> +
> are these really needed?

No, they're not needed.  That is the legacy NAND interface that has been 
superseded and removed.

-Scott

[U-Boot] [PATCH] OMAP3EVM: Added NAND support

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Nishanth Menon [mailto:menon.nishanth at gmail.com]
> Sent: Wednesday, November 18, 2009 11:38 PM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH] OMAP3EVM: Added NAND support
> 
> On Wed, Nov 18, 2009 at 12:58 AM,  <hvaibhav@ti.com> wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > User can now choose between NAND and ONENAND support in
> omap3_evm.h
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > ---
> > ?include/configs/omap3_evm.h | ? 27 ++++++++++++++++++++++++++-
> > ?1 files changed, 26 insertions(+), 1 deletions(-)
> >
> > diff --git a/include/configs/omap3_evm.h
> b/include/configs/omap3_evm.h
> > index a5514ae..3434306 100644
> > --- a/include/configs/omap3_evm.h
> > +++ b/include/configs/omap3_evm.h
> > @@ -110,7 +110,8 @@
> >
> > ?#define CONFIG_CMD_I2C ? ? ? ? /* I2C serial bus support ? ? ? */
> > ?#define CONFIG_CMD_MMC ? ? ? ? /* MMC support ? ? ? ? ? ? ? ? ?*/
> > -#define CONFIG_CMD_ONENAND ? ? /* ONENAND support ? ? ? ? ? ? ?*/
> > +/*#define CONFIG_CMD_ONENAND*/ /* ONENAND support ? ? ? ? ? ? ?*/
> do you wish to use #undef instead of commented code? also adding a
> comment on top saying this is an option might help..
> 
[Hiremath, Vaibhav] Good point, I will add this.

> This patch opens up a chain for me: how do we have the same build of
> u-boot boot accross nand, onenand, mmc  type devices?
> current  u-boot looks constrainted in that respect.
> 
[Hiremath, Vaibhav] Atleast for NAND and MMC we are using same build for obvious reasons, but I am not sure about onenand though. I need to look at it.

> > +#define CONFIG_CMD_NAND ? ? ? ? ? ? ? ?/* NAND support
> ? ? ? */
> > ?#define CONFIG_CMD_DHCP
> > ?#define CONFIG_CMD_PING
> >
> > @@ -141,6 +142,7 @@
> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?/* to
> access */
> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?/* nand at
> CS0 */
> >
> > +
> > ?#define CONFIG_SYS_MAX_NAND_DEVICE ? ? 1 ? ? ? ? ? ? ? /* Max
> number of */
> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?/* NAND
> devices */
> > ?#define CONFIG_SYS_64BIT_VSPRINTF ? ? ? ? ? ? ?/* needed for
> nand_util.c */
> > @@ -268,7 +270,13 @@
> > ?#define CONFIG_SYS_MONITOR_BASE
> ?CONFIG_SYS_FLASH_BASE
> > ?#define CONFIG_SYS_ONENAND_BASE ? ? ? ? ? ? ? ?ONENAND_MAP
> >
> > +#if defined(CONFIG_CMD_NAND)
> > +#define CONFIG_NAND_OMAP_GPMC
> > +#define GPMC_NAND_ECC_LP_x16_LAYOUT ? ?1
> > +#define CONFIG_ENV_IS_IN_NAND ? ? ? ? ?1
> > +#elif defined(CONFIG_CMD_ONENAND)
> > ?#define CONFIG_ENV_IS_IN_ONENAND ? ? ? 1
> > +#endif
> 
> what if a user decided to enable NAND and ONENAND?
> 
> > ?#define ONENAND_ENV_OFFSET ? ? ? ? ? ? 0x260000 /* environment
> starts here */
> > ?#define SMNAND_ENV_OFFSET ? ? ? ? ? ? ?0x260000 /* environment
> starts here */
> >
> > @@ -300,6 +308,23 @@ extern unsigned int boot_flash_sec;
> > ?extern unsigned int boot_flash_type;
> > ?#endif
> >
> > +
> > +#define WRITE_NAND_COMMAND(d, adr)\
> > + ? ? ? ? ? ? ? ? ? ? ? writel(d, &nand_cs_base->nand_cmd)
> writel? i thought u had 16 bit nand device.
> 
> > +#define WRITE_NAND_ADDRESS(d, adr)\
> > + ? ? ? ? ? ? ? ? ? ? ? writel(d, &nand_cs_base->nand_adr)
> > +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
> > +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
> readl?? should'nt you be using readw?
> 
> Why these functions? does'nt mtd layer handle this? look at beagle -
> >
> it does not use that..
> 
> > +
> > +/* Other NAND Access APIs */
> > +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |=
> GPMC_CONFIG_WP; } \
> > + ? ? ? ? ? ? ? ? ? ? ? while (0)
> > +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &=
> ~GPMC_CONFIG_WP; } \
> > + ? ? ? ? ? ? ? ? ? ? ? while (0)
> > +#define NAND_DISABLE_CE(nand)
> > +#define NAND_ENABLE_CE(nand)
> > +#define NAND_WAIT_READY(nand) ?udelay(10)
> > +
> are these really needed?
[Hiremath, Vaibhav] Nishant, you are looking at old patchset which I sent by mistake. Please review new V3 version of patch.

Thanks,
Vaibhav

> 
> > ?/*---------------------------------------------------------------
> -------------
> > ?* SMSC9115 Ethernet from SMSC9118 family
> > ?*----------------------------------------------------------------
> ------------
> > --
> > 1.6.2.4
> >
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
> >

[U-Boot] [PATCH] OMAP3EVM: Added NAND support

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>


Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 include/configs/omap3_evm.h |   10 +++++++++-
 1 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index a5514ae..fbc45dc 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -110,7 +110,8 @@
 
 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+/*#define CONFIG_CMD_ONENAND*/	/* ONENAND support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING
 
@@ -141,6 +142,7 @@
 							/* to access */
 							/* nand at CS0 */
 
+
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
 							/* NAND devices */
 #define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
@@ -268,7 +270,13 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
 
+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND		1
+#elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_ENV_IS_IN_ONENAND	1
+#endif
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
 
-- 
1.6.2.4

[U-Boot] [PATCH] OMAP3EVM: Added NAND support

[Dirk Behme]

It would have been nice if subject had a 'v2' now.

hvaibhav at ti.com wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>

Patch description missing here now. And if you re-add, it would be 
good to mention that you switch from ONENAND to NAND, too.

> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
>  include/configs/omap3_evm.h |   10 +++++++++-
>  1 files changed, 9 insertions(+), 1 deletions(-)
> 
> diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
> index a5514ae..fbc45dc 100644
> --- a/include/configs/omap3_evm.h
> +++ b/include/configs/omap3_evm.h
> @@ -110,7 +110,8 @@
>  
>  #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
>  #define CONFIG_CMD_MMC		/* MMC support			*/
> -#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
> +/*#define CONFIG_CMD_ONENAND*/	/* ONENAND support		*/
> +#define CONFIG_CMD_NAND		/* NAND support			*/

Often it can be irritating for users if default changes silently. But 
EVM people have to discuss about this, I can't say what the preferred 
NAND support is.

>  #define CONFIG_CMD_DHCP
>  #define CONFIG_CMD_PING
>  
> @@ -141,6 +142,7 @@
>  							/* to access */
>  							/* nand at CS0 */
>  
> +

What's this?

Best regards

Dirk

>  #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
>  							/* NAND devices */
>  #define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
> @@ -268,7 +270,13 @@
>  #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
>  #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
>  
> +#if defined(CONFIG_CMD_NAND)
> +#define CONFIG_NAND_OMAP_GPMC
> +#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
> +#define CONFIG_ENV_IS_IN_NAND		1
> +#elif defined(CONFIG_CMD_ONENAND)
>  #define CONFIG_ENV_IS_IN_ONENAND	1
> +#endif
>  #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
>  #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
>  

[U-Boot] [PATCH] OMAP3EVM: Added NAND support

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Dirk Behme [mailto:dirk.behme at googlemail.com]
> Sent: Wednesday, November 18, 2009 2:07 PM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH] OMAP3EVM: Added NAND support
> 
> 
> It would have been nice if subject had a 'v2' now.
> 
[Hiremath, Vaibhav] Ok.

> hvaibhav at ti.com wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> Patch description missing here now. And if you re-add, it would be
> good to mention that you switch from ONENAND to NAND, too.
> 
[Hiremath, Vaibhav] Will add the description accordingly and submit 'v3'.

> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > ---
> >  include/configs/omap3_evm.h |   10 +++++++++-
> >  1 files changed, 9 insertions(+), 1 deletions(-)
> >
> > diff --git a/include/configs/omap3_evm.h
> b/include/configs/omap3_evm.h
> > index a5514ae..fbc45dc 100644
> > --- a/include/configs/omap3_evm.h
> > +++ b/include/configs/omap3_evm.h
> > @@ -110,7 +110,8 @@
> >
> >  #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
> >  #define CONFIG_CMD_MMC		/* MMC support			*/
> > -#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
> > +/*#define CONFIG_CMD_ONENAND*/	/* ONENAND support		*/
> > +#define CONFIG_CMD_NAND		/* NAND support			*/
> 
> Often it can be irritating for users if default changes silently.
> But
> EVM people have to discuss about this, I can't say what the
> preferred
> NAND support is.
> 
[Hiremath, Vaibhav] If we don't get any objection/comments for this change, then I think it should be safe to change to NAND support by default.

> >  #define CONFIG_CMD_DHCP
> >  #define CONFIG_CMD_PING
> >
> > @@ -141,6 +142,7 @@
> >  							/* to access */
> >  							/* nand at CS0 */
> >
> > +
> 
> What's this?
[Hiremath, Vaibhav] Will remove in next version.

Thanks Dirk for reviewing this patch.

Thanks,
Vaibhav
> 
> Best regards
> 
> Dirk
> 
> >  #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number
> of */
> >  							/* NAND devices */
> >  #define CONFIG_SYS_64BIT_VSPRINTF		/* needed for
> nand_util.c */
> > @@ -268,7 +270,13 @@
> >  #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
> >  #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
> >
> > +#if defined(CONFIG_CMD_NAND)
> > +#define CONFIG_NAND_OMAP_GPMC
> > +#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
> > +#define CONFIG_ENV_IS_IN_NAND		1
> > +#elif defined(CONFIG_CMD_ONENAND)
> >  #define CONFIG_ENV_IS_IN_ONENAND	1
> > +#endif
> >  #define ONENAND_ENV_OFFSET		0x260000 /* environment starts
> here */
> >  #define SMNAND_ENV_OFFSET		0x260000 /* environment starts
> here */
> >
> 

[U-Boot] [PATCH V4] OMAP3EVM: Added NAND support

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

The EVMS have been shipping with NAND (instead of OneNAND) as default. So, this
patch sets NAND as default.

To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the config file
omap3_evm.h

Changes from V3 :-
	- Added undef statement for CMD_ONENAND.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 include/configs/omap3_evm.h |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 6709edc..36cb5e0 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -113,7 +113,8 @@

 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#undef CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING

@@ -271,7 +272,13 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND		1
+#elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_ENV_IS_IN_ONENAND	1
+#endif
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

--
1.6.2.4

[U-Boot] [PATCH V4] OMAP3EVM: Added NAND support

[Tom]

hvaibhav at ti.com wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> The EVMS have been shipping with NAND (instead of OneNAND) as default. So, this
> patch sets NAND as default.
> 
> To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the config file
> omap3_evm.h
> 
> Changes from V3 :-
> 	- Added undef statement for CMD_ONENAND.
> 

This is looking good.
Is there interest in making the onenand a makefile config option?
It would depend on how common the onenand boards are.
Tom

[U-Boot] [PATCH V4] OMAP3EVM: Added NAND support

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Tom [mailto:Tom.Rix at windriver.com]
> Sent: Friday, November 27, 2009 9:21 PM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH V4] OMAP3EVM: Added NAND support
> 
> hvaibhav at ti.com wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > The EVMS have been shipping with NAND (instead of OneNAND) as
> default. So, this
> > patch sets NAND as default.
> >
> > To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the
> config file
> > omap3_evm.h
> >
> > Changes from V3 :-
> > 	- Added undef statement for CMD_ONENAND.
> >
> 
> This is looking good.
> Is there interest in making the onenand a makefile config option?
> It would depend on how common the onenand boards are.
[Hiremath, Vaibhav] As far as I know, majority of the EVM's shipping out are with NAND parts, so should be safe to move to NAND as a default.

Thanks,
Vaibhav

> Tom

[U-Boot] [PATCH] omap3_mmc: Encapsulate twl4030 under option CONFIG_TWL4030_POWER

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

Fixes the build/compilation error if we try to re-use the omap3_mmc code
without TWL4030_POWER.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 drivers/mmc/omap3_mmc.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c
index 513dd25..96c0e65 100644
--- a/drivers/mmc/omap3_mmc.c
+++ b/drivers/mmc/omap3_mmc.c
@@ -63,7 +63,9 @@ unsigned char mmc_board_init(void)
 {
 	t2_t *t2_base = (t2_t *)T2_BASE;

+#if defined(CONFIG_TWL4030_POWER)
 	twl4030_power_mmc_init();
+#endif

 	writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
 		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
--
1.6.2.4

[U-Boot] [PATCH] omap3_mmc: Encapsulate twl4030 under option CONFIG_TWL4030_POWER

[Tom]

hvaibhav at ti.com wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> Fixes the build/compilation error if we try to re-use the omap3_mmc code
> without TWL4030_POWER.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>

This is fine.
I have pushed this to arm/next.

Thanks
Tom

[U-Boot] [PATCH] omap3_mmc: Encapsulate twl4030 under option CONFIG_TWL4030_POWER

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Tom [mailto:Tom.Rix at windriver.com]
> Sent: Friday, November 27, 2009 7:34 PM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH] omap3_mmc: Encapsulate twl4030 under
> option CONFIG_TWL4030_POWER
> 
> hvaibhav at ti.com wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > Fixes the build/compilation error if we try to re-use the
> omap3_mmc code
> > without TWL4030_POWER.
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> This is fine.
> I have pushed this to arm/next.
> 
[Hiremath, Vaibhav] Thanks, 

Thanks,
Vaibhav

> Thanks
> Tom

[U-Boot] [PATCH 1/5] Introducing AM3517EVM support

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

Changes:-
	- Added board specific directory under board/ti/am3517/
	- Basic board support.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 board/ti/am3517evm/Makefile      |   46 +++++
 board/ti/am3517evm/am3517evm.c   |   76 ++++++++
 board/ti/am3517evm/am3517evm.h   |  388 ++++++++++++++++++++++++++++++++++++++
 board/ti/am3517evm/config.mk     |   29 +++
 include/asm-arm/arch-omap3/mem.h |   10 +
 5 files changed, 549 insertions(+), 0 deletions(-)
 create mode 100644 board/ti/am3517evm/Makefile
 create mode 100644 board/ti/am3517evm/am3517evm.c
 create mode 100644 board/ti/am3517evm/am3517evm.h
 create mode 100644 board/ti/am3517evm/config.mk

diff --git a/board/ti/am3517evm/Makefile b/board/ti/am3517evm/Makefile
new file mode 100644
index 0000000..68fb574
--- /dev/null
+++ b/board/ti/am3517evm/Makefile
@@ -0,0 +1,46 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Derived from evm code
+#
+# Copyright (C) 2009 Texas Instruments Incorporated
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= am3517evm.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/ti/am3517evm/am3517evm.c b/board/ti/am3517evm/am3517evm.c
new file mode 100644
index 0000000..0b6b5a4
--- /dev/null
+++ b/board/ti/am3517evm/am3517evm.c
@@ -0,0 +1,76 @@
+/*
+ * am3517evm.c - board file for TI's AM3517 family of devices.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Derived from evm code
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+#include "am3517evm.h"
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_AM3517EVM();
+}
diff --git a/board/ti/am3517evm/am3517evm.h b/board/ti/am3517evm/am3517evm.h
new file mode 100644
index 0000000..7897912
--- /dev/null
+++ b/board/ti/am3517evm/am3517evm.h
@@ -0,0 +1,388 @@
+/*
+ * am3517evm.h - board header file for TI's AM3517 family of devices.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Derived from evm code
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _AM3517EVM_H_
+#define _AM3517EVM_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"am3517evm board",
+	"NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_AM3517EVM() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) /*GPMC_A8*/\
+ MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) /*GPMC_A9*/\
+ MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) /*GPMC_A10*/\
+ MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS3*/\
+ MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)) /*GPMC_nCS4*/\
+ MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
+ MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) /*GPMC_nCS6*/\
+ MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) /*GPMC_nCS7*/\
+ MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) /*GPMC_nBE0_CLE*/\
+ MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) /*GPMC_nBE1*/\
+ MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
+ MUX_VAL(CP(GPMC_WAIT0),	(IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT1),	(IEN  | PTU | EN  | M0)) /*GPMC_WAIT1*/\
+ MUX_VAL(CP(GPMC_WAIT2),	(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+							 /* - ETH_nRESET*/\
+ MUX_VAL(CP(GPMC_WAIT3),	(IEN  | PTU | EN  | M0)) /*GPMC_WAIT3*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
+ MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10),	(IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11),	(IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12),	(IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13),	(IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14),	(IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15),	(IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16),	(IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17),	(IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18),	(IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
+ MUX_VAL(CP(DSS_DATA19),	(IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
+ MUX_VAL(CP(DSS_DATA20),	(IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
+ MUX_VAL(CP(DSS_DATA21),	(IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
+ MUX_VAL(CP(DSS_DATA22),	(IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
+ MUX_VAL(CP(DSS_DATA23),	(IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+							 /* - CAM_RESET*/\
+ MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE),	(IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX),	(IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card  */\
+ MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) /*MMC1_DAT4,\
+							   WriteProtect*/\
+ MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) /*MMC1_DAT5,\
+							   CardDetect*/\
+ MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN | M4)) /*MMC1_DAT6*/\
+ MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN | M4)) /*MMC1_DAT7*/\
+ /*Wireless LAN */\
+ MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD),		(IEN  | PTD | DIS | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTD | DIS | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTD | DIS | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTD | DIS | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTD | DIS | M0)) /*MMC2_DAT3*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) /*McBSP3_DX*/\
+ MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) /*McBSP3_DR*/\
+ MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) /*McBSP3_CLKX  */\
+ MUX_VAL(CP(MCBSP3_FSX),	(IEN  | PTD | DIS | M0)) /*McBSP3_FSX*/\
+ MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) /*UART2_CTS*/\
+ MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
+ MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) /*UART2_TX*/\
+ MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) /*UART2_RX*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
+ MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) /*UART1_CTS*/\
+ MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+							 /* - LCD_INI*/\
+ MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+							 /* - LCD_ENVDD */\
+ MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+							 /* - LCD_QVGA/nVGA */\
+ MUX_VAL(CP(MCBSP4_FSX),	(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+							 /* - LCD_RESB */\
+ MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) /*MCBSP1_CLKR  */\
+ MUX_VAL(CP(MCBSP1_FSR),	(IDIS | PTU | EN  | M0)) /*MCBSP1_FSR*/\
+ MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) /*MCBSP1_DX*/\
+ MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) /*MCBSP1_DR*/\
+ MUX_VAL(CP(MCBSP_CLKS),	(IEN  | PTU | DIS | M0)) /*MCBSP_CLKS  */\
+ MUX_VAL(CP(MCBSP1_FSX),	(IEN  | PTD | DIS | M0)) /*MCBSP1_FSX*/\
+ MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) /*MCBSP1_CLKX  */\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | DIS  | M0)) /*UART3_CTS_*/\
+							 /* RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK),	(IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP),	(IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT),	(IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) /*HDQ_SIO*/\
+ MUX_VAL(CP(MCSPI1_CLK),	(IEN  | PTD | DIS | M0)) /*McSPI1_CLK*/\
+ MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI1_SIMO  */\
+ MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI1_SOMI  */\
+ MUX_VAL(CP(MCSPI1_CS0),	(IEN  | PTD | EN  | M0)) /*McSPI1_CS0*/\
+ MUX_VAL(CP(MCSPI1_CS1),	(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
+							 /* TS_PEN_IRQ */\
+ MUX_VAL(CP(MCSPI1_CS2),	(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
+							 /* - LAN_INTR*/\
+ MUX_VAL(CP(MCSPI1_CS3),	(IEN  | PTD | EN  | M0)) /*McSPI1_CS3*/\
+ MUX_VAL(CP(MCSPI2_CLK),	(IEN  | PTD | DIS | M0)) /*McSPI2_CLK*/\
+ MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+ MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+ MUX_VAL(CP(MCSPI2_CS0),	(IEN  | PTD | EN  | M4)) /*McSPI2_CS0*/\
+ MUX_VAL(CP(MCSPI2_CS1),	(IEN  | PTD | EN  | M4)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ),	(IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+							 /* - PEN_IRQ */\
+ MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+ MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+ MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+ MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+ MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+							 /* - VIO_1V8*/\
+ MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
+ MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) /*SYS_CLKOUT2*/\
+ MUX_VAL(CP(JTAG_nTRST),	(IEN  | PTD | DIS | M0)) /*JTAG_nTRST*/\
+ MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) /*JTAG_TCK*/\
+ MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) /*JTAG_TMS*/\
+ MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) /*JTAG_TDI*/\
+ MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU0*/\
+ MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) /*JTAG_EMU1*/\
+ MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M0)) /*ETK_CLK*/\
+ MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M0)) /*ETK_CTL*/\
+ MUX_VAL(CP(ETK_D0_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D0*/\
+ MUX_VAL(CP(ETK_D1_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D1*/\
+ MUX_VAL(CP(ETK_D2_ES2 ),	(IEN  | PTD | EN  | M0)) /*ETK_D2*/\
+ MUX_VAL(CP(ETK_D3_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D3*/\
+ MUX_VAL(CP(ETK_D4_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D4*/\
+ MUX_VAL(CP(ETK_D5_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D5*/\
+ MUX_VAL(CP(ETK_D6_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D6*/\
+ MUX_VAL(CP(ETK_D7_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D7*/\
+ MUX_VAL(CP(ETK_D8_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D8*/\
+ MUX_VAL(CP(ETK_D9_ES2 ),	(IEN  | PTD | DIS | M0)) /*ETK_D9*/\
+ MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D10*/\
+ MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D11*/\
+ MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D12*/\
+ MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D13*/\
+ MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D14*/\
+ MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0)) /*ETK_D15*/\
+ /*Die to Die */\
+ MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) /*ccdc_pclk*/\
+ MUX_VAL(CP(CCDC_FIELD),	(IEN  | PTD | DIS  | M1)) /*ccdc_field*/\
+ MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) /*ccdc_hd*/\
+ MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) /*ccdc_vd*/\
+ MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS  | M1)) /*ccdc_wen*/\
+ MUX_VAL(CP(CCDC_DATA0),	(IEN  | PTD | DIS | M0)) /*ccdc_data0*/\
+ MUX_VAL(CP(CCDC_DATA1),        (IEN  | PTD | DIS | M0)) /*ccdc_data1*/\
+ MUX_VAL(CP(CCDC_DATA2),	(IEN  | PTD | DIS | M0)) /*ccdc_data2*/\
+ MUX_VAL(CP(CCDC_DATA3),	(IEN  | PTD | DIS | M0)) /*ccdc_data3*/\
+ MUX_VAL(CP(CCDC_DATA4),	(IEN  | PTD | DIS | M0)) /*ccdc_data4*/\
+ MUX_VAL(CP(CCDC_DATA5),	(IEN  | PTD | DIS | M0)) /*ccdc_data5*/\
+ MUX_VAL(CP(CCDC_DATA6),	(IEN  | PTD | DIS | M0)) /*ccdc_data6*/\
+ MUX_VAL(CP(CCDC_DATA7),	(IEN  | PTD | DIS | M0)) /*ccdc_data7*/\
+ MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) /*rmii_mdio_data*/\
+ MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) /*rmii_mdio_clk*/\
+ MUX_VAL(CP(RMII_RXD0)	,	(IEN  | PTD | M0)) /*rmii_rxd0*/\
+ MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) /*rmii_rxd1*/\
+ MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) /*rmii_crs_dv*/\
+ MUX_VAL(CP(RMII_RXER),		(PTD | M0)) /*rmii_rxer*/\
+ MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) /*rmii_txd0*/\
+ MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) /*rmii_txd1*/\
+ MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) /*rmii_txen*/\
+ MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) /*rmii_50mhz_clk*/\
+ MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) /*usb0_drvbus*/\
+ MUX_VAL(CP(HECC1_TXD),		(IEN  | PTU | EN  | M0)) /*hecc1_txd*/\
+ MUX_VAL(CP(HECC1_RXD),		(IEN  | PTU | EN  | M0)) /*hecc1_rxd*/\
+ MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | EN  | M0)) /*sys_boot7*/\
+ MUX_VAL(CP(SDRC_DQS0N),	(IEN  | PTD | EN  | M0)) /*sdrc_dqs0n*/\
+ MUX_VAL(CP(SDRC_DQS1N),	(IEN  | PTD | EN  | M0)) /*sdrc_dqs1n*/\
+ MUX_VAL(CP(SDRC_DQS2N),	(IEN  | PTD | EN  | M0)) /*sdrc_dqs2n*/\
+ MUX_VAL(CP(SDRC_DQS3N),	(IEN  | PTD | EN  | M0)) /*sdrc_dqs3n*/\
+ MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) /*sdrc_strben_dly0*/\
+ MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) /*sdrc_strben_dly1*/\
+ MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) /*sys_boot8*/\
+ MUX_VAL(CP(D2D_MCAD34),	(IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35),	(IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36),	(IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY),	(IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE),	(IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE),	(IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0),		(M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1),		(M0)) /*sdrc_cke1*/\
+
+#endif
diff --git a/board/ti/am3517evm/config.mk b/board/ti/am3517evm/config.mk
new file mode 100644
index 0000000..869e719
--- /dev/null
+++ b/board/ti/am3517evm/config.mk
@@ -0,0 +1,29 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Derived from evm code
+#
+# Copyright (C) 2009 Texas Instruments Incorporated
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
index 9439758..7dbfc92 100644
--- a/include/asm-arm/arch-omap3/mem.h
+++ b/include/asm-arm/arch-omap3/mem.h
@@ -191,6 +191,15 @@ enum {
 #define SMNAND_GPMC_CONFIG6	0x1F0F0A80
 #define SMNAND_GPMC_CONFIG7	0x00000C44
 
+#if defined (CONFIG_OMAP3_AM3517EVM)
+#define M_NAND_GPMC_CONFIG1	0x00001800
+#define M_NAND_GPMC_CONFIG2	0x00080800
+#define M_NAND_GPMC_CONFIG3	0x00080800
+#define M_NAND_GPMC_CONFIG4	0x06000600
+#define M_NAND_GPMC_CONFIG5	0x00080808
+#define M_NAND_GPMC_CONFIG6	0x000003cf
+#define M_NAND_GPMC_CONFIG7	0x00000848
+#else	/* CONFIG_OMAP3_AM3517EVM */
 #define M_NAND_GPMC_CONFIG1	0x00001800
 #define M_NAND_GPMC_CONFIG2	0x00141400
 #define M_NAND_GPMC_CONFIG3	0x00141400
@@ -198,6 +207,7 @@ enum {
 #define M_NAND_GPMC_CONFIG5	0x010C1414
 #define M_NAND_GPMC_CONFIG6	0x1f0f0A80
 #define M_NAND_GPMC_CONFIG7	0x00000C44
+#endif	/* CONFIG_OMAP3_AM3517EVM */
 
 #define STNOR_GPMC_CONFIG1	0x3
 #define STNOR_GPMC_CONFIG2	0x00151501
-- 
1.6.2.4

[U-Boot] [PATCH 1/5] Introducing AM3517EVM support

[Wolfgang Denk]

Dear hvaibhav at ti.com,

In message <1258974382-26568-1-git-send-email-hvaibhav@ti.com> you wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> Changes:-
> 	- Added board specific directory under board/ti/am3517/
> 	- Basic board support.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
>  board/ti/am3517evm/Makefile      |   46 +++++
>  board/ti/am3517evm/am3517evm.c   |   76 ++++++++
>  board/ti/am3517evm/am3517evm.h   |  388 ++++++++++++++++++++++++++++++++++++++
>  board/ti/am3517evm/config.mk     |   29 +++
>  include/asm-arm/arch-omap3/mem.h |   10 +
>  5 files changed, 549 insertions(+), 0 deletions(-)
>  create mode 100644 board/ti/am3517evm/Makefile
>  create mode 100644 board/ti/am3517evm/am3517evm.c
>  create mode 100644 board/ti/am3517evm/am3517evm.h
>  create mode 100644 board/ti/am3517evm/config.mk
...
> diff --git a/board/ti/am3517evm/am3517evm.h b/board/ti/am3517evm/am3517evm.h
> new file mode 100644
> index 0000000..7897912
> --- /dev/null
> +++ b/board/ti/am3517evm/am3517evm.h
...
> +#define MUX_AM3517EVM() \
> + /*SDRC*/\
> + MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
> + MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
...

Indentation by TAB, please.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There are no data that cannot be plotted on a straight  line  if  the
axis are chosen correctly.

[U-Boot] [PATCH 1/5] Introducing AM3517EVM support

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Tuesday, November 24, 2009 1:13 AM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 1/5] Introducing AM3517EVM support
> 
> Dear hvaibhav at ti.com,
> 
> In message <1258974382-26568-1-git-send-email-hvaibhav@ti.com> you
> wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > Changes:-
> > 	- Added board specific directory under board/ti/am3517/
> > 	- Basic board support.
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > ---
> >  board/ti/am3517evm/Makefile      |   46 +++++
> >  board/ti/am3517evm/am3517evm.c   |   76 ++++++++
> >  board/ti/am3517evm/am3517evm.h   |  388
> ++++++++++++++++++++++++++++++++++++++
> >  board/ti/am3517evm/config.mk     |   29 +++
> >  include/asm-arm/arch-omap3/mem.h |   10 +
> >  5 files changed, 549 insertions(+), 0 deletions(-)
> >  create mode 100644 board/ti/am3517evm/Makefile
> >  create mode 100644 board/ti/am3517evm/am3517evm.c
> >  create mode 100644 board/ti/am3517evm/am3517evm.h
> >  create mode 100644 board/ti/am3517evm/config.mk
> ...
> > diff --git a/board/ti/am3517evm/am3517evm.h
> b/board/ti/am3517evm/am3517evm.h
> > new file mode 100644
> > index 0000000..7897912
> > --- /dev/null
> > +++ b/board/ti/am3517evm/am3517evm.h
> ...
> > +#define MUX_AM3517EVM() \
> > + /*SDRC*/\
> > + MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0))
> /*SDRC_D0*/\
> > + MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0))
> /*SDRC_D1*/\
> ...
> 
> Indentation by TAB, please.
> 
[Hiremath, Vaibhav] Ok, Will fix in next version.

Thanks,
Vaibhav
> 
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev
> Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email:
> wd at denx.de
> There are no data that cannot be plotted on a straight  line  if
> the
> axis are chosen correctly.

[U-Boot] [PATCH 0/5] Introducing TI's New SoC/board AM3517EVM

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

AM3517 device is high-performance, industrial applications processor designed
and developed keeping Software Compatible with OMAP3 Processors.

Below are some of the useful links -
AM3517 device is high-performance, industrial applications processor designed
and developed keeping Software Compatible with OMAP3 Processors.

Below are some of the useful links -

Migration from OMAP35x to AM35x :-
http://focus.ti.com/lit/an/sprab91/sprab91.pdf

Specs/TRM :-
http://focus.ti.com/docs/prod/folders/print/am3517.html

EVM Link -:
http://www.logicpd.com/products/development-kits/zoom-am3517-experimenter-kit

Vaibhav Hiremath (5):
  Introducing AM3517EVM support
  am3517_evm_config options added to Makfile
  Added configuration file for AM3517EVM
  Added AM3517EVM specific mux configuration to omap3/mux.h
  AM3517: Add support for EMIF4

 Makefile                               |    3 +
 board/ti/am3517evm/Makefile            |   46 ++++
 board/ti/am3517evm/am3517evm.c         |   76 +++++++
 board/ti/am3517evm/am3517evm.h         |  388 ++++++++++++++++++++++++++++++++
 board/ti/am3517evm/config.mk           |   29 +++
 cpu/arm_cortexa8/omap3/board.c         |   11 +-
 cpu/arm_cortexa8/omap3/mem.c           |  110 ++++++++--
 cpu/arm_cortexa8/omap3/sys_info.c      |   12 +-
 include/asm-arm/arch-omap3/cpu.h       |   26 +++
 include/asm-arm/arch-omap3/mem.h       |   66 ++++++-
 include/asm-arm/arch-omap3/mux.h       |   35 +++
 include/asm-arm/arch-omap3/sys_proto.h |    4 +
 include/configs/am3517_evm.h           |  299 ++++++++++++++++++++++++
 include/configs/devkit8000.h           |    4 +
 include/configs/omap3_beagle.h         |    4 +
 include/configs/omap3_evm.h            |    4 +
 include/configs/omap3_overo.h          |    4 +
 include/configs/omap3_pandora.h        |    4 +
 include/configs/omap3_sdp3430.h        |    4 +
 include/configs/omap3_zoom1.h          |    4 +
 include/configs/omap3_zoom2.h          |    4 +
 21 files changed, 1112 insertions(+), 25 deletions(-)
 create mode 100644 board/ti/am3517evm/Makefile
 create mode 100644 board/ti/am3517evm/am3517evm.c
 create mode 100644 board/ti/am3517evm/am3517evm.h
 create mode 100644 board/ti/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h

[U-Boot] [PATCH 0/5] Introducing TI's New SoC/board AM3517EVM

[Paulraj, Sandeep]

> 
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> AM3517 device is high-performance, industrial applications processor
> designed
> and developed keeping Software Compatible with OMAP3 Processors.
> 
> Below are some of the useful links -
> AM3517 device is high-performance, industrial applications processor
> designed
> and developed keeping Software Compatible with OMAP3 Processors.
> 
> Below are some of the useful links -
> 
> Migration from OMAP35x to AM35x :-
> http://focus.ti.com/lit/an/sprab91/sprab91.pdf
> 
> Specs/TRM :-
> http://focus.ti.com/docs/prod/folders/print/am3517.html
> 
> EVM Link -:
> http://www.logicpd.com/products/development-kits/zoom-am3517-experimenter-
> kit
> 
> Vaibhav Hiremath (5):
>   Introducing AM3517EVM support
>   am3517_evm_config options added to Makfile
>   Added configuration file for AM3517EVM
>   Added AM3517EVM specific mux configuration to omap3/mux.h
>   AM3517: Add support for EMIF4
> 
>  Makefile                               |    3 +
>  board/ti/am3517evm/Makefile            |   46 ++++
>  board/ti/am3517evm/am3517evm.c         |   76 +++++++
>  board/ti/am3517evm/am3517evm.h         |  388
> ++++++++++++++++++++++++++++++++
>  board/ti/am3517evm/config.mk           |   29 +++
>  cpu/arm_cortexa8/omap3/board.c         |   11 +-
>  cpu/arm_cortexa8/omap3/mem.c           |  110 ++++++++--
>  cpu/arm_cortexa8/omap3/sys_info.c      |   12 +-
>  include/asm-arm/arch-omap3/cpu.h       |   26 +++
>  include/asm-arm/arch-omap3/mem.h       |   66 ++++++-
>  include/asm-arm/arch-omap3/mux.h       |   35 +++
>  include/asm-arm/arch-omap3/sys_proto.h |    4 +
>  include/configs/am3517_evm.h           |  299 ++++++++++++++++++++++++
>  include/configs/devkit8000.h           |    4 +
>  include/configs/omap3_beagle.h         |    4 +
>  include/configs/omap3_evm.h            |    4 +
>  include/configs/omap3_overo.h          |    4 +
>  include/configs/omap3_pandora.h        |    4 +
>  include/configs/omap3_sdp3430.h        |    4 +
>  include/configs/omap3_zoom1.h          |    4 +
>  include/configs/omap3_zoom2.h          |    4 +
>  21 files changed, 1112 insertions(+), 25 deletions(-)
>  create mode 100644 board/ti/am3517evm/Makefile
>  create mode 100644 board/ti/am3517evm/am3517evm.c
>  create mode 100644 board/ti/am3517evm/am3517evm.h
>  create mode 100644 board/ti/am3517evm/config.mk
>  create mode 100644 include/configs/am3517_evm.h

Vaibhav,

We will need entries to MAINTAINERS and MAKEALL as well.

Please submit it when you submit the next set of patches. I am sure you will receive some comments.

I hope you made the patches against the current u-boot-ti/master

Thanks,
Sandeep

[U-Boot] [PATCH 0/5] Introducing TI's New SoC/board AM3517EVM

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Paulraj, Sandeep
> Sent: Monday, November 23, 2009 7:20 PM
> To: Hiremath, Vaibhav; u-boot at lists.denx.de
> Subject: RE: [PATCH 0/5] Introducing TI's New SoC/board AM3517EVM
> 
> 
> 
> >
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > AM3517 device is high-performance, industrial applications
> processor
> > designed
> > and developed keeping Software Compatible with OMAP3 Processors.
> >
> > Below are some of the useful links -
> > AM3517 device is high-performance, industrial applications
> processor
> > designed
> > and developed keeping Software Compatible with OMAP3 Processors.
> >
> > Below are some of the useful links -
> >
> > Migration from OMAP35x to AM35x :-
> > http://focus.ti.com/lit/an/sprab91/sprab91.pdf
> >
> > Specs/TRM :-
> > http://focus.ti.com/docs/prod/folders/print/am3517.html
> >
> > EVM Link -:
> > http://www.logicpd.com/products/development-kits/zoom-am3517-
> experimenter-
> > kit
> >
> > Vaibhav Hiremath (5):
> >   Introducing AM3517EVM support
> >   am3517_evm_config options added to Makfile
> >   Added configuration file for AM3517EVM
> >   Added AM3517EVM specific mux configuration to omap3/mux.h
> >   AM3517: Add support for EMIF4
> >
> >  Makefile                               |    3 +
> >  board/ti/am3517evm/Makefile            |   46 ++++
> >  board/ti/am3517evm/am3517evm.c         |   76 +++++++
> >  board/ti/am3517evm/am3517evm.h         |  388
> > ++++++++++++++++++++++++++++++++
> >  board/ti/am3517evm/config.mk           |   29 +++
> >  cpu/arm_cortexa8/omap3/board.c         |   11 +-
> >  cpu/arm_cortexa8/omap3/mem.c           |  110 ++++++++--
> >  cpu/arm_cortexa8/omap3/sys_info.c      |   12 +-
> >  include/asm-arm/arch-omap3/cpu.h       |   26 +++
> >  include/asm-arm/arch-omap3/mem.h       |   66 ++++++-
> >  include/asm-arm/arch-omap3/mux.h       |   35 +++
> >  include/asm-arm/arch-omap3/sys_proto.h |    4 +
> >  include/configs/am3517_evm.h           |  299
> ++++++++++++++++++++++++
> >  include/configs/devkit8000.h           |    4 +
> >  include/configs/omap3_beagle.h         |    4 +
> >  include/configs/omap3_evm.h            |    4 +
> >  include/configs/omap3_overo.h          |    4 +
> >  include/configs/omap3_pandora.h        |    4 +
> >  include/configs/omap3_sdp3430.h        |    4 +
> >  include/configs/omap3_zoom1.h          |    4 +
> >  include/configs/omap3_zoom2.h          |    4 +
> >  21 files changed, 1112 insertions(+), 25 deletions(-)
> >  create mode 100644 board/ti/am3517evm/Makefile
> >  create mode 100644 board/ti/am3517evm/am3517evm.c
> >  create mode 100644 board/ti/am3517evm/am3517evm.h
> >  create mode 100644 board/ti/am3517evm/config.mk
> >  create mode 100644 include/configs/am3517_evm.h
> 
> Vaibhav,
> 
> We will need entries to MAINTAINERS and MAKEALL as well.
> 
[Hiremath, Vaibhav] Ok, will do that.

> Please submit it when you submit the next set of patches. I am sure
> you will receive some comments.
[Hiremath, Vaibhav] I hope so.
> 
> I hope you made the patches against the current u-boot-ti/master
[Hiremath, Vaibhav] Yes that's correct.

Thanks,
Vaibhav
> 
> Thanks,
> Sandeep

[U-Boot] [PATCH 0/5] Introducing TI's New SoC/board AM3517EVM

[Wolfgang Denk]

Dear "Paulraj, Sandeep",

In message <0554BEF07D437848AF01B9C9B5F0BC5D942DC993@dlee01.ent.ti.com> you wrote:
> 
> I hope you made the patches against the current u-boot-ti/master

Please note that this is a tendency I seriously dislike.


Please do NOT do this.


Please see bullet # 3 at http://www.denx.de/wiki/U-Boot/Patches :

	Please use the "master" branch of the mainline U-Boot git
	repository (git://git.denx.de/u-boot.git) as reference, unless
	(usually late in a release cycle) there has been an
	announcement to use the "next" branch of this repository
	instead.

If we see patches againt any of 30 or so custodian trees, which don't
apply against the "official" master tree, we will see chaos pretty
soon. Please let's make sure there is only minimal difference between
custdian trees and "master" (or "next"), so there is no reason to use
custodian tress as reference for patches instead.


Please _always_ use "master" (or "next") as base for patches!

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A Perl script is correct if it's halfway readable and  gets  the  job
done before your boss fires you.
                       - L. Wall & R. L. Schwartz, _Programming Perl_

[U-Boot] [PATCH 0/5] Introducing TI's New SoC/board AM3517EVM

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Tuesday, November 24, 2009 1:33 AM
> To: Paulraj, Sandeep
> Cc: Hiremath, Vaibhav; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 0/5] Introducing TI's New SoC/board
> AM3517EVM
> 
> Dear "Paulraj, Sandeep",
> 
> In message
> <0554BEF07D437848AF01B9C9B5F0BC5D942DC993@dlee01.ent.ti.com> you
> wrote:
> >
> > I hope you made the patches against the current u-boot-ti/master
> 
> Please note that this is a tendency I seriously dislike.
> 
> 
> Please do NOT do this.
> 
> 
> Please see bullet # 3 at http://www.denx.de/wiki/U-Boot/Patches :
> 
> 	Please use the "master" branch of the mainline U-Boot git
> 	repository (git://git.denx.de/u-boot.git) as reference, unless
> 	(usually late in a release cycle) there has been an
> 	announcement to use the "next" branch of this repository
> 	instead.
> 
> If we see patches againt any of 30 or so custodian trees, which
> don't
> apply against the "official" master tree, we will see chaos pretty
> soon. Please let's make sure there is only minimal difference
> between
> custdian trees and "master" (or "next"), so there is no reason to
> use
> custodian tress as reference for patches instead.
> 
> 
> Please _always_ use "master" (or "next") as base for patches!
> 
[Hiremath, Vaibhav] Before submitting patch I conformed that the patches gets applied on master branch cleanly.

Thanks,
Vaibhav

> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev
> Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email:
> wd at denx.de
> A Perl script is correct if it's halfway readable and  gets  the
> job
> done before your boss fires you.
>                        - L. Wall & R. L. Schwartz, _Programming
> Perl_

[U-Boot] [PATCH 0/5] Introducing TI's New SoC/board AM3517EVM

[Tom]

hvaibhav at ti.com wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> AM3517 device is high-performance, industrial applications processor designed
> and developed keeping Software Compatible with OMAP3 Processors.
> 

On the next revision of your patch set, please run it through
the linux kernel's checkpatch.pl script.  It is a good automated tool
to check basic whitespace issues.

I use checkpatch first when I have to review a large patch set.

Tom

[U-Boot] [PATCH 2/5] am3517_evm_config options added to Makfile

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>


Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 Makefile |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/Makefile b/Makefile
index bcb3fe9..d1aa8ff 100644
--- a/Makefile
+++ b/Makefile
@@ -3156,6 +3156,9 @@ omap3_overo_config :	unconfig
 omap3_evm_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 evm ti omap3
 
+am3517_evm_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm ti omap3
+
 omap3_pandora_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 pandora NULL omap3
 
-- 
1.6.2.4

[U-Boot] [PATCH 2/5] am3517_evm_config options added to Makfile

[Wolfgang Denk]

Dear hvaibhav at ti.com,

In message <1258974509-28062-1-git-send-email-hvaibhav@ti.com> you wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
>  Makefile |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)

This patch must be part of the commit that adds the code. Don't split
it off.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When the bosses talk about improving  productivity,  they  are  never
talking about themselves.

[U-Boot] [PATCH 2/5] am3517_evm_config options added to Makfile

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Tuesday, November 24, 2009 1:14 AM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 2/5] am3517_evm_config options added to
> Makfile
> 
> Dear hvaibhav at ti.com,
> 
> In message <1258974509-28062-1-git-send-email-hvaibhav@ti.com> you
> wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > ---
> >  Makefile |    3 +++
> >  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> This patch must be part of the commit that adds the code. Don't
> split
> it off.
> 
[Hiremath, Vaibhav] Ok, Will fix in next version.

Thanks,
Vaibhav
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev
> Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email:
> wd at denx.de
> When the bosses talk about improving  productivity,  they  are
> never
> talking about themselves.

[U-Boot] [PATCH 3/5] Added configuration file for AM3517EVM

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>


Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 include/configs/am3517_evm.h |  293 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 293 insertions(+), 0 deletions(-)
 create mode 100644 include/configs/am3517_evm.h

diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
new file mode 100644
index 0000000..d7eef73
--- /dev/null
+++ b/include/configs/am3517_evm.h
@@ -0,0 +1,293 @@
+/*
+ * am3517_evm.h - Configuration settings for the TI's AM3517 EVM board.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Derived from evm code
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */
+
+#include <asm/arch/cpu.h>	/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ			/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+/*
+ * DDR size interfaced
+ */
+#define CONFIG_SYS_CS0_SIZE             (256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 on AM3517 EVM */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+#undef CONFIG_CMD_NET
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_BOOTFILE		uImage
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc init; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT		"AM3517_EVM # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor@start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			boot_flash_env_addr
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#ifndef __ASSEMBLY__
+extern struct gpmc *gpmc_cfg;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */
-- 
1.6.2.4

[U-Boot] [PATCH 3/5] Added configuration file for AM3517EVM

[Wolfgang Denk]

Dear hvaibhav at ti.com,

In message <1258974524-28097-1-git-send-email-hvaibhav@ti.com> you wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
>  include/configs/am3517_evm.h |  293 ++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 293 insertions(+), 0 deletions(-)
>  create mode 100644 include/configs/am3517_evm.h

See before: this patch must be part of the commit that adds the board
code.


> +#ifndef __ASSEMBLY__
> +extern struct gpmc *gpmc_cfg;
> +extern unsigned int boot_flash_base;
> +extern volatile unsigned int boot_flash_env_addr;
> +extern unsigned int boot_flash_off;
> +extern unsigned int boot_flash_sec;
> +extern unsigned int boot_flash_type;
> +#endif

Please add prototype declarations to some appropriate header file
instead.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Es sind ?berhaupt nur die Dummk?pfe, die sich den Befehlen der  M?ch-
tigen  widersetzen.  Um  sie  zu ruinieren ist es genug, ihre Befehle
treu zu erf?llen.                  - Peter Hacks: "Die sch?ne Helena"

[U-Boot] [PATCH 3/5] Added configuration file for AM3517EVM

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Tuesday, November 24, 2009 1:16 AM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 3/5] Added configuration file for
> AM3517EVM
> 
> Dear hvaibhav at ti.com,
> 
> In message <1258974524-28097-1-git-send-email-hvaibhav@ti.com> you
> wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > ---
> >  include/configs/am3517_evm.h |  293
> ++++++++++++++++++++++++++++++++++++++++++
> >  1 files changed, 293 insertions(+), 0 deletions(-)
> >  create mode 100644 include/configs/am3517_evm.h
> 
> See before: this patch must be part of the commit that adds the
> board
> code.
> 
> 
> > +#ifndef __ASSEMBLY__
> > +extern struct gpmc *gpmc_cfg;
> > +extern unsigned int boot_flash_base;
> > +extern volatile unsigned int boot_flash_env_addr;
> > +extern unsigned int boot_flash_off;
> > +extern unsigned int boot_flash_sec;
> > +extern unsigned int boot_flash_type;
> > +#endif
> 
> Please add prototype declarations to some appropriate header file
> instead.
> 
[Hiremath, Vaibhav] Actually this code is borrowed from OMAP3EVM file, and I think almost all devices handles this same way.

It is bit difficult to handle this, since we are supporting multiple flash devices and these variables are initialized run-time and so the macros below,

CONFIG_SYS_FLASH_BASE,
CONFIG_ENV_OFFSET,
CONFIG_SYS_ENV_SECT_SIZE

I will try to dig bit more on this, but I think as of now we can go with this.

Thanks,
Vaibhav

> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev
> Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email:
> wd at denx.de
> Es sind ?berhaupt nur die Dummk?pfe, die sich den Befehlen der
> M?ch-
> tigen  widersetzen.  Um  sie  zu ruinieren ist es genug, ihre
> Befehle
> treu zu erf?llen.                  - Peter Hacks: "Die sch?ne
> Helena"

[U-Boot] [PATCH 3/5] Added configuration file for AM3517EVM

[Tom]

Hiremath, Vaibhav wrote:
>> -----Original Message-----
>> From: Wolfgang Denk [mailto:wd at denx.de]
>> Sent: Tuesday, November 24, 2009 1:16 AM
>> To: Hiremath, Vaibhav
>> Cc: u-boot at lists.denx.de
>> Subject: Re: [U-Boot] [PATCH 3/5] Added configuration file for
>> AM3517EVM
>>
>> Dear hvaibhav at ti.com,
>>
>> In message <1258974524-28097-1-git-send-email-hvaibhav@ti.com> you
>> wrote:
>>> From: Vaibhav Hiremath <hvaibhav@ti.com>
>>>
>>>
>>> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
>>> ---
>>>  include/configs/am3517_evm.h |  293
>> ++++++++++++++++++++++++++++++++++++++++++
>>>  1 files changed, 293 insertions(+), 0 deletions(-)
>>>  create mode 100644 include/configs/am3517_evm.h
>> See before: this patch must be part of the commit that adds the
>> board
>> code.
>>
>>
>>> +#ifndef __ASSEMBLY__
>>> +extern struct gpmc *gpmc_cfg;
>>> +extern unsigned int boot_flash_base;
>>> +extern volatile unsigned int boot_flash_env_addr;
>>> +extern unsigned int boot_flash_off;
>>> +extern unsigned int boot_flash_sec;
>>> +extern unsigned int boot_flash_type;
>>> +#endif
>> Please add prototype declarations to some appropriate header file
>> instead.
>>
> [Hiremath, Vaibhav] Actually this code is borrowed from OMAP3EVM file, and I think almost all devices handles this same way.
> 
> It is bit difficult to handle this, since we are supporting multiple flash devices and these variables are initialized run-time and so the macros below,
> 
> CONFIG_SYS_FLASH_BASE,
> CONFIG_ENV_OFFSET,
> CONFIG_SYS_ENV_SECT_SIZE
> 
> I will try to dig bit more on this, but I think as of now we can go with this.

This code is changing so you may want to wait on investing a lot of
effort into it.  Please see the CM-T35 board submission.
Please review what is already been proposed to fix this for all the omap3's and
comment.

Tom

> 
> Thanks,
> Vaibhav
> 
>> Best regards,
>>
>> Wolfgang Denk

[U-Boot] [PATCH 3/5] Added configuration file for AM3517EVM

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Tom [mailto:Tom.Rix at windriver.com]
> Sent: Thursday, November 26, 2009 9:34 PM
> To: Hiremath, Vaibhav
> Cc: Wolfgang Denk; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 3/5] Added configuration file for
> AM3517EVM
> 
> Hiremath, Vaibhav wrote:
> >> -----Original Message-----
> >> From: Wolfgang Denk [mailto:wd at denx.de]
> >> Sent: Tuesday, November 24, 2009 1:16 AM
> >> To: Hiremath, Vaibhav
> >> Cc: u-boot at lists.denx.de
> >> Subject: Re: [U-Boot] [PATCH 3/5] Added configuration file for
> >> AM3517EVM
> >>
> >> Dear hvaibhav at ti.com,
> >>
> >> In message <1258974524-28097-1-git-send-email-hvaibhav@ti.com>
> you
> >> wrote:
> >>> From: Vaibhav Hiremath <hvaibhav@ti.com>
> >>>
> >>>
> >>> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> >>> ---
> >>>  include/configs/am3517_evm.h |  293
> >> ++++++++++++++++++++++++++++++++++++++++++
> >>>  1 files changed, 293 insertions(+), 0 deletions(-)
> >>>  create mode 100644 include/configs/am3517_evm.h
> >> See before: this patch must be part of the commit that adds the
> >> board
> >> code.
> >>
> >>
> >>> +#ifndef __ASSEMBLY__
> >>> +extern struct gpmc *gpmc_cfg;
> >>> +extern unsigned int boot_flash_base;
> >>> +extern volatile unsigned int boot_flash_env_addr;
> >>> +extern unsigned int boot_flash_off;
> >>> +extern unsigned int boot_flash_sec;
> >>> +extern unsigned int boot_flash_type;
> >>> +#endif
> >> Please add prototype declarations to some appropriate header file
> >> instead.
> >>
> > [Hiremath, Vaibhav] Actually this code is borrowed from OMAP3EVM
> file, and I think almost all devices handles this same way.
> >
> > It is bit difficult to handle this, since we are supporting
> multiple flash devices and these variables are initialized run-time
> and so the macros below,
> >
> > CONFIG_SYS_FLASH_BASE,
> > CONFIG_ENV_OFFSET,
> > CONFIG_SYS_ENV_SECT_SIZE
> >
> > I will try to dig bit more on this, but I think as of now we can
> go with this.
> 
> This code is changing so you may want to wait on investing a lot of
> effort into it.  Please see the CM-T35 board submission.
> Please review what is already been proposed to fix this for all the
> omap3's and
> comment.
> 
[Hiremath, Vaibhav] Thanks for pointing me to this, I will definitely go through this and get back to you if I have any issues/questions.

Thanks,
Vaibhav

> Tom
> 
> >
> > Thanks,
> > Vaibhav
> >
> >> Best regards,
> >>
> >> Wolfgang Denk

[U-Boot] [PATCH 3/5] Added configuration file for AM3517EVM

[Wolfgang Denk]

Dear "Hiremath, Vaibhav",

In message <19F8576C6E063C45BE387C64729E739404370D7ACC@dbde02.ent.ti.com> you wrote:
> 
...
> > > +#ifndef __ASSEMBLY__
> > > +extern struct gpmc *gpmc_cfg;
> > > +extern unsigned int boot_flash_base;
> > > +extern volatile unsigned int boot_flash_env_addr;
> > > +extern unsigned int boot_flash_off;
> > > +extern unsigned int boot_flash_sec;
> > > +extern unsigned int boot_flash_type;
> > > +#endif
> > 
> > Please add prototype declarations to some appropriate header file
> > instead.
> > 
> [Hiremath, Vaibhav] Actually this code is borrowed from OMAP3EVM file, and
> I think almost all devices handles this same way.

Yes, this escaped us before - but now we got aware of this problem we
don't want to add more of this (and clean up the existing code ASAP).

> It is bit difficult to handle this, since we are supporting multiple flash
> devices and these variables are initialized run-time and so the macros below,
>
> CONFIG_SYS_FLASH_BASE,
> CONFIG_ENV_OFFSET,
> CONFIG_SYS_ENV_SECT_SIZE

Um... I cannot parse this senstence. Some words seem to be missing?

> I will try to dig bit more on this, but I think as of now we can go with this.

Sorry, I disagree.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The IQ of the group is the lowest IQ of a member of the group divided
by the number of people in the group.

[U-Boot] [PATCH 4/5] AM3517EVM: Add mux configuration

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

Updated mux.h file for AM3517 specific mux configuration.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 include/asm-arm/arch-omap3/mux.h |   35 +++++++++++++++++++++++++++++++++++
 1 files changed, 35 insertions(+), 0 deletions(-)

diff --git a/include/asm-arm/arch-omap3/mux.h b/include/asm-arm/arch-omap3/mux.h
index 0c01c73..9f06fbb 100644
--- a/include/asm-arm/arch-omap3/mux.h
+++ b/include/asm-arm/arch-omap3/mux.h
@@ -403,6 +403,41 @@
 #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
 #define CONTROL_PADCONF_SDRC_CKE0	0x0262
 #define CONTROL_PADCONF_SDRC_CKE1	0x0264
+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK       0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD      0x01E6
+#define CONTROL_PADCONF_CCDC_HD         0x01E8
+#define CONTROL_PADCONF_CCDC_VD         0x01EA
+#define CONTROL_PADCONF_CCDC_WEN        0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0      0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1      0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2      0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3      0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4      0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5      0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6      0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7      0x01FC
+#define CONTROL_PADCONF_RMII_MDIO_DATA  0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK   0x0200
+#define CONTROL_PADCONF_RMII_RXD0       0x0202
+#define CONTROL_PADCONF_RMII_RXD1       0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV     0x0206
+#define CONTROL_PADCONF_RMII_RXER       0x0208
+#define CONTROL_PADCONF_RMII_TXD0       0x020A
+#define CONTROL_PADCONF_RMII_TXD1       0x020C
+#define CONTROL_PADCONF_RMII_TXEN       0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK  0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS     0x0212
+#define CONTROL_PADCONF_HECC1_TXD       0x0214
+#define CONTROL_PADCONF_HECC1_RXD       0x0216
+#define CONTROL_PADCONF_SYS_BOOT7       0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N      0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N      0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N      0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N      0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0     0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1     0x0224
+#define CONTROL_PADCONF_SYS_BOOT8       0x0226

 #define MUX_VAL(OFFSET,VALUE)\
 	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
--
1.6.2.4

[U-Boot] [PATCH 4/5] AM3517EVM: Add mux configuration

[Wolfgang Denk]

Dear hvaibhav at ti.com,

In message <1258974539-28130-1-git-send-email-hvaibhav@ti.com> you wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> Updated mux.h file for AM3517 specific mux configuration.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
>  include/asm-arm/arch-omap3/mux.h |   35 +++++++++++++++++++++++++++++++++++
>  1 files changed, 35 insertions(+), 0 deletions(-)
> 
> diff --git a/include/asm-arm/arch-omap3/mux.h b/include/asm-arm/arch-omap3/mux.h
> index 0c01c73..9f06fbb 100644
> --- a/include/asm-arm/arch-omap3/mux.h
> +++ b/include/asm-arm/arch-omap3/mux.h
> @@ -403,6 +403,41 @@
>  #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
>  #define CONTROL_PADCONF_SDRC_CKE0	0x0262
>  #define CONTROL_PADCONF_SDRC_CKE1	0x0264
> +/* AM3517 specific */
> +#define CONTROL_PADCONF_CCDC_PCLK       0x01E4
> +#define CONTROL_PADCONF_CCDC_FIELD      0x01E6
> +#define CONTROL_PADCONF_CCDC_HD         0x01E8
> +#define CONTROL_PADCONF_CCDC_VD         0x01EA
> +#define CONTROL_PADCONF_CCDC_WEN        0x01EC
...

Where are these defines used? I think I don't see them in any of the
patches of this patch series?


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
f u cn rd ths, u cn gt a gd jb n cmptr prgrmmng.

[U-Boot] [PATCH 4/5] AM3517EVM: Add mux configuration

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Tuesday, November 24, 2009 1:19 AM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 4/5] AM3517EVM: Add mux configuration
> 
> Dear hvaibhav at ti.com,
> 
> In message <1258974539-28130-1-git-send-email-hvaibhav@ti.com> you
> wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > Updated mux.h file for AM3517 specific mux configuration.
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > ---
> >  include/asm-arm/arch-omap3/mux.h |   35
> +++++++++++++++++++++++++++++++++++
> >  1 files changed, 35 insertions(+), 0 deletions(-)
> >
> > diff --git a/include/asm-arm/arch-omap3/mux.h b/include/asm-
> arm/arch-omap3/mux.h
> > index 0c01c73..9f06fbb 100644
> > --- a/include/asm-arm/arch-omap3/mux.h
> > +++ b/include/asm-arm/arch-omap3/mux.h
> > @@ -403,6 +403,41 @@
> >  #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
> >  #define CONTROL_PADCONF_SDRC_CKE0	0x0262
> >  #define CONTROL_PADCONF_SDRC_CKE1	0x0264
> > +/* AM3517 specific */
> > +#define CONTROL_PADCONF_CCDC_PCLK       0x01E4
> > +#define CONTROL_PADCONF_CCDC_FIELD      0x01E6
> > +#define CONTROL_PADCONF_CCDC_HD         0x01E8
> > +#define CONTROL_PADCONF_CCDC_VD         0x01EA
> > +#define CONTROL_PADCONF_CCDC_WEN        0x01EC
> ...
> 
> Where are these defines used? I think I don't see them in any of the
> patches of this patch series?
> 
[Hiremath, Vaibhav] These are being used in board/ty/am3517/am3517evm.c file under the function set_muxconf_regs().

Thanks,
Vaibhav

> 
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev
> Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email:
> wd at denx.de
> f u cn rd ths, u cn gt a gd jb n cmptr prgrmmng.

[U-Boot] [PATCH 4/5] AM3517EVM: Add mux configuration

[Tom]

Hiremath, Vaibhav wrote:
>> -----Original Message-----
>> From: Wolfgang Denk [mailto:wd at denx.de]
>> Sent: Tuesday, November 24, 2009 1:19 AM
>> To: Hiremath, Vaibhav
>> Cc: u-boot at lists.denx.de
>> Subject: Re: [U-Boot] [PATCH 4/5] AM3517EVM: Add mux configuration
>>
>> Dear hvaibhav at ti.com,
>>
>> In message <1258974539-28130-1-git-send-email-hvaibhav@ti.com> you
>> wrote:
>>> From: Vaibhav Hiremath <hvaibhav@ti.com>
>>>
>>> Updated mux.h file for AM3517 specific mux configuration.
>>>
>>> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
>>> ---
>>>  include/asm-arm/arch-omap3/mux.h |   35
>> +++++++++++++++++++++++++++++++++++
>>>  1 files changed, 35 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/include/asm-arm/arch-omap3/mux.h b/include/asm-
>> arm/arch-omap3/mux.h
>>> index 0c01c73..9f06fbb 100644
>>> --- a/include/asm-arm/arch-omap3/mux.h
>>> +++ b/include/asm-arm/arch-omap3/mux.h
>>> @@ -403,6 +403,41 @@
>>>  #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
>>>  #define CONTROL_PADCONF_SDRC_CKE0	0x0262
>>>  #define CONTROL_PADCONF_SDRC_CKE1	0x0264
>>> +/* AM3517 specific */
>>> +#define CONTROL_PADCONF_CCDC_PCLK       0x01E4
>>> +#define CONTROL_PADCONF_CCDC_FIELD      0x01E6
>>> +#define CONTROL_PADCONF_CCDC_HD         0x01E8
>>> +#define CONTROL_PADCONF_CCDC_VD         0x01EA
>>> +#define CONTROL_PADCONF_CCDC_WEN        0x01EC
>> ...
>>
>> Where are these defines used? I think I don't see them in any of the
>> patches of this patch series?
>>
> [Hiremath, Vaibhav] These are being used in board/ty/am3517/am3517evm.c file under the function set_muxconf_regs().
> 

It seems like these defines are only going to be used by the am3517.
If this is so, please move them to a board specific file.

Tom

> Thanks,
> Vaibhav
> 
>> Best regards,
>>
>> Wolfgang Denk

[U-Boot] [PATCH 4/5] AM3517EVM: Add mux configuration

[Wolfgang Denk]

Dear "Hiremath, Vaibhav",

In message <19F8576C6E063C45BE387C64729E739404370D7ACF@dbde02.ent.ti.com> you wrote:
>
> > >  #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
> > >  #define CONTROL_PADCONF_SDRC_CKE0	0x0262
> > >  #define CONTROL_PADCONF_SDRC_CKE1	0x0264
> > > +/* AM3517 specific */
> > > +#define CONTROL_PADCONF_CCDC_PCLK       0x01E4
> > > +#define CONTROL_PADCONF_CCDC_FIELD      0x01E6
> > > +#define CONTROL_PADCONF_CCDC_HD         0x01E8
> > > +#define CONTROL_PADCONF_CCDC_VD         0x01EA
> > > +#define CONTROL_PADCONF_CCDC_WEN        0x01EC
> > ...
> > 
> > Where are these defines used? I think I don't see them in any of the
> > patches of this patch series?
> > 
> [Hiremath, Vaibhav] These are being used in board/ty/am3517/am3517evm.c
> file under the function set_muxconf_regs().

As Tom noted it probably makes sense to move these to a board specific
file.

But then, this looks very much like register offsets for some device.
If this should be the case, plase make sure to convert this into a C
struct and use appropriate accesor macros.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The so-called "desktop metaphor" of today's workstations  is  instead
an  "airplane-seat"  metaphor.  Anyone who has shuffled a lap full of
papers while seated between two portly passengers will recognize  the
difference -- one can see only a very few things at once.
                                                   - Fred Brooks, Jr.

[U-Boot] [PATCH 5/5] AM3517: Add support for EMIF4

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

Changes:-

	- Created 2 seperate config option
		* CONFIG_SDRC (omap34xx family)
		* CONFIG_EMIF4 (am3517 family)
	- Changed all omap3 dependent file for CONFIG_SDRC

Tested On:-

        - AM3517EVM board
        - OMAP3EVM board
        - BEAGLE board

I would need help here from people to validate this change for SDP/ZOOMx
and other OMAP3 version of boards.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 cpu/arm_cortexa8/omap3/board.c         |   11 ++-
 cpu/arm_cortexa8/omap3/mem.c           |  110 ++++++++++++++++++++++++++------
 cpu/arm_cortexa8/omap3/sys_info.c      |   12 +++-
 include/asm-arm/arch-omap3/cpu.h       |   26 ++++++++
 include/asm-arm/arch-omap3/mem.h       |   58 ++++++++++++++++-
 include/asm-arm/arch-omap3/sys_proto.h |    4 +
 include/configs/am3517_evm.h           |    6 ++
 include/configs/devkit8000.h           |    4 +
 include/configs/omap3_beagle.h         |    4 +
 include/configs/omap3_evm.h            |    4 +
 include/configs/omap3_overo.h          |    4 +
 include/configs/omap3_pandora.h        |    4 +
 include/configs/omap3_sdp3430.h        |    4 +
 include/configs/omap3_zoom1.h          |    4 +
 include/configs/omap3_zoom2.h          |    4 +
 15 files changed, 233 insertions(+), 26 deletions(-)

diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index dd2c940..ce60f99 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -227,7 +227,11 @@ void s_init(void)
 	per_clocks_enable();

 	if (!in_sdram)
+#if defined(CONFIG_SDRC)
 		sdrc_init();
+#elif defined(CONFIG_EMIF4)
+		emif4_init();
+#endif
 }

 /******************************************************************************
@@ -276,19 +280,20 @@ int dram_init(void)
 	DECLARE_GLOBAL_DATA_PTR;
 	unsigned int size0 = 0, size1 = 0;

+	size0 = get_sdr_cs_size(CS0);
 	/*
 	 * If a second bank of DDR is attached to CS1 this is
 	 * where it can be started.  Early init code will init
 	 * memory on CS0.
 	 */
 	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
+#if defined(CONFIG_SDRC)
 		do_sdrc_init(CS1, NOT_EARLY);
 		make_cs1_contiguous();
+#endif
+		size1 = get_sdr_cs_size(CS1);
 	}

-	size0 = get_sdr_cs_size(CS0);
-	size1 = get_sdr_cs_size(CS1);
-
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 	gd->bd->bi_dram[0].size = size0;
 	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index dfb7e4c..73e0918 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -79,26 +79,6 @@ static const u32 gpmc_onenand[GPMC_MAX_REG] = {

 #endif

-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
-
-/**************************************************************************
- * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
- *  command line mem=xyz use all memory with out discontinuous support
- *  compiled in.  Could do it at the ATAG, but there really is two banks...
- * Called as part of 2nd phase DDR init.
- **************************************************************************/
-void make_cs1_contiguous(void)
-{
-	u32 size, a_add_low, a_add_high;
-
-	size = get_sdr_cs_size(CS0);
-	size >>= 25;	/* divide by 32 MiB to find size to offset CS1 */
-	a_add_high = (size & 3) << 8;	/* set up low field */
-	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
-	writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
-
-}
-
 /********************************************************
  *  mem_ok() - test used to see if timings are correct
  *             for a part. Helps in guessing which part
@@ -123,6 +103,27 @@ u32 mem_ok(u32 cs)
 		return 1;
 }

+#if defined(CONFIG_SDRC)
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+
+/**************************************************************************
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ *  command line mem=xyz use all memory with out discontinuous support
+ *  compiled in.  Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ **************************************************************************/
+void make_cs1_contiguous(void)
+{
+	u32 size, a_add_low, a_add_high;
+
+	size = get_sdr_cs_size(CS0);
+	size >>= 25;	/* divide by 32 MiB to find size to offset CS1 */
+	a_add_high = (size & 3) << 8;	/* set up low field */
+	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
+	writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
+
+}
+
 /********************************************************
  *  sdrc_init() - init the sdrc chip selects CS0 and CS1
  *  - early init routines, called from flash or
@@ -192,6 +193,75 @@ void do_sdrc_init(u32 cs, u32 early)
 	if (!mem_ok(cs))
 		writel(0, &sdrc_base->cs[cs].mcfg);
 }
+#elif defined(CONFIG_EMIF4)	/* #if define (CONFIG_SDRC) */
+
+static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
+
+/********************************************************
+ * emif4 _init() - init the emif4 module for DDR access
+ *  - early init routines, called from flash or
+ *  SRAM.
+ *******************************************************/
+void emif4_init(void)
+{
+	unsigned int regval;
+	/* Set the DDR PHY parameters in PHY ctrl registers */
+	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
+		EMIF4_DDR1_EXT_STRB_DIS);
+	writel(regval, &emif4_base->ddr_phyctrl1);
+	writel(regval, &emif4_base->ddr_phyctrl1_shdw);
+	writel(0, &emif4_base->ddr_phyctrl2);
+
+	/* Reset the DDR PHY and wait till completed */
+	regval = readl(&emif4_base->sdram_iodft_tlgc);
+	regval |= (1<<10);
+	writel(regval, &emif4_base->sdram_iodft_tlgc);
+	/*Wait till that bit clears*/
+	while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
+	/*Re-verify the DDR PHY status*/
+	while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
+
+	regval |= (1<<0);
+	writel(regval, &emif4_base->sdram_iodft_tlgc);
+	/* Set SDR timing registers */
+	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
+		EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
+		EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
+		EMIF4_TIM1_T_RP);
+	writel(regval, &emif4_base->sdram_time1);
+	writel(regval, &emif4_base->sdram_time1_shdw);
+
+	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
+		EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
+		EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
+	writel(regval, &emif4_base->sdram_time2);
+	writel(regval, &emif4_base->sdram_time2_shdw);
+
+	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
+	writel(regval, &emif4_base->sdram_time3);
+	writel(regval, &emif4_base->sdram_time3_shdw);
+
+	/* Set the PWR control register */
+	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
+		EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
+	writel(regval, &emif4_base->sdram_pwr_mgmt);
+	writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
+
+	/* Set the DDR refresh rate control register */
+	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
+	writel(regval, &emif4_base->sdram_refresh_ctrl);
+	writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
+
+	/* set the SDRAM configuration register */
+	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
+		EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
+		EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
+		EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
+		EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
+		EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
+	writel(regval, &emif4_base->sdram_config);
+}
+#endif	/* #if define (CONFIG_SDRC) */

 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size)
diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c
index 08fb32e..f396898 100644
--- a/cpu/arm_cortexa8/omap3/sys_info.c
+++ b/cpu/arm_cortexa8/omap3/sys_info.c
@@ -109,8 +109,10 @@ u32 get_cpu_rev(void)
  ****************************************************/
 u32 is_mem_sdr(void)
 {
+#if defined(CONFIG_SDRC)
 	if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
 		return 1;
+#endif
 	return 0;
 }

@@ -121,10 +123,16 @@ u32 get_sdr_cs_size(u32 cs)
 {
 	u32 size;

+#if defined(CONFIG_EMIF4)
+	/* TODO: Calculate the size based on EMIF4 configuration */
+	size = CONFIG_SYS_CS0_SIZE;
+#elif defined(CONFIG_SDRC)
 	/* get ram size field */
 	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
 	size &= 0x3FF;		/* remove unwanted bits */
 	size <<= 21;		/* multiply by 2 MiB to find size in MB */
+#endif
+
 	return size;
 }

@@ -133,13 +141,15 @@ u32 get_sdr_cs_size(u32 cs)
  ************************************************************************/
 u32 get_sdr_cs_offset(u32 cs)
 {
-	u32 offset;
+	u32 offset = 0;

 	if (!cs)
 		return 0;

+#if defined(CONFIG_SDRC)
 	offset = readl(&sdrc_base->cs_cfg);
 	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+#endif

 	return offset;
 }
diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
index e51c4f3..f9aacb4 100644
--- a/include/asm-arm/arch-omap3/cpu.h
+++ b/include/asm-arm/arch-omap3/cpu.h
@@ -214,6 +214,32 @@ struct sdrc {
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */

+/* EMIF4 */
+#ifndef __ASSEMBLY__
+typedef struct emif4 {
+	unsigned int sdram_sts;
+	unsigned int sdram_config;
+	unsigned int res1;
+	unsigned int sdram_refresh_ctrl;
+	unsigned int sdram_refresh_ctrl_shdw;
+	unsigned int sdram_time1;
+	unsigned int sdram_time1_shdw;
+	unsigned int sdram_time2;
+	unsigned int sdram_time2_shdw;
+	unsigned int sdram_time3;
+	unsigned int sdram_time3_shdw;
+	unsigned char res2[8];
+	unsigned int sdram_pwr_mgmt;
+	unsigned int sdram_pwr_mgmt_shdw;
+	unsigned char res3[32];
+	unsigned int sdram_iodft_tlgc;
+	unsigned char res4[128];
+	unsigned int ddr_phyctrl1;
+	unsigned int ddr_phyctrl1_shdw;
+	unsigned int ddr_phyctrl2;
+} emif4_t;
+#endif /* __ASSEMBLY__ */
+
 #define DLLPHASE_90		(0x1 << 1)
 #define LOADDLL			(0x1 << 2)
 #define ENADLL			(0x1 << 3)
diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
index 7dbfc92..8e7df37 100644
--- a/include/asm-arm/arch-omap3/mem.h
+++ b/include/asm-arm/arch-omap3/mem.h
@@ -39,6 +39,60 @@ enum {

 #define EARLY_INIT	1

+/*
+ * EMIF4 -
+ * 	Configuration values
+ */
+#define EMIF4_TIM1_T_RP		(0x3 << 25)
+#define EMIF4_TIM1_T_RCD	(0x3 << 21)
+#define EMIF4_TIM1_T_WR		(0x3 << 17)
+#define EMIF4_TIM1_T_RAS	(0x8 << 12)
+#define EMIF4_TIM1_T_RC		(0xA << 6)
+#define EMIF4_TIM1_T_RRD	(0x2 << 3)
+#define EMIF4_TIM1_T_WTR	(0x2 << 0)
+
+#define EMIF4_TIM2_T_XP		(0x2 << 28)
+#define EMIF4_TIM2_T_ODT	(0x0 << 25)
+#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
+#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
+#define EMIF4_TIM2_T_RTP	(0x1 << 3)
+#define EMIF4_TIM2_T_CKE	(0x2 << 0)
+
+#define EMIF4_TIM3_T_RFC	(0x25 << 4)
+#define EMIF4_TIM3_T_RAS_MAX	(0x7 << 0)
+
+#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
+#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
+#define EMIF4_PWR_DPD_EN	(0x1 << 10)
+#define EMIF4_PWR_LP_MODE	(0x0 << 8)
+#define EMIF4_PWR_PM_TIM	(0x0 << 0)
+
+#define EMIF4_INITREF_DIS	(0x0 << 31)
+#define EMIF4_REFRESH_RATE	(0x50F << 0)
+
+#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
+#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
+#define EMIF4_CFG_DDR_TERM	(0x0 << 24)
+#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
+#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
+#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
+#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
+#define EMIF4_CFG_CL		(0x5 << 10)
+#define EMIF4_CFG_ROWSIZE	(0x0 << 7)
+#define EMIF4_CFG_IBANK		(0x3 << 4)
+#define EMIF4_CFG_EBANK		(0x0 << 3)
+#define EMIF4_CFG_PGSIZE	(0x2 << 0)
+/*
+ * EMIF4 PHY Control 1 register configuration
+ */
+#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
+#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
+#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
+#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
+#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
+
+#if defined(CONFIG_SDRC)
+
 /* Slower full frequency range default timings for x32 operation*/
 #define SDRC_SHARING	0x00000100
 #define SDRC_MR_0_SDR	0x00000031
@@ -140,7 +194,7 @@ enum {
 #if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
 #error "Please choose the right DDR type in config header"
 #endif
-
+#endif	/* #if defined (CONFIG_SDRC) */
 /*
  * GPMC settings -
  * Definitions is as per the following format
@@ -191,7 +245,7 @@ enum {
 #define SMNAND_GPMC_CONFIG6	0x1F0F0A80
 #define SMNAND_GPMC_CONFIG7	0x00000C44

-#if defined (CONFIG_OMAP3_AM3517EVM)
+#if defined(CONFIG_OMAP3_AM3517EVM)
 #define M_NAND_GPMC_CONFIG1	0x00001800
 #define M_NAND_GPMC_CONFIG2	0x00080800
 #define M_NAND_GPMC_CONFIG3	0x00080800
diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h
index 34bd515..cfbc84b 100644
--- a/include/asm-arm/arch-omap3/sys_proto.h
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -31,8 +31,12 @@ void prcm_init(void);
 void per_clocks_enable(void);

 void memif_init(void);
+#if defined(CONFIG_SDRC)
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+#elif defined(CONFIG_EMIF4)
+void emif4_init(void);
+#endif
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index d7eef73..74e52c1 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -62,6 +62,12 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
+
+/*
+ * Support for EMIF4
+ */
+#define CONFIG_EMIF4			1
+
 /*
  * DDR size interfaced
  */
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 1011770..8041416 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -66,6 +66,10 @@

 /* Hardware drivers */

+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 024b9b8..7fb3434 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -97,6 +97,10 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1

+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 36cb5e0..68e0569 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -101,6 +101,10 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1

+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1

diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 0f812a7..7ae4f0c 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -89,6 +89,10 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1

+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1

diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 0cafeb8..45c38bf 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -92,6 +92,10 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1

+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1

diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index d91c8ff..a8deab5 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -137,6 +137,10 @@
 #define CONFIG_SYS_I2C_BUS_SELECT	1
 #define CONFIG_DRIVER_OMAP34XX_I2C	1

+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Infineon DDR */
 #define CONFIG_OMAP3_INFINEON_DDR	1

diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 2aef973..17cb3fb 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -98,6 +98,10 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1

+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1

diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index 5b03fb6..cf09832 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -98,6 +98,10 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1

+/*
+ * Support for SDRC
+ */
+#define CONFIG_SDRC			1
 /* DDR - I use Micron DDR */
 #define CONFIG_OMAP3_MICRON_DDR		1

--
1.6.2.4

[U-Boot] [PATCH 5/5] AM3517: Add support for EMIF4

[Wolfgang Denk]

Dear hvaibhav at ti.com,

In message <1258974555-28173-1-git-send-email-hvaibhav@ti.com> you wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> Changes:-
> 
> 	- Created 2 seperate config option
> 		* CONFIG_SDRC (omap34xx family)
> 		* CONFIG_EMIF4 (am3517 family)
> 	- Changed all omap3 dependent file for CONFIG_SDRC
> 
> Tested On:-
> 
>         - AM3517EVM board
>         - OMAP3EVM board
>         - BEAGLE board
> 
> I would need help here from people to validate this change for SDP/ZOOMx
> and other OMAP3 version of boards.

This commit adds a lot of  #ifdef's - maybe it would make more sense
to split code into different files?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
You are an excellent tactician, Captain. You let your second in  com-
mand attack while you sit and watch for weakness.
	-- Khan Noonian Singh, "Space Seed", stardate 3141.9

[U-Boot] [PATCH 5/5] AM3517: Add support for EMIF4

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Tuesday, November 24, 2009 1:21 AM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 5/5] AM3517: Add support for EMIF4
> 
> Dear hvaibhav at ti.com,
> 
> In message <1258974555-28173-1-git-send-email-hvaibhav@ti.com> you
> wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > Changes:-
> >
> > 	- Created 2 seperate config option
> > 		* CONFIG_SDRC (omap34xx family)
> > 		* CONFIG_EMIF4 (am3517 family)
> > 	- Changed all omap3 dependent file for CONFIG_SDRC
> >
> > Tested On:-
> >
> >         - AM3517EVM board
> >         - OMAP3EVM board
> >         - BEAGLE board
> >
> > I would need help here from people to validate this change for
> SDP/ZOOMx
> > and other OMAP3 version of boards.
> 
> This commit adds a lot of  #ifdef's - maybe it would make more sense
> to split code into different files?
> 
[Hiremath, Vaibhav] Initially I thought of this, but since currently AM3517 is the only device in OMAP3 series which uses EMIF and all others use SDRC. So I thought lets start with this approach and get peoples opinion on this, and then we can split the files.

Thanks,
Vaibhav

> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev
> Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email:
> wd at denx.de
> You are an excellent tactician, Captain. You let your second in
> com-
> mand attack while you sit and watch for weakness.
> 	-- Khan Noonian Singh, "Space Seed", stardate 3141.9

[U-Boot] [PATCH 5/5] AM3517: Add support for EMIF4

[Tom]

Hiremath, Vaibhav wrote:
>> -----Original Message-----
>> From: Wolfgang Denk [mailto:wd at denx.de]
>> Sent: Tuesday, November 24, 2009 1:21 AM
>> To: Hiremath, Vaibhav
>> Cc: u-boot at lists.denx.de
>> Subject: Re: [U-Boot] [PATCH 5/5] AM3517: Add support for EMIF4
>>
>> Dear hvaibhav at ti.com,
>>
>> In message <1258974555-28173-1-git-send-email-hvaibhav@ti.com> you
>> wrote:
>>> From: Vaibhav Hiremath <hvaibhav@ti.com>
>>>
>>> Changes:-
>>>
>>> 	- Created 2 seperate config option
>>> 		* CONFIG_SDRC (omap34xx family)
>>> 		* CONFIG_EMIF4 (am3517 family)
>>> 	- Changed all omap3 dependent file for CONFIG_SDRC
>>>
>>> Tested On:-
>>>
>>>         - AM3517EVM board
>>>         - OMAP3EVM board
>>>         - BEAGLE board
>>>
>>> I would need help here from people to validate this change for
>> SDP/ZOOMx
>>> and other OMAP3 version of boards.
>> This commit adds a lot of  #ifdef's - maybe it would make more sense
>> to split code into different files?
>>
> [Hiremath, Vaibhav] Initially I thought of this, but since currently AM3517 is the only device in OMAP3 series which uses EMIF and all others use SDRC. So I thought lets start with this approach and get peoples opinion on this, and then we can split the files.
>

Please split this patch.
Add the logic for the exiting boards as the first patch.
Add the logic for the am3517 as the second.
This will allow this change to be bisected.

I would prefer each set of defines to have their own file.

Tom

> Thanks,
> Vaibhav
> 
>> Best regards,
>>
>> Wolfgang Denk
>>
>> --
>> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev
>> Zundel
>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
>> Germany
>> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email:
>> wd at denx.de
>> You are an excellent tactician, Captain. You let your second in
>> com-
>> mand attack while you sit and watch for weakness.
>> 	-- Khan Noonian Singh, "Space Seed", stardate 3141.9
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 5/5] AM3517: Add support for EMIF4

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Tom [mailto:Tom.Rix at windriver.com]
> Sent: Thursday, November 26, 2009 9:44 PM
> To: Hiremath, Vaibhav
> Cc: Wolfgang Denk; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH 5/5] AM3517: Add support for EMIF4
> 
> Hiremath, Vaibhav wrote:
> >> -----Original Message-----
> >> From: Wolfgang Denk [mailto:wd at denx.de]
> >> Sent: Tuesday, November 24, 2009 1:21 AM
> >> To: Hiremath, Vaibhav
> >> Cc: u-boot at lists.denx.de
> >> Subject: Re: [U-Boot] [PATCH 5/5] AM3517: Add support for EMIF4
> >>
> >> Dear hvaibhav at ti.com,
> >>
> >> In message <1258974555-28173-1-git-send-email-hvaibhav@ti.com>
> you
> >> wrote:
> >>> From: Vaibhav Hiremath <hvaibhav@ti.com>
> >>>
> >>> Changes:-
> >>>
> >>> 	- Created 2 seperate config option
> >>> 		* CONFIG_SDRC (omap34xx family)
> >>> 		* CONFIG_EMIF4 (am3517 family)
> >>> 	- Changed all omap3 dependent file for CONFIG_SDRC
> >>>
> >>> Tested On:-
> >>>
> >>>         - AM3517EVM board
> >>>         - OMAP3EVM board
> >>>         - BEAGLE board
> >>>
> >>> I would need help here from people to validate this change for
> >> SDP/ZOOMx
> >>> and other OMAP3 version of boards.
> >> This commit adds a lot of  #ifdef's - maybe it would make more
> sense
> >> to split code into different files?
> >>
> > [Hiremath, Vaibhav] Initially I thought of this, but since
> currently AM3517 is the only device in OMAP3 series which uses EMIF
> and all others use SDRC. So I thought lets start with this approach
> and get peoples opinion on this, and then we can split the files.
> >
> 
> Please split this patch.
> Add the logic for the exiting boards as the first patch.
> Add the logic for the am3517 as the second.
> This will allow this change to be bisected.
> 
[Hiremath, Vaibhav] Ok, will do in next version.

> I would prefer each set of defines to have their own file.
[Hiremath, Vaibhav] How about taking this is second version?

Thanks,
Vaibhav

> 
> Tom
> 
> > Thanks,
> > Vaibhav
> >
> >> Best regards,
> >>
> >> Wolfgang Denk
> >>
> >> --
> >> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev
> >> Zundel
> >> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> >> Germany
> >> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email:
> >> wd at denx.de
> >> You are an excellent tactician, Captain. You let your second in
> >> com-
> >> mand attack while you sit and watch for weakness.
> >> 	-- Khan Noonian Singh, "Space Seed", stardate 3141.9
> > _______________________________________________
> > U-Boot mailing list
> > U-Boot at lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 0/3] Add Support for AM3517EVM with EMIF4

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

AM3517 device is high-performance, industrial applications processor designed
and developed keeping Software Compatible with OMAP3 Processors.

Differances :-
===========
	- The SDRC controller has been replaced with EMIF4.
	- Some new IP's got added like, CAN, VPFE, etc...
	- Removed ISP completely

This patch series adds support for AM3517EVM along with EMIF4 configuration.

Tested :-
===========
	- OMAP3 EVM (both NAND and MMC boot mode)
	- OMAP3 BEAGLE (MMC boot mode)
	- AM3517 EVM (both NAND and MMC boot mode)

Below are some of the useful links :-
===========
AM3517 device is high-performance, industrial applications processor designed
and developed keeping Software Compatible with OMAP3 Processors.

Below are some of the useful links -

Migration from OMAP35x to AM35x :-
http://focus.ti.com/lit/an/sprab91/sprab91.pdf

Specs/TRM :-
http://focus.ti.com/docs/prod/folders/print/am3517.html

EVM Link -:
http://www.logicpd.com/products/development-kits/zoom-am3517-experimenter-kit


Vaibhav Hiremath (3):
  OMAP3: Consolidate SDRC related operations
  AM35x: Add support for AM3517EVM
  AM35x: Add support for EMIF4

 MAINTAINERS                            |    4 +
 Makefile                               |    3 +
 board/ti/am3517evm/Makefile            |   47 ++++
 board/ti/am3517evm/am3517evm.c         |   76 ++++++
 board/ti/am3517evm/am3517evm.h         |  400 ++++++++++++++++++++++++++++++++
 board/ti/am3517evm/config.mk           |   29 +++
 cpu/arm_cortexa8/omap3/Makefile        |    6 +
 cpu/arm_cortexa8/omap3/board.c         |   34 +---
 cpu/arm_cortexa8/omap3/emif4.c         |  160 +++++++++++++
 cpu/arm_cortexa8/omap3/mem.c           |   90 -------
 cpu/arm_cortexa8/omap3/sdrc.c          |  186 +++++++++++++++
 cpu/arm_cortexa8/omap3/sys_info.c      |   42 +----
 include/asm-arm/arch-omap3/cpu.h       |   26 ++
 include/asm-arm/arch-omap3/emif4.h     |   77 ++++++
 include/asm-arm/arch-omap3/mem.h       |   24 ++
 include/asm-arm/arch-omap3/mux.h       |   35 +++
 include/asm-arm/arch-omap3/sys_proto.h |    7 +-
 include/configs/am3517_evm.h           |  293 +++++++++++++++++++++++
 include/configs/omap3_beagle.h         |    2 +
 include/configs/omap3_evm.h            |    2 +
 include/configs/omap3_overo.h          |    2 +
 include/configs/omap3_pandora.h        |    2 +
 include/configs/omap3_sdp3430.h        |    2 +
 include/configs/omap3_zoom1.h          |    2 +
 include/configs/omap3_zoom2.h          |    2 +
 25 files changed, 1387 insertions(+), 166 deletions(-)
 create mode 100644 board/ti/am3517evm/Makefile
 create mode 100644 board/ti/am3517evm/am3517evm.c
 create mode 100644 board/ti/am3517evm/am3517evm.h
 create mode 100644 board/ti/am3517evm/config.mk
 create mode 100644 cpu/arm_cortexa8/omap3/emif4.c
 create mode 100644 cpu/arm_cortexa8/omap3/sdrc.c
 create mode 100644 include/asm-arm/arch-omap3/emif4.h
 create mode 100644 include/configs/am3517_evm.h

[U-Boot] [PATCH 0/3] Add Support for AM3517EVM with EMIF4

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Hiremath, Vaibhav
> Sent: Saturday, January 30, 2010 3:47 PM
> To: u-boot at lists.denx.de
> Cc: Paulraj, Sandeep; Tom.Rix at windriver.com; Hiremath, Vaibhav
> Subject: [PATCH 0/3] Add Support for AM3517EVM with EMIF4
> 
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> AM3517 device is high-performance, industrial applications processor
> designed
> and developed keeping Software Compatible with OMAP3 Processors.
> 
> Differances :-
> ===========
> 	- The SDRC controller has been replaced with EMIF4.
> 	- Some new IP's got added like, CAN, VPFE, etc...
> 	- Removed ISP completely
> 
> This patch series adds support for AM3517EVM along with EMIF4
> configuration.
> 
> Tested :-
> ===========
> 	- OMAP3 EVM (both NAND and MMC boot mode)
> 	- OMAP3 BEAGLE (MMC boot mode)
> 	- AM3517 EVM (both NAND and MMC boot mode)
> 
> Below are some of the useful links :-
> ===========
> AM3517 device is high-performance, industrial applications processor
> designed
> and developed keeping Software Compatible with OMAP3 Processors.
> 
> Below are some of the useful links -
> 
> Migration from OMAP35x to AM35x :-
> http://focus.ti.com/lit/an/sprab91/sprab91.pdf
> 
> Specs/TRM :-
> http://focus.ti.com/docs/prod/folders/print/am3517.html
> 
> EVM Link -:
> http://www.logicpd.com/products/development-kits/zoom-am3517-
> experimenter-kit
> 
> 
> Vaibhav Hiremath (3):
>   OMAP3: Consolidate SDRC related operations
>   AM35x: Add support for AM3517EVM
>   AM35x: Add support for EMIF4
> 
[Hiremath, Vaibhav] Sandeep,

Can you please merge these series of patches for next window?

Thanks,
Vaibhav

>  MAINTAINERS                            |    4 +
>  Makefile                               |    3 +
>  board/ti/am3517evm/Makefile            |   47 ++++
>  board/ti/am3517evm/am3517evm.c         |   76 ++++++
>  board/ti/am3517evm/am3517evm.h         |  400
> ++++++++++++++++++++++++++++++++
>  board/ti/am3517evm/config.mk           |   29 +++
>  cpu/arm_cortexa8/omap3/Makefile        |    6 +
>  cpu/arm_cortexa8/omap3/board.c         |   34 +---
>  cpu/arm_cortexa8/omap3/emif4.c         |  160 +++++++++++++
>  cpu/arm_cortexa8/omap3/mem.c           |   90 -------
>  cpu/arm_cortexa8/omap3/sdrc.c          |  186 +++++++++++++++
>  cpu/arm_cortexa8/omap3/sys_info.c      |   42 +----
>  include/asm-arm/arch-omap3/cpu.h       |   26 ++
>  include/asm-arm/arch-omap3/emif4.h     |   77 ++++++
>  include/asm-arm/arch-omap3/mem.h       |   24 ++
>  include/asm-arm/arch-omap3/mux.h       |   35 +++
>  include/asm-arm/arch-omap3/sys_proto.h |    7 +-
>  include/configs/am3517_evm.h           |  293
> +++++++++++++++++++++++
>  include/configs/omap3_beagle.h         |    2 +
>  include/configs/omap3_evm.h            |    2 +
>  include/configs/omap3_overo.h          |    2 +
>  include/configs/omap3_pandora.h        |    2 +
>  include/configs/omap3_sdp3430.h        |    2 +
>  include/configs/omap3_zoom1.h          |    2 +
>  include/configs/omap3_zoom2.h          |    2 +
>  25 files changed, 1387 insertions(+), 166 deletions(-)
>  create mode 100644 board/ti/am3517evm/Makefile
>  create mode 100644 board/ti/am3517evm/am3517evm.c
>  create mode 100644 board/ti/am3517evm/am3517evm.h
>  create mode 100644 board/ti/am3517evm/config.mk
>  create mode 100644 cpu/arm_cortexa8/omap3/emif4.c
>  create mode 100644 cpu/arm_cortexa8/omap3/sdrc.c
>  create mode 100644 include/asm-arm/arch-omap3/emif4.h
>  create mode 100644 include/configs/am3517_evm.h

[U-Boot] [PATCH 0/3] Add Support for AM3517EVM with EMIF4

[Tom]

Hiremath, Vaibhav wrote:
>> -----Original Message-----
>> From: Hiremath, Vaibhav
>> Sent: Saturday, January 30, 2010 3:47 PM
>> To: u-boot at lists.denx.de
>> Cc: Paulraj, Sandeep; Tom.Rix at windriver.com; Hiremath, Vaibhav
>> Subject: [PATCH 0/3] Add Support for AM3517EVM with EMIF4
>>
>> From: Vaibhav Hiremath <hvaibhav@ti.com>
>>
<snip>

>>
> [Hiremath, Vaibhav] Sandeep,
> 
> Can you please merge these series of patches for next window?
> 

This patchset still needs to be reviewed.
I will post my review this weekend.
Tom

[U-Boot] [PATCH 0/3] Add Support for AM3517EVM with EMIF4

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Tom [mailto:Tom.Rix at windriver.com]
> Sent: Wednesday, February 03, 2010 6:54 PM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de; Paulraj, Sandeep
> Subject: Re: [PATCH 0/3] Add Support for AM3517EVM with EMIF4
> 
> Hiremath, Vaibhav wrote:
> >> -----Original Message-----
> >> From: Hiremath, Vaibhav
> >> Sent: Saturday, January 30, 2010 3:47 PM
> >> To: u-boot at lists.denx.de
> >> Cc: Paulraj, Sandeep; Tom.Rix at windriver.com; Hiremath, Vaibhav
> >> Subject: [PATCH 0/3] Add Support for AM3517EVM with EMIF4
> >>
> >> From: Vaibhav Hiremath <hvaibhav@ti.com>
> >>
> <snip>
> 
> >>
> > [Hiremath, Vaibhav] Sandeep,
> >
> > Can you please merge these series of patches for next window?
> >
> 
> This patchset still needs to be reviewed.
> I will post my review this weekend.
[Hiremath, Vaibhav] Review comments are always welcomed. Since this is second version and we haven't had any comments last time. I requested to merge.

Looking forward for your comments.

Thanks,
Vaibhav

> Tom

[U-Boot] [PATCH 1/3] OMAP3: Consolidate SDRC related operations

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

Consolidated all SDRC related functions/operations into separate
file - sdrc.c.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 cpu/arm_cortexa8/omap3/Makefile        |    3 +
 cpu/arm_cortexa8/omap3/board.c         |   34 +------
 cpu/arm_cortexa8/omap3/mem.c           |   90 ---------------
 cpu/arm_cortexa8/omap3/sdrc.c          |  186 ++++++++++++++++++++++++++++++++
 cpu/arm_cortexa8/omap3/sys_info.c      |   42 +-------
 include/asm-arm/arch-omap3/mem.h       |   14 +++
 include/asm-arm/arch-omap3/sys_proto.h |    4 +-
 include/configs/omap3_beagle.h         |    2 +
 include/configs/omap3_evm.h            |    2 +
 include/configs/omap3_overo.h          |    2 +
 include/configs/omap3_pandora.h        |    2 +
 include/configs/omap3_sdp3430.h        |    2 +
 include/configs/omap3_zoom1.h          |    2 +
 include/configs/omap3_zoom2.h          |    2 +
 14 files changed, 221 insertions(+), 166 deletions(-)
 create mode 100644 cpu/arm_cortexa8/omap3/sdrc.c

diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index 136b163..8cc7802 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -33,6 +33,9 @@ COBJS	+= board.o
 COBJS	+= clock.o
 COBJS	+= gpio.o
 COBJS	+= mem.o
+ifdef	CONFIG_SDRC
+COBJS	+= sdrc.o
+endif
 COBJS	+= syslib.o
 COBJS	+= sys_info.o
 COBJS	+= timer.o
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 2aa69b3..0bad682 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -40,8 +40,6 @@

 extern omap3_sysinfo sysinfo;

-extern u32 is_mem_sdr(void);
-
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works
@@ -227,7 +225,7 @@ void s_init(void)
 	per_clocks_enable();

 	if (!in_sdram)
-		sdrc_init();
+		mem_init();
 }

 /******************************************************************************
@@ -268,36 +266,6 @@ void watchdog_init(void)
 }

 /******************************************************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- *****************************************************************************/
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	unsigned int size0 = 0, size1 = 0;
-
-	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
-	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
-		do_sdrc_init(CS1, NOT_EARLY);
-		make_cs1_contiguous();
-	}
-
-	size0 = get_sdr_cs_size(CS0);
-	size1 = get_sdr_cs_size(CS1);
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
-
-	return 0;
-}
-
-/******************************************************************************
  * Dummy function to handle errors for EABI incompatibility
  *****************************************************************************/
 void abort(void)
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index dfb7e4c..bd914b0 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -79,26 +79,6 @@ static const u32 gpmc_onenand[GPMC_MAX_REG] = {

 #endif

-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
-
-/**************************************************************************
- * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
- *  command line mem=xyz use all memory with out discontinuous support
- *  compiled in.  Could do it at the ATAG, but there really is two banks...
- * Called as part of 2nd phase DDR init.
- **************************************************************************/
-void make_cs1_contiguous(void)
-{
-	u32 size, a_add_low, a_add_high;
-
-	size = get_sdr_cs_size(CS0);
-	size >>= 25;	/* divide by 32 MiB to find size to offset CS1 */
-	a_add_high = (size & 3) << 8;	/* set up low field */
-	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
-	writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
-
-}
-
 /********************************************************
  *  mem_ok() - test used to see if timings are correct
  *             for a part. Helps in guessing which part
@@ -123,76 +103,6 @@ u32 mem_ok(u32 cs)
 		return 1;
 }

-/********************************************************
- *  sdrc_init() - init the sdrc chip selects CS0 and CS1
- *  - early init routines, called from flash or
- *  SRAM.
- *******************************************************/
-void sdrc_init(void)
-{
-	/* only init up first bank here */
-	do_sdrc_init(CS0, EARLY_INIT);
-}
-
-/*************************************************************************
- * do_sdrc_init(): initialize the SDRAM for use.
- *  -code sets up SDRAM basic SDRC timings for CS0
- *  -optimal settings can be placed here, or redone after i2c
- *      inspection of board info
- *
- *  - code called once in C-Stack only context for CS0 and a possible 2nd
- *      time depending on memory configuration from stack+global context
- **************************************************************************/
-
-void do_sdrc_init(u32 cs, u32 early)
-{
-	struct sdrc_actim *sdrc_actim_base;
-
-	if(cs)
-		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
-	else
-		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-
-	if (early) {
-		/* reset sdrc controller */
-		writel(SOFTRESET, &sdrc_base->sysconfig);
-		wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
-			      12000000);
-		writel(0, &sdrc_base->sysconfig);
-
-		/* setup sdrc to ball mux */
-		writel(SDRC_SHARING, &sdrc_base->sharing);
-
-		/* Disable Power Down of CKE cuz of 1 CKE on combo part */
-		writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
-				&sdrc_base->power);
-
-		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
-		sdelay(0x20000);
-	}
-
-	writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
-		RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
-		DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
-	writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
-	writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
-	writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
-
-	writel(CMD_NOP, &sdrc_base ->cs[cs].manual);
-	writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
-	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-
-	/*
-	 * CAS latency 3, Write Burst = Read Burst, Serial Mode,
-	 * Burst length = 4
-	 */
-	writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
-
-	if (!mem_ok(cs))
-		writel(0, &sdrc_base->cs[cs].mcfg);
-}
-
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size)
 {
diff --git a/cpu/arm_cortexa8/omap3/sdrc.c b/cpu/arm_cortexa8/omap3/sdrc.c
new file mode 100644
index 0000000..9a46155
--- /dev/null
+++ b/cpu/arm_cortexa8/omap3/sdrc.c
@@ -0,0 +1,186 @@
+/*
+ * Functions related to SDRC.
+ *
+ * This file has been created after exctracting and consolidating
+ * the SDRC related content from mem.c and board.c.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+
+extern omap3_sysinfo sysinfo;
+
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+
+/**
+ * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
+ *  command line mem=xyz use all memory with out discontinuous support
+ *  compiled in.  Could do it at the ATAG, but there really is two banks...
+ * Called as part of 2nd phase DDR init.
+ */
+void make_cs1_contiguous(void)
+{
+	u32 size, a_add_low, a_add_high;
+
+	size = get_sdr_cs_size(CS0);
+	size >>= 25;	/* divide by 32 MiB to find size to offset CS1 */
+	a_add_high = (size & 3) << 8;	/* set up low field */
+	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
+	writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
+
+}
+/**
+ * is_mem_sdr() - return 1 if mem type in use is SDR
+ */
+u32 is_mem_sdr(void)
+{
+	if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
+		return 1;
+	return 0;
+}
+
+/**
+ * get_sdr_cs_size() - get size of chip select 0/1
+ */
+u32 get_sdr_cs_size(u32 cs)
+{
+	u32 size;
+
+	/* get ram size field */
+	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
+	size &= 0x3FF;		/* remove unwanted bits */
+	size <<= 21;		/* multiply by 2 MiB to find size in MB */
+	return size;
+}
+
+/**
+ * get_sdr_cs_offset() - get offset of cs from cs0 start
+ */
+u32 get_sdr_cs_offset(u32 cs)
+{
+	u32 offset;
+
+	if (!cs)
+		return 0;
+
+	offset = readl(&sdrc_base->cs_cfg);
+	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+
+	return offset;
+}
+
+/**
+ * do_sdrc_init(): initialize the SDRAM for use.
+ *  -Sets up SDRAM basic SDRC timings for CS0
+ *  -Optimal settings can be placed here, or redone after i2c
+ *      inspection of board info
+ *
+ *  - code called once in C-Stack only context for CS0 and a possible 2nd
+ *    time depending on memory configuration from stack+global context
+ */
+void do_sdrc_init(u32 cs, u32 early)
+{
+	struct sdrc_actim *sdrc_actim_base;
+
+	if (cs)
+		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+	else
+		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+
+	if (early) {
+		/* reset sdrc controller */
+		writel(SOFTRESET, &sdrc_base->sysconfig);
+		wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
+			      12000000);
+		writel(0, &sdrc_base->sysconfig);
+
+		/* setup sdrc to ball mux */
+		writel(SDRC_SHARING, &sdrc_base->sharing);
+
+		/* Disable Power Down of CKE cuz of 1 CKE on combo part */
+		writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
+				&sdrc_base->power);
+
+		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
+		sdelay(0x20000);
+	}
+
+	writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
+		RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
+		DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
+	writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
+	writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
+	writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
+
+	writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+	writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+
+	/*
+	 * CAS latency 3, Write Burst = Read Burst, Serial Mode,
+	 * Burst length = 4
+	 */
+	writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
+
+	if (!mem_ok(cs))
+		writel(0, &sdrc_base->cs[cs].mcfg);
+}
+
+/**
+ * dram_init - Sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int size0 = 0, size1 = 0;
+
+	size0 = get_sdr_cs_size(CS0);
+	/*
+	 * If a second bank of DDR is attached to CS1 this is
+	 * where it can be started.  Early init code will init
+	 * memory on CS0.
+	 */
+	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
+		do_sdrc_init(CS1, NOT_EARLY);
+		make_cs1_contiguous();
+
+		size1 = get_sdr_cs_size(CS1);
+	}
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
+}
+
+/**
+ * mem_init() - init the sdrc chip selects CS0 and CS1
+ *  - early init routines, called from flash or SRAM.
+ */
+void mem_init(void)
+{
+	/* only init up first bank here */
+	do_sdrc_init(CS0, EARLY_INIT);
+}
diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c
index 08fb32e..1458b89 100644
--- a/cpu/arm_cortexa8/omap3/sys_info.c
+++ b/cpu/arm_cortexa8/omap3/sys_info.c
@@ -32,7 +32,7 @@
 #include <i2c.h>

 extern omap3_sysinfo sysinfo;
-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+
 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 static char *rev_s[CPU_3XX_MAX_REV] = {
 				"1.0",
@@ -104,46 +104,6 @@ u32 get_cpu_rev(void)
 	}
 }

-/****************************************************
- * is_mem_sdr() - return 1 if mem type in use is SDR
- ****************************************************/
-u32 is_mem_sdr(void)
-{
-	if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
-		return 1;
-	return 0;
-}
-
-/***********************************************************************
- * get_cs0_size() - get size of chip select 0/1
- ************************************************************************/
-u32 get_sdr_cs_size(u32 cs)
-{
-	u32 size;
-
-	/* get ram size field */
-	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
-	size &= 0x3FF;		/* remove unwanted bits */
-	size <<= 21;		/* multiply by 2 MiB to find size in MB */
-	return size;
-}
-
-/***********************************************************************
- * get_sdr_cs_offset() - get offset of cs from cs0 start
- ************************************************************************/
-u32 get_sdr_cs_offset(u32 cs)
-{
-	u32 offset;
-
-	if (!cs)
-		return 0;
-
-	offset = readl(&sdrc_base->cs_cfg);
-	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
-
-	return offset;
-}
-
 /***************************************************************************
  *  get_gpmc0_base() - Return current address hardware will be
  *     fetching from. The below effectively gives what is correct, its a bit
diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
index 9439758..0f3733f 100644
--- a/include/asm-arm/arch-omap3/mem.h
+++ b/include/asm-arm/arch-omap3/mem.h
@@ -270,4 +270,18 @@ enum {
 #define PISMO1_ONEN_BASE	ONENAND_MAP
 #define DBG_MPDB_BASE		DEBUG_BASE

+#ifndef __ASSEMBLY__
+/*
+ * Function prototypes
+ */
+void mem_init(void);
+
+u32 is_mem_sdr(void);
+u32 mem_ok(u32 cs);
+
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* endif _MEM_H_ */
diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h
index 34bd515..34e4e0d 100644
--- a/include/asm-arm/arch-omap3/sys_proto.h
+++ b/include/asm-arm/arch-omap3/sys_proto.h
@@ -31,8 +31,10 @@ void prcm_init(void);
 void per_clocks_enable(void);

 void memif_init(void);
+#if defined(CONFIG_SDRC)
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+#endif
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);
@@ -46,8 +48,6 @@ u32 get_sysboot_value(void);
 u32 is_gpmc_muxed(void);
 u32 get_gpmc0_type(void);
 u32 get_gpmc0_width(void);
-u32 get_sdr_cs_size(u32);
-u32 get_sdr_cs_offset(u32);
 u32 is_running_in_sdram(void);
 u32 is_running_in_sram(void);
 u32 is_running_in_flash(void);
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index a8abb0e..eeeb324 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -37,6 +37,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 52cb202..72b2f72 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_EVM	1	/* working with EVM */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index c72fb9d..d36b8f7 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -29,6 +29,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_OVERO	1	/* working with overo */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index f22fab5..f323d76 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -32,6 +32,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_PANDORA	1	/* working with pandora */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index 4d01933..ce20c9f 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index cdf95c0..22aca38 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -38,6 +38,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index 7a8beb8..49bf72f 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -39,6 +39,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM2	1	/* working with Zoom II */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>

--
1.6.2.4

[U-Boot] [PATCH 1/3] OMAP3: Consolidate SDRC related operations

[Tom]

hvaibhav at ti.com wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> Consolidated all SDRC related functions/operations into separate
> file - sdrc.c.

Please add a long comment to explain why this is necessary.
Something like..
'Generalizing omap memory setup is necessary to support the new emif4 interface
that for am3517 uses.. '

> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Sanjeev Premi <premi@ti.com>

There is a regression.
Please check devkit8000
cpu/arm_cortexa8/omap3/libomap3.a(board.o): In function `checkboard':
.../cpu/arm_cortexa8/omap3/board.c:313: undefined reference to `is_mem_sdr'
cpu/arm_cortexa8/omap3/libomap3.a(board.o): In function `s_init':
.../cpu/arm_cortexa8/omap3/board.c:228: undefined reference to `mem_init'
cpu/arm_cortexa8/omap3/libomap3.a(mem.o): In function `mem_ok':
.../cpu/arm_cortexa8/omap3/mem.c:92: undefined reference to `get_sdr_cs_offset'
lib_arm/libarm.a(board.o):(.data+0x28): undefined reference to `dram_init'

The biggest problem with this patch is that though the comment says it is
a code movement patch, it has other changes it in.  These changes must
be separated into its own patch(s).

Because of these problems, this is only a partial review.

> ---
>  cpu/arm_cortexa8/omap3/Makefile        |    3 +
>  cpu/arm_cortexa8/omap3/board.c         |   34 +------

<snip>

>  			u32 size)
>  {
> diff --git a/cpu/arm_cortexa8/omap3/sdrc.c b/cpu/arm_cortexa8/omap3/sdrc.c
> new file mode 100644
> index 0000000..9a46155
> --- /dev/null
> +++ b/cpu/arm_cortexa8/omap3/sdrc.c
> @@ -0,0 +1,186 @@
> +/*
> + * Functions related to SDRC.
> + *
> + * This file has been created after exctracting and consolidating
> + * the SDRC related content from mem.c and board.c.
> + *
> + * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
> + *

Because this is code movement, include the original copyrights

> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +

<snip>

> +
> +	if (!mem_ok(cs))
> +		writel(0, &sdrc_base->cs[cs].mcfg);
> +}
> +
> +/**

Follow the multi-line comment.
Remove the extra '*'
This happens other places in this patch.
Fix globally

> + * dram_init - Sets uboots idea of sdram size
> + */
> +int dram_init(void)
> +{
> +	DECLARE_GLOBAL_DATA_PTR;
> +	unsigned int size0 = 0, size1 = 0;
> +
> +	size0 = get_sdr_cs_size(CS0);
> +	/*
> +	 * If a second bank of DDR is attached to CS1 this is
> +	 * where it can be started.  Early init code will init
> +	 * memory on CS0.
> +	 */
> +	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
> +		do_sdrc_init(CS1, NOT_EARLY);
> +		make_cs1_contiguous();
> +
> +		size1 = get_sdr_cs_size(CS1);

This is different that a code movement change.
The comment of the change does not match what you have done.
Split the real changes into a separate patch.

Tom

[U-Boot] [PATCH 1/3] OMAP3: Consolidate SDRC related operations

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Tom [mailto:Tom.Rix at windriver.com]
> Sent: Sunday, February 07, 2010 9:44 PM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de; Paulraj, Sandeep; Premi, Sanjeev
> Subject: Re: [PATCH 1/3] OMAP3: Consolidate SDRC related operations
> 
> hvaibhav at ti.com wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > Consolidated all SDRC related functions/operations into separate
> > file - sdrc.c.
> 
> Please add a long comment to explain why this is necessary.
> Something like..
> 'Generalizing omap memory setup is necessary to support the new
> emif4 interface
> that for am3517 uses.. '
[Hiremath, Vaibhav] Ok, will update in next version.

> 
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > Signed-off-by: Sanjeev Premi <premi@ti.com>
> 
> There is a regression.
> Please check devkit8000
> cpu/arm_cortexa8/omap3/libomap3.a(board.o): In function
> `checkboard':
> .../cpu/arm_cortexa8/omap3/board.c:313: undefined reference to
> `is_mem_sdr'
> cpu/arm_cortexa8/omap3/libomap3.a(board.o): In function `s_init':
> .../cpu/arm_cortexa8/omap3/board.c:228: undefined reference to
> `mem_init'
> cpu/arm_cortexa8/omap3/libomap3.a(mem.o): In function `mem_ok':
> .../cpu/arm_cortexa8/omap3/mem.c:92: undefined reference to
> `get_sdr_cs_offset'
> lib_arm/libarm.a(board.o):(.data+0x28): undefined reference to
> `dram_init'
> 
> The biggest problem with this patch is that though the comment says
> it is
> a code movement patch, it has other changes it in.  These changes
> must
> be separated into its own patch(s).
> 
> Because of these problems, this is only a partial review.
[Hiremath, Vaibhav] I will separate such changes into separate commit and submit it to list.

> 
> > ---
> >  cpu/arm_cortexa8/omap3/Makefile        |    3 +
> >  cpu/arm_cortexa8/omap3/board.c         |   34 +------
> 
> <snip>
> 
> >  			u32 size)
> >  {
> > diff --git a/cpu/arm_cortexa8/omap3/sdrc.c
> b/cpu/arm_cortexa8/omap3/sdrc.c
> > new file mode 100644
> > index 0000000..9a46155
> > --- /dev/null
> > +++ b/cpu/arm_cortexa8/omap3/sdrc.c
> > @@ -0,0 +1,186 @@
> > +/*
> > + * Functions related to SDRC.
> > + *
> > + * This file has been created after exctracting and consolidating
> > + * the SDRC related content from mem.c and board.c.
> > + *
> > + * Copyright (C) 2009 Texas Instruments Incorporated -
> http://www.ti.com/
> > + *
> 
> Because this is code movement, include the original copyrights
[Hiremath, Vaibhav] Ok, will update in next version.

> 
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be
> useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public
> License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> > + * MA 02111-1307 USA
> > + */
> > +
> 
> <snip>
> 
> > +
> > +	if (!mem_ok(cs))
> > +		writel(0, &sdrc_base->cs[cs].mcfg);
> > +}
> > +
> > +/**
> 
> Follow the multi-line comment.
> Remove the extra '*'
> This happens other places in this patch.
> Fix globally
[Hiremath, Vaibhav] Ok.

Thanks Tom for the review, I will update the patch series and submit it again.

Thanks,
Vaibhav

> 
> > + * dram_init - Sets uboots idea of sdram size
> > + */
> > +int dram_init(void)
> > +{
> > +	DECLARE_GLOBAL_DATA_PTR;
> > +	unsigned int size0 = 0, size1 = 0;
> > +
> > +	size0 = get_sdr_cs_size(CS0);
> > +	/*
> > +	 * If a second bank of DDR is attached to CS1 this is
> > +	 * where it can be started.  Early init code will init
> > +	 * memory on CS0.
> > +	 */
> > +	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype ==
> DDR_STACKED)) {
> > +		do_sdrc_init(CS1, NOT_EARLY);
> > +		make_cs1_contiguous();
> > +
> > +		size1 = get_sdr_cs_size(CS1);
> 
> This is different that a code movement change.
> The comment of the change does not match what you have done.
> Split the real changes into a separate patch.
> 
> Tom

[U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

The EVMS have been shipping with NAND (instead of OneNAND) as default.
So, this patch sets NAND as default.

To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the
config file omap3_evm.h,

Changes from V3 :-
	- Added undef statement for CMD_ONENAND.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 include/configs/omap3_evm.h |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 0d99f7d..1d31731 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -151,7 +151,8 @@

 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#undef CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING

@@ -306,7 +307,13 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND
+#elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_ENV_IS_IN_ONENAND	1
+#endif
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

--
1.6.2.4

[U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support

[Wolfgang Denk]

Dear hvaibhav at ti.com,

In message <1272034546-26041-2-git-send-email-hvaibhav@ti.com> you wrote:
>
> diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
> index 0d99f7d..1d31731 100644
> --- a/include/configs/omap3_evm.h
> +++ b/include/configs/omap3_evm.h
> @@ -151,7 +151,8 @@
> 
>  #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
>  #define CONFIG_CMD_MMC		/* MMC support			*/
> -#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
> +#undef CONFIG_CMD_ONENAND	/* ONENAND support		*/

Please do not #undef what is not #define'd anyway.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
What is tolerance? -- it is the consequence of humanity. We  are  all
formed  of frailty and error; let us pardon reciprocally each other's
folly -- that is the first law of nature.                  - Voltaire

[U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Thursday, May 06, 2010 1:31 AM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support
> 
> Dear hvaibhav at ti.com,
> 
> In message <1272034546-26041-2-git-send-email-hvaibhav@ti.com> you wrote:
> >
> > diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
> > index 0d99f7d..1d31731 100644
> > --- a/include/configs/omap3_evm.h
> > +++ b/include/configs/omap3_evm.h
> > @@ -151,7 +151,8 @@
> >
> >  #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
> >  #define CONFIG_CMD_MMC		/* MMC support			*/
> > -#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
> > +#undef CONFIG_CMD_ONENAND	/* ONENAND support		*/
> 
> Please do not #undef what is not #define'd anyway.
> 
[Hiremath, Vaibhav] This was the initial comment received from Nishanth Menon on very first path, and that's where I added undef line.

The initial patch was something -

> -#define CONFIG_CMD_ONENAND     /* ONENAND support              */
> +/*#define CONFIG_CMD_ONENAND*/ /* ONENAND support              */
> +#define CONFIG_CMD_NAND        /* NAND support                 */

I do agree that we don't have to undef here, but agreed to Nishant's comment only because from user point of view, if user would like to enable ONENAND support then for him it's easy he just have to comment NAND line and make change this #define. He doesn't have to dig inside code to find out whether ONENAND is supported or not.


Thanks,
Vaibhav

> 
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> What is tolerance? -- it is the consequence of humanity. We  are  all
> formed  of frailty and error; let us pardon reciprocally each other's
> folly -- that is the first law of nature.                  - Voltaire

[U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support

[Nishanth Menon]

On Thu, May 6, 2010 at 12:36 AM, Hiremath, Vaibhav <hvaibhav@ti.com> wrote:
>
>> -----Original Message-----
>> From: Wolfgang Denk [mailto:wd at denx.de]
>> Sent: Thursday, May 06, 2010 1:31 AM
>> To: Hiremath, Vaibhav
>> Cc: u-boot at lists.denx.de
>> Subject: Re: [U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support
>>
>> Dear hvaibhav at ti.com,
>>
>> In message <1272034546-26041-2-git-send-email-hvaibhav@ti.com> you wrote:
>> >
>> > diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
>> > index 0d99f7d..1d31731 100644
>> > --- a/include/configs/omap3_evm.h
>> > +++ b/include/configs/omap3_evm.h
>> > @@ -151,7 +151,8 @@
>> >
>> > ?#define CONFIG_CMD_I2C ? ? ? ? ? ? /* I2C serial bus support ? ? ? */
>> > ?#define CONFIG_CMD_MMC ? ? ? ? ? ? /* MMC support ? ? ? ? ? ? ? ? ?*/
>> > -#define CONFIG_CMD_ONENAND /* ONENAND support ? ? ? ? ? ? ?*/
>> > +#undef CONFIG_CMD_ONENAND ?/* ONENAND support ? ? ? ? ? ? ?*/
>>
>> Please do not #undef what is not #define'd anyway.
>>
> [Hiremath, Vaibhav] This was the initial comment received from Nishanth Menon on very first path, and that's where I added
> undef line.
>
> The initial patch was something -
>
>> -#define CONFIG_CMD_ONENAND ? ? /* ONENAND support ? ? ? ? ? ? ?*/
>> +/*#define CONFIG_CMD_ONENAND*/ /* ONENAND support ? ? ? ? ? ? ?*/
>> +#define CONFIG_CMD_NAND ? ? ? ?/* NAND support ? ? ? ? ? ? ? ? */
>
> I do agree that we don't have to undef here, but agreed to Nishant's comment only because from user point of view, if user would
> like to enable ONENAND support then for him it's easy he just have to comment NAND line and make change this #define. He
> doesn't have to dig inside code to find out whether ONENAND is supported or not.
my 2cents as a background:
platforms such as SDP platforms have three flash devices - nand,
onenand and nor - these are development platforms and are meant to
bootup from any of these devices based on which ever dip switch is
set. having a #undef is more elegant than /* */ and easier to use from
a developer perspective.

Regards,
Nishanth Menon

[U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support

[Wolfgang Denk]

Dear Nishanth Menon,

In message <u2h782515bb1005060340o3b366389mfdb71c240cbc7f90@mail.gmail.com> you wrote:
> On Thu, May 6, 2010 at 12:36 AM, Hiremath, Vaibhav <hvaibhav@ti.com> wrote:
...
> > I do agree that we don't have to undef here, but agreed to Nishant's comment only because from user point of view, if user would
> > like to enable ONENAND support then for him it's easy he just have to comment NAND line and make change this #define. He
> > doesn't have to dig inside code to find out whether ONENAND is supported or not.

Well, of course the user _has_ to dig into the code and check if the
feature is supported, because there is no information what the
"#undef" or the comment means - it can mean anything:

- disabled here and left in so you can easily re-add it if you like
- disabled because known to be unsupported or broken
- disabled because untested
- ...

> platforms such as SDP platforms have three flash devices - nand,
> onenand and nor - these are development platforms and are meant to
> bootup from any of these devices based on which ever dip switch is
> set. having a #undef is more elegant than /* */ and easier to use from
> a developer perspective.

Please provide one working configuration, or several config options,
but don't try to add kind of configuration menues using "#define" /
"#undef" lists. These are useless and confusing at best.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Motto of the Electrical Engineer: Working computer hardware is a  lot
like an erect penis: it stays up as long as you don't fuck with it.

[U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support

[Nishanth Menon]

On Thu, May 6, 2010 at 5:50 AM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Nishanth Menon,
>
> In message <u2h782515bb1005060340o3b366389mfdb71c240cbc7f90@mail.gmail.com> you wrote:
>> On Thu, May 6, 2010 at 12:36 AM, Hiremath, Vaibhav <hvaibhav@ti.com> wrote:
> ...
>> > I do agree that we don't have to undef here, but agreed to Nishant's comment only because from user point of view, if user would
>> > like to enable ONENAND support then for him it's easy he just have to comment NAND line and make change this #define. He
>> > doesn't have to dig inside code to find out whether ONENAND is supported or not.
>
> Well, of course the user _has_ to dig into the code and check if the
> feature is supported, because there is no information what the
> "#undef" or the comment means - it can mean anything:
>
> - disabled here and left in so you can easily re-add it if you like
> - disabled because known to be unsupported or broken
> - disabled because untested
> - ...
>
>> platforms such as SDP platforms have three flash devices - nand,
>> onenand and nor - these are development platforms and are meant to
>> bootup from any of these devices based on which ever dip switch is
>> set. having a #undef is more elegant than /* */ and easier to use from
>> a developer perspective.
>
> Please provide one working configuration, or several config options,
> but don't try to add kind of configuration menues using "#define" /
> "#undef" lists. These are useless and confusing at best.
>
your points are valid, two options as I see here:
a) build configurations - nand_boot, nor_boot etc..
b) IMHO, the better solution would be to allow the same u-boot to boot
from all devices (nand, nor, onenand, mmc) without needing a rebuild.
but the neccessity for that is to have environment variable which can
be moved around.. TI has an implementation based on an ancient u-boot
which actually does this, it will be interesting to know if there are
others who may be interested in a similar feature in mainline u-boot.

Regards,
Nishanth Menon

[U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support

[Wolfgang Denk]

Dear Nishanth Menon,

In message <j2h782515bb1005060354tc4574d80wb4a1aa3a2b40bc89@mail.gmail.com> you wrote:
>
> your points are valid, two options as I see here:
> a) build configurations - nand_boot, nor_boot etc..
> b) IMHO, the better solution would be to allow the same u-boot to boot
> from all devices (nand, nor, onenand, mmc) without needing a rebuild.

b) is clearly the better and more user-friendly solution.

> but the neccessity for that is to have environment variable which can
> be moved around.. ...

Hm... really? Assuming that all the storage devices are always
present, you can decide to use one standard location for the
environment independent of where the U-Boot image gets loaded from
(that may actually be considered an advantage by some).

>               ... TI has an implementation based on an ancient u-boot
> which actually does this, it will be interesting to know if there are
> others who may be interested in a similar feature in mainline u-boot.

Sure - please post a patch (as RFC) so we can see what you have in
mind.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Always leave room to add an explanation if it doesn't work out.

[U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support

[Nishanth Menon]

On Thu, May 6, 2010 at 6:03 AM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Nishanth Menon,
>
> In message <j2h782515bb1005060354tc4574d80wb4a1aa3a2b40bc89@mail.gmail.com> you wrote:
>>
>> your points are valid, two options as I see here:
>> a) build configurations - nand_boot, nor_boot etc..
>> b) IMHO, the better solution would be to allow the same u-boot to boot
>> from all devices (nand, nor, onenand, mmc) without needing a rebuild.
>
> b) is clearly the better and more user-friendly solution.
>
>> but the neccessity for that is to have environment variable which can
>> be moved around.. ...
>
> Hm... really? Assuming that all the storage devices are always
> present, you can decide to use one standard location for the
> environment independent of where the U-Boot image gets loaded from
> (that may actually be considered an advantage by some).
it is like
http://dev.omapzoom.org/?p=bootloader/u-boot.git;a=blob;f=board/omap3430sdp/mem.c;h=a3dad962390b35501c83f8cde1dd2fd1f6d779d6;hb=HEAD#l107

Infact in some of the settings, one of the chips might even not be mapped :(..

yes, one option could have been to use a single flash for all env (in
fact some platforms like (if i recollect beagle booting off MMC uses
NAND for env) - but is not a nice idea if the usecase is to use that
entire flash for filesystem.. so the safe option in general has been
to expect the environment to stick to the memory u-boot booted off
from..

>
>> ? ? ? ? ? ? ? ... TI has an implementation based on an ancient u-boot
>> which actually does this, it will be interesting to know if there are
>> others who may be interested in a similar feature in mainline u-boot.
>
> Sure - please post a patch (as RFC) so we can see what you have in
> mind.
Yep.. waiting for my next free cycle ;) i would have pointed as an RFC
to the git repo history, unfortunately the transition from clearcase
to git was done as a single blob :(

Regards,
Nishanth Menon

[U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support

[Wolfgang Denk]

Dear Nishanth Menon,

In message <o2q782515bb1005060411u9e53fd21idbfcf95cd5e1ea59@mail.gmail.com> you wrote:
>
> Yep.. waiting for my next free cycle ;) i would have pointed as an RFC
> to the git repo history, unfortunately the transition from clearcase
> to git was done as a single blob :(

Heh. This matches my experience - each and every contact with
ClearCase has always been a clear case of PITA :-(

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Honest error is to be pitied, not ridiculed.
                                       -- Philip Earl of Chesterfield

[U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Thursday, May 06, 2010 4:20 PM
> To: Nishanth Menon
> Cc: Hiremath, Vaibhav; u-boot at lists.denx.de
> Subject: Re: [U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support
> 
> Dear Nishanth Menon,
> 
> In message <u2h782515bb1005060340o3b366389mfdb71c240cbc7f90@mail.gmail.com>
> you wrote:
> > On Thu, May 6, 2010 at 12:36 AM, Hiremath, Vaibhav <hvaibhav@ti.com>
> wrote:
> ...
> > > I do agree that we don't have to undef here, but agreed to Nishant's
> comment only because from user point of view, if user would
> > > like to enable ONENAND support then for him it's easy he just have to
> comment NAND line and make change this #define. He
> > > doesn't have to dig inside code to find out whether ONENAND is supported
> or not.
> 
> Well, of course the user _has_ to dig into the code and check if the
> feature is supported, because there is no information what the
> "#undef" or the comment means - it can mean anything:
> 
> - disabled here and left in so you can easily re-add it if you like
> - disabled because known to be unsupported or broken
> - disabled because untested
> - ...
[Hiremath, Vaibhav] Ok. Agreed. I will remove undef line and submit the patch.

Thanks,
Vaibhav

> 
> > platforms such as SDP platforms have three flash devices - nand,
> > onenand and nor - these are development platforms and are meant to
> > bootup from any of these devices based on which ever dip switch is
> > set. having a #undef is more elegant than /* */ and easier to use from
> > a developer perspective.
> 
> Please provide one working configuration, or several config options,
> but don't try to add kind of configuration menues using "#define" /
> "#undef" lists. These are useless and confusing at best.
> 
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> Motto of the Electrical Engineer: Working computer hardware is a  lot
> like an erect penis: it stays up as long as you don't fuck with it.

[U-Boot] [RESEND:PATCH-V4] OMAP3EVM: Added NAND support

[Wolfgang Denk]

Dear "Hiremath, Vaibhav",

In message <19F8576C6E063C45BE387C64729E7394044E351B9F@dbde02.ent.ti.com> you wrote:
> 
> I do agree that we don't have to undef here, but agreed to Nishant's
> comment only because from user point of view, if user would like to
> enable ONENAND support then for him it's easy he just have to comment
> NAND line and make change this #define. He doesn't have to dig inside
> code to find out whether ONENAND is supported or not.

Hm... what makes you think we could assume that commented out code is
actually working and can be enabled as we like?  This is a highly
speculative assumption, and probably more often wrong than right.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Why can you only have two doors on a chicken coop? If it had four  it
would be a chicken sedan.

[U-Boot] [PATCH-V2 2/4] omap3: Consolidate SDRC related operations

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

Consolidated SDRC related functions into one file - sdrc.c

And also replaced sdrc_init with generic memory init
function (mem_init), this generalization of omap memory setup
is necessary to support the new emif4 interface introduced in AM3517.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    3 +
 arch/arm/cpu/arm_cortexa8/omap3/board.c     |   35 +-----
 arch/arm/cpu/arm_cortexa8/omap3/mem.c       |   90 ------------
 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c      |  202 +++++++++++++++++++++++++++
 arch/arm/cpu/arm_cortexa8/omap3/sys_info.c  |   41 ------
 arch/arm/include/asm/arch-omap3/cpu.h       |    3 +
 arch/arm/include/asm/arch-omap3/mem.h       |   13 ++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    4 +-
 include/configs/devkit8000.h                |    2 +
 include/configs/omap3_beagle.h              |    2 +
 include/configs/omap3_evm.h                 |    2 +
 include/configs/omap3_overo.h               |    2 +
 include/configs/omap3_pandora.h             |    2 +
 include/configs/omap3_sdp3430.h             |    2 +
 include/configs/omap3_zoom1.h               |    2 +
 include/configs/omap3_zoom2.h               |    2 +
 16 files changed, 240 insertions(+), 167 deletions(-)
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c

diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
index 136b163..8cc7802 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
@@ -33,6 +33,9 @@ COBJS	+= board.o
 COBJS	+= clock.o
 COBJS	+= gpio.o
 COBJS	+= mem.o
+ifdef	CONFIG_SDRC
+COBJS	+= sdrc.o
+endif
 COBJS	+= syslib.o
 COBJS	+= sys_info.o
 COBJS	+= timer.o
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/board.c b/arch/arm/cpu/arm_cortexa8/omap3/board.c
index 69a08fd..d2500ca 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/board.c
+++ b/arch/arm/cpu/arm_cortexa8/omap3/board.c
@@ -40,8 +40,6 @@

 extern omap3_sysinfo sysinfo;

-extern u32 is_mem_sdr(void);
-
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works
@@ -233,7 +231,7 @@ void s_init(void)
 	per_clocks_enable();

 	if (!in_sdram)
-		sdrc_init();
+		mem_init();
 }

 /******************************************************************************
@@ -274,37 +272,6 @@ void watchdog_init(void)
 }

 /******************************************************************************
- * Routine: dram_init
- * Description: sets uboots idea of sdram size
- *****************************************************************************/
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	unsigned int size0 = 0, size1 = 0;
-
-	size0 = get_sdr_cs_size(CS0);
-
-	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
-	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
-		do_sdrc_init(CS1, NOT_EARLY);
-		make_cs1_contiguous();
-
-		size1 = get_sdr_cs_size(CS1);
-	}
-
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = size0;
-	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
-	gd->bd->bi_dram[1].size = size1;
-
-	return 0;
-}
-
-/******************************************************************************
  * Dummy function to handle errors for EABI incompatibility
  *****************************************************************************/
 void abort(void)
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/mem.c b/arch/arm/cpu/arm_cortexa8/omap3/mem.c
index dfb7e4c..bd914b0 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/mem.c
+++ b/arch/arm/cpu/arm_cortexa8/omap3/mem.c
@@ -79,26 +79,6 @@ static const u32 gpmc_onenand[GPMC_MAX_REG] = {

 #endif

-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
-
-/**************************************************************************
- * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
- *  command line mem=xyz use all memory with out discontinuous support
- *  compiled in.  Could do it at the ATAG, but there really is two banks...
- * Called as part of 2nd phase DDR init.
- **************************************************************************/
-void make_cs1_contiguous(void)
-{
-	u32 size, a_add_low, a_add_high;
-
-	size = get_sdr_cs_size(CS0);
-	size >>= 25;	/* divide by 32 MiB to find size to offset CS1 */
-	a_add_high = (size & 3) << 8;	/* set up low field */
-	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
-	writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
-
-}
-
 /********************************************************
  *  mem_ok() - test used to see if timings are correct
  *             for a part. Helps in guessing which part
@@ -123,76 +103,6 @@ u32 mem_ok(u32 cs)
 		return 1;
 }

-/********************************************************
- *  sdrc_init() - init the sdrc chip selects CS0 and CS1
- *  - early init routines, called from flash or
- *  SRAM.
- *******************************************************/
-void sdrc_init(void)
-{
-	/* only init up first bank here */
-	do_sdrc_init(CS0, EARLY_INIT);
-}
-
-/*************************************************************************
- * do_sdrc_init(): initialize the SDRAM for use.
- *  -code sets up SDRAM basic SDRC timings for CS0
- *  -optimal settings can be placed here, or redone after i2c
- *      inspection of board info
- *
- *  - code called once in C-Stack only context for CS0 and a possible 2nd
- *      time depending on memory configuration from stack+global context
- **************************************************************************/
-
-void do_sdrc_init(u32 cs, u32 early)
-{
-	struct sdrc_actim *sdrc_actim_base;
-
-	if(cs)
-		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
-	else
-		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-
-	if (early) {
-		/* reset sdrc controller */
-		writel(SOFTRESET, &sdrc_base->sysconfig);
-		wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
-			      12000000);
-		writel(0, &sdrc_base->sysconfig);
-
-		/* setup sdrc to ball mux */
-		writel(SDRC_SHARING, &sdrc_base->sharing);
-
-		/* Disable Power Down of CKE cuz of 1 CKE on combo part */
-		writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
-				&sdrc_base->power);
-
-		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
-		sdelay(0x20000);
-	}
-
-	writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
-		RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
-		DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
-	writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
-	writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
-	writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
-
-	writel(CMD_NOP, &sdrc_base ->cs[cs].manual);
-	writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
-	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-
-	/*
-	 * CAS latency 3, Write Burst = Read Burst, Serial Mode,
-	 * Burst length = 4
-	 */
-	writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
-
-	if (!mem_ok(cs))
-		writel(0, &sdrc_base->cs[cs].mcfg);
-}
-
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size)
 {
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c b/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
new file mode 100644
index 0000000..96fd990
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c
@@ -0,0 +1,202 @@
+/*
+ * Functions related to OMAP3 SDRC.
+ *
+ * This file has been created after exctracting and consolidating
+ * the SDRC related content from mem.c and board.c, also created
+ * generic init function (mem_init).
+ *
+ * Copyright (C) 2004-2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Author :
+ *     Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Original implementation by (mem.c, board.c) :
+ *      Sunil Kumar <sunilsaini05@gmail.com>
+ *      Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *      Manikandan Pillai <mani.pillai@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+
+extern omap3_sysinfo sysinfo;
+
+static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
+
+/*
+ * is_mem_sdr -
+ *  - Return 1 if mem type in use is SDR
+ */
+u32 is_mem_sdr(void)
+{
+	if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
+		return 1;
+	return 0;
+}
+
+/*
+ * make_cs1_contiguous -
+ *  - For es2 and above remap cs1 behind cs0 to allow command line
+ *    mem=xyz use all memory with out discontinuous support compiled in.
+ *    Could do it at the ATAG, but there really is two banks...
+ *  - Called as part of 2nd phase DDR init.
+ */
+void make_cs1_contiguous(void)
+{
+	u32 size, a_add_low, a_add_high;
+
+	size = get_sdr_cs_size(CS0);
+	size >>= 25;	/* divide by 32 MiB to find size to offset CS1 */
+	a_add_high = (size & 3) << 8;	/* set up low field */
+	a_add_low = (size & 0x3C) >> 2;	/* set up high field */
+	writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
+
+}
+
+
+/*
+ * get_sdr_cs_size -
+ *  - Get size of chip select 0/1
+ */
+u32 get_sdr_cs_size(u32 cs)
+{
+	u32 size;
+
+	/* get ram size field */
+	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
+	size &= 0x3FF;		/* remove unwanted bits */
+	size <<= 21;		/* multiply by 2 MiB to find size in MB */
+	return size;
+}
+
+/*
+ * get_sdr_cs_offset -
+ *  - Get offset of cs from cs0 start
+ */
+u32 get_sdr_cs_offset(u32 cs)
+{
+	u32 offset;
+
+	if (!cs)
+		return 0;
+
+	offset = readl(&sdrc_base->cs_cfg);
+	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+
+	return offset;
+}
+
+/*
+ * do_sdrc_init -
+ *  - Initialize the SDRAM for use.
+ *  - Sets up SDRC timings for CS0
+ *  - code called once in C-Stack only context for CS0 and a possible 2nd
+ *    time depending on memory configuration from stack+global context
+ */
+void do_sdrc_init(u32 cs, u32 early)
+{
+	struct sdrc_actim *sdrc_actim_base;
+
+	if (cs)
+		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+	else
+		sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+
+	if (early) {
+		/* reset sdrc controller */
+		writel(SOFTRESET, &sdrc_base->sysconfig);
+		wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
+				12000000);
+		writel(0, &sdrc_base->sysconfig);
+
+		/* setup sdrc to ball mux */
+		writel(SDRC_SHARING, &sdrc_base->sharing);
+
+		/* Disable Power Down of CKE cuz of 1 CKE on combo part */
+		writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
+				&sdrc_base->power);
+
+		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
+		sdelay(0x20000);
+	}
+
+	writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY |
+			RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 |
+			DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg);
+	writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl);
+	writel(V_ACTIMA_165, &sdrc_actim_base->ctrla);
+	writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb);
+
+	writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+	writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+
+	/*
+	 * CAS latency 3, Write Burst = Read Burst, Serial Mode,
+	 * Burst length = 4
+	 */
+	writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr);
+
+	if (!mem_ok(cs))
+		writel(0, &sdrc_base->cs[cs].mcfg);
+}
+
+/*
+ * dram_init -
+ *  - Sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int size0 = 0, size1 = 0;
+
+	size0 = get_sdr_cs_size(CS0);
+	/*
+	 * If a second bank of DDR is attached to CS1 this is
+	 * where it can be started.  Early init code will init
+	 * memory on CS0.
+	 */
+	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
+		do_sdrc_init(CS1, NOT_EARLY);
+		make_cs1_contiguous();
+
+		size1 = get_sdr_cs_size(CS1);
+	}
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
+}
+
+/*
+ * mem_init -
+ *  - Init the sdrc chip,
+ *  - Selects CS0 and CS1,
+ */
+void mem_init(void)
+{
+	/* only init up first bank here */
+	do_sdrc_init(CS0, EARLY_INIT);
+}
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c b/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c
index 08fb32e..1df4401 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c
+++ b/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c
@@ -32,7 +32,6 @@
 #include <i2c.h>

 extern omap3_sysinfo sysinfo;
-static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
 static char *rev_s[CPU_3XX_MAX_REV] = {
 				"1.0",
@@ -104,46 +103,6 @@ u32 get_cpu_rev(void)
 	}
 }

-/****************************************************
- * is_mem_sdr() - return 1 if mem type in use is SDR
- ****************************************************/
-u32 is_mem_sdr(void)
-{
-	if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
-		return 1;
-	return 0;
-}
-
-/***********************************************************************
- * get_cs0_size() - get size of chip select 0/1
- ************************************************************************/
-u32 get_sdr_cs_size(u32 cs)
-{
-	u32 size;
-
-	/* get ram size field */
-	size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
-	size &= 0x3FF;		/* remove unwanted bits */
-	size <<= 21;		/* multiply by 2 MiB to find size in MB */
-	return size;
-}
-
-/***********************************************************************
- * get_sdr_cs_offset() - get offset of cs from cs0 start
- ************************************************************************/
-u32 get_sdr_cs_offset(u32 cs)
-{
-	u32 offset;
-
-	if (!cs)
-		return 0;
-
-	offset = readl(&sdrc_base->cs_cfg);
-	offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
-
-	return offset;
-}
-
 /***************************************************************************
  *  get_gpmc0_base() - Return current address hardware will be
  *     fetching from. The below effectively gives what is correct, its a bit
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index aa8de32..a49af10 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -183,6 +183,7 @@ struct sms {
 /* SDRC */
 #ifndef __KERNEL_STRICT_NAMES
 #ifndef __ASSEMBLY__
+#if defined(CONFIG_SDRC)
 struct sdrc_cs {
 	u32 mcfg;		/* 0x80 || 0xB0 */
 	u32 mr;			/* 0x84 || 0xB4 */
@@ -215,6 +216,8 @@ struct sdrc {
 	u8 res4[0xC];
 	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };
+
+#endif	/* CONFIG_SDRC */
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */

diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index 9439758..a78cf9f 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -270,4 +270,17 @@ enum {
 #define PISMO1_ONEN_BASE	ONENAND_MAP
 #define DBG_MPDB_BASE		DEBUG_BASE

+#ifndef __ASSEMBLY__
+
+/* Function prototypes */
+void mem_init(void);
+
+u32 is_mem_sdr(void);
+u32 mem_ok(u32 cs);
+
+u32 get_sdr_cs_size(u32);
+u32 get_sdr_cs_offset(u32);
+
+#endif	/* __ASSEMBLY__ */
+
 #endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 34bd515..34e4e0d 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -31,8 +31,10 @@ void prcm_init(void);
 void per_clocks_enable(void);

 void memif_init(void);
+#if defined(CONFIG_SDRC)
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+#endif
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);
@@ -46,8 +48,6 @@ u32 get_sysboot_value(void);
 u32 is_gpmc_muxed(void);
 u32 get_gpmc0_type(void);
 u32 get_gpmc0_width(void);
-u32 get_sdr_cs_size(u32);
-u32 get_sdr_cs_offset(u32);
 u32 is_running_in_sdram(void);
 u32 is_running_in_sram(void);
 u32 is_running_in_flash(void);
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 7d1332f..1798bc6 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -38,6 +38,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_DEVKIT8000	1	/* working with DevKit8000 */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 08d79ac..7584063 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -37,6 +37,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_BEAGLE	1	/* working with BEAGLE */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 1d31731..8c17388 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_EVM	1	/* working with EVM */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index a43500b..5ca9f3a 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -29,6 +29,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_OVERO	1	/* working with overo */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 945c053..7c62685 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -32,6 +32,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_PANDORA	1	/* working with pandora */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h
index b4919db..f751592 100644
--- a/include/configs/omap3_sdp3430.h
+++ b/include/configs/omap3_sdp3430.h
@@ -42,6 +42,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_3430SDP	1	/* working with SDP Rev2 */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index ae7ebf9..30515b0 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -38,6 +38,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM1	1	/* working with Zoom MDK Rev1 */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>

diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index c88c732..2861608 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -39,6 +39,8 @@
 #define CONFIG_OMAP3430		1	/* which is in a 3430 */
 #define CONFIG_OMAP3_ZOOM2	1	/* working with Zoom II */

+#define CONFIG_SDRC		1	/* The chip has SDRC controller */
+
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>

--
1.6.2.4

[U-Boot] [PATCH-V2 2/4] omap3: Consolidate SDRC related operations

[Wolfgang Denk]

Dear hvaibhav at ti.com,

In message <1272034546-26041-4-git-send-email-hvaibhav@ti.com> you wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> Consolidated SDRC related functions into one file - sdrc.c
> 
> And also replaced sdrc_init with generic memory init
> function (mem_init), this generalization of omap memory setup
> is necessary to support the new emif4 interface introduced in AM3517.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Sanjeev Premi <premi@ti.com>

> diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> index 136b163..8cc7802 100644
> --- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> +++ b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> @@ -33,6 +33,9 @@ COBJS	+= board.o
>  COBJS	+= clock.o
>  COBJS	+= gpio.o
>  COBJS	+= mem.o
> +ifdef	CONFIG_SDRC
> +COBJS	+= sdrc.o
> +endif

Please don't use 'ifdef" here; instead, use `COBJS-$(CONFIG_SDRC)' 

> diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
> index aa8de32..a49af10 100644
> --- a/arch/arm/include/asm/arch-omap3/cpu.h
> +++ b/arch/arm/include/asm/arch-omap3/cpu.h
> @@ -183,6 +183,7 @@ struct sms {
>  /* SDRC */
>  #ifndef __KERNEL_STRICT_NAMES
>  #ifndef __ASSEMBLY__
> +#if defined(CONFIG_SDRC)
>  struct sdrc_cs {
>  	u32 mcfg;		/* 0x80 || 0xB0 */
>  	u32 mr;			/* 0x84 || 0xB4 */
> @@ -215,6 +216,8 @@ struct sdrc {
>  	u8 res4[0xC];
>  	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
>  };
> +
> +#endif	/* CONFIG_SDRC */

I don't like such a #ifdef here - it is absolutely necessary? Why?

> diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
> index 34bd515..34e4e0d 100644
> --- a/arch/arm/include/asm/arch-omap3/sys_proto.h
> +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
> @@ -31,8 +31,10 @@ void prcm_init(void);
>  void per_clocks_enable(void);
> 
>  void memif_init(void);
> +#if defined(CONFIG_SDRC)
>  void sdrc_init(void);
>  void do_sdrc_init(u32, u32);
> +#endif

Ditto - please drop this #ifdef.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
People seldom know what they want until you give them what  they  ask
for.

[U-Boot] [PATCH-V2 2/4] omap3: Consolidate SDRC related operations

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Thursday, May 06, 2010 1:38 AM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH-V2 2/4] omap3: Consolidate SDRC related
> operations
> 
> Dear hvaibhav at ti.com,
> 
[Hiremath, Vaibhav] Thanks Denk for your comments, see my response below -

> In message <1272034546-26041-4-git-send-email-hvaibhav@ti.com> you wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > Consolidated SDRC related functions into one file - sdrc.c
> >
> > And also replaced sdrc_init with generic memory init
> > function (mem_init), this generalization of omap memory setup
> > is necessary to support the new emif4 interface introduced in AM3517.
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > Signed-off-by: Sanjeev Premi <premi@ti.com>
> 
> > diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> > index 136b163..8cc7802 100644
> > --- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> > +++ b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> > @@ -33,6 +33,9 @@ COBJS	+= board.o
> >  COBJS	+= clock.o
> >  COBJS	+= gpio.o
> >  COBJS	+= mem.o
> > +ifdef	CONFIG_SDRC
> > +COBJS	+= sdrc.o
> > +endif
> 
> Please don't use 'ifdef" here; instead, use `COBJS-$(CONFIG_SDRC)'
[Hiremath, Vaibhav] ok, will incorporate in next version.


> 
> > diff --git a/arch/arm/include/asm/arch-omap3/cpu.h
> b/arch/arm/include/asm/arch-omap3/cpu.h
> > index aa8de32..a49af10 100644
> > --- a/arch/arm/include/asm/arch-omap3/cpu.h
> > +++ b/arch/arm/include/asm/arch-omap3/cpu.h
> > @@ -183,6 +183,7 @@ struct sms {
> >  /* SDRC */
> >  #ifndef __KERNEL_STRICT_NAMES
> >  #ifndef __ASSEMBLY__
> > +#if defined(CONFIG_SDRC)
> >  struct sdrc_cs {
> >  	u32 mcfg;		/* 0x80 || 0xB0 */
> >  	u32 mr;			/* 0x84 || 0xB4 */
> > @@ -215,6 +216,8 @@ struct sdrc {
> >  	u8 res4[0xC];
> >  	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
> >  };
> > +
> > +#endif	/* CONFIG_SDRC */
> 
> I don't like such a #ifdef here - it is absolutely necessary? Why?
> 
[Hiremath, Vaibhav] Denk,

This is common file being used for all OMAP series of devices (OMAP2, OMAP3 and AM35x family) and OMAP2/3 family supports SDRC controller and AM35x family support EMIF4.

And due to this difference we need to add this #ifdef.

> > diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h
> b/arch/arm/include/asm/arch-omap3/sys_proto.h
> > index 34bd515..34e4e0d 100644
> > --- a/arch/arm/include/asm/arch-omap3/sys_proto.h
> > +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
> > @@ -31,8 +31,10 @@ void prcm_init(void);
> >  void per_clocks_enable(void);
> >
> >  void memif_init(void);
> > +#if defined(CONFIG_SDRC)
> >  void sdrc_init(void);
> >  void do_sdrc_init(u32, u32);
> > +#endif
> 
> Ditto - please drop this #ifdef.
> 
[Hiremath, Vaibhav] Same as above.

Thanks,
Vaibhav

> 
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> People seldom know what they want until you give them what  they  ask
> for.

[U-Boot] [PATCH-V2 2/4] omap3: Consolidate SDRC related operations

[Wolfgang Denk]

Dear "Hiremath, Vaibhav",

In message <19F8576C6E063C45BE387C64729E7394044E351BE0@dbde02.ent.ti.com> you wrote:
> 
> > > diff --git a/arch/arm/include/asm/arch-omap3/cpu.h
> > b/arch/arm/include/asm/arch-omap3/cpu.h
> > > index aa8de32..a49af10 100644
> > > --- a/arch/arm/include/asm/arch-omap3/cpu.h
> > > +++ b/arch/arm/include/asm/arch-omap3/cpu.h
> > > @@ -183,6 +183,7 @@ struct sms {
> > >  /* SDRC */
> > >  #ifndef __KERNEL_STRICT_NAMES
> > >  #ifndef __ASSEMBLY__
> > > +#if defined(CONFIG_SDRC)
> > >  struct sdrc_cs {
> > >  	u32 mcfg;		/* 0x80 || 0xB0 */
> > >  	u32 mr;			/* 0x84 || 0xB4 */
> > > @@ -215,6 +216,8 @@ struct sdrc {
> > >  	u8 res4[0xC];
> > >  	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
> > >  };
> > > +
> > > +#endif	/* CONFIG_SDRC */
> > 
> > I don't like such a #ifdef here - it is absolutely necessary? Why?
> > 
> [Hiremath, Vaibhav] Denk,
> 
> This is common file being used for all OMAP series of devices (OMAP2, OMAP3
>  and AM35x family) and OMAP2/3 family supports SDRC controller and AM35x fa
> mily support EMIF4.
> 
> And due to this difference we need to add this #ifdef.

No. If different CPU fmilies need different versions of this struct
then they should use separate header files for these.

> > > diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h
> > b/arch/arm/include/asm/arch-omap3/sys_proto.h
> > > index 34bd515..34e4e0d 100644
> > > --- a/arch/arm/include/asm/arch-omap3/sys_proto.h
> > > +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
> > > @@ -31,8 +31,10 @@ void prcm_init(void);
> > >  void per_clocks_enable(void);
> > >
> > >  void memif_init(void);
> > > +#if defined(CONFIG_SDRC)
> > >  void sdrc_init(void);
> > >  void do_sdrc_init(u32, u32);
> > > +#endif
> > 
> > Ditto - please drop this #ifdef.
> > 
> [Hiremath, Vaibhav] Same as above.

Even less so here. The prototypes should not do any harm - just remove
the #if/#endif

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Ahead warp factor 1"                                  - Captain Kirk

[U-Boot] [PATCH-V2 3/4] AM35x: Add support for AM3517EVM

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

This patch adds basic support for the AM3517EVM.
It includes:
	- Board int file (.c and .h)
	- Default configuration file
	- Updates for Makefile

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 Makefile                              |    3 +
 arch/arm/include/asm/arch-omap3/mux.h |   36 +++
 board/logicpd/am3517evm/Makefile      |   47 ++++
 board/logicpd/am3517evm/am3517evm.c   |   76 ++++++
 board/logicpd/am3517evm/am3517evm.h   |  405 +++++++++++++++++++++++++++++++++
 board/logicpd/am3517evm/config.mk     |   30 +++
 include/configs/am3517_evm.h          |  297 ++++++++++++++++++++++++
 7 files changed, 894 insertions(+), 0 deletions(-)
 create mode 100644 board/logicpd/am3517evm/Makefile
 create mode 100644 board/logicpd/am3517evm/am3517evm.c
 create mode 100644 board/logicpd/am3517evm/am3517evm.h
 create mode 100644 board/logicpd/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h

diff --git a/Makefile b/Makefile
index 34f10ce..487ae73 100644
--- a/Makefile
+++ b/Makefile
@@ -3169,6 +3169,9 @@ omap3_zoom1_config :	unconfig
 omap3_zoom2_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3

+am3517_evm_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3
+
 smdkc100_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx

diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
index 0c01c73..8ea47b6 100644
--- a/arch/arm/include/asm/arch-omap3/mux.h
+++ b/arch/arm/include/asm/arch-omap3/mux.h
@@ -283,6 +283,7 @@
 /*Control and debug */
 #define CONTROL_PADCONF_SYS_32K		0x0A04
 #define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
+#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
 #define CONTROL_PADCONF_SYS_NIRQ	0x01E0
 #define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
 #define CONTROL_PADCONF_SYS_BOOT1	0x0A0C
@@ -403,6 +404,41 @@
 #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
 #define CONTROL_PADCONF_SDRC_CKE0	0x0262
 #define CONTROL_PADCONF_SDRC_CKE1	0x0264
+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
+#define CONTROL_PADCONF_CCDC_HD		0x01E8
+#define CONTROL_PADCONF_CCDC_VD		0x01EA
+#define CONTROL_PADCONF_CCDC_WEN	0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0	0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1	0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2	0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3	0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4	0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5	0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6	0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7	0x01FC
+#define CONTROL_PADCONF_RMII_MDIO_DATA	0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK	0x0200
+#define CONTROL_PADCONF_RMII_RXD0	0x0202
+#define CONTROL_PADCONF_RMII_RXD1	0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV	0x0206
+#define CONTROL_PADCONF_RMII_RXER	0x0208
+#define CONTROL_PADCONF_RMII_TXD0	0x020A
+#define CONTROL_PADCONF_RMII_TXD1	0x020C
+#define CONTROL_PADCONF_RMII_TXEN	0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK	0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS	0x0212
+#define CONTROL_PADCONF_HECC1_TXD	0x0214
+#define CONTROL_PADCONF_HECC1_RXD	0x0216
+#define CONTROL_PADCONF_SYS_BOOT7	0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N	0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N	0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N	0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N	0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0	0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1	0x0224
+#define CONTROL_PADCONF_SYS_BOOT8	0x0226

 #define MUX_VAL(OFFSET,VALUE)\
 	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile
new file mode 100644
index 0000000..3c71fef
--- /dev/null
+++ b/board/logicpd/am3517evm/Makefile
@@ -0,0 +1,47 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Based on ti/evm/Makefile
+#
+# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= am3517evm.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
new file mode 100644
index 0000000..2b912a9
--- /dev/null
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -0,0 +1,76 @@
+/*
+ * am3517evm.c - board file for TI's AM3517 family of devices.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include "am3517evm.h"
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init i2c, ethernet, etc... (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_AM3517EVM();
+}
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h
new file mode 100644
index 0000000..68d746c
--- /dev/null
+++ b/board/logicpd/am3517evm/am3517evm.h
@@ -0,0 +1,405 @@
+/*
+ * am3517evm.h - Header file for the AM3517 EVM.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.h
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _AM3517EVM_H_
+#define _AM3517EVM_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"AM3517EVM Board",
+	"NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_AM3517EVM() \
+	/* SDRC */\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
+	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
+	/*sdrc_strben_dly0*/\
+	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
+	 /*sdrc_strben_dly1*/\
+	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
+	/* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+							 /* - ETH_nRESET*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) \
+	/* DSS */\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
+	/* CAMERA */\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+							 /* - CAM_RESET*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) \
+	/* MMC */\
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
+	/* WriteProtect */\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) /*CardDetect*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
+	\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTD | DIS | M0)) \
+	/* McBSP */\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+							 /* - LCD_INI*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+							 /* - LCD_ENVDD */\
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+							 /* - LCD_QVGA/nVGA */\
+	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+							 /* - LCD_RESB */\
+	/* UART */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
+	/* I2C */\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
+	/* McSPI */\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
+							 /* - LAN_INTR*/\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M4)) \
+	/* CCDC */\
+	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M0)) \
+	/* RMII */\
+	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
+	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
+	MUX_VAL(CP(RMII_RXD0)	,	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
+	/* HECC */\
+	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTU | EN  | M0)) \
+	/* HSUSB */\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
+	/* HDQ */\
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) \
+	/* Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
+	/*SYS_nRESWARM */\
+	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | DIS | M4)) \
+							/* - GPIO30 */\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+							 /* - PEN_IRQ */\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+							 /* - VIO_1V8*/\
+	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
+	/* JTAG */\
+	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) \
+	/* ETK (ES2 onwards) */\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0)) \
+	/* Die to Die */\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+
+#endif
diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk
new file mode 100644
index 0000000..f7a35ce
--- /dev/null
+++ b/board/logicpd/am3517evm/config.mk
@@ -0,0 +1,30 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Based on ti/evm/config.mk
+#
+# Copyright (C) 2010
+# Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
new file mode 100644
index 0000000..115bd0f
--- /dev/null
+++ b/include/configs/am3517_evm.h
@@ -0,0 +1,297 @@
+/*
+ * am3517_evm.h - Default configuration for AM3517 EVM board.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on omap3_evm_config.h
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */
+
+#define CONFIG_EMIF4		1	/* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ				/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+/*
+ * DDR related
+ */
+#define CONFIG_OMAP3_MICRON_DDR		1	/* Micron DDR */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 on AM3517 EVM */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+#undef CONFIG_CMD_NET
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_BOOTFILE		uImage
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc init; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT			"AM3517_EVM # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor@start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			boot_flash_env_addr
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#ifndef __ASSEMBLY__
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */
+
--
1.6.2.4

[U-Boot] [PATCH-V2 3/4] AM35x: Add support for AM3517EVM

[Wolfgang Denk]

Dear hvaibhav at ti.com,

In message <1272034546-26041-5-git-send-email-hvaibhav@ti.com> you wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> This patch adds basic support for the AM3517EVM.
> It includes:
> 	- Board int file (.c and .h)
> 	- Default configuration file
> 	- Updates for Makefile
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Sanjeev Premi <premi@ti.com>
> ---
>  Makefile                              |    3 +
>  arch/arm/include/asm/arch-omap3/mux.h |   36 +++
>  board/logicpd/am3517evm/Makefile      |   47 ++++
>  board/logicpd/am3517evm/am3517evm.c   |   76 ++++++
>  board/logicpd/am3517evm/am3517evm.h   |  405 +++++++++++++++++++++++++++++++++
>  board/logicpd/am3517evm/config.mk     |   30 +++
>  include/configs/am3517_evm.h          |  297 ++++++++++++++++++++++++
>  7 files changed, 894 insertions(+), 0 deletions(-)
>  create mode 100644 board/logicpd/am3517evm/Makefile
>  create mode 100644 board/logicpd/am3517evm/am3517evm.c
>  create mode 100644 board/logicpd/am3517evm/am3517evm.h
>  create mode 100644 board/logicpd/am3517evm/config.mk
>  create mode 100644 include/configs/am3517_evm.h

Entries to MAKEALL and MAINTAINERS missing.

> diff --git a/Makefile b/Makefile
> index 34f10ce..487ae73 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -3169,6 +3169,9 @@ omap3_zoom1_config :	unconfig
>  omap3_zoom2_config :	unconfig
>  	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
> 
> +am3517_evm_config :	unconfig
> +	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3
> +
>  smdkc100_config:	unconfig
>  	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx

Please keep list sorted.

> diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
> index 0c01c73..8ea47b6 100644
> --- a/arch/arm/include/asm/arch-omap3/mux.h
> +++ b/arch/arm/include/asm/arch-omap3/mux.h
> @@ -283,6 +283,7 @@
>  /*Control and debug */
>  #define CONTROL_PADCONF_SYS_32K		0x0A04
>  #define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
> +#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
>  #define CONTROL_PADCONF_SYS_NIRQ	0x01E0
>  #define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
>  #define CONTROL_PADCONF_SYS_BOOT1	0x0A0C

CONTROL_PADCONF_SYS_NIRQ looks out of place here. And all this asks
to be converted into a proper C struct.

> diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile
> new file mode 100644
> index 0000000..3c71fef
> --- /dev/null
> +++ b/board/logicpd/am3517evm/Makefile
...
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +

Don't add trailing empty lines. [Please check & fix globally.]


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Any sufficiently advanced technology is indistinguishable from magic.
Clarke's Third Law       - _Profiles of the Future_ (1962; rev. 1973)
                  ``Hazards of Prophecy: The Failure of Imagination''

[U-Boot] [PATCH-V2 3/4] AM35x: Add support for AM3517EVM

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Thursday, May 06, 2010 1:42 AM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH-V2 3/4] AM35x: Add support for AM3517EVM
> 
> Dear hvaibhav at ti.com,
> 
> In message <1272034546-26041-5-git-send-email-hvaibhav@ti.com> you wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > This patch adds basic support for the AM3517EVM.
> > It includes:
> > 	- Board int file (.c and .h)
> > 	- Default configuration file
> > 	- Updates for Makefile
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > Signed-off-by: Sanjeev Premi <premi@ti.com>
> > ---
> >  Makefile                              |    3 +
> >  arch/arm/include/asm/arch-omap3/mux.h |   36 +++
> >  board/logicpd/am3517evm/Makefile      |   47 ++++
> >  board/logicpd/am3517evm/am3517evm.c   |   76 ++++++
> >  board/logicpd/am3517evm/am3517evm.h   |  405
> +++++++++++++++++++++++++++++++++
> >  board/logicpd/am3517evm/config.mk     |   30 +++
> >  include/configs/am3517_evm.h          |  297 ++++++++++++++++++++++++
> >  7 files changed, 894 insertions(+), 0 deletions(-)
> >  create mode 100644 board/logicpd/am3517evm/Makefile
> >  create mode 100644 board/logicpd/am3517evm/am3517evm.c
> >  create mode 100644 board/logicpd/am3517evm/am3517evm.h
> >  create mode 100644 board/logicpd/am3517evm/config.mk
> >  create mode 100644 include/configs/am3517_evm.h
> 
> Entries to MAKEALL and MAINTAINERS missing.
[Hiremath, Vaibhav] Ok, will add this in next version.

> 
> > diff --git a/Makefile b/Makefile
> > index 34f10ce..487ae73 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -3169,6 +3169,9 @@ omap3_zoom1_config :	unconfig
> >  omap3_zoom2_config :	unconfig
> >  	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
> >
> > +am3517_evm_config :	unconfig
> > +	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3
> > +
> >  smdkc100_config:	unconfig
> >  	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx
> 
> Please keep list sorted.
> 
[Hiremath, Vaibhav] ok, will move up.

> > diff --git a/arch/arm/include/asm/arch-omap3/mux.h
> b/arch/arm/include/asm/arch-omap3/mux.h
> > index 0c01c73..8ea47b6 100644
> > --- a/arch/arm/include/asm/arch-omap3/mux.h
> > +++ b/arch/arm/include/asm/arch-omap3/mux.h
> > @@ -283,6 +283,7 @@
> >  /*Control and debug */
> >  #define CONTROL_PADCONF_SYS_32K		0x0A04
> >  #define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
> > +#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
> >  #define CONTROL_PADCONF_SYS_NIRQ	0x01E0
> >  #define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
> >  #define CONTROL_PADCONF_SYS_BOOT1	0x0A0C
> 
> CONTROL_PADCONF_SYS_NIRQ looks out of place here. 
[Hiremath, Vaibhav] ok I will place it appropriately.

> And all this asks
> to be converted into a proper C struct.
[Hiremath, Vaibhav] This is following up the existing way of configuration like all other OMAP devices. I do agree that we need to clean this up.

Can it be done in sub-sequent series of patches on top of this? Let AM3517EVm support goes in. What's your opinion on this?

> 
> > diff --git a/board/logicpd/am3517evm/Makefile
> b/board/logicpd/am3517evm/Makefile
> > new file mode 100644
> > index 0000000..3c71fef
> > --- /dev/null
> > +++ b/board/logicpd/am3517evm/Makefile
> ...
> > +include $(SRCTREE)/rules.mk
> > +
> > +sinclude $(obj).depend
> > +
> 
> Don't add trailing empty lines. [Please check & fix globally.]
> 
[Hiremath, Vaibhav] Ok, I will cross-check and will fix in next version.

Thanks,
Vaibhav

> 
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> Any sufficiently advanced technology is indistinguishable from magic.
> Clarke's Third Law       - _Profiles of the Future_ (1962; rev. 1973)
>                   ``Hazards of Prophecy: The Failure of Imagination''

[U-Boot] [PATCH-V2 3/4] AM35x: Add support for AM3517EVM

[Wolfgang Denk]

Dear "Hiremath, Vaibhav",

In message <19F8576C6E063C45BE387C64729E7394044E351BE4@dbde02.ent.ti.com> you wrote:
> 
...
> > > --- a/arch/arm/include/asm/arch-omap3/mux.h
> > > +++ b/arch/arm/include/asm/arch-omap3/mux.h
...
> > And all this asks
> > to be converted into a proper C struct.
> [Hiremath, Vaibhav] This is following up the existing way of configuration
> like all other OMAP devices. I do agree that we need to clean this up.
> 
> Can it be done in sub-sequent series of patches on top of this? Let AM3517E
> Vm support goes in. What's your opinion on this?

Agreed.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It would seem that evil retreats when forcibly confronted
	-- Yarnek of Excalbia, "The Savage Curtain", stardate 5906.5

[U-Boot] [PATCH-V2 4/4] AM35x: Add support for EMIF4

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

This patch adds support for the EMIF4 interface
available in the AM35x processors.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    3 +
 arch/arm/cpu/arm_cortexa8/omap3/emif4.c     |  168 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/cpu.h       |   24 ++++
 arch/arm/include/asm/arch-omap3/emif4.h     |   79 +++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    3 +
 5 files changed, 277 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/emif4.c
 create mode 100644 arch/arm/include/asm/arch-omap3/emif4.h

diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
index 8cc7802..0a23fa5 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
@@ -36,6 +36,9 @@ COBJS	+= mem.o
 ifdef	CONFIG_SDRC
 COBJS	+= sdrc.o
 endif
+ifdef	CONFIG_EMIF4
+COBJS	+= emif4.o
+endif
 COBJS	+= syslib.o
 COBJS	+= sys_info.o
 COBJS	+= timer.o
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/emif4.c b/arch/arm/cpu/arm_cortexa8/omap3/emif4.c
new file mode 100644
index 0000000..749a394
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/omap3/emif4.c
@@ -0,0 +1,168 @@
+/*
+ * Author :
+ *     Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on mem.c and sdrc.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/emif4.h>
+
+extern omap3_sysinfo sysinfo;
+
+static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
+
+/*
+ * is_mem_sdr -
+ *  - Return 1 if mem type in use is SDR
+ */
+u32 is_mem_sdr(void)
+{
+	return 0;
+}
+
+/*
+ * get_sdr_cs_size -
+ *  - Get size of chip select 0/1
+ */
+u32 get_sdr_cs_size(u32 cs)
+{
+	u32 size;
+
+	/* TODO: Calculate the size based on EMIF4 configuration */
+	size = CONFIG_SYS_CS0_SIZE;
+
+	return size;
+}
+
+/*
+ * get_sdr_cs_offset -
+ *  - Get offset of cs from cs0 start
+ */
+u32 get_sdr_cs_offset(u32 cs)
+{
+	u32 offset = 0;
+
+	return offset;
+}
+
+/*
+ * do_emif4_init -
+ *  - Init the emif4 module for DDR access
+ *  - Early init routines, called from flash or SRAM.
+ */
+void do_emif4_init(void)
+{
+	unsigned int regval;
+	/* Set the DDR PHY parameters in PHY ctrl registers */
+	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
+		EMIF4_DDR1_EXT_STRB_DIS);
+	writel(regval, &emif4_base->ddr_phyctrl1);
+	writel(regval, &emif4_base->ddr_phyctrl1_shdw);
+	writel(0, &emif4_base->ddr_phyctrl2);
+
+	/* Reset the DDR PHY and wait till completed */
+	regval = readl(&emif4_base->sdram_iodft_tlgc);
+	regval |= (1<<10);
+	writel(regval, &emif4_base->sdram_iodft_tlgc);
+	/*Wait till that bit clears*/
+	while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
+	/*Re-verify the DDR PHY status*/
+	while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
+
+	regval |= (1<<0);
+	writel(regval, &emif4_base->sdram_iodft_tlgc);
+	/* Set SDR timing registers */
+	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
+		EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
+		EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
+		EMIF4_TIM1_T_RP);
+	writel(regval, &emif4_base->sdram_time1);
+	writel(regval, &emif4_base->sdram_time1_shdw);
+
+	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
+		EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
+		EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
+	writel(regval, &emif4_base->sdram_time2);
+	writel(regval, &emif4_base->sdram_time2_shdw);
+
+	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
+	writel(regval, &emif4_base->sdram_time3);
+	writel(regval, &emif4_base->sdram_time3_shdw);
+
+	/* Set the PWR control register */
+	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
+		EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
+	writel(regval, &emif4_base->sdram_pwr_mgmt);
+	writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
+
+	/* Set the DDR refresh rate control register */
+	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
+	writel(regval, &emif4_base->sdram_refresh_ctrl);
+	writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
+
+	/* set the SDRAM configuration register */
+	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
+		EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
+		EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
+		EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
+		EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
+		EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
+	writel(regval, &emif4_base->sdram_config);
+}
+
+/*
+ * dram_init -
+ *  - Sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int size0 = 0, size1 = 0;
+
+	size0 = get_sdr_cs_size(CS0);
+	/*
+	 * If a second bank of DDR is attached to CS1 this is
+	 * where it can be started.  Early init code will init
+	 * memory on CS0.
+	 */
+	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
+		size1 = get_sdr_cs_size(CS1);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
+}
+
+/*
+ * mem_init() -
+ *  - Initialize memory subsystem
+ */
+void mem_init(void)
+{
+	do_emif4_init();
+}
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index a49af10..25668bd 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -217,6 +217,30 @@ struct sdrc {
 	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };

+#elif defined(CONFIG_EMIF4)
+/* EMIF4 */
+typedef struct emif4 {
+	unsigned int sdram_sts;
+	unsigned int sdram_config;
+	unsigned int res1;
+	unsigned int sdram_refresh_ctrl;
+	unsigned int sdram_refresh_ctrl_shdw;
+	unsigned int sdram_time1;
+	unsigned int sdram_time1_shdw;
+	unsigned int sdram_time2;
+	unsigned int sdram_time2_shdw;
+	unsigned int sdram_time3;
+	unsigned int sdram_time3_shdw;
+	unsigned char res2[8];
+	unsigned int sdram_pwr_mgmt;
+	unsigned int sdram_pwr_mgmt_shdw;
+	unsigned char res3[32];
+	unsigned int sdram_iodft_tlgc;
+	unsigned char res4[128];
+	unsigned int ddr_phyctrl1;
+	unsigned int ddr_phyctrl1_shdw;
+	unsigned int ddr_phyctrl2;
+} emif4_t;
 #endif	/* CONFIG_SDRC */
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
diff --git a/arch/arm/include/asm/arch-omap3/emif4.h b/arch/arm/include/asm/arch-omap3/emif4.h
new file mode 100644
index 0000000..579da0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/emif4.h
@@ -0,0 +1,79 @@
+/*
+ * Auther:
+ *       Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+
+/*
+ * Configuration values
+ */
+#define EMIF4_TIM1_T_RP		(0x3 << 25)
+#define EMIF4_TIM1_T_RCD	(0x3 << 21)
+#define EMIF4_TIM1_T_WR		(0x3 << 17)
+#define EMIF4_TIM1_T_RAS	(0x8 << 12)
+#define EMIF4_TIM1_T_RC		(0xA << 6)
+#define EMIF4_TIM1_T_RRD	(0x2 << 3)
+#define EMIF4_TIM1_T_WTR	(0x2)
+
+#define EMIF4_TIM2_T_XP		(0x2 << 28)
+#define EMIF4_TIM2_T_ODT	(0x0 << 25)
+#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
+#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
+#define EMIF4_TIM2_T_RTP	(0x1 << 3)
+#define EMIF4_TIM2_T_CKE	(0x2)
+
+#define EMIF4_TIM3_T_RFC	(0x25 << 4)
+#define EMIF4_TIM3_T_RAS_MAX	(0x7)
+
+#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
+#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
+#define EMIF4_PWR_DPD_EN	(0x1 << 10)
+#define EMIF4_PWR_LP_MODE	(0x0 << 8)
+#define EMIF4_PWR_PM_TIM	(0x0)
+
+#define EMIF4_INITREF_DIS	(0x0 << 31)
+#define EMIF4_REFRESH_RATE	(0x50F)
+
+#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
+#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
+#define EMIF4_CFG_DDR_TERM	(0x0 << 24)
+#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
+#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
+#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
+#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
+#define EMIF4_CFG_CL		(0x5 << 10)
+#define EMIF4_CFG_ROWSIZE	(0x0 << 7)
+#define EMIF4_CFG_IBANK		(0x3 << 4)
+#define EMIF4_CFG_EBANK		(0x0 << 3)
+#define EMIF4_CFG_PGSIZE	(0x2)
+
+/*
+ * EMIF4 PHY Control 1 register configuration
+ */
+#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
+#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
+#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
+#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
+#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
+
+#endif /* endif _EMIF_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 34e4e0d..7b425be 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -35,6 +35,9 @@ void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
 #endif
+#if defined(CONFIG_EMIF4)
+void emif4_init(void);
+#endif
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);
--
1.6.2.4

[U-Boot] [PATCH-V2 4/4] AM35x: Add support for EMIF4

[Wolfgang Denk]

Dear hvaibhav at ti.com,

In message <1272034546-26041-6-git-send-email-hvaibhav@ti.com> you wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> This patch adds support for the EMIF4 interface
> available in the AM35x processors.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Sanjeev Premi <premi@ti.com>
> ---
>  arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    3 +
>  arch/arm/cpu/arm_cortexa8/omap3/emif4.c     |  168 +++++++++++++++++++++++++++
>  arch/arm/include/asm/arch-omap3/cpu.h       |   24 ++++
>  arch/arm/include/asm/arch-omap3/emif4.h     |   79 +++++++++++++
>  arch/arm/include/asm/arch-omap3/sys_proto.h |    3 +
>  5 files changed, 277 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/emif4.c
>  create mode 100644 arch/arm/include/asm/arch-omap3/emif4.h
> 
> diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> index 8cc7802..0a23fa5 100644
> --- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> +++ b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> @@ -36,6 +36,9 @@ COBJS	+= mem.o
>  ifdef	CONFIG_SDRC
>  COBJS	+= sdrc.o
>  endif
> +ifdef	CONFIG_EMIF4
> +COBJS	+= emif4.o
> +endif

Don't use ifdef, use COBJS-$(CONFIG_EMIF4) instead.

> diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
> index 34e4e0d..7b425be 100644
> --- a/arch/arm/include/asm/arch-omap3/sys_proto.h
> +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
> @@ -35,6 +35,9 @@ void memif_init(void);
>  void sdrc_init(void);
>  void do_sdrc_init(u32, u32);
>  #endif
> +#if defined(CONFIG_EMIF4)
> +void emif4_init(void);
> +#endif

I guess you can omit the #ifdef here, right?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
A failure will not appear until a unit has passed final inspection.

[U-Boot] [PATCH-V2 4/4] AM35x: Add support for EMIF4

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Thursday, May 06, 2010 1:44 AM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH-V2 4/4] AM35x: Add support for EMIF4
> 
> Dear hvaibhav at ti.com,
> 
> In message <1272034546-26041-6-git-send-email-hvaibhav@ti.com> you wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > This patch adds support for the EMIF4 interface
> > available in the AM35x processors.
> >
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > Signed-off-by: Sanjeev Premi <premi@ti.com>
> > ---
> >  arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    3 +
> >  arch/arm/cpu/arm_cortexa8/omap3/emif4.c     |  168
> +++++++++++++++++++++++++++
> >  arch/arm/include/asm/arch-omap3/cpu.h       |   24 ++++
> >  arch/arm/include/asm/arch-omap3/emif4.h     |   79 +++++++++++++
> >  arch/arm/include/asm/arch-omap3/sys_proto.h |    3 +
> >  5 files changed, 277 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/emif4.c
> >  create mode 100644 arch/arm/include/asm/arch-omap3/emif4.h
> >
> > diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> > index 8cc7802..0a23fa5 100644
> > --- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> > +++ b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> > @@ -36,6 +36,9 @@ COBJS	+= mem.o
> >  ifdef	CONFIG_SDRC
> >  COBJS	+= sdrc.o
> >  endif
> > +ifdef	CONFIG_EMIF4
> > +COBJS	+= emif4.o
> > +endif
> 
> Don't use ifdef, use COBJS-$(CONFIG_EMIF4) instead.
> 
> > diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h
> b/arch/arm/include/asm/arch-omap3/sys_proto.h
> > index 34e4e0d..7b425be 100644
> > --- a/arch/arm/include/asm/arch-omap3/sys_proto.h
> > +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
> > @@ -35,6 +35,9 @@ void memif_init(void);
> >  void sdrc_init(void);
> >  void do_sdrc_init(u32, u32);
> >  #endif
> > +#if defined(CONFIG_EMIF4)
> > +void emif4_init(void);
> > +#endif
> 
> I guess you can omit the #ifdef here, right?
> 
[Hiremath, Vaibhav] Denk,

We have OMAP families supporting both SDRC and EMIF4 (obviously mutually exclusive), so we need to add this #ifdef.

Thanks,
Vaibhav

> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> A failure will not appear until a unit has passed final inspection.

[U-Boot] [PATCH-V2 4/4] AM35x: Add support for EMIF4

[Wolfgang Denk]

Dear "Hiremath, Vaibhav",

In message <19F8576C6E063C45BE387C64729E7394044E351BE7@dbde02.ent.ti.com> you wrote:
> 
> > >  void sdrc_init(void);
> > >  void do_sdrc_init(u32, u32);
> > >  #endif
> > > +#if defined(CONFIG_EMIF4)
> > > +void emif4_init(void);
> > > +#endif
> > 
> > I guess you can omit the #ifdef here, right?
> > 
> [Hiremath, Vaibhav] Denk,
> 
> We have OMAP families supporting both SDRC and EMIF4 (obviously mutually ex
> clusive), so we need to add this #ifdef.

What makes you think you need it? Did you try what happens when you
just remove the #if/#endif ?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Given a choice between two theories, take the one which is funnier.

[U-Boot] [PATCH-V5] OMAP3EVM: Added NAND support

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

The EVMS have been shipping with NAND (instead of OneNAND) as default.
So, this patch sets NAND as default.

To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the
config file omap3_evm.h,

Changes From V4 :-
	- Removed #undef ONENAND line (comment from Denk)
Changes from V3 :-
	- Refreshed against latest u-boot/master
Changes from V2 :-
	- Added undef statement for CMD_ONENAND.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 include/configs/omap3_evm.h |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 0d99f7d..88af492 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -151,7 +151,7 @@

 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support			*/
-#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_PING

@@ -306,7 +306,13 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

+#if defined(CONFIG_CMD_NAND)
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND
+#elif defined(CONFIG_CMD_ONENAND)
 #define CONFIG_ENV_IS_IN_ONENAND	1
+#endif
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

--
1.6.2.4

[U-Boot] [PATCH-V5] OMAP3EVM: Added NAND support

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Hiremath, Vaibhav
> Sent: Thursday, May 06, 2010 10:49 PM
> To: u-boot at lists.denx.de
> Cc: wd at denx.de; tom at bumblecow.com; Paulraj, Sandeep; Hiremath, Vaibhav
> Subject: [PATCH-V5] OMAP3EVM: Added NAND support
> 
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> The EVMS have been shipping with NAND (instead of OneNAND) as default.
> So, this patch sets NAND as default.
> 
> To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the
> config file omap3_evm.h,
> 
> Changes From V4 :-
> 	- Removed #undef ONENAND line (comment from Denk)
> Changes from V3 :-
> 	- Refreshed against latest u-boot/master
> Changes from V2 :-
> 	- Added undef statement for CMD_ONENAND.
> 
[Hiremath, Vaibhav] Denk,

If we do not have any further comments, can we merge these patches?

Thanks,
Vaibhav

> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
>  include/configs/omap3_evm.h |    8 +++++++-
>  1 files changed, 7 insertions(+), 1 deletions(-)
> 
> diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
> index 0d99f7d..88af492 100644
> --- a/include/configs/omap3_evm.h
> +++ b/include/configs/omap3_evm.h
> @@ -151,7 +151,7 @@
> 
>  #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
>  #define CONFIG_CMD_MMC		/* MMC support			*/
> -#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
> +#define CONFIG_CMD_NAND		/* NAND support			*/
>  #define CONFIG_CMD_DHCP
>  #define CONFIG_CMD_PING
> 
> @@ -306,7 +306,13 @@
>  #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
>  #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
> 
> +#if defined(CONFIG_CMD_NAND)
> +#define CONFIG_NAND_OMAP_GPMC
> +#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
> +#define CONFIG_ENV_IS_IN_NAND
> +#elif defined(CONFIG_CMD_ONENAND)
>  #define CONFIG_ENV_IS_IN_ONENAND	1
> +#endif
>  #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
>  #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
> 
> --
> 1.6.2.4

[U-Boot] [PATCH-V5] OMAP3EVM: Added NAND support

[Wolfgang Denk]

Dear "Hiremath, Vaibhav",

In message <19F8576C6E063C45BE387C64729E7394044E404A8A@dbde02.ent.ti.com> you wrote:
>
> > Subject: [PATCH-V5] OMAP3EVM: Added NAND support
> > 
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> > 
> > The EVMS have been shipping with NAND (instead of OneNAND) as default.
> > So, this patch sets NAND as default.
> > 
> > To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the
> > config file omap3_evm.h,
> > 
> > Changes From V4 :-
> > 	- Removed #undef ONENAND line (comment from Denk)
> > Changes from V3 :-
> > 	- Refreshed against latest u-boot/master
> > Changes from V2 :-
> > 	- Added undef statement for CMD_ONENAND.
> > 
> [Hiremath, Vaibhav] Denk,
>
> If we do not have any further comments, can we merge these patches?

The patches you listed are either ARM related and as such to be
handdled by the ARM custodian, Tom, and/or NAND related ans as such to
be addressed by the NAND custodian, Scott.


I just wait for their pull requests.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"The glory of creation is in its infinite diversity." "And in the way
our differences combine to create meaning and beauty."
	-- Dr. Miranda Jones and Spock, "Is There in Truth No Beauty?",
	   stardate 5630.8

[U-Boot] [PATCH-V5] OMAP3EVM: Added NAND support

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Tuesday, May 11, 2010 2:29 PM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de; tom at bumblecow.com; Paulraj, Sandeep; Scott Wood
> Subject: Re: [PATCH-V5] OMAP3EVM: Added NAND support
> 
> Dear "Hiremath, Vaibhav",
> 
> In message <19F8576C6E063C45BE387C64729E7394044E404A8A@dbde02.ent.ti.com>
> you wrote:
> >
> > > Subject: [PATCH-V5] OMAP3EVM: Added NAND support
> > >
> > > From: Vaibhav Hiremath <hvaibhav@ti.com>
> > >
> > > The EVMS have been shipping with NAND (instead of OneNAND) as default.
> > > So, this patch sets NAND as default.
> > >
> > > To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the
> > > config file omap3_evm.h,
> > >
> > > Changes From V4 :-
> > > 	- Removed #undef ONENAND line (comment from Denk)
> > > Changes from V3 :-
> > > 	- Refreshed against latest u-boot/master
> > > Changes from V2 :-
> > > 	- Added undef statement for CMD_ONENAND.
> > >
> > [Hiremath, Vaibhav] Denk,
> >
> > If we do not have any further comments, can we merge these patches?
> 
> The patches you listed are either ARM related and as such to be
> handdled by the ARM custodian, Tom, and/or NAND related ans as such to
> be addressed by the NAND custodian, Scott.
> 
> 
> I just wait for their pull requests.
[Hiremath, Vaibhav] Thanks Denk,

I think all these patches falls under Tom's list.

Tom,

Can you please merge these patches?

Thanks,
Vaibhav

> 
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> "The glory of creation is in its infinite diversity." "And in the way
> our differences combine to create meaning and beauty."
> 	-- Dr. Miranda Jones and Spock, "Is There in Truth No Beauty?",
> 	   stardate 5630.8

[U-Boot] [PATCH-V5] OMAP3EVM: Added NAND support

[Scott Wood]

On 05/11/2010 03:59 AM, Wolfgang Denk wrote:
> Dear "Hiremath, Vaibhav",
>
> In message<19F8576C6E063C45BE387C64729E7394044E404A8A@dbde02.ent.ti.com>  you wrote:
>>
>>> Subject: [PATCH-V5] OMAP3EVM: Added NAND support
>>>
>>> From: Vaibhav Hiremath<hvaibhav@ti.com>
>>>
>>> The EVMS have been shipping with NAND (instead of OneNAND) as default.
>>> So, this patch sets NAND as default.
>>>
>>> To choose OneNAND, define CMD_ONENAND instead of CMD_NAND in the
>>> config file omap3_evm.h,
>>>
>>> Changes From V4 :-
>>> 	- Removed #undef ONENAND line (comment from Denk)
>>> Changes from V3 :-
>>> 	- Refreshed against latest u-boot/master
>>> Changes from V2 :-
>>> 	- Added undef statement for CMD_ONENAND.
>>>
>> [Hiremath, Vaibhav] Denk,
>>
>> If we do not have any further comments, can we merge these patches?
>
> The patches you listed are either ARM related and as such to be
> handdled by the ARM custodian, Tom, and/or NAND related ans as such to
> be addressed by the NAND custodian, Scott.
>
>
> I just wait for their pull requests.

It's a board config change to turn on NAND, not a change to NAND itself, 
so it should go via the ARM tree.

-Scott

[U-Boot] [PATCH-V3 1/2] AM35x: Add support for AM3517EVM

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

This patch adds basic support for the AM3517EVM.
It includes:
	- Board int file (.c and .h)
	- Default configuration file
	- Updates for Makefile

Changes from V2:
	- Removed trailing spaces
	- Updated MAINTAINERS & MAKEALL for am3517_evm

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 MAINTAINERS                           |    4 +
 MAKEALL                               |    1 +
 Makefile                              |    3 +
 arch/arm/include/asm/arch-omap3/mux.h |   38 +++-
 board/logicpd/am3517evm/Makefile      |   46 ++++
 board/logicpd/am3517evm/am3517evm.c   |   76 ++++++
 board/logicpd/am3517evm/am3517evm.h   |  405 +++++++++++++++++++++++++++++++++
 board/logicpd/am3517evm/config.mk     |   30 +++
 include/configs/am3517_evm.h          |  296 ++++++++++++++++++++++++
 9 files changed, 898 insertions(+), 1 deletions(-)
 create mode 100644 board/logicpd/am3517evm/Makefile
 create mode 100644 board/logicpd/am3517evm/am3517evm.c
 create mode 100644 board/logicpd/am3517evm/am3517evm.h
 create mode 100644 board/logicpd/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 5cbc845..0bc65e1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -798,6 +798,10 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110

+Vaibhav Hiremath <hvaibhav@ti.com>
+
+	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
+
 -------------------------------------------------------------------------

 Unknown / orphaned boards:
diff --git a/MAKEALL b/MAKEALL
index bb09627..cd59daa 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -641,6 +641,7 @@ LIST_ARM11="			\
 ## ARM Cortex-A8 Systems
 #########################################################################
 LIST_ARM_CORTEX_A8="		\
+	am3517_evm		\
 	devkit8000		\
 	mx51evk			\
 	omap3_beagle		\
diff --git a/Makefile b/Makefile
index 2d96574..57b3491 100644
--- a/Makefile
+++ b/Makefile
@@ -3155,6 +3155,9 @@ SMN42_config	:	unconfig
 ## ARM CORTEX Systems
 #########################################################################

+am3517_evm_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3
+
 devkit8000_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3

diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
index 0c01c73..ffeb982 100644
--- a/arch/arm/include/asm/arch-omap3/mux.h
+++ b/arch/arm/include/asm/arch-omap3/mux.h
@@ -283,7 +283,7 @@
 /*Control and debug */
 #define CONTROL_PADCONF_SYS_32K		0x0A04
 #define CONTROL_PADCONF_SYS_CLKREQ	0x0A06
-#define CONTROL_PADCONF_SYS_NIRQ	0x01E0
+#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
 #define CONTROL_PADCONF_SYS_BOOT0	0x0A0A
 #define CONTROL_PADCONF_SYS_BOOT1	0x0A0C
 #define CONTROL_PADCONF_SYS_BOOT2	0x0A0E
@@ -337,6 +337,7 @@
 #define CONTROL_PADCONF_ETK_D14_ES2	0x05F8
 #define CONTROL_PADCONF_ETK_D15_ES2	0x05FA
 /*Die to Die */
+#define CONTROL_PADCONF_SYS_NIRQ	0x01E0
 #define CONTROL_PADCONF_D2D_MCAD0	0x01E4
 #define CONTROL_PADCONF_D2D_MCAD1	0x01E6
 #define CONTROL_PADCONF_D2D_MCAD2	0x01E8
@@ -403,6 +404,41 @@
 #define CONTROL_PADCONF_D2D_SBUSFLAG	0x0260
 #define CONTROL_PADCONF_SDRC_CKE0	0x0262
 #define CONTROL_PADCONF_SDRC_CKE1	0x0264
+/* AM3517 specific */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
+#define CONTROL_PADCONF_CCDC_HD		0x01E8
+#define CONTROL_PADCONF_CCDC_VD		0x01EA
+#define CONTROL_PADCONF_CCDC_WEN	0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0	0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1	0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2	0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3	0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4	0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5	0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6	0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7	0x01FC
+#define CONTROL_PADCONF_RMII_MDIO_DATA	0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK	0x0200
+#define CONTROL_PADCONF_RMII_RXD0	0x0202
+#define CONTROL_PADCONF_RMII_RXD1	0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV	0x0206
+#define CONTROL_PADCONF_RMII_RXER	0x0208
+#define CONTROL_PADCONF_RMII_TXD0	0x020A
+#define CONTROL_PADCONF_RMII_TXD1	0x020C
+#define CONTROL_PADCONF_RMII_TXEN	0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK	0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS	0x0212
+#define CONTROL_PADCONF_HECC1_TXD	0x0214
+#define CONTROL_PADCONF_HECC1_RXD	0x0216
+#define CONTROL_PADCONF_SYS_BOOT7	0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N	0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N	0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N	0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N	0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0	0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1	0x0224
+#define CONTROL_PADCONF_SYS_BOOT8	0x0226

 #define MUX_VAL(OFFSET,VALUE)\
 	writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile
new file mode 100644
index 0000000..3a6b1a1
--- /dev/null
+++ b/board/logicpd/am3517evm/Makefile
@@ -0,0 +1,46 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Based on ti/evm/Makefile
+#
+# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= am3517evm.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
new file mode 100644
index 0000000..2b912a9
--- /dev/null
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -0,0 +1,76 @@
+/*
+ * am3517evm.c - board file for TI's AM3517 family of devices.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include "am3517evm.h"
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init i2c, ethernet, etc... (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_AM3517EVM();
+}
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h
new file mode 100644
index 0000000..68d746c
--- /dev/null
+++ b/board/logicpd/am3517evm/am3517evm.h
@@ -0,0 +1,405 @@
+/*
+ * am3517evm.h - Header file for the AM3517 EVM.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.h
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _AM3517EVM_H_
+#define _AM3517EVM_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"AM3517EVM Board",
+	"NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_AM3517EVM() \
+	/* SDRC */\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
+	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
+	/*sdrc_strben_dly0*/\
+	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
+	 /*sdrc_strben_dly1*/\
+	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
+	/* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+							 /* - ETH_nRESET*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) \
+	/* DSS */\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
+	/* CAMERA */\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+							 /* - CAM_RESET*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) \
+	/* MMC */\
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
+	/* WriteProtect */\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) /*CardDetect*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
+	\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTD | DIS | M0)) \
+	/* McBSP */\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+							 /* - LCD_INI*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+							 /* - LCD_ENVDD */\
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+							 /* - LCD_QVGA/nVGA */\
+	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+							 /* - LCD_RESB */\
+	/* UART */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
+	/* I2C */\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
+	/* McSPI */\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
+							 /* - LAN_INTR*/\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M4)) \
+	/* CCDC */\
+	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M0)) \
+	/* RMII */\
+	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
+	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
+	MUX_VAL(CP(RMII_RXD0)	,	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
+	/* HECC */\
+	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTU | EN  | M0)) \
+	/* HSUSB */\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
+	/* HDQ */\
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) \
+	/* Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
+	/*SYS_nRESWARM */\
+	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | DIS | M4)) \
+							/* - GPIO30 */\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+							 /* - PEN_IRQ */\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+							 /* - VIO_1V8*/\
+	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
+	/* JTAG */\
+	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) \
+	/* ETK (ES2 onwards) */\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0)) \
+	/* Die to Die */\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+
+#endif
diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk
new file mode 100644
index 0000000..f7a35ce
--- /dev/null
+++ b/board/logicpd/am3517evm/config.mk
@@ -0,0 +1,30 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Based on ti/evm/config.mk
+#
+# Copyright (C) 2010
+# Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
new file mode 100644
index 0000000..63f853a
--- /dev/null
+++ b/include/configs/am3517_evm.h
@@ -0,0 +1,296 @@
+/*
+ * am3517_evm.h - Default configuration for AM3517 EVM board.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on omap3_evm_config.h
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */
+
+#define CONFIG_EMIF4		1	/* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ				/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+/*
+ * DDR related
+ */
+#define CONFIG_OMAP3_MICRON_DDR		1	/* Micron DDR */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 on AM3517 EVM */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+#undef CONFIG_CMD_NET
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_BOOTFILE		uImage
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc init; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT			"AM3517_EVM # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor@start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			boot_flash_env_addr
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#ifndef __ASSEMBLY__
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */
--
1.6.2.4

[U-Boot] [PATCH-V3 1/2] AM35x: Add support for AM3517EVM

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Hiremath, Vaibhav
> Sent: Thursday, May 06, 2010 10:53 PM
> To: u-boot at lists.denx.de
> Cc: wd at denx.de; tom at bumblecow.com; Paulraj, Sandeep; Hiremath, Vaibhav;
> Premi, Sanjeev
> Subject: [PATCH-V3 1/2] AM35x: Add support for AM3517EVM
>
> From: Vaibhav Hiremath <hvaibhav@ti.com>
>
> This patch adds basic support for the AM3517EVM.
> It includes:
>       - Board int file (.c and .h)
>       - Default configuration file
>       - Updates for Makefile
>
> Changes from V2:
>       - Removed trailing spaces
>       - Updated MAINTAINERS & MAKEALL for am3517_evm
>
[Hiremath, Vaibhav] Denk,

If we do not have any further comments, can we merge these patches?

Thanks,
Vaibhav

> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Sanjeev Premi <premi@ti.com>
> ---
>  MAINTAINERS                           |    4 +
>  MAKEALL                               |    1 +
>  Makefile                              |    3 +
>  arch/arm/include/asm/arch-omap3/mux.h |   38 +++-
>  board/logicpd/am3517evm/Makefile      |   46 ++++
>  board/logicpd/am3517evm/am3517evm.c   |   76 ++++++
>  board/logicpd/am3517evm/am3517evm.h   |  405
> +++++++++++++++++++++++++++++++++
>  board/logicpd/am3517evm/config.mk     |   30 +++
>  include/configs/am3517_evm.h          |  296 ++++++++++++++++++++++++
>  9 files changed, 898 insertions(+), 1 deletions(-)
>  create mode 100644 board/logicpd/am3517evm/Makefile
>  create mode 100644 board/logicpd/am3517evm/am3517evm.c
>  create mode 100644 board/logicpd/am3517evm/am3517evm.h
>  create mode 100644 board/logicpd/am3517evm/config.mk
>  create mode 100644 include/configs/am3517_evm.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5cbc845..0bc65e1 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -798,6 +798,10 @@ Alex Z
>       lart            SA1100
>       dnp1110         SA1110
>
> +Vaibhav Hiremath <hvaibhav@ti.com>
> +
> +     am3517_evm      ARM CORTEX-A8 (AM35x SoC)
> +
>  -------------------------------------------------------------------------
>
>  Unknown / orphaned boards:
> diff --git a/MAKEALL b/MAKEALL
> index bb09627..cd59daa 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -641,6 +641,7 @@ LIST_ARM11="                      \
>  ## ARM Cortex-A8 Systems
>  #########################################################################
>  LIST_ARM_CORTEX_A8="         \
> +     am3517_evm              \
>       devkit8000              \
>       mx51evk                 \
>       omap3_beagle            \
> diff --git a/Makefile b/Makefile
> index 2d96574..57b3491 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -3155,6 +3155,9 @@ SMN42_config    :       unconfig
>  ## ARM CORTEX Systems
>  #########################################################################
>
> +am3517_evm_config :  unconfig
> +     @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3
> +
>  devkit8000_config :  unconfig
>       @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3
>
> diff --git a/arch/arm/include/asm/arch-omap3/mux.h
> b/arch/arm/include/asm/arch-omap3/mux.h
> index 0c01c73..ffeb982 100644
> --- a/arch/arm/include/asm/arch-omap3/mux.h
> +++ b/arch/arm/include/asm/arch-omap3/mux.h
> @@ -283,7 +283,7 @@
>  /*Control and debug */
>  #define CONTROL_PADCONF_SYS_32K              0x0A04
>  #define CONTROL_PADCONF_SYS_CLKREQ   0x0A06
> -#define CONTROL_PADCONF_SYS_NIRQ     0x01E0
> +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08
>  #define CONTROL_PADCONF_SYS_BOOT0    0x0A0A
>  #define CONTROL_PADCONF_SYS_BOOT1    0x0A0C
>  #define CONTROL_PADCONF_SYS_BOOT2    0x0A0E
> @@ -337,6 +337,7 @@
>  #define CONTROL_PADCONF_ETK_D14_ES2  0x05F8
>  #define CONTROL_PADCONF_ETK_D15_ES2  0x05FA
>  /*Die to Die */
> +#define CONTROL_PADCONF_SYS_NIRQ     0x01E0
>  #define CONTROL_PADCONF_D2D_MCAD0    0x01E4
>  #define CONTROL_PADCONF_D2D_MCAD1    0x01E6
>  #define CONTROL_PADCONF_D2D_MCAD2    0x01E8
> @@ -403,6 +404,41 @@
>  #define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260
>  #define CONTROL_PADCONF_SDRC_CKE0    0x0262
>  #define CONTROL_PADCONF_SDRC_CKE1    0x0264
> +/* AM3517 specific */
> +#define CONTROL_PADCONF_CCDC_PCLK    0x01E4
> +#define CONTROL_PADCONF_CCDC_FIELD   0x01E6
> +#define CONTROL_PADCONF_CCDC_HD              0x01E8
> +#define CONTROL_PADCONF_CCDC_VD              0x01EA
> +#define CONTROL_PADCONF_CCDC_WEN     0x01EC
> +#define CONTROL_PADCONF_CCDC_DATA0   0x01EE
> +#define CONTROL_PADCONF_CCDC_DATA1   0x01F0
> +#define CONTROL_PADCONF_CCDC_DATA2   0x01F2
> +#define CONTROL_PADCONF_CCDC_DATA3   0x01F4
> +#define CONTROL_PADCONF_CCDC_DATA4   0x01F6
> +#define CONTROL_PADCONF_CCDC_DATA5   0x01F8
> +#define CONTROL_PADCONF_CCDC_DATA6   0x01FA
> +#define CONTROL_PADCONF_CCDC_DATA7   0x01FC
> +#define CONTROL_PADCONF_RMII_MDIO_DATA       0x01FE
> +#define CONTROL_PADCONF_RMII_MDIO_CLK        0x0200
> +#define CONTROL_PADCONF_RMII_RXD0    0x0202
> +#define CONTROL_PADCONF_RMII_RXD1    0x0204
> +#define CONTROL_PADCONF_RMII_CRS_DV  0x0206
> +#define CONTROL_PADCONF_RMII_RXER    0x0208
> +#define CONTROL_PADCONF_RMII_TXD0    0x020A
> +#define CONTROL_PADCONF_RMII_TXD1    0x020C
> +#define CONTROL_PADCONF_RMII_TXEN    0x020E
> +#define CONTROL_PADCONF_RMII_50MHZ_CLK       0x0210
> +#define CONTROL_PADCONF_USB0_DRVBUS  0x0212
> +#define CONTROL_PADCONF_HECC1_TXD    0x0214
> +#define CONTROL_PADCONF_HECC1_RXD    0x0216
> +#define CONTROL_PADCONF_SYS_BOOT7    0x0218
> +#define CONTROL_PADCONF_SDRC_DQS0N   0x021A
> +#define CONTROL_PADCONF_SDRC_DQS1N   0x021C
> +#define CONTROL_PADCONF_SDRC_DQS2N   0x021E
> +#define CONTROL_PADCONF_SDRC_DQS3N   0x0220
> +#define CONTROL_PADCONF_STRBEN_DLY0  0x0222
> +#define CONTROL_PADCONF_STRBEN_DLY1  0x0224
> +#define CONTROL_PADCONF_SYS_BOOT8    0x0226
>
>  #define MUX_VAL(OFFSET,VALUE)\
>       writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
> diff --git a/board/logicpd/am3517evm/Makefile
> b/board/logicpd/am3517evm/Makefile
> new file mode 100644
> index 0000000..3a6b1a1
> --- /dev/null
> +++ b/board/logicpd/am3517evm/Makefile
> @@ -0,0 +1,46 @@
> +#
> +# Author: Vaibhav Hiremath <hvaibhav@ti.com>
> +#
> +# Based on ti/evm/Makefile
> +#
> +# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
> +#
> +# This program is free software; you can redistribute it and/or modify
> +# it under the terms of the GNU General Public License as published by
> +# the Free Software Foundation; either version 2 of the License, or
> +# (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB  = $(obj)lib$(BOARD).a
> +
> +COBJS        := am3517evm.o
> +
> +SRCS := $(COBJS:.o=.c)
> +OBJS := $(addprefix $(obj),$(COBJS))
> +
> +$(LIB):      $(obj).depend $(OBJS)
> +     $(AR) $(ARFLAGS) $@ $(OBJS)
> +
> +clean:
> +     rm -f $(OBJS)
> +
> +distclean:   clean
> +     rm -f $(LIB) core *.bak $(obj).depend
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> diff --git a/board/logicpd/am3517evm/am3517evm.c
> b/board/logicpd/am3517evm/am3517evm.c
> new file mode 100644
> index 0000000..2b912a9
> --- /dev/null
> +++ b/board/logicpd/am3517evm/am3517evm.c
> @@ -0,0 +1,76 @@
> +/*
> + * am3517evm.c - board file for TI's AM3517 family of devices.
> + *
> + * Author: Vaibhav Hiremath <hvaibhav@ti.com>
> + *
> + * Based on ti/evm/evm.c
> + *
> + * Copyright (C) 2010
> + * Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/mem.h>
> +#include <asm/arch/mux.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/mach-types.h>
> +#include <i2c.h>
> +#include "am3517evm.h"
> +
> +/*
> + * Routine: board_init
> + * Description: Early hardware init.
> + */
> +int board_init(void)
> +{
> +     DECLARE_GLOBAL_DATA_PTR;
> +
> +     gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
> +     /* board id for Linux */
> +     gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;
> +     /* boot param addr */
> +     gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> +
> +     return 0;
> +}
> +
> +/*
> + * Routine: misc_init_r
> + * Description: Init i2c, ethernet, etc... (done here so udelay works)
> + */
> +int misc_init_r(void)
> +{
> +#ifdef CONFIG_DRIVER_OMAP34XX_I2C
> +     i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
> +#endif
> +
> +     dieid_num_r();
> +
> +     return 0;
> +}
> +
> +/*
> + * Routine: set_muxconf_regs
> + * Description: Setting up the configuration Mux registers specific to the
> + *           hardware. Many pins need to be moved from protect to primary
> + *           mode.
> + */
> +void set_muxconf_regs(void)
> +{
> +     MUX_AM3517EVM();
> +}
> diff --git a/board/logicpd/am3517evm/am3517evm.h
> b/board/logicpd/am3517evm/am3517evm.h
> new file mode 100644
> index 0000000..68d746c
> --- /dev/null
> +++ b/board/logicpd/am3517evm/am3517evm.h
> @@ -0,0 +1,405 @@
> +/*
> + * am3517evm.h - Header file for the AM3517 EVM.
> + *
> + * Author: Vaibhav Hiremath <hvaibhav@ti.com>
> + *
> + * Based on ti/evm/evm.h
> + *
> + * Copyright (C) 2010
> + * Texas Instruments Incorporated - http://www.ti.com/
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#ifndef _AM3517EVM_H_
> +#define _AM3517EVM_H_
> +
> +const omap3_sysinfo sysinfo = {
> +     DDR_DISCRETE,
> +     "AM3517EVM Board",
> +     "NAND",
> +};
> +
> +/*
> + * IEN  - Input Enable
> + * IDIS - Input Disable
> + * PTD  - Pull type Down
> + * PTU  - Pull type Up
> + * DIS  - Pull type selection is inactive
> + * EN   - Pull type selection is active
> + * M0   - Mode 0
> + * The commented string gives the final mux configuration for that pin
> + */
> +#define MUX_AM3517EVM() \
> +     /* SDRC */\
> +     MUX_VAL(CP(SDRC_D0),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D1),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D2),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D3),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D4),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D5),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D6),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D7),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D8),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D9),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D10),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D11),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D12),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D13),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D14),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D15),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D16),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D17),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D18),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D19),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D20),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D21),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D22),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D23),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D24),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D25),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D26),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D27),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D28),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D29),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D30),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_D31),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_CLK),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_DQS0),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_DQS1),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_DQS2),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_DQS3),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SDRC_DQS0N),         (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(SDRC_DQS1N),         (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(SDRC_DQS2N),         (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(SDRC_DQS3N),         (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(SDRC_CKE0),          (M0)) \
> +     MUX_VAL(CP(SDRC_CKE1),          (M0)) \
> +     /*sdrc_strben_dly0*/\
> +     MUX_VAL(CP(STRBEN_DLY0),        (IEN  | PTD | EN  | M0)) \
> +      /*sdrc_strben_dly1*/\
> +     MUX_VAL(CP(STRBEN_DLY1),        (IEN  | PTD | EN  | M0)) \
> +     /* GPMC */\
> +     MUX_VAL(CP(GPMC_A1),            (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_A2),            (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_A3),            (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_A4),            (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_A5),            (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_A6),            (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_A7),            (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_A8),            (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_A9),            (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_A10),           (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D0),            (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D1),            (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D2),            (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D3),            (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D4),            (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D5),            (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D6),            (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D7),            (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D8),            (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D9),            (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D10),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D11),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D12),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D13),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D14),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_D15),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_NCS0),          (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_NCS1),          (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_NCS2),          (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_NCS3),          (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_NCS4),          (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_NCS5),          (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_NCS6),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(GPMC_NCS7),          (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_CLK),           (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_NADV_ALE),      (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(GPMC_NOE),           (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(GPMC_NWE),           (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(GPMC_NBE0_CLE),      (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_NBE1),          (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_NWP),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(GPMC_WAIT0),         (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_WAIT1),         (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(GPMC_WAIT2),         (IEN  | PTU | EN  | M4)) /*GPIO_64*/\
> +                                                      /* - ETH_nRESET*/\
> +     MUX_VAL(CP(GPMC_WAIT3),         (IEN  | PTU | EN  | M0)) \
> +     /* DSS */\
> +     MUX_VAL(CP(DSS_PCLK),           (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_HSYNC),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_VSYNC),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_ACBIAS),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA0),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA1),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA2),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA3),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA4),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA5),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA6),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA7),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA8),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA9),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA10),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA11),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA12),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA13),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA14),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA15),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA16),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA17),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA18),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA19),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA20),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA21),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA22),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(DSS_DATA23),         (IDIS | PTD | DIS | M0)) \
> +     /* CAMERA */\
> +     MUX_VAL(CP(CAM_HS),             (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(CAM_VS),             (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(CAM_XCLKA),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_PCLK),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(CAM_FLD),            (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
> +                                                      /* - CAM_RESET*/\
> +     MUX_VAL(CP(CAM_D0),             (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_D1),             (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_D2),             (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_D3),             (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_D4),             (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_D5),             (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_D6),             (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_D7),             (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_D8),             (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_D9),             (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_D10),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_D11),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_XCLKB),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CAM_WEN),            (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
> +     MUX_VAL(CP(CAM_STROBE),         (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CSI2_DX0),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CSI2_DY0),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CSI2_DX1),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CSI2_DY1),           (IEN  | PTD | DIS | M0)) \
> +     /* MMC */\
> +     MUX_VAL(CP(MMC1_CLK),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(MMC1_CMD),           (IEN  | PTU | DIS | M0)) \
> +     MUX_VAL(CP(MMC1_DAT0),          (IEN  | PTU | DIS | M0)) \
> +     MUX_VAL(CP(MMC1_DAT1),          (IEN  | PTU | DIS | M0)) \
> +     MUX_VAL(CP(MMC1_DAT2),          (IEN  | PTU | DIS | M0)) \
> +     MUX_VAL(CP(MMC1_DAT3),          (IEN  | PTU | DIS | M0)) \
> +     /* WriteProtect */\
> +     MUX_VAL(CP(MMC1_DAT4),          (IEN  | PTU | EN  | M4)) \
> +     MUX_VAL(CP(MMC1_DAT5),          (IEN  | PTU | EN  | M4)) /*CardDetect*/\
> +     MUX_VAL(CP(MMC1_DAT6),          (IEN  | PTU | EN  | M4)) \
> +     MUX_VAL(CP(MMC1_DAT7),          (IEN  | PTU | EN  | M4)) \
> +     \
> +     MUX_VAL(CP(MMC2_CLK),           (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(MMC2_CMD),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MMC2_DAT0),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MMC2_DAT1),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MMC2_DAT2),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MMC2_DAT3),          (IEN  | PTD | DIS | M0)) \
> +     /* McBSP */\
> +     MUX_VAL(CP(MCBSP_CLKS),         (IEN  | PTU | DIS | M0)) \
> +     MUX_VAL(CP(MCBSP1_CLKR),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCBSP1_FSR),         (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(MCBSP1_DX),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCBSP1_DR),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCBSP1_FSX),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCBSP1_CLKX),        (IEN  | PTD | DIS | M0)) \
> +     \
> +     MUX_VAL(CP(MCBSP2_FSX),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCBSP2_CLKX),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCBSP2_DR),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCBSP2_DX),          (IDIS | PTD | DIS | M0)) \
> +     \
> +     MUX_VAL(CP(MCBSP3_DX),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCBSP3_DR),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCBSP3_CLKX),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCBSP3_FSX),         (IEN  | PTD | DIS | M0)) \
> +     \
> +     MUX_VAL(CP(MCBSP4_CLKX),        (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
> +                                                      /* - LCD_INI*/\
> +     MUX_VAL(CP(MCBSP4_DR),          (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
> +                                                      /* - LCD_ENVDD */\
> +     MUX_VAL(CP(MCBSP4_DX),          (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
> +                                                      /* - LCD_QVGA/nVGA */\
> +     MUX_VAL(CP(MCBSP4_FSX),         (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
> +                                                      /* - LCD_RESB */\
> +     /* UART */\
> +     MUX_VAL(CP(UART1_TX),           (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(UART1_RTS),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(UART1_CTS),          (IEN  | PTU | DIS | M0)) \
> +     \
> +     MUX_VAL(CP(UART1_RX),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(UART2_CTS),          (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(UART2_RTS),          (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(UART2_TX),           (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(UART2_RX),           (IEN  | PTD | DIS | M0)) \
> +     \
> +     MUX_VAL(CP(UART3_CTS_RCTX),     (IEN  | PTU | DIS | M0)) \
> +     MUX_VAL(CP(UART3_RTS_SD),       (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(UART3_RX_IRRX),      (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(UART3_TX_IRTX),      (IDIS | PTD | DIS | M0)) \
> +     /* I2C */\
> +     MUX_VAL(CP(I2C1_SCL),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(I2C1_SDA),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(I2C2_SCL),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(I2C2_SDA),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(I2C3_SCL),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(I2C3_SDA),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(I2C4_SCL),           (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(I2C4_SDA),           (IEN  | PTU | EN  | M0)) \
> +     /* McSPI */\
> +     MUX_VAL(CP(MCSPI1_CLK),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCSPI1_SIMO),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCSPI1_SOMI),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCSPI1_CS0),         (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(MCSPI1_CS1),         (IEN  | PTD | EN  | M4)) /*GPIO_175*/\
> +     MUX_VAL(CP(MCSPI1_CS2),         (IEN  | PTU | DIS | M4)) /*GPIO_176*/\
> +                                                      /* - LAN_INTR*/\
> +     MUX_VAL(CP(MCSPI1_CS3),         (IEN  | PTD | EN  | M0)) \
> +     \
> +     MUX_VAL(CP(MCSPI2_CLK),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCSPI2_SIMO),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCSPI2_SOMI),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(MCSPI2_CS0),         (IEN  | PTD | EN  | M4)) \
> +     MUX_VAL(CP(MCSPI2_CS1),         (IEN  | PTD | EN  | M4)) \
> +     /* CCDC */\
> +     MUX_VAL(CP(CCDC_PCLK),          (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(CCDC_FIELD),         (IEN  | PTD | DIS | M1)) \
> +     MUX_VAL(CP(CCDC_HD),            (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(CCDC_VD),            (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(CCDC_WEN),           (IEN  | PTD | DIS | M1)) \
> +     MUX_VAL(CP(CCDC_DATA0),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CCDC_DATA1),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CCDC_DATA2),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CCDC_DATA3),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CCDC_DATA4),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CCDC_DATA5),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CCDC_DATA6),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(CCDC_DATA7),         (IEN  | PTD | DIS | M0)) \
> +     /* RMII */\
> +     MUX_VAL(CP(RMII_MDIO_DATA),     (IEN  |  M0)) \
> +     MUX_VAL(CP(RMII_MDIO_CLK),      (M0)) \
> +     MUX_VAL(CP(RMII_RXD0)   ,       (IEN  | PTD | M0)) \
> +     MUX_VAL(CP(RMII_RXD1),          (IEN  | PTD | M0)) \
> +     MUX_VAL(CP(RMII_CRS_DV),        (IEN  | PTD | M0)) \
> +     MUX_VAL(CP(RMII_RXER),          (PTD | M0)) \
> +     MUX_VAL(CP(RMII_TXD0),          (PTD | M0)) \
> +     MUX_VAL(CP(RMII_TXD1),          (PTD | M0)) \
> +     MUX_VAL(CP(RMII_TXEN),          (PTD | M0)) \
> +     MUX_VAL(CP(RMII_50MHZ_CLK),     (IEN  | PTD | EN  | M0)) \
> +     /* HECC */\
> +     MUX_VAL(CP(HECC1_TXD),          (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(HECC1_RXD),          (IEN  | PTU | EN  | M0)) \
> +     /* HSUSB */\
> +     MUX_VAL(CP(HSUSB0_CLK),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(HSUSB0_STP),         (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(HSUSB0_DIR),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(HSUSB0_NXT),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(HSUSB0_DATA0),       (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(HSUSB0_DATA1),       (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(HSUSB0_DATA2),       (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(HSUSB0_DATA3),       (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(HSUSB0_DATA4),       (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(HSUSB0_DATA5),       (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(HSUSB0_DATA6),       (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(HSUSB0_DATA7),       (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(USB0_DRVBUS),        (IEN  | PTD | EN  | M0)) \
> +     /* HDQ */\
> +     MUX_VAL(CP(HDQ_SIO),            (IEN  | PTU | EN  | M0)) \
> +     /* Control and debug */\
> +     MUX_VAL(CP(SYS_32K),            (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SYS_CLKREQ),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SYS_NIRQ),           (IEN  | PTU | EN  | M0)) \
> +     /*SYS_nRESWARM */\
> +     MUX_VAL(CP(SYS_NRESWARM),       (IDIS | PTU | DIS | M4)) \
> +                                                     /* - GPIO30 */\
> +     MUX_VAL(CP(SYS_BOOT0),          (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
> +                                                      /* - PEN_IRQ */\
> +     MUX_VAL(CP(SYS_BOOT1),          (IEN  | PTD | DIS | M4)) /*GPIO_3 */\
> +     MUX_VAL(CP(SYS_BOOT2),          (IEN  | PTD | DIS | M4)) /*GPIO_4*/\
> +     MUX_VAL(CP(SYS_BOOT3),          (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
> +     MUX_VAL(CP(SYS_BOOT4),          (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
> +     MUX_VAL(CP(SYS_BOOT5),          (IEN  | PTD | DIS | M4)) /*GPIO_7*/\
> +     MUX_VAL(CP(SYS_BOOT6),          (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
> +                                                      /* - VIO_1V8*/\
> +     MUX_VAL(CP(SYS_BOOT7),          (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(SYS_BOOT8),          (IEN  | PTD | EN  | M0)) \
> +     \
> +     MUX_VAL(CP(SYS_OFF_MODE),       (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SYS_CLKOUT1),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(SYS_CLKOUT2),        (IEN  | PTU | EN  | M0)) \
> +     /* JTAG */\
> +     MUX_VAL(CP(JTAG_nTRST),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(JTAG_TCK),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(JTAG_TMS),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(JTAG_TDI),           (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(JTAG_EMU0),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(JTAG_EMU1),          (IEN  | PTD | DIS | M0)) \
> +     /* ETK (ES2 onwards) */\
> +     MUX_VAL(CP(ETK_CLK_ES2),        (IDIS | PTU | EN  | M0)) \
> +     MUX_VAL(CP(ETK_CTL_ES2),        (IDIS | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D0_ES2),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D1_ES2),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D2_ES2),         (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(ETK_D3_ES2),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D4_ES2),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D5_ES2),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D6_ES2),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D7_ES2),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D8_ES2),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D9_ES2),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D10_ES2),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D11_ES2),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D12_ES2),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D13_ES2),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D14_ES2),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(ETK_D15_ES2),        (IEN  | PTD | DIS | M0)) \
> +     /* Die to Die */\
> +     MUX_VAL(CP(D2D_MCAD34),         (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(D2D_MCAD35),         (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(D2D_MCAD36),         (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(D2D_CLK26MI),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_NRESPWRON),      (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(D2D_NRESWARM),       (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(D2D_ARM9NIRQ),       (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_UMA2P6FIQ),      (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_SPINT),          (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(D2D_FRINT),          (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(D2D_DMAREQ0),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_DMAREQ1),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_DMAREQ2),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_DMAREQ3),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_N3GTRST),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_N3GTDI),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_N3GTDO),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_N3GTMS),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_N3GTCK),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_N3GRTCK),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_MSTDBY),         (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(D2D_SWAKEUP),        (IEN  | PTD | EN  | M0)) \
> +     MUX_VAL(CP(D2D_IDLEREQ),        (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_IDLEACK),        (IEN  | PTU | EN  | M0)) \
> +     MUX_VAL(CP(D2D_MWRITE),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_SWRITE),         (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_MREAD),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_SREAD),          (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_MBUSFLAG),       (IEN  | PTD | DIS | M0)) \
> +     MUX_VAL(CP(D2D_SBUSFLAG),       (IEN  | PTD | DIS | M0)) \
> +
> +#endif
> diff --git a/board/logicpd/am3517evm/config.mk
> b/board/logicpd/am3517evm/config.mk
> new file mode 100644
> index 0000000..f7a35ce
> --- /dev/null
> +++ b/board/logicpd/am3517evm/config.mk
> @@ -0,0 +1,30 @@
> +#
> +# Author: Vaibhav Hiremath <hvaibhav@ti.com>
> +#
> +# Based on ti/evm/config.mk
> +#
> +# Copyright (C) 2010
> +# Texas Instruments Incorporated - http://www.ti.com/
> +#
> +# This program is free software; you can redistribute it and/or modify
> +# it under the terms of the GNU General Public License as published by
> +# the Free Software Foundation; either version 2 of the License, or
> +# (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> +#
> +# Physical Address:
> +# 8000'0000 (bank0)
> +# A000/0000 (bank1)
> +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
> +# (mem base + reserved)
> +
> +# For use with external or internal boots.
> +TEXT_BASE = 0x80e80000
> diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
> new file mode 100644
> index 0000000..63f853a
> --- /dev/null
> +++ b/include/configs/am3517_evm.h
> @@ -0,0 +1,296 @@
> +/*
> + * am3517_evm.h - Default configuration for AM3517 EVM board.
> + *
> + * Author: Vaibhav Hiremath <hvaibhav@ti.com>
> + *
> + * Based on omap3_evm_config.h
> + *
> + * Copyright (C) 2009 Texas Instruments Incorporated
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * High Level Configuration Options
> + */
> +#define CONFIG_ARMCORTEXA8   1       /* This is an ARM V7 CPU core */
> +#define CONFIG_OMAP          1       /* in a TI OMAP core */
> +#define CONFIG_OMAP34XX              1       /* which is a 34XX */
> +#define CONFIG_OMAP3_AM3517EVM       1       /* working with AM3517EVM */
> +
> +#define CONFIG_EMIF4         1       /* The chip has EMIF4 controller */
> +
> +#include <asm/arch/cpu.h>            /* get chip and board defs */
> +#include <asm/arch/omap3.h>
> +
> +/*
> + * Display CPU and Board information
> + */
> +#define CONFIG_DISPLAY_CPUINFO               1
> +#define CONFIG_DISPLAY_BOARDINFO     1
> +
> +/* Clock Defines */
> +#define V_OSCK                       26000000        /* Clock output from T2 */
> +#define V_SCLK                       (V_OSCK >> 1)
> +
> +#undef CONFIG_USE_IRQ                                /* no support for IRQs */
> +#define CONFIG_MISC_INIT_R
> +
> +#define CONFIG_CMDLINE_TAG           1       /* enable passing of ATAGs */
> +#define CONFIG_SETUP_MEMORY_TAGS     1
> +#define CONFIG_INITRD_TAG            1
> +#define CONFIG_REVISION_TAG          1
> +
> +/*
> + * Size of malloc() pool
> + */
> +#define CONFIG_ENV_SIZE                      (128 << 10)     /* 128 KiB sector */
> +#define CONFIG_SYS_MALLOC_LEN                (CONFIG_ENV_SIZE + (128 << 10))
> +#define CONFIG_SYS_GBL_DATA_SIZE     128     /* bytes reserved for */
> +                                             /* initial data */
> +/*
> + * DDR related
> + */
> +#define CONFIG_OMAP3_MICRON_DDR              1       /* Micron DDR */
> +#define CONFIG_SYS_CS0_SIZE          (256 * 1024 * 1024)
> +
> +/*
> + * Hardware drivers
> + */
> +
> +/*
> + * NS16550 Configuration
> + */
> +#define V_NS16550_CLK                        48000000        /* 48MHz (APLL96/2) */
> +
> +#define CONFIG_SYS_NS16550
> +#define CONFIG_SYS_NS16550_SERIAL
> +#define CONFIG_SYS_NS16550_REG_SIZE  (-4)
> +#define CONFIG_SYS_NS16550_CLK               V_NS16550_CLK
> +
> +/*
> + * select serial console configuration
> + */
> +#define CONFIG_CONS_INDEX            3
> +#define CONFIG_SYS_NS16550_COM3              OMAP34XX_UART3
> +#define CONFIG_SERIAL3                       3       /* UART3 on AM3517 EVM */
> +
> +/* allow to overwrite serial and ethaddr */
> +#define CONFIG_ENV_OVERWRITE
> +#define CONFIG_BAUDRATE                      115200
> +#define CONFIG_SYS_BAUDRATE_TABLE    {4800, 9600, 19200, 38400, 57600,\
> +                                     115200}
> +#define CONFIG_MMC                   1
> +#define CONFIG_OMAP3_MMC             1
> +#define CONFIG_DOS_PARTITION         1
> +
> +/* commands to include */
> +#include <config_cmd_default.h>
> +
> +#define CONFIG_CMD_EXT2              /* EXT2 Support                 */
> +#define CONFIG_CMD_FAT               /* FAT support                  */
> +#define CONFIG_CMD_JFFS2     /* JFFS2 Support                */
> +
> +#define CONFIG_CMD_I2C               /* I2C serial bus support       */
> +#define CONFIG_CMD_MMC               /* MMC support                  */
> +#define CONFIG_CMD_NAND              /* NAND support                 */
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_PING
> +
> +#undef CONFIG_CMD_FLASH              /* flinfo, erase, protect       */
> +#undef CONFIG_CMD_FPGA               /* FPGA configuration Support   */
> +#undef CONFIG_CMD_IMI                /* iminfo                       */
> +#undef CONFIG_CMD_IMLS               /* List all found images        */
> +
> +#define CONFIG_SYS_NO_FLASH
> +#define CONFIG_HARD_I2C                      1
> +#define CONFIG_SYS_I2C_SPEED         100000
> +#define CONFIG_SYS_I2C_SLAVE         1
> +#define CONFIG_SYS_I2C_BUS           0
> +#define CONFIG_SYS_I2C_BUS_SELECT    1
> +#define CONFIG_DRIVER_OMAP34XX_I2C   1
> +
> +#undef CONFIG_CMD_NET
> +/*
> + * Board NAND Info.
> + */
> +#define CONFIG_SYS_NAND_ADDR         NAND_BASE       /* physical address */
> +                                                     /* to access nand */
> +#define CONFIG_SYS_NAND_BASE         NAND_BASE       /* physical address */
> +                                                     /* to access */
> +                                                     /* nand at CS0 */
> +
> +#define CONFIG_SYS_MAX_NAND_DEVICE   1               /* Max number of */
> +                                                     /* NAND devices */
> +#define CONFIG_SYS_64BIT_VSPRINTF            /* needed for nand_util.c */
> +
> +#define CONFIG_JFFS2_NAND
> +/* nand device jffs2 lives on */
> +#define CONFIG_JFFS2_DEV             "nand0"
> +/* start of jffs2 partition */
> +#define CONFIG_JFFS2_PART_OFFSET     0x680000
> +#define CONFIG_JFFS2_PART_SIZE               0xf980000       /* sz of jffs2 part */
> +
> +/* Environment information */
> +#define CONFIG_BOOTDELAY     10
> +
> +#define CONFIG_BOOTFILE              uImage
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +     "loadaddr=0x82000000\0" \
> +     "console=ttyS2,115200n8\0" \
> +     "mmcargs=setenv bootargs console=${console} " \
> +             "root=/dev/mmcblk0p2 rw " \
> +             "rootfstype=ext3 rootwait\0" \
> +     "nandargs=setenv bootargs console=${console} " \
> +             "root=/dev/mtdblock4 rw " \
> +             "rootfstype=jffs2\0" \
> +     "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
> +     "bootscript=echo Running bootscript from mmc ...; " \
> +             "source ${loadaddr}\0" \
> +     "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
> +     "mmcboot=echo Booting from mmc ...; " \
> +             "run mmcargs; " \
> +             "bootm ${loadaddr}\0" \
> +     "nandboot=echo Booting from nand ...; " \
> +             "run nandargs; " \
> +             "nand read ${loadaddr} 280000 400000; " \
> +             "bootm ${loadaddr}\0" \
> +
> +#define CONFIG_BOOTCOMMAND \
> +     "if mmc init; then " \
> +             "if run loadbootscript; then " \
> +                     "run bootscript; " \
> +             "else " \
> +                     "if run loaduimage; then " \
> +                             "run mmcboot; " \
> +                     "else run nandboot; " \
> +                     "fi; " \
> +             "fi; " \
> +     "else run nandboot; fi"
> +
> +#define CONFIG_AUTO_COMPLETE 1
> +/*
> + * Miscellaneous configurable options
> + */
> +#define V_PROMPT                     "AM3517_EVM # "
> +
> +#define CONFIG_SYS_LONGHELP          /* undef to save memory */
> +#define CONFIG_SYS_HUSH_PARSER               /* use "hush" command parser */
> +#define CONFIG_SYS_PROMPT_HUSH_PS2   "> "
> +#define CONFIG_SYS_PROMPT            V_PROMPT
> +#define CONFIG_SYS_CBSIZE            512     /* Console I/O Buffer Size */
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE            (CONFIG_SYS_CBSIZE + \
> +                                     sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS           32      /* max number of command */
> +                                             /* args */
> +/* Boot Argument Buffer Size */
> +#define CONFIG_SYS_BARGSIZE          (CONFIG_SYS_CBSIZE)
> +/* memtest works on */
> +#define CONFIG_SYS_MEMTEST_START     (OMAP34XX_SDRC_CS0)
> +#define CONFIG_SYS_MEMTEST_END               (OMAP34XX_SDRC_CS0 + \
> +                                     0x01F00000) /* 31MB */
> +
> +#define CONFIG_SYS_LOAD_ADDR         (OMAP34XX_SDRC_CS0) /* default load */
> +                                                             /* address */
> +
> +/*
> + * AM3517 has 12 GP timers, they can be driven by the system clock
> + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
> + * This rate is divided by a local divisor.
> + */
> +#define CONFIG_SYS_TIMERBASE         OMAP34XX_GPT2
> +#define CONFIG_SYS_PTV                       2       /* Divisor: 2^(PTV+1) => 8 */
> +#define CONFIG_SYS_HZ                        1000
> +
> +/*-----------------------------------------------------------------------
> + * Stack sizes
> + *
> + * The stack sizes are set up in start.S using the settings below
> + */
> +#define CONFIG_STACKSIZE     (128 << 10)     /* regular stack 128 KiB */
> +#ifdef CONFIG_USE_IRQ
> +#define CONFIG_STACKSIZE_IRQ (4 << 10)       /* IRQ stack 4 KiB */
> +#define CONFIG_STACKSIZE_FIQ (4 << 10)       /* FIQ stack 4 KiB */
> +#endif
> +
> +/*-----------------------------------------------------------------------
> + * Physical Memory Map
> + */
> +#define CONFIG_NR_DRAM_BANKS 2       /* CS1 may or may not be populated */
> +#define PHYS_SDRAM_1         OMAP34XX_SDRC_CS0
> +#define PHYS_SDRAM_1_SIZE    (32 << 20)      /*@least 32 MiB */
> +#define PHYS_SDRAM_2         OMAP34XX_SDRC_CS1
> +
> +/* SDRAM Bank Allocation method */
> +#define SDRC_R_B_C           1
> +
> +/*-----------------------------------------------------------------------
> + * FLASH and environment organization
> + */
> +
> +/* **** PISMO SUPPORT *** */
> +
> +/* Configure the PISMO */
> +#define PISMO1_NAND_SIZE             GPMC_SIZE_128M
> +#define PISMO1_ONEN_SIZE             GPMC_SIZE_128M
> +
> +#define CONFIG_SYS_MAX_FLASH_SECT    520     /* max number of sectors */
> +                                             /* on one chip */
> +#define CONFIG_SYS_MAX_FLASH_BANKS   2       /* max number of flash banks */
> +#define CONFIG_SYS_MONITOR_LEN               (256 << 10)     /* Reserve 2 sectors
> */
> +
> +#define CONFIG_SYS_FLASH_BASE                boot_flash_base
> +
> +/* Monitor at start of flash */
> +#define CONFIG_SYS_MONITOR_BASE              CONFIG_SYS_FLASH_BASE
> +
> +#define CONFIG_NAND_OMAP_GPMC
> +#define GPMC_NAND_ECC_LP_x16_LAYOUT  1
> +#define CONFIG_ENV_IS_IN_NAND                1
> +#define SMNAND_ENV_OFFSET            0x260000 /* environment starts here */
> +
> +#define CONFIG_SYS_ENV_SECT_SIZE     boot_flash_sec
> +#define CONFIG_ENV_OFFSET            boot_flash_off
> +#define CONFIG_ENV_ADDR                      boot_flash_env_addr
> +
> +/*-----------------------------------------------------------------------
> + * CFI FLASH driver setup
> + */
> +/* timeout values are in ticks */
> +#define CONFIG_SYS_FLASH_ERASE_TOUT  (100 * CONFIG_SYS_HZ)
> +#define CONFIG_SYS_FLASH_WRITE_TOUT  (100 * CONFIG_SYS_HZ)
> +
> +/* Flash banks JFFS2 should use */
> +#define CONFIG_SYS_MAX_MTD_BANKS     (CONFIG_SYS_MAX_FLASH_BANKS + \
> +                                     CONFIG_SYS_MAX_NAND_DEVICE)
> +#define CONFIG_SYS_JFFS2_MEM_NAND
> +/* use flash_info[2] */
> +#define CONFIG_SYS_JFFS2_FIRST_BANK  CONFIG_SYS_MAX_FLASH_BANKS
> +#define CONFIG_SYS_JFFS2_NUM_BANKS   1
> +
> +#ifndef __ASSEMBLY__
> +extern unsigned int boot_flash_base;
> +extern volatile unsigned int boot_flash_env_addr;
> +extern unsigned int boot_flash_off;
> +extern unsigned int boot_flash_sec;
> +extern unsigned int boot_flash_type;
> +#endif
> +
> +#endif /* __CONFIG_H */
> --
> 1.6.2.4

[U-Boot] [PATCH-V3 1/2] AM35x: Add support for AM3517EVM

[Wolfgang Denk]

Dear hvaibhav at ti.com,

In message <1273166585-26101-1-git-send-email-hvaibhav@ti.com> you wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> This patch adds basic support for the AM3517EVM.
> It includes:
> 	- Board int file (.c and .h)
> 	- Default configuration file
> 	- Updates for Makefile
> 
> Changes from V2:
> 	- Removed trailing spaces
> 	- Updated MAINTAINERS & MAKEALL for am3517_evm

Such comments do not belong into the commit message. Please place thes
ebelow the "---" line:

> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Sanjeev Premi <premi@ti.com>
> ---

==> Comments should go here.

> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5cbc845..0bc65e1 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -798,6 +798,10 @@ Alex Z
>  	lart		SA1100
>  	dnp1110		SA1110
> 
> +Vaibhav Hiremath <hvaibhav@ti.com>
> +
> +	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
> +

Please keep list sorted.

...
> diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
> index 0c01c73..ffeb982 100644
> --- a/arch/arm/include/asm/arch-omap3/mux.h
> +++ b/arch/arm/include/asm/arch-omap3/mux.h
...
> +/* AM3517 specific */
> +#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
> +#define CONTROL_PADCONF_CCDC_FIELD	0x01E6

Board specific defoinitions should not be added to global header
files. Please use a board specific header instead.

> --- /dev/null
> +++ b/board/logicpd/am3517evm/am3517evm.c
> @@ -0,0 +1,76 @@
...
> +int board_init(void)
> +{
> +	DECLARE_GLOBAL_DATA_PTR;

This is bound to break. DECLARE_GLOBAL_DATA_PTR must always be used on
file scope only; never use this on function scope.  Please check all
your code.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Genius doesn't work on an assembly line basis.  You can't simply say,
"Today I will be brilliant."
	-- Kirk, "The Ultimate Computer", stardate 4731.3

[U-Boot] [PATCH-V3 1/2] AM35x: Add support for AM3517EVM

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Monday, May 31, 2010 3:11 PM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de; tom at bumblecow.com; Paulraj, Sandeep; Premi,
> Sanjeev
> Subject: Re: [PATCH-V3 1/2] AM35x: Add support for AM3517EVM
> 
> Dear hvaibhav at ti.com,
> 
> In message <1273166585-26101-1-git-send-email-hvaibhav@ti.com> you wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > This patch adds basic support for the AM3517EVM.
> > It includes:
> > 	- Board int file (.c and .h)
> > 	- Default configuration file
> > 	- Updates for Makefile
> >
> > Changes from V2:
> > 	- Removed trailing spaces
> > 	- Updated MAINTAINERS & MAKEALL for am3517_evm
> 
> Such comments do not belong into the commit message. Please place thes
> ebelow the "---" line:
> 
[Hiremath, Vaibhav] Ok will incorporate in next post.

> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > Signed-off-by: Sanjeev Premi <premi@ti.com>
> > ---
> 
> ==> Comments should go here.
> 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 5cbc845..0bc65e1 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -798,6 +798,10 @@ Alex Z
> >  	lart		SA1100
> >  	dnp1110		SA1110
> >
> > +Vaibhav Hiremath <hvaibhav@ti.com>
> > +
> > +	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
> > +
> 
> Please keep list sorted.
> 
[Hiremath, Vaibhav] How does this sorted, I could not see any relation between the entries there. 

> ...
> > diff --git a/arch/arm/include/asm/arch-omap3/mux.h
> b/arch/arm/include/asm/arch-omap3/mux.h
> > index 0c01c73..ffeb982 100644
> > --- a/arch/arm/include/asm/arch-omap3/mux.h
> > +++ b/arch/arm/include/asm/arch-omap3/mux.h
> ...
> > +/* AM3517 specific */
> > +#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
> > +#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
> 
> Board specific defoinitions should not be added to global header
> files. Please use a board specific header instead.
> 
[Hiremath, Vaibhav] I think this has been placed at the right place. This is mux definition and got added to mux.h file. You could see all mux definition are present in this file.

Do you see any issues with this?

> > --- /dev/null
> > +++ b/board/logicpd/am3517evm/am3517evm.c
> > @@ -0,0 +1,76 @@
> ...
> > +int board_init(void)
> > +{
> > +	DECLARE_GLOBAL_DATA_PTR;
> 
> This is bound to break. DECLARE_GLOBAL_DATA_PTR must always be used on
> file scope only; never use this on function scope.  
[Hiremath, Vaibhav] Agreed. Actually this code is derived form board/ti/evm/, so followed the same here.

I will change it in next post.

> Please check all
> your code.
> 
[Hiremath, Vaibhav] Do you see any other issues? I don't get this statement.

Thanks,
Vaibhav

> 
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> Genius doesn't work on an assembly line basis.  You can't simply say,
> "Today I will be brilliant."
> 	-- Kirk, "The Ultimate Computer", stardate 4731.3

[U-Boot] [PATCH-V3 1/2] AM35x: Add support for AM3517EVM

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Hiremath, Vaibhav
> Sent: Thursday, June 03, 2010 10:57 PM
> To: 'Wolfgang Denk'
> Cc: u-boot at lists.denx.de; tom at bumblecow.com; Paulraj, Sandeep; Premi,
> Sanjeev
> Subject: RE: [PATCH-V3 1/2] AM35x: Add support for AM3517EVM
> 
[Hiremath, Vaibhav] Denk,

Can you please reply to below queries of mine, so that I can incorporate the changes and submit it again?

Thanks,
Vaibhav

> 
> > -----Original Message-----
> > From: Wolfgang Denk [mailto:wd at denx.de]
> > Sent: Monday, May 31, 2010 3:11 PM
> > To: Hiremath, Vaibhav
> > Cc: u-boot at lists.denx.de; tom at bumblecow.com; Paulraj, Sandeep; Premi,
> > Sanjeev
> > Subject: Re: [PATCH-V3 1/2] AM35x: Add support for AM3517EVM
> >
> > Dear hvaibhav at ti.com,
> >
> > In message <1273166585-26101-1-git-send-email-hvaibhav@ti.com> you wrote:
> > > From: Vaibhav Hiremath <hvaibhav@ti.com>
> > >
> > > This patch adds basic support for the AM3517EVM.
> > > It includes:
> > > 	- Board int file (.c and .h)
> > > 	- Default configuration file
> > > 	- Updates for Makefile
> > >
> > > Changes from V2:
> > > 	- Removed trailing spaces
> > > 	- Updated MAINTAINERS & MAKEALL for am3517_evm
> >
> > Such comments do not belong into the commit message. Please place thes
> > ebelow the "---" line:
> >
> [Hiremath, Vaibhav] Ok will incorporate in next post.
> 
> > > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > > Signed-off-by: Sanjeev Premi <premi@ti.com>
> > > ---
> >
> > ==> Comments should go here.
> >
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index 5cbc845..0bc65e1 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -798,6 +798,10 @@ Alex Z
> > >  	lart		SA1100
> > >  	dnp1110		SA1110
> > >
> > > +Vaibhav Hiremath <hvaibhav@ti.com>
> > > +
> > > +	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
> > > +
> >
> > Please keep list sorted.
> >
> [Hiremath, Vaibhav] How does this sorted, I could not see any relation
> between the entries there.
> 
[Hiremath, Vaibhav] Denk,
> > ...
> > > diff --git a/arch/arm/include/asm/arch-omap3/mux.h
> > b/arch/arm/include/asm/arch-omap3/mux.h
> > > index 0c01c73..ffeb982 100644
> > > --- a/arch/arm/include/asm/arch-omap3/mux.h
> > > +++ b/arch/arm/include/asm/arch-omap3/mux.h
> > ...
> > > +/* AM3517 specific */
> > > +#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
> > > +#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
> >
> > Board specific defoinitions should not be added to global header
> > files. Please use a board specific header instead.
> >
> [Hiremath, Vaibhav] I think this has been placed at the right place. This is
> mux definition and got added to mux.h file. You could see all mux definition
> are present in this file.
> 
> Do you see any issues with this?
> 
> > > --- /dev/null
> > > +++ b/board/logicpd/am3517evm/am3517evm.c
> > > @@ -0,0 +1,76 @@
> > ...
> > > +int board_init(void)
> > > +{
> > > +	DECLARE_GLOBAL_DATA_PTR;
> >
> > This is bound to break. DECLARE_GLOBAL_DATA_PTR must always be used on
> > file scope only; never use this on function scope.
> [Hiremath, Vaibhav] Agreed. Actually this code is derived form
> board/ti/evm/, so followed the same here.
> 
> I will change it in next post.
> 
> > Please check all
> > your code.
> >
> [Hiremath, Vaibhav] Do you see any other issues? I don't get this statement.
> 
> Thanks,
> Vaibhav
> 
> >
> > Best regards,
> >
> > Wolfgang Denk
> >
> > --
> > DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> > Genius doesn't work on an assembly line basis.  You can't simply say,
> > "Today I will be brilliant."
> > 	-- Kirk, "The Ultimate Computer", stardate 4731.3

[U-Boot] [PATCH-V3 1/2] AM35x: Add support for AM3517EVM

[Wolfgang Denk]

Dear "Hiremath, Vaibhav",

In message <19F8576C6E063C45BE387C64729E7394044E7A16B5@dbde02.ent.ti.com> you wrote:
...
> > > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > > index 5cbc845..0bc65e1 100644
> > > > --- a/MAINTAINERS
> > > > +++ b/MAINTAINERS
> > > > @@ -798,6 +798,10 @@ Alex Z
> > > >  	lart		SA1100
> > > >  	dnp1110		SA1110
> > > >
> > > > +Vaibhav Hiremath <hvaibhav@ti.com>
> > > > +
> > > > +	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
> > > > +
> > >
> > > Please keep list sorted.
> > >
> > [Hiremath, Vaibhav] How does this sorted, I could not see any relation
> > between the entries there.

The list is sorted alphabetically by maintainer' last names, and then
by CPU / board names.

> > > > diff --git a/arch/arm/include/asm/arch-omap3/mux.h
> > > b/arch/arm/include/asm/arch-omap3/mux.h
> > > > index 0c01c73..ffeb982 100644
> > > > --- a/arch/arm/include/asm/arch-omap3/mux.h
> > > > +++ b/arch/arm/include/asm/arch-omap3/mux.h
> > > ...
> > > > +/* AM3517 specific */
> > > > +#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
> > > > +#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
> > >
> > > Board specific defoinitions should not be added to global header
> > > files. Please use a board specific header instead.
> > >
> > [Hiremath, Vaibhav] I think this has been placed at the right place. This is
> > mux definition and got added to mux.h file. You could see all mux definition
> > are present in this file.
> > 
> > Do you see any issues with this?

Yes, as I wrote: board specific definitions should not be added to
global header files. They should be added to board specific files
only, avoiding the need for tons of #ifdef's in global files.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When you die, the first thing you lose is your life. The  next  thing
is the illusions.                       - Terry Pratchett, _Pyramids_

[U-Boot] [PATCH-V3 1/2] AM35x: Add support for AM3517EVM

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Monday, June 07, 2010 5:55 PM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de; tom at bumblecow.com; Paulraj, Sandeep; Premi,
> Sanjeev
> Subject: Re: [PATCH-V3 1/2] AM35x: Add support for AM3517EVM
> 
> Dear "Hiremath, Vaibhav",
> 
> In message <19F8576C6E063C45BE387C64729E7394044E7A16B5@dbde02.ent.ti.com>
> you wrote:
> ...
> > > > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > > > index 5cbc845..0bc65e1 100644
> > > > > --- a/MAINTAINERS
> > > > > +++ b/MAINTAINERS
> > > > > @@ -798,6 +798,10 @@ Alex Z
> > > > >  	lart		SA1100
> > > > >  	dnp1110		SA1110
> > > > >
> > > > > +Vaibhav Hiremath <hvaibhav@ti.com>
> > > > > +
> > > > > +	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
> > > > > +
> > > >
> > > > Please keep list sorted.
> > > >
> > > [Hiremath, Vaibhav] How does this sorted, I could not see any relation
> > > between the entries there.
> 
> The list is sorted alphabetically by maintainer' last names, and then
> by CPU / board names.
> 
[Hiremath, Vaibhav] Thanks, I will update the patch and submit is shortly.

> > > > > diff --git a/arch/arm/include/asm/arch-omap3/mux.h
> > > > b/arch/arm/include/asm/arch-omap3/mux.h
> > > > > index 0c01c73..ffeb982 100644
> > > > > --- a/arch/arm/include/asm/arch-omap3/mux.h
> > > > > +++ b/arch/arm/include/asm/arch-omap3/mux.h
> > > > ...
> > > > > +/* AM3517 specific */
> > > > > +#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
> > > > > +#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
> > > >
> > > > Board specific defoinitions should not be added to global header
> > > > files. Please use a board specific header instead.
> > > >
> > > [Hiremath, Vaibhav] I think this has been placed at the right place.
> This is
> > > mux definition and got added to mux.h file. You could see all mux
> definition
> > > are present in this file.
> > >
> > > Do you see any issues with this?
> 
> Yes, as I wrote: board specific definitions should not be added to
> global header files. They should be added to board specific files
> only, avoiding the need for tons of #ifdef's in global files.
> 
[Hiremath, Vaibhav] Yes I agree this has to be there in board header file, but I don't think we are using #ifdefs anywhere for this, since the usage of this is happening through board header file.

I am moving these definitions to board/logicpd/am3517evm/am3517evm.h file.

Thanks,
Vaibhav
> 
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> When you die, the first thing you lose is your life. The  next  thing
> is the illusions.                       - Terry Pratchett, _Pyramids_

[U-Boot] [PATCH-V3 2/2] AM35x: Add support for EMIF4

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

This patch adds support for the EMIF4 interface
available in the AM35x processors.

Changes from V2:
	- Removed all instances of #ifdef CONFIG_EMIF4

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 arch/arm/cpu/arm_cortexa8/omap3/Makefile    |    1 +
 arch/arm/cpu/arm_cortexa8/omap3/emif4.c     |  168 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/cpu.h       |   24 ++++
 arch/arm/include/asm/arch-omap3/emif4.h     |   79 +++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 include/configs/am3517_evm.h                |    2 +-
 6 files changed, 274 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/emif4.c
 create mode 100644 arch/arm/include/asm/arch-omap3/emif4.h

diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
index 1e80eb3..d25bfd5 100644
--- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
+++ b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
@@ -38,6 +38,7 @@ COBJS	+= sys_info.o
 COBJS	+= timer.o

 COBJS-$(CONFIG_SDRC)	+= sdrc.o
+COBJS-$(CONFIG_EMIF4)	+=emif4.o

 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/arm_cortexa8/omap3/emif4.c b/arch/arm/cpu/arm_cortexa8/omap3/emif4.c
new file mode 100644
index 0000000..fae5b11
--- /dev/null
+++ b/arch/arm/cpu/arm_cortexa8/omap3/emif4.c
@@ -0,0 +1,168 @@
+/*
+ * Author :
+ *     Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on mem.c and sdrc.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/emif4.h>
+
+extern omap3_sysinfo sysinfo;
+
+static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
+
+/*
+ * is_mem_sdr -
+ *  - Return 1 if mem type in use is SDR
+ */
+u32 is_mem_sdr(void)
+{
+	return 0;
+}
+
+/*
+ * get_sdr_cs_size -
+ *  - Get size of chip select 0/1
+ */
+u32 get_sdr_cs_size(u32 cs)
+{
+	u32 size;
+
+	/* TODO: Calculate the size based on EMIF4 configuration */
+	size = CONFIG_SYS_CS0_SIZE;
+
+	return size;
+}
+
+/*
+ * get_sdr_cs_offset -
+ *  - Get offset of cs from cs0 start
+ */
+u32 get_sdr_cs_offset(u32 cs)
+{
+	u32 offset = 0;
+
+	return offset;
+}
+
+/*
+ * do_emif4_init -
+ *  - Init the emif4 module for DDR access
+ *  - Early init routines, called from flash or SRAM.
+ */
+void do_emif4_init(void)
+{
+	unsigned int regval;
+	/* Set the DDR PHY parameters in PHY ctrl registers */
+	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
+		EMIF4_DDR1_EXT_STRB_DIS);
+	writel(regval, &emif4_base->ddr_phyctrl1);
+	writel(regval, &emif4_base->ddr_phyctrl1_shdw);
+	writel(0, &emif4_base->ddr_phyctrl2);
+
+	/* Reset the DDR PHY and wait till completed */
+	regval = readl(&emif4_base->sdram_iodft_tlgc);
+	regval |= (1<<10);
+	writel(regval, &emif4_base->sdram_iodft_tlgc);
+	/*Wait till that bit clears*/
+	while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1);
+	/*Re-verify the DDR PHY status*/
+	while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
+
+	regval |= (1<<0);
+	writel(regval, &emif4_base->sdram_iodft_tlgc);
+	/* Set SDR timing registers */
+	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
+		EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
+		EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
+		EMIF4_TIM1_T_RP);
+	writel(regval, &emif4_base->sdram_time1);
+	writel(regval, &emif4_base->sdram_time1_shdw);
+
+	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
+		EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
+		EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
+	writel(regval, &emif4_base->sdram_time2);
+	writel(regval, &emif4_base->sdram_time2_shdw);
+
+	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
+	writel(regval, &emif4_base->sdram_time3);
+	writel(regval, &emif4_base->sdram_time3_shdw);
+
+	/* Set the PWR control register */
+	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
+		EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
+	writel(regval, &emif4_base->sdram_pwr_mgmt);
+	writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
+
+	/* Set the DDR refresh rate control register */
+	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
+	writel(regval, &emif4_base->sdram_refresh_ctrl);
+	writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
+
+	/* set the SDRAM configuration register */
+	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
+		EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
+		EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
+		EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
+		EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
+		EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
+	writel(regval, &emif4_base->sdram_config);
+}
+
+/*
+ * dram_init -
+ *  - Sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int size0 = 0, size1 = 0;
+
+	size0 = get_sdr_cs_size(CS0);
+	/*
+	 * If a second bank of DDR is attached to CS1 this is
+	 * where it can be started.  Early init code will init
+	 * memory on CS0.
+	 */
+	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
+		size1 = get_sdr_cs_size(CS1);
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = size0;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+	gd->bd->bi_dram[1].size = size1;
+
+	return 0;
+}
+
+/*
+ * mem_init() -
+ *  - Initialize memory subsystem
+ */
+void mem_init(void)
+{
+	do_emif4_init();
+}
diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h
index ce16da7..c072c27 100644
--- a/arch/arm/include/asm/arch-omap3/cpu.h
+++ b/arch/arm/include/asm/arch-omap3/cpu.h
@@ -216,6 +216,30 @@ struct sdrc {
 	struct sdrc_cs cs[2];	/* 0x80 || 0xB0 */
 };

+/* EMIF4 */
+typedef struct emif4 {
+	unsigned int sdram_sts;
+	unsigned int sdram_config;
+	unsigned int res1;
+	unsigned int sdram_refresh_ctrl;
+	unsigned int sdram_refresh_ctrl_shdw;
+	unsigned int sdram_time1;
+	unsigned int sdram_time1_shdw;
+	unsigned int sdram_time2;
+	unsigned int sdram_time2_shdw;
+	unsigned int sdram_time3;
+	unsigned int sdram_time3_shdw;
+	unsigned char res2[8];
+	unsigned int sdram_pwr_mgmt;
+	unsigned int sdram_pwr_mgmt_shdw;
+	unsigned char res3[32];
+	unsigned int sdram_iodft_tlgc;
+	unsigned char res4[128];
+	unsigned int ddr_phyctrl1;
+	unsigned int ddr_phyctrl1_shdw;
+	unsigned int ddr_phyctrl2;
+} emif4_t;
+
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */

diff --git a/arch/arm/include/asm/arch-omap3/emif4.h b/arch/arm/include/asm/arch-omap3/emif4.h
new file mode 100644
index 0000000..579da0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap3/emif4.h
@@ -0,0 +1,79 @@
+/*
+ * Auther:
+ *       Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+
+/*
+ * Configuration values
+ */
+#define EMIF4_TIM1_T_RP		(0x3 << 25)
+#define EMIF4_TIM1_T_RCD	(0x3 << 21)
+#define EMIF4_TIM1_T_WR		(0x3 << 17)
+#define EMIF4_TIM1_T_RAS	(0x8 << 12)
+#define EMIF4_TIM1_T_RC		(0xA << 6)
+#define EMIF4_TIM1_T_RRD	(0x2 << 3)
+#define EMIF4_TIM1_T_WTR	(0x2)
+
+#define EMIF4_TIM2_T_XP		(0x2 << 28)
+#define EMIF4_TIM2_T_ODT	(0x0 << 25)
+#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
+#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
+#define EMIF4_TIM2_T_RTP	(0x1 << 3)
+#define EMIF4_TIM2_T_CKE	(0x2)
+
+#define EMIF4_TIM3_T_RFC	(0x25 << 4)
+#define EMIF4_TIM3_T_RAS_MAX	(0x7)
+
+#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
+#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
+#define EMIF4_PWR_DPD_EN	(0x1 << 10)
+#define EMIF4_PWR_LP_MODE	(0x0 << 8)
+#define EMIF4_PWR_PM_TIM	(0x0)
+
+#define EMIF4_INITREF_DIS	(0x0 << 31)
+#define EMIF4_REFRESH_RATE	(0x50F)
+
+#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
+#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
+#define EMIF4_CFG_DDR_TERM	(0x0 << 24)
+#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
+#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
+#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
+#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
+#define EMIF4_CFG_CL		(0x5 << 10)
+#define EMIF4_CFG_ROWSIZE	(0x0 << 7)
+#define EMIF4_CFG_IBANK		(0x3 << 4)
+#define EMIF4_CFG_EBANK		(0x0 << 3)
+#define EMIF4_CFG_PGSIZE	(0x2)
+
+/*
+ * EMIF4 PHY Control 1 register configuration
+ */
+#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
+#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
+#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
+#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
+#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
+
+#endif /* endif _EMIF_H_ */
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 4608f30..db7b42a 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -33,6 +33,7 @@ void per_clocks_enable(void);
 void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+void emif4_init(void);
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 			u32 size);
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 63f853a..0106031 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -33,7 +33,7 @@
 #define CONFIG_OMAP34XX		1	/* which is a 34XX */
 #define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */

-#define CONFIG_EMIF4		1	/* The chip has EMIF4 controller */
+#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <asm/arch/omap3.h>
--
1.6.2.4

[U-Boot] [PATCH-V3 2/2] AM35x: Add support for EMIF4

[Wolfgang Denk]

Dear hvaibhav at ti.com,

In message <1273166585-26101-2-git-send-email-hvaibhav@ti.com> you wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> This patch adds support for the EMIF4 interface
> available in the AM35x processors.
> 
> Changes from V2:
> 	- Removed all instances of #ifdef CONFIG_EMIF4

See previeos comment - such comments belong below the "---" line and
not into the commit message.

> diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> index 1e80eb3..d25bfd5 100644
> --- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> +++ b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> @@ -38,6 +38,7 @@ COBJS	+= sys_info.o
>  COBJS	+= timer.o
> 
>  COBJS-$(CONFIG_SDRC)	+= sdrc.o
> +COBJS-$(CONFIG_EMIF4)	+=emif4.o

Please keep lists sorted.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The complexity of software is an essential property, not an  acciden-
tal  one. Hence, descriptions of a software entity that abstract away
its complexity often abstract away its essence.    - Fred Brooks, Jr.

[U-Boot] [PATCH-V3 2/2] AM35x: Add support for EMIF4

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Wolfgang Denk [mailto:wd at denx.de]
> Sent: Monday, May 31, 2010 3:14 PM
> To: Hiremath, Vaibhav
> Cc: u-boot at lists.denx.de; tom at bumblecow.com; Paulraj, Sandeep; Premi,
> Sanjeev
> Subject: Re: [PATCH-V3 2/2] AM35x: Add support for EMIF4
> 
> Dear hvaibhav at ti.com,
> 
> In message <1273166585-26101-2-git-send-email-hvaibhav@ti.com> you wrote:
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > This patch adds support for the EMIF4 interface
> > available in the AM35x processors.
> >
> > Changes from V2:
> > 	- Removed all instances of #ifdef CONFIG_EMIF4
> 
> See previeos comment - such comments belong below the "---" line and
> not into the commit message.
> 
[Hiremath, Vaibhav] OK, I will incorporate changes in next post.

> > diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> > index 1e80eb3..d25bfd5 100644
> > --- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> > +++ b/arch/arm/cpu/arm_cortexa8/omap3/Makefile
> > @@ -38,6 +38,7 @@ COBJS	+= sys_info.o
> >  COBJS	+= timer.o
> >
> >  COBJS-$(CONFIG_SDRC)	+= sdrc.o
> > +COBJS-$(CONFIG_EMIF4)	+=emif4.o
> 
> Please keep lists sorted.
> 
[Hiremath, Vaibhav] Will change and submit it again.

Thanks,
Vaibhav

> 
> Best regards,
> 
> Wolfgang Denk
> 
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> The complexity of software is an essential property, not an  acciden-
> tal  one. Hence, descriptions of a software entity that abstract away
> its complexity often abstract away its essence.    - Fred Brooks, Jr.

[U-Boot] [PATCH-V4 1/2] AM35x: Add support for AM3517EVM

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

This patch adds basic support for the AM3517EVM.
It includes:
	- Board files (.c and .h)
	- Default configuration file
	- Updates for Makefile

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
---
Changes from V2:
	- Removed trailing spaces
	- Updated MAINTAINERS & MAKEALL for am3517_evm
Changes from V3:
	- Corrected Maintainer entry to keep list sorted
	- Moved AM3537 macros to board header file

 MAINTAINERS                         |    4 +
 MAKEALL                             |    1 +
 Makefile                            |    3 +
 board/logicpd/am3517evm/Makefile    |   46 ++++
 board/logicpd/am3517evm/am3517evm.c |   76 ++++++
 board/logicpd/am3517evm/am3517evm.h |  445 +++++++++++++++++++++++++++++++++++
 board/logicpd/am3517evm/config.mk   |   30 +++
 include/configs/am3517_evm.h        |  296 +++++++++++++++++++++++
 8 files changed, 901 insertions(+), 0 deletions(-)
 create mode 100644 board/logicpd/am3517evm/Makefile
 create mode 100644 board/logicpd/am3517evm/am3517evm.c
 create mode 100644 board/logicpd/am3517evm/am3517evm.h
 create mode 100644 board/logicpd/am3517evm/config.mk
 create mode 100644 include/configs/am3517_evm.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 7a13d28..3f9df78 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -600,6 +600,10 @@ Kshitij Gupta <kshitij@ti.com>
 	omap1510inn	ARM925T
 	omap1610inn	ARM926EJS

+Vaibhav Hiremath <hvaibhav@ti.com>
+
+	am3517_evm	ARM CORTEX-A8 (AM35x SoC)
+
 Grazvydas Ignotas <notasas@gmail.com>

 	omap3_pandora	ARM CORTEX-A8 (OMAP3xx SoC)
diff --git a/MAKEALL b/MAKEALL
index 2527352..2066587 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -641,6 +641,7 @@ LIST_ARM11="			\
 ## ARM Cortex-A8 Systems
 #########################################################################
 LIST_ARM_CORTEX_A8="		\
+	am3517_evm		\
 	devkit8000		\
 	mx51evk			\
 	omap3_beagle		\
diff --git a/Makefile b/Makefile
index c26e491..b935c1a 100644
--- a/Makefile
+++ b/Makefile
@@ -3155,6 +3155,9 @@ SMN42_config	:	unconfig
 ## ARM CORTEX Systems
 #########################################################################

+am3517_evm_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 am3517evm logicpd omap3
+
 devkit8000_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 devkit8000 timll omap3

diff --git a/board/logicpd/am3517evm/Makefile b/board/logicpd/am3517evm/Makefile
new file mode 100644
index 0000000..3a6b1a1
--- /dev/null
+++ b/board/logicpd/am3517evm/Makefile
@@ -0,0 +1,46 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Based on ti/evm/Makefile
+#
+# Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= am3517evm.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
new file mode 100644
index 0000000..bbb6e83
--- /dev/null
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -0,0 +1,76 @@
+/*
+ * am3517evm.c - board file for TI's AM3517 family of devices.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include <i2c.h>
+#include "am3517evm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3517EVM;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Init i2c, ethernet, etc... (done here so udelay works)
+ */
+int misc_init_r(void)
+{
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_AM3517EVM();
+}
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h
new file mode 100644
index 0000000..3d74ef1
--- /dev/null
+++ b/board/logicpd/am3517evm/am3517evm.h
@@ -0,0 +1,445 @@
+/*
+ * am3517evm.h - Header file for the AM3517 EVM.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on ti/evm/evm.h
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _AM3517EVM_H_
+#define _AM3517EVM_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"AM3517EVM Board",
+	"NAND",
+};
+/* AM3517 specific mux configuration */
+#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
+/* CCDC */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
+#define CONTROL_PADCONF_CCDC_HD		0x01E8
+#define CONTROL_PADCONF_CCDC_VD		0x01EA
+#define CONTROL_PADCONF_CCDC_WEN	0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0	0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1	0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2	0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3	0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4	0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5	0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6	0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7	0x01FC
+/* RMII */
+#define CONTROL_PADCONF_RMII_MDIO_DATA	0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK	0x0200
+#define CONTROL_PADCONF_RMII_RXD0	0x0202
+#define CONTROL_PADCONF_RMII_RXD1	0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV	0x0206
+#define CONTROL_PADCONF_RMII_RXER	0x0208
+#define CONTROL_PADCONF_RMII_TXD0	0x020A
+#define CONTROL_PADCONF_RMII_TXD1	0x020C
+#define CONTROL_PADCONF_RMII_TXEN	0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK	0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS	0x0212
+/* CAN */
+#define CONTROL_PADCONF_HECC1_TXD	0x0214
+#define CONTROL_PADCONF_HECC1_RXD	0x0216
+
+#define CONTROL_PADCONF_SYS_BOOT7	0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N	0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N	0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N	0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N	0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0	0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1	0x0224
+#define CONTROL_PADCONF_SYS_BOOT8	0x0226
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_AM3517EVM() \
+	/* SDRC */\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
+	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
+	/*sdrc_strben_dly0*/\
+	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
+	 /*sdrc_strben_dly1*/\
+	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
+	/* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)) /*GPIO_64*/\
+							 /* - ETH_nRESET*/\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) \
+	/* DSS */\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA0),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA1),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA2),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA8),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA9),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA16),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA17),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA18),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
+	/* CAMERA */\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_XCLKA),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CAM_FLD),		(IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+							 /* - CAM_RESET*/\
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_XCLKB),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+	MUX_VAL(CP(CAM_STROBE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | DIS | M0)) \
+	/* MMC */\
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
+	/* WriteProtect */\
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) /*CardDetect*/\
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
+	\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MMC2_CMD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTD | DIS | M0)) \
+	/* McBSP */\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP2_DX),		(IDIS | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP3_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) /*GPIO_152*/\
+							 /* - LCD_INI*/\
+	MUX_VAL(CP(MCBSP4_DR),		(IDIS | PTD | DIS | M4)) /*GPIO_153*/\
+							 /* - LCD_ENVDD */\
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) /*GPIO_154*/\
+							 /* - LCD_QVGA/nVGA */\
+	MUX_VAL(CP(MCBSP4_FSX),		(IDIS | PTD | DIS | M4)) /*GPIO_155*/\
+							 /* - LCD_RESB */\
+	/* UART */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
+	/* I2C */\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
+	/* McSPI */\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTD | EN  | M4)) /*GPIO_175*/\
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | DIS | M4)) /*GPIO_176*/\
+							 /* - LAN_INTR*/\
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | EN  | M4)) \
+	/* CCDC */\
+	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_HD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_VD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | DIS | M1)) \
+	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | DIS | M0)) \
+	/* RMII */\
+	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
+	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
+	MUX_VAL(CP(RMII_RXD0)	,	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
+	/* HECC */\
+	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTU | EN  | M0)) \
+	/* HSUSB */\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
+	/* HDQ */\
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTU | EN  | M0)) \
+	/* Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M0)) \
+	/*SYS_nRESWARM */\
+	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | DIS | M4)) \
+							/* - GPIO30 */\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) /*GPIO_2*/\
+							 /* - PEN_IRQ */\
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) /*GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) /*GPIO_4*/\
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) /*GPIO_5*/\
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) /*GPIO_6*/\
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4)) /*GPIO_7*/\
+	MUX_VAL(CP(SYS_BOOT6),		(IDIS | PTD | DIS | M4)) /*GPIO_8*/\
+							 /* - VIO_1V8*/\
+	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | EN  | M0)) \
+	\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT2),	(IEN  | PTU | EN  | M0)) \
+	/* JTAG */\
+	MUX_VAL(CP(JTAG_nTRST),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_TDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(JTAG_EMU1),		(IEN  | PTD | DIS | M0)) \
+	/* ETK (ES2 onwards) */\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M0)) \
+	/* Die to Die */\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+
+#endif
diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk
new file mode 100644
index 0000000..f7a35ce
--- /dev/null
+++ b/board/logicpd/am3517evm/config.mk
@@ -0,0 +1,30 @@
+#
+# Author: Vaibhav Hiremath <hvaibhav@ti.com>
+#
+# Based on ti/evm/config.mk
+#
+# Copyright (C) 2010
+# Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
new file mode 100644
index 0000000..595b99c
--- /dev/null
+++ b/include/configs/am3517_evm.h
@@ -0,0 +1,296 @@
+/*
+ * am3517_evm.h - Default configuration for AM3517 EVM board.
+ *
+ * Author: Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on omap3_evm_config.h
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */
+
+#define CONFIG_EMIF4		1	/* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ				/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+/*
+ * DDR related
+ */
+#define CONFIG_OMAP3_MICRON_DDR		1	/* Micron DDR */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 on AM3517 EVM */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+#undef CONFIG_CMD_NET
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_BOOTFILE		uImage
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyS2,115200n8\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc init; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT			"AM3517_EVM # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		32	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	(4 << 10)	/* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ	(4 << 10)	/* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
+						/* on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor@start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			boot_flash_env_addr
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#ifndef __ASSEMBLY__
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */
--
1.6.2.4

[U-Boot] [PATCH-V4 1/2] AM35x: Add support for AM3517EVM

[Paulraj, Sandeep]

> 
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> This patch adds basic support for the AM3517EVM.
> It includes:
> 	- Board files (.c and .h)
> 	- Default configuration file
> 	- Updates for Makefile
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Sanjeev Premi <premi@ti.com>
> ---
> Changes from V2:
> 	- Removed trailing spaces
> 	- Updated MAINTAINERS & MAKEALL for am3517_evm
> Changes from V3:
> 	- Corrected Maintainer entry to keep list sorted
> 	- Moved AM3537 macros to board header file
> 
>  MAINTAINERS                         |    4 +
>  MAKEALL                             |    1 +
>  Makefile                            |    3 +
>  board/logicpd/am3517evm/Makefile    |   46 ++++
>  board/logicpd/am3517evm/am3517evm.c |   76 ++++++
>  board/logicpd/am3517evm/am3517evm.h |  445
> +++++++++++++++++++++++++++++++++++
>  board/logicpd/am3517evm/config.mk   |   30 +++
>  include/configs/am3517_evm.h        |  296 +++++++++++++++++++++++
>  8 files changed, 901 insertions(+), 0 deletions(-)
>  create mode 100644 board/logicpd/am3517evm/Makefile
>  create mode 100644 board/logicpd/am3517evm/am3517evm.c
>  create mode 100644 board/logicpd/am3517evm/am3517evm.h
>  create mode 100644 board/logicpd/am3517evm/config.mk
>  create mode 100644 include/configs/am3517_evm.h

I have pushed the following to u-boot-ti AFTER running MAKEALL for ALL
CORTEX AB boards

I pushed the following patches. There were some checkpatch errors. I fixed them myself.

[PATCH-V4 1/2] AM35x: Add support for AM3517EVM
[PATCH-V4 2/2] AM35x: Add support for EMIF4

[PATCH-V3 1/2] omap3: Calculate CS1 size only when SDRC is initialized for CS1
[PATCH-V3 2/2] omap3: Consolidate SDRC related operations

[PATCH-V4] OMAP3EVM: Added NAND support

Thanks,
Sandeep

[U-Boot] [PATCH] AM3517:Fix for ARM Relocation support

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

Also change the CONFIG_SYS_TEXT_BASE to 0x80008000, required
with relocation support. This is the load address for primary
boot loader (x-loader).

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 board/logicpd/am3517evm/config.mk |    2 +-
 include/configs/am3517_evm.h      |    6 ++++++
 2 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk
index 102d32b..71ec5d0 100644
--- a/board/logicpd/am3517evm/config.mk
+++ b/board/logicpd/am3517evm/config.mk
@@ -27,4 +27,4 @@
 # (mem base + reserved)
 
 # For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80e80000
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 9a9ba88..3dda1e9 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -330,4 +330,10 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif
 
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #endif /* __CONFIG_H */
-- 
1.6.2.4

[U-Boot] [PATCH] AM3517:Fix for ARM Relocation support

[Hiremath, Vaibhav]

> -----Original Message-----
> From: Hiremath, Vaibhav
> Sent: Monday, November 29, 2010 9:52 PM
> To: u-boot at lists.denx.de
> Cc: albert at aribaud.net; Paulraj, Sandeep; Hiremath, Vaibhav
> Subject: [PATCH] AM3517:Fix for ARM Relocation support
> 
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> Also change the CONFIG_SYS_TEXT_BASE to 0x80008000, required
> with relocation support. This is the load address for primary
> boot loader (x-loader).
> 
[Hiremath, Vaibhav] Albert, Denk and Sandeep,

I have tested this patch with Makefile change (remove sorting of $LIB) on AM3517EVM.

Thanks,
Vaibhav

> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
>  board/logicpd/am3517evm/config.mk |    2 +-
>  include/configs/am3517_evm.h      |    6 ++++++
>  2 files changed, 7 insertions(+), 1 deletions(-)
> 
> diff --git a/board/logicpd/am3517evm/config.mk
> b/board/logicpd/am3517evm/config.mk
> index 102d32b..71ec5d0 100644
> --- a/board/logicpd/am3517evm/config.mk
> +++ b/board/logicpd/am3517evm/config.mk
> @@ -27,4 +27,4 @@
>  # (mem base + reserved)
> 
>  # For use with external or internal boots.
> -CONFIG_SYS_TEXT_BASE = 0x80e80000
> +CONFIG_SYS_TEXT_BASE = 0x80008000
> diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
> index 9a9ba88..3dda1e9 100644
> --- a/include/configs/am3517_evm.h
> +++ b/include/configs/am3517_evm.h
> @@ -330,4 +330,10 @@ extern unsigned int boot_flash_sec;
>  extern unsigned int boot_flash_type;
>  #endif
> 
> +#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
> +#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
> +#define CONFIG_SYS_INIT_RAM_SIZE	0x800
> +#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
> +					 CONFIG_SYS_INIT_RAM_SIZE - \
> +					 GENERATED_GBL_DATA_SIZE)
>  #endif /* __CONFIG_H */
> --
> 1.6.2.4

[U-Boot] [PATCH] AM3517:Fix for ARM Relocation support

[Paulraj, Sandeep]

> 
> > -----Original Message-----
> > From: Hiremath, Vaibhav
> > Sent: Monday, November 29, 2010 9:52 PM
> > To: u-boot at lists.denx.de
> > Cc: albert at aribaud.net; Paulraj, Sandeep; Hiremath, Vaibhav
> > Subject: [PATCH] AM3517:Fix for ARM Relocation support
> >
> > From: Vaibhav Hiremath <hvaibhav@ti.com>
> >
> > Also change the CONFIG_SYS_TEXT_BASE to 0x80008000, required
> > with relocation support. This is the load address for primary
> > boot loader (x-loader).
> >
> [Hiremath, Vaibhav] Albert, Denk and Sandeep,

Thanks,

I will apply this set to u-boot-ti/master sometime tonight and send a pull request to Wolfgang.



> 
> I have tested this patch with Makefile change (remove sorting of $LIB) on
> AM3517EVM.
> 
> Thanks,
> Vaibhav

Regards,
Sandeep

[U-Boot] [PATCH] AM3517:Build FIX: undef CONFIG_CMD_NFS support

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

Without CONFIG_CMD_NET support CONFIG_CMD_NFS leads
to linking error, so disable CONFIG_CMD_NFS option.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 include/configs/am3517_evm.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 3dda1e9..70e8f07 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -163,6 +163,7 @@
 #define CONFIG_DRIVER_OMAP34XX_I2C	1
 
 #undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
 /*
  * Board NAND Info.
  */
-- 
1.6.2.4

[U-Boot] [PATCH] AM3517:Build FIX: undef CONFIG_CMD_NFS support

[Paulraj, Sandeep]

> 
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> Without CONFIG_CMD_NET support CONFIG_CMD_NFS leads
> to linking error, so disable CONFIG_CMD_NFS option.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
>  include/configs/am3517_evm.h |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
> index 3dda1e9..70e8f07 100644
> --- a/include/configs/am3517_evm.h
> +++ b/include/configs/am3517_evm.h
> @@ -163,6 +163,7 @@
>  #define CONFIG_DRIVER_OMAP34XX_I2C	1
> 
>  #undef CONFIG_CMD_NET
> +#undef CONFIG_CMD_NFS
>  /*
>   * Board NAND Info.
>   */
> --
> 1.6.2.4
Pushed to u-boot-ti

[U-Boot] [PATCH] AM3517:EMIF4: fix SDRAM size to 256Mb

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

With addition of "dram_init_banksize()" function from Heiko,Schocher
(commit ID: 561142af20f1fd7b425d9425730014e656defb91), the DRAM size
is getting configured wrongly to 512Mb (CS0 & CS1).
So fix it to 256Mb.

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
---
 arch/arm/cpu/armv7/omap3/emif4.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c
index 0870857..2227576 100644
--- a/arch/arm/cpu/armv7/omap3/emif4.c
+++ b/arch/arm/cpu/armv7/omap3/emif4.c
@@ -48,10 +48,11 @@ u32 is_mem_sdr(void)
  */
 u32 get_sdr_cs_size(u32 cs)
 {
-	u32 size;
+	u32 size = 0;
 
 	/* TODO: Calculate the size based on EMIF4 configuration */
-	size = CONFIG_SYS_CS0_SIZE;
+	if (cs == CS0)
+		size = CONFIG_SYS_CS0_SIZE;
 
 	return size;
 }
-- 
1.6.2.4

[U-Boot] [PATCH] AM3517:EMIF4: fix SDRAM size to 256Mb

[Paulraj, Sandeep]

> 
> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> With addition of "dram_init_banksize()" function from Heiko,Schocher
> (commit ID: 561142af20f1fd7b425d9425730014e656defb91), the DRAM size
> is getting configured wrongly to 512Mb (CS0 & CS1).
> So fix it to 256Mb.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
Pushed to u-boot-ti

[U-Boot] [PATCH] AM3517:EMIF4: fix SDRAM size to 256Mb

[Paulraj, Sandeep]

> From: Vaibhav Hiremath <hvaibhav@ti.com>
> 
> With addition of "dram_init_banksize()" function from Heiko,Schocher
> (commit ID: 561142af20f1fd7b425d9425730014e656defb91), the DRAM size
> is getting configured wrongly to 512Mb (CS0 & CS1).
> So fix it to 256Mb.
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> ---
>  arch/arm/cpu/armv7/omap3/emif4.c |    5 +++--
>  1 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/omap3/emif4.c
> b/arch/arm/cpu/armv7/omap3/emif4.c
> index 0870857..2227576 100644
> --- a/arch/arm/cpu/armv7/omap3/emif4.c
> +++ b/arch/arm/cpu/armv7/omap3/emif4.c
> @@ -48,10 +48,11 @@ u32 is_mem_sdr(void)
>   */
>  u32 get_sdr_cs_size(u32 cs)
>  {
> -	u32 size;
> +	u32 size = 0;
> 
>  	/* TODO: Calculate the size based on EMIF4 configuration */
> -	size = CONFIG_SYS_CS0_SIZE;
> +	if (cs == CS0)
> +		size = CONFIG_SYS_CS0_SIZE;
> 
>  	return size;
>  }
> --
> 1.6.2.4

Pushed to u-boot-ti

[U-Boot] [PATCH] omap3evm: Use generic MMC driver

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

Switch from the legacy mmc driver to the
new generic mmc driver.

This patch is based on similar patch for beagle[1].

 [1] http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=0cd31144240

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 board/ti/evm/evm.c          |    9 +++++++++
 include/configs/omap3_evm.h |   10 ++++++----
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index aaf3033..916a13e 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -33,6 +33,7 @@
 #include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
 #include <i2c.h>
 #include <asm/mach-types.h>
 #include "evm.h"
@@ -192,3 +193,11 @@ int board_eth_init(bd_t *bis)
 #endif
 	return rc;
 }
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+       omap_mmc_init(0);
+       return 0;
+}
+#endif
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 6455b0e..72c00ab 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -99,7 +99,8 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 #define CONFIG_MMC			1
-#define CONFIG_OMAP3_MMC		1
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_OMAP_HSMMC		1
 #define CONFIG_DOS_PARTITION		1

 /* DDR - I use Micron DDR */
@@ -200,6 +201,7 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"usbtty=cdc_acm\0" \
+	"mmcdev=0\0" \
 	"console=ttyS2,115200n8\0" \
 	"mmcargs=setenv bootargs console=${console} " \
 		"root=/dev/mmcblk0p2 rw " \
@@ -207,10 +209,10 @@
 	"nandargs=setenv bootargs console=${console} " \
 		"root=/dev/mtdblock4 rw " \
 		"rootfstype=jffs2\0" \
-	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source ${loadaddr}\0" \
-	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"bootm ${loadaddr}\0" \
@@ -220,7 +222,7 @@
 		"bootm ${loadaddr}\0" \

 #define CONFIG_BOOTCOMMAND \
-	"if mmc init; then " \
+	"if mmc rescan ${mmcdev}; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
--
1.6.2.4

[U-Boot] [PATCH] omap3evm: Use generic MMC driver

[Andy Fleming]

On Mon, Aug 1, 2011 at 9:21 AM,  <hvaibhav@ti.com> wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
>
> Switch from the legacy mmc driver to the
> new generic mmc driver.
>
> This patch is based on similar patch for beagle[1].
>
> ?[1] http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=0cd31144240
>
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Sanjeev Premi <premi@ti.com>

Acked-by: Andy Fleming <afleming@freescale.com>

[U-Boot] [PATCH] am3517evm: Use generic MMC driver

[hvaibhav at ti.com]

From: Vaibhav Hiremath <hvaibhav@ti.com>

Switch from the legacy mmc driver to the
new generic mmc driver.

This patch is based on similar patch for beagle[1].

 [1] http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=0cd31144240

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 board/logicpd/am3517evm/am3517evm.c |    9 +++++++++
 include/configs/am3517_evm.h        |   12 +++++++-----
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index bbb6e83..c0a006a 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -28,6 +28,7 @@
 #include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
 #include <asm/mach-types.h>
 #include <i2c.h>
 #include "am3517evm.h"
@@ -74,3 +75,11 @@ void set_muxconf_regs(void)
 {
 	MUX_AM3517EVM();
 }
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+       omap_mmc_init(0);
+       return 0;
+}
+#endif
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 70e8f07..caae7fe 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -95,7 +95,8 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 #define CONFIG_MMC			1
-#define CONFIG_OMAP3_MMC		1
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_OMAP_HSMMC		1
 #define CONFIG_DOS_PARTITION		1

 /*
@@ -191,17 +192,18 @@

 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
-	"console=ttyS2,115200n8\0" \
+	"console=ttyO2,115200n8\0" \
+	"mmcdev=0\0" \
 	"mmcargs=setenv bootargs console=${console} " \
 		"root=/dev/mmcblk0p2 rw " \
 		"rootfstype=ext3 rootwait\0" \
 	"nandargs=setenv bootargs console=${console} " \
 		"root=/dev/mtdblock4 rw " \
 		"rootfstype=jffs2\0" \
-	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source ${loadaddr}\0" \
-	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"bootm ${loadaddr}\0" \
@@ -211,7 +213,7 @@
 		"bootm ${loadaddr}\0" \

 #define CONFIG_BOOTCOMMAND \
-	"if mmc init; then " \
+	"if mmc rescan ${mmcdev}; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
--
1.6.2.4

[U-Boot] [PATCH] am3517evm: Use generic MMC driver

[Andy Fleming]

On Mon, Aug 1, 2011 at 9:21 AM,  <hvaibhav@ti.com> wrote:
> From: Vaibhav Hiremath <hvaibhav@ti.com>
>
> Switch from the legacy mmc driver to the
> new generic mmc driver.
>
> This patch is based on similar patch for beagle[1].
>
> ?[1] http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=0cd31144240
>
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Sanjeev Premi <premi@ti.com>

Acked-by: Andy Fleming <afleming@freescale.com>

[U-Boot] [PATCH] am335x: Enable DDR PHY dynamic power down bit for DDR3 boards

[Vaibhav Hiremath]

Enable DDR PHY dynamic power down bit, which enables
powering down the IO receiver when not performing read.

This also helps in reducing overall power consumption in
low power states (suspend/standby).

Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Cc: Tom Rini <trini@ti.com>
---
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |    1 +
 board/ti/am335x/board.c                     |    6 ++++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index ae43ef8..7ab3baf 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -28,6 +28,7 @@
 #define VTP_CTRL_START_EN	(0x1)
 #define PHY_DLL_LOCK_DIFF	0x0
 #define DDR_CKE_CTRL_NORMAL	0x1
+#define PHY_EN_DYN_PWRDN	(0x1 << 20)
 
 /* Micron MT47H128M16RT-25E */
 #define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 48e6896..22d7b25 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -251,7 +251,8 @@ static struct emif_regs ddr3_emif_reg_data = {
 	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 	.zq_config = MT41J128MJT125_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
+	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
 };
 
 static struct emif_regs ddr3_evm_emif_reg_data = {
@@ -261,7 +262,8 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
 	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 	.zq_config = MT41J512M8RH125_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY,
+	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
 };
 #endif
 
-- 
1.7.0.4

[U-Boot] [PATCH] am335x: Enable DDR PHY dynamic power down bit for DDR3 boards

[Tom Rini]

On Fri, Mar 15, 2013 at 12:41:16PM +0530, Vaibhav Hiremath wrote:

> Enable DDR PHY dynamic power down bit, which enables
> powering down the IO receiver when not performing read.
> 
> This also helps in reducing overall power consumption in
> low power states (suspend/standby).
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
> Cc: Tom Rini <trini@ti.com>
> ---
>  arch/arm/include/asm/arch-am33xx/ddr_defs.h |    1 +
>  board/ti/am335x/board.c                     |    6 ++++--
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> index ae43ef8..7ab3baf 100644
> --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> @@ -28,6 +28,7 @@
>  #define VTP_CTRL_START_EN	(0x1)
>  #define PHY_DLL_LOCK_DIFF	0x0
>  #define DDR_CKE_CTRL_NORMAL	0x1
> +#define PHY_EN_DYN_PWRDN	(0x1 << 20)
>  
>  /* Micron MT47H128M16RT-25E */
>  #define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005
> diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
> index 48e6896..22d7b25 100644
> --- a/board/ti/am335x/board.c
> +++ b/board/ti/am335x/board.c
> @@ -251,7 +251,8 @@ static struct emif_regs ddr3_emif_reg_data = {
>  	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
>  	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
>  	.zq_config = MT41J128MJT125_ZQ_CFG,
> -	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
> +	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
> +				PHY_EN_DYN_PWRDN,
>  };
>  
>  static struct emif_regs ddr3_evm_emif_reg_data = {
> @@ -261,7 +262,8 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
>  	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
>  	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
>  	.zq_config = MT41J512M8RH125_ZQ_CFG,
> -	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY,
> +	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
> +				PHY_EN_DYN_PWRDN,
>  };
>  #endif

Reviewed-by: Tom Rini <trini@ti.com>

Lars, I suspect pcm051 also could use a change like this.

-- 
Tom
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[U-Boot] [PATCH] am335x: Enable DDR PHY dynamic power down bit for DDR3 boards

[Lars Poeschel]

On Friday 15 March 2013 at 16:05:24, Tom Rini wrote:
> On Fri, Mar 15, 2013 at 12:41:16PM +0530, Vaibhav Hiremath wrote:
> > Enable DDR PHY dynamic power down bit, which enables
> > powering down the IO receiver when not performing read.
> > 
> > This also helps in reducing overall power consumption in
> > low power states (suspend/standby).
> > 
> > Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> > Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
> > Cc: Tom Rini <trini@ti.com>
> > ---
> > 
> >  arch/arm/include/asm/arch-am33xx/ddr_defs.h |    1 +
> >  board/ti/am335x/board.c                     |    6 ++++--
> >  2 files changed, 5 insertions(+), 2 deletions(-)
> > 
> > diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> > b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index ae43ef8..7ab3baf
> > 100644
> > --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> > +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
> > @@ -28,6 +28,7 @@
> > 
> >  #define VTP_CTRL_START_EN	(0x1)
> >  #define PHY_DLL_LOCK_DIFF	0x0
> >  #define DDR_CKE_CTRL_NORMAL	0x1
> > 
> > +#define PHY_EN_DYN_PWRDN	(0x1 << 20)
> > 
> >  /* Micron MT47H128M16RT-25E */
> >  #define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005
> > 
> > diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
> > index 48e6896..22d7b25 100644
> > --- a/board/ti/am335x/board.c
> > +++ b/board/ti/am335x/board.c
> > @@ -251,7 +251,8 @@ static struct emif_regs ddr3_emif_reg_data = {
> > 
> >  	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
> >  	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
> >  	.zq_config = MT41J128MJT125_ZQ_CFG,
> > 
> > -	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY,
> > +	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
> > +				PHY_EN_DYN_PWRDN,
> > 
> >  };
> >  
> >  static struct emif_regs ddr3_evm_emif_reg_data = {
> > 
> > @@ -261,7 +262,8 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
> > 
> >  	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
> >  	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
> >  	.zq_config = MT41J512M8RH125_ZQ_CFG,
> > 
> > -	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY,
> > +	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
> > +				PHY_EN_DYN_PWRDN,
> > 
> >  };
> >  #endif
> 
> Reviewed-by: Tom Rini <trini@ti.com>
> 
> Lars, I suspect pcm051 also could use a change like this.

Many thanks for the hint! Yes, I think this could also be of use for pcm051. 
I can care about it and make a patch for pcm051 after my two weeks holiday :)

Lars

[U-Boot] am335x: Enable DDR PHY dynamic power down bit for DDR3 boards

[Tom Rini]

On Thu, Mar 14, 2013 at 09:11:16PM -0000, hvaibhav at ti.com wrote:

> Enable DDR PHY dynamic power down bit, which enables
> powering down the IO receiver when not performing read.
> 
> This also helps in reducing overall power consumption in
> low power states (suspend/standby).
> 
> Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
> Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
> Cc: Tom Rini <trini@ti.com>
> Reviewed-by: Tom Rini <trini@ti.com>

Applied to u-boot-ti/master (and already pulled into u-boot-arm),
thanks!

-- 
Tom
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