From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Date: Thu, 04 Mar 2010 07:55:08 -0600 Subject: [U-Boot] [PATCH] arm: kirkwood: suen3: fixed build warning In-Reply-To: <1267610257-23631-1-git-send-email-prafulla@marvell.com> References: <1267610257-23631-1-git-send-email-prafulla@marvell.com> Message-ID: <4B8FBBBC.7060405@windriver.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Prafulla Wadaskar wrote: > This patch fixes following build warning > > Invalid Kwbimage command Type - valid names are: BOOT_FROM, NAND_ECC_MODE, NAND_PAGE_SIZE, SATA_PIO_MODE, DDR_INIT_DELAY, DATA, , spi, nand, sata, pex, uart > > Signed-off-by: Prafulla Wadaskar > --- > board/keymile/km_arm/kwbimage.cfg | 3 +-- > 1 files changed, 1 insertions(+), 2 deletions(-) > > diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg > index d6edd27..26d6aa0 100644 > --- a/board/keymile/km_arm/kwbimage.cfg > +++ b/board/keymile/km_arm/kwbimage.cfg > @@ -64,7 +64,6 @@ DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register > # bit31-30: 01 > > DATA 0xFFD01404 0x36343000 # DDR Controller Control Low > - 0x38543000 > # bit 3-0: 0 reserved > # bit 4: 0=addr/cmd in smame cycle > # bit 5: 0=clk is driven during self refresh, we don't care for APX > @@ -170,7 +169,7 @@ DATA 0xFFD0149C 0x0000E90F # CPU ODT Control > # bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm > > DATA 0xFFD01480 0x00000001 # DDR Initialization Control > -#bit0=1, enable DDR init upon this register write > +# bit0=1, enable DDR init upon this register write > > # End of Header extension > DATA 0x0 0x0 This patch did not fix any of the warnings I saw. Please recheck. Tom