* [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch @ 2010-03-19 7:43 Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 01/28] nios2: add nios2-generic board Thomas Chou 2010-03-19 14:41 ` [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch Thomas Chou 0 siblings, 2 replies; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot These patches are for next u-boot release. I udnerstand the merge window is not opened yet. But there are quite a few things to review, so please allow me submit them early. This is a generic approach to port u-boot for nios2 boards. We try to ease the porting of a new nios2 design. We will rely on tools generated header file which contains the devices base address, instead of entering the hex numbers by hand. Thomas Chou (28): nios2: add nios2-generic board cfi flash: add status polling method for amd flash serial: move altera uart driver to drivers/serial serial: move altera jtaguart driver to drivers/serial serial: move yanu driver to drivers/serial spi: add altera spi controller support net: add opencore 10/100 ethernet mac support net: add altera triple speeds ethernet mac support nios2: change asm-nios2/io.h to compatible with nios2 linux nios2: add asm-nios2/errno.h nios2: add local_irq_enable/disable to asm-nios2/system.h nios2: use bitops from linux-2.6 asm-generic nios2: fix __fswab64 link error with asm-nios2/byteorder.h nios2: add dma_alloc_coherent with asm-nios2/dma-mapping.h nios2: add gpio support with asm-nios2/gpio.h nios2: move timer handler from interrupt.c to timer.c nios2: define text_base in start.S for linker script nios2: pass command line and initrd to linux nios2: board init for eth, no flash, nand and mmc nios2: fix writel in board/altera/common/epled.c nios2: add cf ide init and reset handler nios2: add gpio led driver nios2: convert ep1c20 board to use cfi flash and spi flash nios2: convert ep1s10 board to use cfi flash nios2: convert ep1s40 board to use cfi flash nios2: convert pci5441 board to use cfi flash nios2: convert pk1c20 board to use cfi flash and spi flash nios2: add struct stat support in linux/stat.h MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/altera/common/cfide.c | 79 +++ board/altera/common/epled.c | 12 +- board/altera/common/gpioled.c | 31 + board/altera/ep1c20/Makefile | 2 +- board/altera/ep1c20/config.mk | 2 +- board/altera/ep1c20/u-boot.lds | 1 + board/altera/ep1s10/Makefile | 2 +- board/altera/ep1s10/config.mk | 2 +- board/altera/ep1s10/u-boot.lds | 1 + board/altera/ep1s40/Makefile | 2 +- board/altera/ep1s40/config.mk | 2 +- board/altera/ep1s40/u-boot.lds | 1 + board/altera/nios2-generic/Makefile | 57 ++ board/altera/nios2-generic/config.mk | 32 + board/altera/nios2-generic/custom_fpga.h | 757 ++++++++++++++++++++++ board/altera/nios2-generic/nios2-generic.c | 67 ++ board/altera/nios2-generic/u-boot.lds | 136 ++++ board/psyent/pci5441/Makefile | 2 +- board/psyent/pci5441/config.mk | 2 +- board/psyent/pci5441/u-boot.lds | 1 + board/psyent/pk1c20/Makefile | 2 +- board/psyent/pk1c20/config.mk | 2 +- board/psyent/pk1c20/led.c | 12 +- board/psyent/pk1c20/u-boot.lds | 1 + cpu/nios2/Makefile | 2 +- cpu/nios2/interrupts.c | 64 +-- cpu/nios2/start.S | 6 + cpu/nios2/timer.c | 98 +++ drivers/mtd/cfi_flash.c | 94 +++- drivers/net/Makefile | 2 + drivers/net/altera_tse.c | 969 ++++++++++++++++++++++++++++ drivers/net/altera_tse.h | 500 ++++++++++++++ drivers/net/ethoc.c | 536 +++++++++++++++ drivers/serial/Makefile | 3 + drivers/serial/altera_jtaguart.c | 107 +++ drivers/serial/altera_uart.c | 116 ++++ drivers/serial/yanu.c | 187 ++++++ drivers/serial/yanu.h | 120 ++++ drivers/spi/Makefile | 1 + drivers/spi/altera_spi.c | 103 +++ include/asm-nios2/bitops.h | 14 +- include/asm-nios2/bitops/atomic.h | 189 ++++++ include/asm-nios2/bitops/ffs.h | 41 ++ include/asm-nios2/bitops/non-atomic.h | 108 +++ include/asm-nios2/byteorder.h | 5 + include/asm-nios2/dma-mapping.h | 14 + include/asm-nios2/errno.h | 1 + include/asm-nios2/gpio.h | 72 ++ include/asm-nios2/io.h | 59 +- include/asm-nios2/system.h | 33 + include/configs/EP1C20.h | 60 ++- include/configs/EP1S10.h | 58 +- include/configs/EP1S40.h | 54 +- include/configs/PCI5441.h | 44 +- include/configs/PK1C20.h | 68 ++- include/configs/nios2-generic.h | 360 +++++++++++ include/linux/stat.h | 2 +- lib_nios2/board.c | 33 + lib_nios2/bootm.c | 19 +- 62 files changed, 5110 insertions(+), 245 deletions(-) create mode 100644 board/altera/common/cfide.c create mode 100644 board/altera/common/gpioled.c create mode 100644 board/altera/nios2-generic/Makefile create mode 100644 board/altera/nios2-generic/config.mk create mode 100644 board/altera/nios2-generic/custom_fpga.h create mode 100644 board/altera/nios2-generic/nios2-generic.c create mode 100644 board/altera/nios2-generic/u-boot.lds create mode 100644 cpu/nios2/timer.c create mode 100644 drivers/net/altera_tse.c create mode 100644 drivers/net/altera_tse.h create mode 100644 drivers/net/ethoc.c create mode 100644 drivers/serial/altera_jtaguart.c create mode 100644 drivers/serial/altera_uart.c create mode 100644 drivers/serial/yanu.c create mode 100644 drivers/serial/yanu.h create mode 100644 drivers/spi/altera_spi.c create mode 100644 include/asm-nios2/bitops/atomic.h create mode 100644 include/asm-nios2/bitops/ffs.h create mode 100644 include/asm-nios2/bitops/non-atomic.h create mode 100644 include/asm-nios2/dma-mapping.h create mode 100644 include/asm-nios2/errno.h create mode 100644 include/asm-nios2/gpio.h create mode 100644 include/configs/nios2-generic.h ^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 01/28] nios2: add nios2-generic board 2010-03-19 7:43 [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 02/28] cfi flash: add status polling method for amd flash Thomas Chou 2010-04-05 5:36 ` [U-Boot] [PATCH 01/28] nios2: add nios2-generic board Ben Warren 2010-03-19 14:41 ` [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch Thomas Chou 1 sibling, 2 replies; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This is a generic approach to port u-boot for nios2 boards. It uses a new set of device drivers, such as the cfi flash, spi lash, nand flash and new ethernet drivers. You may find the usage of this approach on the nios2 wiki, http://nioswiki.com/DasUBoot In order to better support MMU and NOMMU targets, we will use virtual addressing in the config file. All references to devices except for the main memory (sdram), should be mapped to uncached (bypass), IO region. While the main memory should use cached, kernel region. For MMU, the uncached, IO region is 0xe0000000-0xffffffff. #define IO_REGION_BASE 0xe0000000 the cached, kernel region is 0xc000000-0xdfffffff. #define KERNEL_REGION_BASE 0xc0000000 For NOMMU, the uncached, IO region is 0x8000000-0xffffffff. #define IO_REGION_BASE 0x80000000 the cached, kernel region is 0x00000000-0x7fffffff. #define KERNEL_REGION_BASE 0x00000000 In stead of editing the hex number of base address, we will use the resource header file generated with tools. An example SMC device def will become, #define CONFIG_SMC91111_BASE (ENET_BASE | IO_REGION_BASE) where the ENET_BASE will be defined in the generated file ../board/altera/nios2-generic/custom_fpga.h . Then when you reassign the base address or turn on/off the MMU, you will only need to regenerate the header file. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/altera/nios2-generic/Makefile | 57 +++ board/altera/nios2-generic/config.mk | 32 ++ board/altera/nios2-generic/custom_fpga.h | 757 ++++++++++++++++++++++++++++ board/altera/nios2-generic/nios2-generic.c | 67 +++ board/altera/nios2-generic/u-boot.lds | 136 +++++ include/configs/nios2-generic.h | 360 +++++++++++++ 9 files changed, 1414 insertions(+), 0 deletions(-) create mode 100644 board/altera/nios2-generic/Makefile create mode 100644 board/altera/nios2-generic/config.mk create mode 100644 board/altera/nios2-generic/custom_fpga.h create mode 100644 board/altera/nios2-generic/nios2-generic.c create mode 100644 board/altera/nios2-generic/u-boot.lds create mode 100644 include/configs/nios2-generic.h diff --git a/MAINTAINERS b/MAINTAINERS index 80057ce..2e1976a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -851,6 +851,7 @@ Scott McNutt <smcnutt@psyent.com> EP1C20 Nios-II EP1S10 Nios-II EP1S40 Nios-II + nios2-generic Nios-II ######################################################################### # MicroBlaze Systems: # diff --git a/MAKEALL b/MAKEALL index beacb5f..f27694e 100755 --- a/MAKEALL +++ b/MAKEALL @@ -826,6 +826,7 @@ LIST_nios2=" \ EP1S40 \ PCI5441 \ PK1C20 \ + nios2-generic \ " ######################################################################### diff --git a/Makefile b/Makefile index d801e25..7035169 100644 --- a/Makefile +++ b/Makefile @@ -3549,6 +3549,9 @@ PK1C20_config : unconfig PCI5441_config : unconfig @$(MKCONFIG) PCI5441 nios2 nios2 pci5441 psyent +nios2-generic_config : unconfig + @$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera + #======================================================================== ## Microblaze #======================================================================== diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile new file mode 100644 index 0000000..f2be4dd --- /dev/null +++ b/board/altera/nios2-generic/Makefile @@ -0,0 +1,57 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-$(CONFIG_CMD_IDE) += ../common/cfide.o +COBJS-$(CONFIG_EPLED) += ../common/epled.o +COBJS-$(CONFIG_GPIOLED) += ../common/gpioled.o +COBJS-$(CONFIG_SEVENSEG) += ../common/sevenseg.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk new file mode 100644 index 0000000..dd4577b --- /dev/null +++ b/board/altera/nios2-generic/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2005, Psyent Corporation <www.psyent.com> +# Scott McNutt <smcnutt@psyent.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for nios2 boards so do not change it +#TEXT_BASE = do-not-use-me + +PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h new file mode 100644 index 0000000..9b4e0e4 --- /dev/null +++ b/board/altera/nios2-generic/custom_fpga.h @@ -0,0 +1,757 @@ +#ifndef _CUSTOM_FPGA_H_ +#define _CUSTOM_FPGA_H_ + +/* + * This file was automatically generated by the swinfo2header utility. + * + * Created from SOPC Builder system 'NiosII_cycloneII_2c35_full_featured_sopc' in + * file './NiosII_cycloneII_2c35_full_featured_sopc.sopcinfo'. + */ + +/* + * This file contains macros for module 'cpu' and devices + * connected to the following masters: + * instruction_master + * tightly_coupled_instruction_master_0 + * data_master + * tightly_coupled_data_master_0 + * + * Do not include this header file and another header file created for a + * different module or master group at the same time. + * Doing so may result in duplicate macro names. + * Instead, use the system header file which has macros with unique names. + */ + +/* + * Macros for module 'cpu', class 'altera_nios2'. + * The macros have no prefix. + */ +#define CPU_IMPLEMENTATION "fast" +#define BIG_ENDIAN 0 +#define CPU_FREQ 85000000 +#define ICACHE_LINE_SIZE 32 +#define ICACHE_LINE_SIZE_LOG2 5 +#define ICACHE_SIZE 4096 +#define DCACHE_LINE_SIZE 32 +#define DCACHE_LINE_SIZE_LOG2 5 +#define DCACHE_SIZE 2048 +#define INITDA_SUPPORTED +#define FLUSHDA_SUPPORTED +#define HAS_JMPI_INSTRUCTION +#define MMU_PRESENT +#define KERNEL_REGION_BASE 0xc0000000 +#define IO_REGION_BASE 0xe0000000 +#define KERNEL_MMU_REGION_BASE 0x80000000 +#define USER_REGION_BASE 0x0 +#define PROCESS_ID_NUM_BITS 10 +#define TLB_NUM_WAYS 16 +#define TLB_NUM_WAYS_LOG2 4 +#define TLB_PTR_SZ 7 +#define TLB_NUM_ENTRIES 128 +#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc8000000 +#define EXCEPTION_ADDR 0xc6000020 +#define RESET_ADDR 0xc0000000 +#define BREAK_ADDR 0xc2120020 +#define HAS_DEBUG_STUB +#define HAS_DEBUG_CORE 1 +#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION +#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION +#define HAS_EXTRA_EXCEPTION_INFO +#define CPU_ID_SIZE 1 +#define CPU_ID_VALUE 0x0 +#define HARDWARE_DIVIDE_PRESENT 0 +#define HARDWARE_MULTIPLY_PRESENT 1 +#define HARDWARE_MULX_PRESENT 0 +#define INST_ADDR_WIDTH 28 +#define DATA_ADDR_WIDTH 28 +#define NUM_OF_SHADOW_REG_SETS 0 + +/* + * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash' + * The macros are prefixed with 'EXT_FLASH_'. + * The prefix is the slave descriptor. + */ +#define EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash +#define EXT_FLASH_COMPONENT_NAME ext_flash +#define EXT_FLASH_BASE 0x0 +#define EXT_FLASH_SPAN 16777216 +#define EXT_FLASH_END 0xffffff +#define EXT_FLASH_SETUP_VALUE 45 +#define EXT_FLASH_WAIT_VALUE 160 +#define EXT_FLASH_HOLD_VALUE 35 +#define EXT_FLASH_TIMING_UNITS "ns" +#define EXT_FLASH_SIZE 16777216 +#define EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8 +#define EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0 +#define EXT_FLASH_MEMORY_INFO_IS_FLASH 1 +#define EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1 +#define EXT_FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR +#define EXT_FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR + +/* + * Macros for device 'cf_ctl', class 'altera_avalon_cf' + * The macros are prefixed with 'CF_CTL_'. + * The prefix is the slave descriptor. + */ +#define CF_CTL_COMPONENT_TYPE altera_avalon_cf +#define CF_CTL_COMPONENT_NAME cf +#define CF_CTL_BASE 0x1000000 +#define CF_CTL_SPAN 16 +#define CF_CTL_END 0x100000f +#define CF_CTL_IRQ 8 + +/* + * Macros for device 'pll', class 'altera_avalon_pll' + * The macros are prefixed with 'PLL_'. + * The prefix is the slave descriptor. + */ +#define PLL_COMPONENT_TYPE altera_avalon_pll +#define PLL_COMPONENT_NAME pll +#define PLL_BASE 0x1000020 +#define PLL_SPAN 32 +#define PLL_END 0x100003f +#define PLL_ARESET "None" +#define PLL_PFDENA "None" +#define PLL_LOCKED "None" +#define PLL_PLLENA "None" +#define PLL_SCANCLK "None" +#define PLL_SCANDATA "None" +#define PLL_SCANREAD "None" +#define PLL_SCANWRITE "None" +#define PLL_SCANCLKENA "None" +#define PLL_SCANACLR "None" +#define PLL_SCANDATAOUT "None" +#define PLL_SCANDONE "None" +#define PLL_CONFIGUPDATE "None" +#define PLL_PHASECOUNTERSELECT "None" +#define PLL_PHASEDONE "None" +#define PLL_PHASEUPDOWN "None" +#define PLL_PHASESTEP "None" + +/* + * Macros for device 'pllsysx2', class 'altera_avalon_pll' + * The macros are prefixed with 'PLLSYSX2_'. + * The prefix is the slave descriptor. + */ +#define PLLSYSX2_COMPONENT_TYPE altera_avalon_pll +#define PLLSYSX2_COMPONENT_NAME pllsysx2 +#define PLLSYSX2_BASE 0x1000040 +#define PLLSYSX2_SPAN 32 +#define PLLSYSX2_END 0x100005f +#define PLLSYSX2_ARESET "None" +#define PLLSYSX2_PFDENA "None" +#define PLLSYSX2_LOCKED "None" +#define PLLSYSX2_PLLENA "None" +#define PLLSYSX2_SCANCLK "None" +#define PLLSYSX2_SCANDATA "None" +#define PLLSYSX2_SCANREAD "None" +#define PLLSYSX2_SCANWRITE "None" +#define PLLSYSX2_SCANCLKENA "None" +#define PLLSYSX2_SCANACLR "None" +#define PLLSYSX2_SCANDATAOUT "None" +#define PLLSYSX2_SCANDONE "None" +#define PLLSYSX2_CONFIGUPDATE "None" +#define PLLSYSX2_PHASECOUNTERSELECT "None" +#define PLLSYSX2_PHASEDONE "None" +#define PLLSYSX2_PHASEUPDOWN "None" +#define PLLSYSX2_PHASESTEP "None" + +/* + * Macros for device 'cf_ide', class 'altera_avalon_cf' + * The macros are prefixed with 'CF_IDE_'. + * The prefix is the slave descriptor. + */ +#define CF_IDE_COMPONENT_TYPE altera_avalon_cf +#define CF_IDE_COMPONENT_NAME cf +#define CF_IDE_BASE 0x1000080 +#define CF_IDE_SPAN 64 +#define CF_IDE_END 0x10000bf +#define CF_IDE_IRQ 9 + +/* + * Macros for device 'ext_ssram', class 'altera_avalon_cy7c1380_ssram' + * The macros are prefixed with 'EXT_SSRAM_'. + * The prefix is the slave descriptor. + */ +#define EXT_SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram +#define EXT_SSRAM_COMPONENT_NAME ext_ssram +#define EXT_SSRAM_BASE 0x1400000 +#define EXT_SSRAM_SPAN 2097152 +#define EXT_SSRAM_END 0x15fffff +#define EXT_SSRAM_SRAM_MEMORY_SIZE 2 +#define EXT_SSRAM_SRAM_MEMORY_UNITS 1048576 +#define EXT_SSRAM_SSRAM_DATA_WIDTH 32 +#define EXT_SSRAM_SSRAM_READ_LATENCY 2 +#define EXT_SSRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32 +#define EXT_SSRAM_MEMORY_INFO_HAS_BYTE_LANE 1 +#define EXT_SSRAM_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define EXT_SSRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR + +/* + * Macros for device 'enet', class 'altera_avalon_lan91c111' + * The macros are prefixed with 'ENET_'. + * The prefix is the slave descriptor. + */ +#define ENET_COMPONENT_TYPE altera_avalon_lan91c111 +#define ENET_COMPONENT_NAME enet +#define ENET_BASE 0x2110000 +#define ENET_SPAN 65536 +#define ENET_END 0x211ffff +#define ENET_IRQ 6 +#define ENET_IS_ETHERNET_MAC 1 +#define ENET_LAN91C111_REGISTERS_OFFSET 768 +#define ENET_LAN91C111_DATA_BUS_WIDTH 32 + +/* + * Macros for device 'timer', class 'altera_avalon_timer' + * The macros are prefixed with 'TIMER_'. + * The prefix is the slave descriptor. + */ +#define TIMER_COMPONENT_TYPE altera_avalon_timer +#define TIMER_COMPONENT_NAME timer +#define TIMER_BASE 0x2120800 +#define TIMER_SPAN 32 +#define TIMER_END 0x212081f +#define TIMER_IRQ 0 +#define TIMER_ALWAYS_RUN 0 +#define TIMER_FIXED_PERIOD 0 +#define TIMER_SNAPSHOT 1 +#define TIMER_PERIOD 10.0 +#define TIMER_PERIOD_UNITS "ms" +#define TIMER_RESET_OUTPUT 0 +#define TIMER_TIMEOUT_PULSE_OUTPUT 0 +#define TIMER_FREQ 85000000 +#define TIMER_LOAD_VALUE 849999ULL +#define TIMER_COUNTER_SIZE 32 +#define TIMER_MULT 0.0010 +#define TIMER_TICKS_PER_SEC 100 + +/* + * Macros for device 'high_res_timer', class 'altera_avalon_timer' + * The macros are prefixed with 'HIGH_RES_TIMER_'. + * The prefix is the slave descriptor. + */ +#define HIGH_RES_TIMER_COMPONENT_TYPE altera_avalon_timer +#define HIGH_RES_TIMER_COMPONENT_NAME high_res_timer +#define HIGH_RES_TIMER_BASE 0x2120820 +#define HIGH_RES_TIMER_SPAN 32 +#define HIGH_RES_TIMER_END 0x212083f +#define HIGH_RES_TIMER_IRQ 3 +#define HIGH_RES_TIMER_ALWAYS_RUN 0 +#define HIGH_RES_TIMER_FIXED_PERIOD 0 +#define HIGH_RES_TIMER_SNAPSHOT 1 +#define HIGH_RES_TIMER_PERIOD 10.0 +#define HIGH_RES_TIMER_PERIOD_UNITS "us" +#define HIGH_RES_TIMER_RESET_OUTPUT 0 +#define HIGH_RES_TIMER_TIMEOUT_PULSE_OUTPUT 0 +#define HIGH_RES_TIMER_FREQ 85000000 +#define HIGH_RES_TIMER_LOAD_VALUE 849ULL +#define HIGH_RES_TIMER_COUNTER_SIZE 32 +#define HIGH_RES_TIMER_MULT 1.0E-6 +#define HIGH_RES_TIMER_TICKS_PER_SEC 100000 + +/* + * Macros for device 'uart', class 'altera_avalon_uart' + * The macros are prefixed with 'UART_'. + * The prefix is the slave descriptor. + */ +#define UART_COMPONENT_TYPE altera_avalon_uart +#define UART_COMPONENT_NAME uart +#define UART_BASE 0x2120840 +#define UART_SPAN 32 +#define UART_END 0x212085f +#define UART_IRQ 4 +#define UART_BAUD 115200 +#define UART_DATA_BITS 8 +#define UART_FIXED_BAUD 1 +#define UART_PARITY 'N' +#define UART_STOP_BITS 1 +#define UART_SYNC_REG_DEPTH 2 +#define UART_USE_CTS_RTS 0 +#define UART_USE_EOP_REGISTER 0 +#define UART_SIM_TRUE_BAUD 0 +#define UART_SIM_CHAR_STREAM "" +#define UART_FREQ 85000000 + +/* + * Macros for device 'button_pio', class 'altera_avalon_pio' + * The macros are prefixed with 'BUTTON_PIO_'. + * The prefix is the slave descriptor. + */ +#define BUTTON_PIO_COMPONENT_TYPE altera_avalon_pio +#define BUTTON_PIO_COMPONENT_NAME button_pio +#define BUTTON_PIO_BASE 0x2120860 +#define BUTTON_PIO_SPAN 16 +#define BUTTON_PIO_END 0x212086f +#define BUTTON_PIO_IRQ 2 +#define BUTTON_PIO_DO_TEST_BENCH_WIRING 1 +#define BUTTON_PIO_DRIVEN_SIM_VALUE 0xf +#define BUTTON_PIO_HAS_TRI 0 +#define BUTTON_PIO_HAS_OUT 0 +#define BUTTON_PIO_HAS_IN 1 +#define BUTTON_PIO_CAPTURE 1 +#define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 0 +#define BUTTON_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define BUTTON_PIO_DATA_WIDTH 4 +#define BUTTON_PIO_RESET_VALUE 0x0 +#define BUTTON_PIO_EDGE_TYPE "ANY" +#define BUTTON_PIO_IRQ_TYPE "EDGE" +#define BUTTON_PIO_FREQ 85000000 + +/* + * Macros for device 'led_pio', class 'altera_avalon_pio' + * The macros are prefixed with 'LED_PIO_'. + * The prefix is the slave descriptor. + */ +#define LED_PIO_COMPONENT_TYPE altera_avalon_pio +#define LED_PIO_COMPONENT_NAME led_pio +#define LED_PIO_BASE 0x2120870 +#define LED_PIO_SPAN 16 +#define LED_PIO_END 0x212087f +#define LED_PIO_DO_TEST_BENCH_WIRING 0 +#define LED_PIO_DRIVEN_SIM_VALUE 0x0 +#define LED_PIO_HAS_TRI 0 +#define LED_PIO_HAS_OUT 1 +#define LED_PIO_HAS_IN 0 +#define LED_PIO_CAPTURE 0 +#define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0 +#define LED_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define LED_PIO_DATA_WIDTH 8 +#define LED_PIO_RESET_VALUE 0x0 +#define LED_PIO_EDGE_TYPE "NONE" +#define LED_PIO_IRQ_TYPE "NONE" +#define LED_PIO_FREQ 85000000 + +/* + * Macros for device 'lcd_display', class 'altera_avalon_lcd_16207' + * The macros are prefixed with 'LCD_DISPLAY_'. + * The prefix is the slave descriptor. + */ +#define LCD_DISPLAY_COMPONENT_TYPE altera_avalon_lcd_16207 +#define LCD_DISPLAY_COMPONENT_NAME lcd_display +#define LCD_DISPLAY_BASE 0x2120880 +#define LCD_DISPLAY_SPAN 16 +#define LCD_DISPLAY_END 0x212088f + +/* + * Macros for device 'seven_seg_pio', class 'altera_avalon_pio' + * The macros are prefixed with 'SEVEN_SEG_PIO_'. + * The prefix is the slave descriptor. + */ +#define SEVEN_SEG_PIO_COMPONENT_TYPE altera_avalon_pio +#define SEVEN_SEG_PIO_COMPONENT_NAME seven_seg_pio +#define SEVEN_SEG_PIO_BASE 0x2120890 +#define SEVEN_SEG_PIO_SPAN 16 +#define SEVEN_SEG_PIO_END 0x212089f +#define SEVEN_SEG_PIO_DO_TEST_BENCH_WIRING 0 +#define SEVEN_SEG_PIO_DRIVEN_SIM_VALUE 0x0 +#define SEVEN_SEG_PIO_HAS_TRI 0 +#define SEVEN_SEG_PIO_HAS_OUT 1 +#define SEVEN_SEG_PIO_HAS_IN 0 +#define SEVEN_SEG_PIO_CAPTURE 0 +#define SEVEN_SEG_PIO_BIT_CLEARING_EDGE_REGISTER 0 +#define SEVEN_SEG_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define SEVEN_SEG_PIO_DATA_WIDTH 16 +#define SEVEN_SEG_PIO_RESET_VALUE 0x0 +#define SEVEN_SEG_PIO_EDGE_TYPE "NONE" +#define SEVEN_SEG_PIO_IRQ_TYPE "NONE" +#define SEVEN_SEG_PIO_FREQ 85000000 + +/* + * Macros for device 'reconfig_request_pio', class 'altera_avalon_pio' + * The macros are prefixed with 'RECONFIG_REQUEST_PIO_'. + * The prefix is the slave descriptor. + */ +#define RECONFIG_REQUEST_PIO_COMPONENT_TYPE altera_avalon_pio +#define RECONFIG_REQUEST_PIO_COMPONENT_NAME reconfig_request_pio +#define RECONFIG_REQUEST_PIO_BASE 0x21208a0 +#define RECONFIG_REQUEST_PIO_SPAN 16 +#define RECONFIG_REQUEST_PIO_END 0x21208af +#define RECONFIG_REQUEST_PIO_DO_TEST_BENCH_WIRING 0 +#define RECONFIG_REQUEST_PIO_DRIVEN_SIM_VALUE 0x0 +#define RECONFIG_REQUEST_PIO_HAS_TRI 1 +#define RECONFIG_REQUEST_PIO_HAS_OUT 0 +#define RECONFIG_REQUEST_PIO_HAS_IN 0 +#define RECONFIG_REQUEST_PIO_CAPTURE 0 +#define RECONFIG_REQUEST_PIO_BIT_CLEARING_EDGE_REGISTER 0 +#define RECONFIG_REQUEST_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0 +#define RECONFIG_REQUEST_PIO_DATA_WIDTH 1 +#define RECONFIG_REQUEST_PIO_RESET_VALUE 0x0 +#define RECONFIG_REQUEST_PIO_EDGE_TYPE "NONE" +#define RECONFIG_REQUEST_PIO_IRQ_TYPE "NONE" +#define RECONFIG_REQUEST_PIO_FREQ 85000000 + +/* + * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart' + * The macros are prefixed with 'JTAG_UART_'. + * The prefix is the slave descriptor. + */ +#define JTAG_UART_COMPONENT_TYPE altera_avalon_jtag_uart +#define JTAG_UART_COMPONENT_NAME jtag_uart +#define JTAG_UART_BASE 0x21208b0 +#define JTAG_UART_SPAN 8 +#define JTAG_UART_END 0x21208b7 +#define JTAG_UART_IRQ 1 +#define JTAG_UART_WRITE_DEPTH 64 +#define JTAG_UART_READ_DEPTH 64 +#define JTAG_UART_WRITE_THRESHOLD 8 +#define JTAG_UART_READ_THRESHOLD 8 + +/* + * Macros for device 'sysid', class 'altera_avalon_sysid' + * The macros are prefixed with 'SYSID_'. + * The prefix is the slave descriptor. + */ +#define SYSID_COMPONENT_TYPE altera_avalon_sysid +#define SYSID_COMPONENT_NAME sysid +#define SYSID_BASE 0x21208b8 +#define SYSID_SPAN 8 +#define SYSID_END 0x21208bf +#define SYSID_ID 1003732523 +#define SYSID_TIMESTAMP 1268227126 + +/* + * Macros for device 'performance_counter', class 'altera_avalon_performance_counter' + * The macros are prefixed with 'PERFORMANCE_COUNTER_'. + * The prefix is the slave descriptor. + */ +#define PERFORMANCE_COUNTER_COMPONENT_TYPE altera_avalon_performance_counter +#define PERFORMANCE_COUNTER_COMPONENT_NAME performance_counter +#define PERFORMANCE_COUNTER_BASE 0x2120900 +#define PERFORMANCE_COUNTER_SPAN 64 +#define PERFORMANCE_COUNTER_END 0x212093f +#define PERFORMANCE_COUNTER_HOW_MANY_SECTIONS 3 + +/* + * Macros for device 'dma', class 'altera_avalon_dma' + * The macros are prefixed with 'DMA_'. + * The prefix is the slave descriptor. + */ +#define DMA_COMPONENT_TYPE altera_avalon_dma +#define DMA_COMPONENT_NAME dma +#define DMA_BASE 0x2120a00 +#define DMA_SPAN 32 +#define DMA_END 0x2120a1f +#define DMA_IRQ 7 +#define DMA_LENGTHWIDTH 13 +#define DMA_ALLOW_BYTE_TRANSACTIONS 1 +#define DMA_ALLOW_HW_TRANSACTIONS 1 +#define DMA_ALLOW_WORD_TRANSACTIONS 1 +#define DMA_ALLOW_DOUBLEWORD_TRANSACTIONS 1 +#define DMA_ALLOW_QUADWORD_TRANSACTIONS 1 +#define DMA_MAX_BURST_SIZE 128 + +/* + * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash' + * Path to the device is from the master group 'dma_read_master'. + * The macros are prefixed with 'DMA_READ_MASTER_EXT_FLASH_'. + * The prefix is the master group descriptor and the slave descriptor. + */ +#define DMA_READ_MASTER_EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash +#define DMA_READ_MASTER_EXT_FLASH_COMPONENT_NAME ext_flash +#define DMA_READ_MASTER_EXT_FLASH_BASE 0x0 +#define DMA_READ_MASTER_EXT_FLASH_SPAN 16777216 +#define DMA_READ_MASTER_EXT_FLASH_END 0xffffff +#define DMA_READ_MASTER_EXT_FLASH_SETUP_VALUE 45 +#define DMA_READ_MASTER_EXT_FLASH_WAIT_VALUE 160 +#define DMA_READ_MASTER_EXT_FLASH_HOLD_VALUE 35 +#define DMA_READ_MASTER_EXT_FLASH_TIMING_UNITS "ns" +#define DMA_READ_MASTER_EXT_FLASH_SIZE 16777216 +#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8 +#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0 +#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_IS_FLASH 1 +#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1 +#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR +#define DMA_READ_MASTER_EXT_FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR + +/* + * Macros for device 'ext_ssram', class 'altera_avalon_cy7c1380_ssram' + * Path to the device is from the master group 'dma_read_master'. + * The macros are prefixed with 'DMA_READ_MASTER_EXT_SSRAM_'. + * The prefix is the master group descriptor and the slave descriptor. + */ +#define DMA_READ_MASTER_EXT_SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram +#define DMA_READ_MASTER_EXT_SSRAM_COMPONENT_NAME ext_ssram +#define DMA_READ_MASTER_EXT_SSRAM_BASE 0x1400000 +#define DMA_READ_MASTER_EXT_SSRAM_SPAN 2097152 +#define DMA_READ_MASTER_EXT_SSRAM_END 0x15fffff +#define DMA_READ_MASTER_EXT_SSRAM_SRAM_MEMORY_SIZE 2 +#define DMA_READ_MASTER_EXT_SSRAM_SRAM_MEMORY_UNITS 1048576 +#define DMA_READ_MASTER_EXT_SSRAM_SSRAM_DATA_WIDTH 32 +#define DMA_READ_MASTER_EXT_SSRAM_SSRAM_READ_LATENCY 2 +#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32 +#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_HAS_BYTE_LANE 1 +#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define DMA_READ_MASTER_EXT_SSRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR + +/* + * Macros for device 'lan91c111', class 'altera_avalon_lan91c111' + * Path to the device is from the master group 'dma_read_master'. + * The macros are prefixed with 'DMA_READ_MASTER_LAN91C111_'. + * The prefix is the master group descriptor and the slave descriptor. + */ +#define DMA_READ_MASTER_LAN91C111_COMPONENT_TYPE altera_avalon_lan91c111 +#define DMA_READ_MASTER_LAN91C111_COMPONENT_NAME lan91c111 +#define DMA_READ_MASTER_LAN91C111_BASE 0x2110000 +#define DMA_READ_MASTER_LAN91C111_SPAN 65536 +#define DMA_READ_MASTER_LAN91C111_END 0x211ffff +#define DMA_READ_MASTER_LAN91C111_IS_ETHERNET_MAC 1 +#define DMA_READ_MASTER_LAN91C111_LAN91C111_REGISTERS_OFFSET 768 +#define DMA_READ_MASTER_LAN91C111_LAN91C111_DATA_BUS_WIDTH 32 + +/* + * Macros for device 'ddr_sdram_0', class 'ddr_sdram_component_classic' + * Path to the device is from the master group 'dma_read_master'. + * The macros are prefixed with 'DMA_READ_MASTER_DDR_SDRAM_0_'. + * The prefix is the master group descriptor and the slave descriptor. + */ +#define DMA_READ_MASTER_DDR_SDRAM_0_COMPONENT_TYPE ddr_sdram_component_classic +#define DMA_READ_MASTER_DDR_SDRAM_0_COMPONENT_NAME ddr_sdram_0 +#define DMA_READ_MASTER_DDR_SDRAM_0_BASE 0x6000000 +#define DMA_READ_MASTER_DDR_SDRAM_0_SPAN 33554432 +#define DMA_READ_MASTER_DDR_SDRAM_0_END 0x7ffffff +#define DMA_READ_MASTER_DDR_SDRAM_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32 +#define DMA_READ_MASTER_DDR_SDRAM_0_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define DMA_READ_MASTER_DDR_SDRAM_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR + +/* + * Macros for device 'tightly_coupled_data_memory', class 'altera_avalon_onchip_memory2' + * Path to the device is from the master group 'dma_read_master'. + * The macros are prefixed with 'DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_'. + * The prefix is the master group descriptor and the slave descriptor. + */ +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_NAME tightly_coupled_data_memory +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_BASE 0x8002000 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SPAN 8192 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_END 0x8003fff +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_data_memory" +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic" +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_WRITABLE 1 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_DUAL_PORT 1 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_VALUE 8192 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_MULTIPLE 1 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_CONTENTS_INFO "" +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_RAM_BLOCK_TYPE "Auto" +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_MEM_CONTENT 1 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INSTANCE_ID "NONE" +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE" +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_HEX 1 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define DMA_READ_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR + +/* + * Macros for device 'ext_flash', class 'altera_avalon_cfi_flash' + * Path to the device is from the master group 'dma_write_master'. + * The macros are prefixed with 'DMA_WRITE_MASTER_EXT_FLASH_'. + * The prefix is the master group descriptor and the slave descriptor. + */ +#define DMA_WRITE_MASTER_EXT_FLASH_COMPONENT_TYPE altera_avalon_cfi_flash +#define DMA_WRITE_MASTER_EXT_FLASH_COMPONENT_NAME ext_flash +#define DMA_WRITE_MASTER_EXT_FLASH_BASE 0x0 +#define DMA_WRITE_MASTER_EXT_FLASH_SPAN 16777216 +#define DMA_WRITE_MASTER_EXT_FLASH_END 0xffffff +#define DMA_WRITE_MASTER_EXT_FLASH_SETUP_VALUE 45 +#define DMA_WRITE_MASTER_EXT_FLASH_WAIT_VALUE 160 +#define DMA_WRITE_MASTER_EXT_FLASH_HOLD_VALUE 35 +#define DMA_WRITE_MASTER_EXT_FLASH_TIMING_UNITS "ns" +#define DMA_WRITE_MASTER_EXT_FLASH_SIZE 16777216 +#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_MEM_INIT_DATA_WIDTH 8 +#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_HAS_BYTE_LANE 0 +#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_IS_FLASH 1 +#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_GENERATE_FLASH 1 +#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR +#define DMA_WRITE_MASTER_EXT_FLASH_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR + +/* + * Macros for device 'ext_ssram', class 'altera_avalon_cy7c1380_ssram' + * Path to the device is from the master group 'dma_write_master'. + * The macros are prefixed with 'DMA_WRITE_MASTER_EXT_SSRAM_'. + * The prefix is the master group descriptor and the slave descriptor. + */ +#define DMA_WRITE_MASTER_EXT_SSRAM_COMPONENT_TYPE altera_avalon_cy7c1380_ssram +#define DMA_WRITE_MASTER_EXT_SSRAM_COMPONENT_NAME ext_ssram +#define DMA_WRITE_MASTER_EXT_SSRAM_BASE 0x1400000 +#define DMA_WRITE_MASTER_EXT_SSRAM_SPAN 2097152 +#define DMA_WRITE_MASTER_EXT_SSRAM_END 0x15fffff +#define DMA_WRITE_MASTER_EXT_SSRAM_SRAM_MEMORY_SIZE 2 +#define DMA_WRITE_MASTER_EXT_SSRAM_SRAM_MEMORY_UNITS 1048576 +#define DMA_WRITE_MASTER_EXT_SSRAM_SSRAM_DATA_WIDTH 32 +#define DMA_WRITE_MASTER_EXT_SSRAM_SSRAM_READ_LATENCY 2 +#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32 +#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_HAS_BYTE_LANE 1 +#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define DMA_WRITE_MASTER_EXT_SSRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR + +/* + * Macros for device 'lan91c111', class 'altera_avalon_lan91c111' + * Path to the device is from the master group 'dma_write_master'. + * The macros are prefixed with 'DMA_WRITE_MASTER_LAN91C111_'. + * The prefix is the master group descriptor and the slave descriptor. + */ +#define DMA_WRITE_MASTER_LAN91C111_COMPONENT_TYPE altera_avalon_lan91c111 +#define DMA_WRITE_MASTER_LAN91C111_COMPONENT_NAME lan91c111 +#define DMA_WRITE_MASTER_LAN91C111_BASE 0x2110000 +#define DMA_WRITE_MASTER_LAN91C111_SPAN 65536 +#define DMA_WRITE_MASTER_LAN91C111_END 0x211ffff +#define DMA_WRITE_MASTER_LAN91C111_IS_ETHERNET_MAC 1 +#define DMA_WRITE_MASTER_LAN91C111_LAN91C111_REGISTERS_OFFSET 768 +#define DMA_WRITE_MASTER_LAN91C111_LAN91C111_DATA_BUS_WIDTH 32 + +/* + * Macros for device 'ddr_sdram_0', class 'ddr_sdram_component_classic' + * Path to the device is from the master group 'dma_write_master'. + * The macros are prefixed with 'DMA_WRITE_MASTER_DDR_SDRAM_0_'. + * The prefix is the master group descriptor and the slave descriptor. + */ +#define DMA_WRITE_MASTER_DDR_SDRAM_0_COMPONENT_TYPE ddr_sdram_component_classic +#define DMA_WRITE_MASTER_DDR_SDRAM_0_COMPONENT_NAME ddr_sdram_0 +#define DMA_WRITE_MASTER_DDR_SDRAM_0_BASE 0x6000000 +#define DMA_WRITE_MASTER_DDR_SDRAM_0_SPAN 33554432 +#define DMA_WRITE_MASTER_DDR_SDRAM_0_END 0x7ffffff +#define DMA_WRITE_MASTER_DDR_SDRAM_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32 +#define DMA_WRITE_MASTER_DDR_SDRAM_0_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define DMA_WRITE_MASTER_DDR_SDRAM_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR + +/* + * Macros for device 'tightly_coupled_data_memory', class 'altera_avalon_onchip_memory2' + * Path to the device is from the master group 'dma_write_master'. + * The macros are prefixed with 'DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_'. + * The prefix is the master group descriptor and the slave descriptor. + */ +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_NAME tightly_coupled_data_memory +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_BASE 0x8002000 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SPAN 8192 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_END 0x8003fff +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_data_memory" +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic" +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_WRITABLE 1 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_DUAL_PORT 1 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_VALUE 8192 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_SIZE_MULTIPLE 1 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_CONTENTS_INFO "" +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_RAM_BLOCK_TYPE "Auto" +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INIT_MEM_CONTENT 1 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_INSTANCE_ID "NONE" +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE" +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_HEX 1 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define DMA_WRITE_MASTER_TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR + +/* + * Macros for device 'epcs_controller', class 'altera_avalon_epcs_flash_controller' + * The macros are prefixed with 'EPCS_CONTROLLER_'. + * The prefix is the slave descriptor. + */ +#define EPCS_CONTROLLER_COMPONENT_TYPE altera_avalon_epcs_flash_controller +#define EPCS_CONTROLLER_COMPONENT_NAME epcs_controller +#define EPCS_CONTROLLER_BASE 0x3200000 +#define EPCS_CONTROLLER_SPAN 2048 +#define EPCS_CONTROLLER_END 0x32007ff +#define EPCS_CONTROLLER_IRQ 5 +#define EPCS_CONTROLLER_REGISTER_OFFSET 512 +#define EPCS_CONTROLLER_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32 +#define EPCS_CONTROLLER_MEMORY_INFO_MEM_INIT_FILENAME epcs_controller_boot_rom +#define EPCS_CONTROLLER_MEMORY_INFO_IS_EPCS 1 +#define EPCS_CONTROLLER_MEMORY_INFO_IS_FLASH 1 +#define EPCS_CONTROLLER_MEMORY_INFO_GENERATE_HEX 1 +#define EPCS_CONTROLLER_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define EPCS_CONTROLLER_MEMORY_INFO_GENERATE_FLASH 1 +#define EPCS_CONTROLLER_MEMORY_INFO_HEX_INSTALL_DIR SIM_DIR +#define EPCS_CONTROLLER_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR +#define EPCS_CONTROLLER_MEMORY_INFO_FLASH_INSTALL_DIR APP_DIR + +/* + * Macros for device 'sdram', class 'ddr_sdram_component_classic' + * The macros are prefixed with 'SDRAM_'. + * The prefix is the slave descriptor. + */ +#define SDRAM_COMPONENT_TYPE ddr_sdram_component_classic +#define SDRAM_COMPONENT_NAME sdram +#define SDRAM_BASE 0x6000000 +#define SDRAM_SPAN 33554432 +#define SDRAM_END 0x7ffffff +#define SDRAM_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32 +#define SDRAM_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define SDRAM_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR + +/* + * Macros for device 'tightly_coupled_instruction_memory', class 'altera_avalon_onchip_memory2' + * The macros are prefixed with 'TIGHTLY_COUPLED_INSTRUCTION_MEMORY_'. + * The prefix is the slave descriptor. + */ +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_COMPONENT_NAME tightly_coupled_instruction_memory +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_BASE 0x8000000 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_SPAN 4096 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_END 0x8000fff +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_instruction_memory" +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic" +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_WRITABLE 1 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_DUAL_PORT 1 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_SIZE_VALUE 4096 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_SIZE_MULTIPLE 1 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_CONTENTS_INFO "" +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_RAM_BLOCK_TYPE "Auto" +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_INIT_MEM_CONTENT 1 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_INSTANCE_ID "NONE" +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE" +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_GENERATE_HEX 1 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define TIGHTLY_COUPLED_INSTRUCTION_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR + +/* + * Macros for device 'tightly_coupled_data_memory', class 'altera_avalon_onchip_memory2' + * The macros are prefixed with 'TIGHTLY_COUPLED_DATA_MEMORY_'. + * The prefix is the slave descriptor. + */ +#define TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_TYPE altera_avalon_onchip_memory2 +#define TIGHTLY_COUPLED_DATA_MEMORY_COMPONENT_NAME tightly_coupled_data_memory +#define TIGHTLY_COUPLED_DATA_MEMORY_BASE 0x8002000 +#define TIGHTLY_COUPLED_DATA_MEMORY_SPAN 8192 +#define TIGHTLY_COUPLED_DATA_MEMORY_END 0x8003fff +#define TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 +#define TIGHTLY_COUPLED_DATA_MEMORY_INIT_CONTENTS_FILE "tightly_coupled_data_memory" +#define TIGHTLY_COUPLED_DATA_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0 +#define TIGHTLY_COUPLED_DATA_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic" +#define TIGHTLY_COUPLED_DATA_MEMORY_WRITABLE 1 +#define TIGHTLY_COUPLED_DATA_MEMORY_DUAL_PORT 1 +#define TIGHTLY_COUPLED_DATA_MEMORY_SIZE_VALUE 8192 +#define TIGHTLY_COUPLED_DATA_MEMORY_SIZE_MULTIPLE 1 +#define TIGHTLY_COUPLED_DATA_MEMORY_CONTENTS_INFO "" +#define TIGHTLY_COUPLED_DATA_MEMORY_RAM_BLOCK_TYPE "Auto" +#define TIGHTLY_COUPLED_DATA_MEMORY_INIT_MEM_CONTENT 1 +#define TIGHTLY_COUPLED_DATA_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 +#define TIGHTLY_COUPLED_DATA_MEMORY_INSTANCE_ID "NONE" +#define TIGHTLY_COUPLED_DATA_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE" +#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32 +#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HAS_BYTE_LANE 0 +#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_HEX 1 +#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR +#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_GENERATE_DAT_SYM 1 +#define TIGHTLY_COUPLED_DATA_MEMORY_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR + + +#endif /* _CUSTOM_FPGA_H_ */ diff --git a/board/altera/nios2-generic/nios2-generic.c b/board/altera/nios2-generic/nios2-generic.c new file mode 100644 index 0000000..d15418d --- /dev/null +++ b/board/altera/nios2-generic/nios2-generic.c @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <nios2-io.h> + +int board_early_init_f(void) +{ + return 0; +} + +int checkboard(void) +{ + printf("BOARD : %s\n", CONFIG_SYS_BOARD_NAME); + return 0; +} + +phys_size_t initdram(int board_type) +{ + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(bis, CONFIG_SMC91111_BASE); +#endif + +#ifdef CONFIG_DRIVER_DM9000 + rc = dm9000_initialize(bis); +#endif + +#ifdef CONFIG_ALTERA_TSE + altera_tse_init(bis, CONFIG_SYS_NUM_TSE_MACS); +#endif + +#ifdef CONFIG_ETHOC + rc = ethoc_initialize(bis, CONFIG_SYS_ETHOC_BASE); +#endif + return rc; +} +#endif diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds new file mode 100644 index 0000000..fa7ed30 --- /dev/null +++ b/board/altera/nios2-generic/u-boot.lds @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-littlenios2") +OUTPUT_ARCH(nios2) +ENTRY(_start) + +SECTIONS +{ + . = text_base; + .text : + { + cpu/nios2/start.o (.text) + *(.text) + *(.text.*) + *(.gnu.linkonce.t*) + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + *(.gnu.linkonce.r*) + } + . = ALIGN (4); + _etext = .; + PROVIDE (etext = .); + + /* CMD TABLE - sandwich this in between text and data so + * the initialization code relocates the command table as + * well -- admittedly, this is just pure laziness ;-) + */ + __u_boot_cmd_start = .; + .u_boot_cmd : + { + *(.u_boot_cmd) + } + . = ALIGN(4); + __u_boot_cmd_end = .; + + /* INIT DATA sections - "Small" data (see the gcc -G option) + * is always gp-relative. Here we make all init data sections + * adjacent to simplify the startup code -- and provide + * the global pointer for gp-relative access. + */ + _data = .; + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + } + + . = ALIGN(16); + _gp = .; /* Global pointer addr */ + PROVIDE (gp = .); + + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* UNINIT DATA - Small uninitialized data is first so it's + * adjacent to sdata and can be referenced via gp. The normal + * bss follows. We keep it adjacent to simplify init code. + */ + __bss_start = .; + .sbss (NOLOAD) : + { + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } + . = ALIGN(4); + .bss (NOLOAD) : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + *(.scommon) + } + . = ALIGN(4); + _end = .; + PROVIDE (end = .); + + /* DEBUG -- symbol table, string table, etc. etc. + */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h new file mode 100644 index 0000000..024070e --- /dev/null +++ b/include/configs/nios2-generic.h @@ -0,0 +1,360 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "../board/altera/nios2-generic/custom_fpga.h" +#define CONFIG_SYS_BOARD_NAME "custom fpga" + +#ifndef KERNEL_REGION_BASE +# define KERNEL_REGION_BASE 0 +#endif + +#ifndef IO_REGION_BASE +# define IO_REGION_BASE 0x80000000 +#endif + +/* + * BOARD/CPU + */ +#define CONFIG_NIOS2_GENERIC 1 /* custom fpga board */ +#define CONFIG_SYS_CLK_FREQ CPU_FREQ /* core clk */ + +#define CONFIG_SYS_RESET_ADDR RESET_ADDR /* Hard-reset address */ +#define CONFIG_SYS_EXCEPTION_ADDR EXCEPTION_ADDR /* Exception entry point */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init */ + +/* + * CACHE -- the following will support II/s and II/f. The II/s does not + * have dcache, so the cache instructions will behave as NOPs. + */ +#define CONFIG_SYS_ICACHE_SIZE ICACHE_SIZE +#define CONFIG_SYS_ICACHELINE_SIZE ICACHE_LINE_SIZE +#define CONFIG_SYS_DCACHE_SIZE DCACHE_SIZE +#define CONFIG_SYS_DCACHELINE_SIZE DCACHE_LINE_SIZE + +/* + * MEMORY BASE ADDRESSES + */ +#define CONFIG_SYS_SDRAM_BASE (SDRAM_BASE | KERNEL_REGION_BASE) /* SDRAM base addr */ +#define CONFIG_SYS_SDRAM_SIZE (SDRAM_SPAN) + +/* + * GPIO + */ +#define CONFIG_SYS_GPIO_BASE (GPIO_BASE | IO_REGION_BASE) +#ifdef CONFIG_SYS_GPIO_BASE +# define CONFIG_SYS_GPIO_SDA 0 /* bitbang i2c sda */ +# define CONFIG_SYS_GPIO_SCL 1 /* bitbang i2c scl */ +# define CONFIG_SYS_GPIO_NRB 2 /* nand flash ready/busy */ +# define CONFIG_SYS_GPIO_HBT 3 /* heartbeat status led */ +#endif + +/* + * Flash Settings + */ +/* #define CONFIG_SYS_NO_FLASH */ +#define CONFIG_FLASH_CFI_DRIVER +/* #define CONFIG_FLASH_CFI_MTD */ + +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix nios2 flash timing issue */ +#define CONFIG_SYS_FLASH_BASE (EXT_FLASH_BASE | IO_REGION_BASE) +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* + * SPI FLash,EPCS Settings + */ +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_ALTERA_SPI + +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SYS_SPI_BASE ((EPCS_CONTROLLER_BASE + EPCS_CONTROLLER_REGISTER_OFFSET) \ + | IO_REGION_BASE) + +/* + * NAND Flash + */ +/* #define CONFIG_CMD_NAND */ +/* #define CONFIG_NAND_PLAT */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE (NAND_FLASH_BASE | IO_REGION_BASE) +#define NIOS2_NAND_PLAT_CLE 2 +#define NIOS2_NAND_PLAT_ALE 3 +#define NAND_PLAT_WRITE_CMD(chip, cmd) \ + writeb(cmd, (unsigned int)(this->IO_ADDR_W) + (1 << NIOS2_NAND_PLAT_CLE)) +#define NAND_PLAT_WRITE_ADR(chip, cmd) \ + writeb(cmd, (unsigned int)(this->IO_ADDR_W) + (1 << NIOS2_NAND_PLAT_ALE)) +#define NAND_PLAT_INIT() {} +#ifdef CONFIG_SYS_GPIO_NRB +# define NAND_PLAT_DEV_READY(chip) \ + readl(CONFIG_SYS_GPIO_BASE + ((CONFIG_SYS_GPIO_NRB) << 2)) +#endif + +/* + * SERIAL + */ +#define CONFIG_ALTERA_JTAGUART +/* #define CONFIG_ALTERA_UART */ +/* #define CONFIG_YANU */ + +#define CONFIG_SYS_JTAGUART_BASE (JTAG_UART_BASE | IO_REGION_BASE) /* JTAGUART base addr */ +#define CONFIG_SYS_UART_BASE (UART_BASE | IO_REGION_BASE) /* UART base addr */ +#define CONFIG_SYS_UART_FREQ UART_FREQ /* UART clock in freq */ +#define CONFIG_SYS_YANU_BASE (YANU_BASE | IO_REGION_BASE) /* YANU base addr */ +#define CONFIG_SYS_YANU_FREQ YANU_FREQ /* YANU clock in freq */ + +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info */ + +/* + * SYSID + */ +#define CONFIG_SYS_NIOS_SYSID_BASE (SYSID_BASE | IO_REGION_BASE) /* Sysid base addr */ + +/* + * TIMER + */ +#define CONFIG_SYS_TIMER_BASE (TIMER_BASE | IO_REGION_BASE) /* Tick timer base addr */ +#define CONFIG_SYS_TIMER_IRQ TIMER_IRQ /* Timer IRQ num */ +#define CONFIG_SYS_TIMER_FREQ TIMER_FREQ /* Timer input freq */ +#define CONFIG_SYS_HZ 1000 /* should be 1000 for flash timing */ + +/* + * STATUS LED + */ +#define CONFIG_STATUS_LED /* Enable status driver */ +#define CONFIG_EPLED /* Enable LED PIO driver */ +#define CONFIG_SYS_LED_PIO_BASE (LED_PIO_BASE | IO_REGION_BASE) /* LED PIO base addr */ +/* #define CONFIG_GPIOLED */ /* Enable gpio LED driver */ + +#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ +#define STATUS_LED_STATE 1 /* Blinking */ +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* Every 500 msec */ + +/* + * IDE support + */ +#define CONFIG_CMD_IDE + +#define CONFIG_SYS_PIO_MODE 1 +#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 1 +#define CONFIG_SYS_ATA_BASE_ADDR (CF_IDE_BASE | IO_REGION_BASE) +#define CONFIG_SYS_ATA_STRIDE 4 /* 1bit shift */ +#define CONFIG_SYS_ATA_DATA_OFFSET 0x0 /* data reg offset */ +#define CONFIG_SYS_ATA_REG_OFFSET 0x0 /* reg offset */ +#define CONFIG_SYS_ATA_ALT_OFFSET 0x20 /* alternate register offset */ +#define CONFIG_SYS_CF_CTL_BASE (CF_CTL_BASE | IO_REGION_BASE) +#define CONFIG_IDE_RESET + +/* + * ETHERNET + */ +#define CONFIG_CMD_NET +#define CONFIG_NET_MULTI + +#define CONFIG_SMC91111 +#define CONFIG_SMC91111_BASE ((ENET_BASE + ENET_LAN91C111_REGISTERS_OFFSET) \ + | IO_REGION_BASE) /* Base addr */ +#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ +#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ + +/* #define CONFIG_DRIVER_DM9000 */ +#define CONFIG_DM9000_BASE (DM9000_BASE | IO_REGION_BASE) +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_USE_16BIT 1 +#define CONFIG_DM9000_NO_SROM 1 +/* #define CONFIG_NET_RETRY_COUNT 20 */ +/* #define CONFIG_RESET_PHY_R 1 */ + +/* #define CONFIG_ALTERA_TSE */ +/* #define CONFIG_MII 1 */ +/* #define CONFIG_CMD_MII */ +#define CONFIG_ETHPRIME "tse0" +#undef CONFIG_PCI + +#define CONFIG_SYS_NUM_TSE_MACS 1 +#define CONFIG_SYS_ALTERA_TSE_0_NAME "tse0" +#define CONFIG_SYS_ALTERA_TSE_0_BASE (TSE_MAC_BASE | IO_REGION_BASE) +#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_BASE (SGDMA_RX_BASE | IO_REGION_BASE) +#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_BASE (SGDMA_TX_BASE | IO_REGION_BASE) +#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_IRQ SGDMA_RX_IRQ +#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_IRQ SGDMA_TX_IRQ +#define CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM 0 +#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE (DESCRIPTOR_MEMORY_BASE | IO_REGION_BASE) +#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN DESCRIPTOR_MEMORY_SPAN +#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH TSE_MAC_RECEIVE_FIFO_DEPTH +#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH TSE_MAC_TRANSMIT_FIFO_DEPTH +#define CONFIG_SYS_ALTERA_TSE_0_PHY_ADDR 18 + +/* TSE Supported modes */ +/* GMII/MII = 0 */ +/* RGMII = 1 */ +/* RGMII_ID = 2 */ +/* RGMII_TXID = 3 */ +/* RGMII_RXID = 4 */ +/* SGMII = 5 */ +#define CONFIG_SYS_ALTERA_TSE_0_FLAGS 0x0 + + +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.2.21 +#define CONFIG_SERVERIP 192.168.2.16 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BOOTD +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + +#ifdef CONFIG_CMD_NET +# define CONFIG_CMD_DHCP +# define CONFIG_CMD_PING +#else +# undef CONFIG_CMD_BOOTD +# undef CONFIG_CMD_NET +# undef CONFIG_CMD_NFS +# endif + +/* #define CONFIG_CMD_SAVES */ +/* #define CONFIG_CMD_JFFS2 */ +/* #define CONFIG_JFFS2_CMDLINE */ +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +/* #define CONFIG_CMD_UBI */ +/* #define CONFIG_CMD_UBIFS */ +/* #define CONFIG_RBTREE */ +/* #define CONFIG_MTD_DEVICE */ +/* #define CONFIG_MTD_PARTITIONS */ +/* #define CONFIG_CMD_MTDPARTS */ +/* #define CONFIG_LZO */ + +/* + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ +#define CONFIG_ENV_SIZE (128 * 1024) /* 128 KByte (1 sector) */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + +#if !defined(CONFIG_ENV_IS_IN_FLASH) +# define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ +#endif + +/* + * MEMORY ORGANIZATION + * -Text (code) at top of sdram. + * -The heap is placed below the text + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). + * -Monitor is the code in flash, we will relocate it to text in sdram + */ +#ifdef CONFIG_CMD_UBI +# define CONFIG_SYS_TEXT_LEN (256 * 1024) /* Reserve 256k */ +#else +# define CONFIG_SYS_TEXT_LEN (512 * 1024) /* Reserve 512k, ubi is big */ +#endif +#define CONFIG_SYS_TEXT_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_TEXT_LEN) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_RESET_ADDR | IO_REGION_BASE) +#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_TEXT_LEN +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* Global data size rsvd */ +#ifdef CONFIG_CMD_UBI /* ubi needs >512KB malloc */ +# define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) +#else +# define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#endif +#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET + +/* + * MISC + */ +#define CONFIG_SYS_LONGHELP /* Provide extended help */ +#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ +#define CONFIG_SYS_MAXARGS 16 /* Max command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ +#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 + +#if defined(CONFIG_NAND_PLAT) +# define MTD_ENV_SETTINGS \ + "mtdids=nand0=nand0\0" \ + "mtdparts=mtdparts=nand0:-(data)\0" +#elif defined(CONFIG_FLASH_CFI_DRIVER) +# define MTD_ENV_SETTINGS \ + "mtdids=nor0=nor0\0" \ + "mtdparts=mtdparts=nor0:2m(boot),6m(romfs),4m(user),4m(factory)\0" +#else +# define MTD_ENV_SETTINGS +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MTD_ENV_SETTINGS + +#define CONFIG_CMDLINE_EDITING + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +#endif /* __CONFIG_H */ -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 02/28] cfi flash: add status polling method for amd flash 2010-03-19 7:43 ` [U-Boot] [PATCH 01/28] nios2: add nios2-generic board Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 03/28] serial: move altera uart driver to drivers/serial Thomas Chou 2010-04-05 5:36 ` [U-Boot] [PATCH 01/28] nios2: add nios2-generic board Ben Warren 1 sibling, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This patch adds status polling method to offer an alternative to data toggle method for amd flash chips. This patch is needed for nios2 cfi flash interface, where the bus controller performs 4 bytes read cycles for a single byte read instruction. The data toggle method can not detect chip busy status correctly. So we have to poll DQ7, which will be inverted when the chip is busy. This feature is enabled with the config def, CONFIG_SYS_CFI_FLASH_STATUS_POLL Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- drivers/mtd/cfi_flash.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 92 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index fdba297..4baa9dc 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -555,6 +555,50 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector, return ERR_OK; } +#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL +static int flash_status_poll(flash_info_t *info, cfiword_t cword, void *addr, + ulong tout, char *prompt) +{ + ulong start; + int ready; + +#if CONFIG_SYS_HZ != 1000 + tout *= CONFIG_SYS_HZ/1000; +#endif + + /* Wait for command completion */ + start = get_timer(0); + while (1) { + switch (info->portwidth) { + case FLASH_CFI_8BIT: + ready = flash_read8(addr) == cword.c; + break; + case FLASH_CFI_16BIT: + ready = flash_read16(addr) == cword.w; + break; + case FLASH_CFI_32BIT: + ready = flash_read32(addr) == cword.l; + break; + case FLASH_CFI_64BIT: + ready = flash_read64(addr) == cword.ll; + break; + default: + ready = 0; + break; + } + if (ready) + break; + if (get_timer(start) > tout) { + printf("Flash %s timeout at address %lx data %lx\n", + prompt, (ulong)addr, (ulong)flash_read8(addr)); + return ERR_TIMOUT; + } + udelay(1); /* also triggers watchdog */ + } + return ERR_OK; +} +#endif + /*----------------------------------------------------------------------- * Wait for XSR.7 to be set, if it times out print an error, otherwise * do a full status check. @@ -749,6 +793,13 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, if (!sect_found) sect = find_sector (info, dest); +#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL + if (info->vendor == CFI_CMDSET_AMD_EXTENDED || + info->vendor == CFI_CMDSET_AMD_STANDARD) + return flash_status_poll(info, cword, dstaddr, + info->write_tout, "write"); + else +#endif return flash_full_status_check (info, sect, info->write_tout, "write"); } @@ -767,6 +818,7 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, uint offset = 0; unsigned int shift; uchar write_cmd; + cfiword_t cword; switch (info->portwidth) { case FLASH_CFI_8BIT: @@ -911,9 +963,35 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, } flash_write_cmd (info, sector, 0, AMD_CMD_WRITE_BUFFER_CONFIRM); +#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL + switch (info->portwidth) { + case FLASH_CFI_8BIT: + cword.c = flash_read8(src - 1); + dst -= 1; + break; + case FLASH_CFI_16BIT: + cword.w = flash_read16(src - 2); + dst -= 2; + break; + case FLASH_CFI_32BIT: + cword.l = flash_read32(src - 4); + dst -= 4; + break; + case FLASH_CFI_64BIT: + cword.ll = flash_read64(src - 8); + dst -= 8; + break; + default: + retcode = ERR_INVAL; + goto out_unmap; + } + retcode = flash_status_poll(info, cword, dst, + info->buffer_write_tout, "buffer write"); +#else retcode = flash_full_status_check (info, sector, info->buffer_write_tout, "buffer write"); +#endif break; default: @@ -935,6 +1013,8 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) int rcode = 0; int prot; flash_sect_t sect; + cfiword_t cword = (cfiword_t) 0xffffffffffffffffULL; + ulong dest; if (info->flash_id != FLASH_MAN_CFI) { puts ("Can't erase unknown flash type - aborted\n"); @@ -998,6 +1078,17 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) break; } +#ifdef CONFIG_SYS_CFI_FLASH_STATUS_POLL + dest = (ulong)flash_map(info, sect, 0); + flash_unmap(info, sect, 0, (void *)dest); + if ((info->vendor == CFI_CMDSET_AMD_EXTENDED || + info->vendor == CFI_CMDSET_AMD_STANDARD) && + flash_status_poll(info, cword, (void *)dest, + info->erase_blk_tout, "erase")) + rcode = 1; + else + +#endif if (flash_full_status_check (info, sect, info->erase_blk_tout, "erase")) { rcode = 1; @@ -1980,8 +2071,7 @@ unsigned long flash_init (void) } /* Monitor protection ON by default */ -#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \ - (!defined(CONFIG_MONITOR_IS_IN_RAM)) +#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 03/28] serial: move altera uart driver to drivers/serial 2010-03-19 7:43 ` [U-Boot] [PATCH 02/28] cfi flash: add status polling method for amd flash Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 04/28] serial: move altera jtaguart " Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This patch moves the altera uart driver from cpu/nios2/serial.c to drivers/serial/altera_uart.c. The registers access is changed from "volatile struct" to readl()/ writel(). This is consistent with Altera HAL and Linux. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- drivers/serial/Makefile | 1 + drivers/serial/altera_uart.c | 116 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 117 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/altera_uart.c diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 3c77a7c..7ce920d 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libserial.a +COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o COBJS-$(CONFIG_AT91RM9200_USART) += at91rm9200_usart.o COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o diff --git a/drivers/serial/altera_uart.c b/drivers/serial/altera_uart.c new file mode 100644 index 0000000..b8c97b2 --- /dev/null +++ b/drivers/serial/altera_uart.c @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * (C) Copyright 2008, Thomas Chou <thomas@wytron.com.tw> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Altera UART reg defs + */ + +#define ALTERA_UART_SIZE 32 + +#define ALTERA_UART_RXDATA_REG 0 +#define ALTERA_UART_TXDATA_REG 4 +#define ALTERA_UART_STATUS_REG 8 +#define ALTERA_UART_CONTROL_REG 12 +#define ALTERA_UART_DIVISOR_REG 16 +#define ALTERA_UART_EOP_REG 20 + +#define ALTERA_UART_STATUS_PE_MSK (0x1) +#define ALTERA_UART_STATUS_FE_MSK (0x2) +#define ALTERA_UART_STATUS_BRK_MSK (0x4) +#define ALTERA_UART_STATUS_ROE_MSK (0x8) +#define ALTERA_UART_STATUS_TOE_MSK (0x10) +#define ALTERA_UART_STATUS_TMT_MSK (0x20) +#define ALTERA_UART_STATUS_TRDY_MSK (0x40) +#define ALTERA_UART_STATUS_RRDY_MSK (0x80) +#define ALTERA_UART_STATUS_E_MSK (0x100) +#define ALTERA_UART_STATUS_DCTS_MSK (0x400) +#define ALTERA_UART_STATUS_CTS_MSK (0x800) +#define ALTERA_UART_STATUS_EOP_MSK (0x1000) + +#define ALTERA_UART_CONTROL_PE_MSK (0x1) +#define ALTERA_UART_CONTROL_FE_MSK (0x2) +#define ALTERA_UART_CONTROL_BRK_MSK (0x4) +#define ALTERA_UART_CONTROL_ROE_MSK (0x8) +#define ALTERA_UART_CONTROL_TOE_MSK (0x10) +#define ALTERA_UART_CONTROL_TMT_MSK (0x20) +#define ALTERA_UART_CONTROL_TRDY_MSK (0x40) +#define ALTERA_UART_CONTROL_RRDY_MSK (0x80) +#define ALTERA_UART_CONTROL_E_MSK (0x100) +#define ALTERA_UART_CONTROL_TRBK_MSK (0x200) +#define ALTERA_UART_CONTROL_DCTS_MSK (0x400) +#define ALTERA_UART_CONTROL_RTS_MSK (0x800) +#define ALTERA_UART_CONTROL_EOP_MSK (0x1000) + +#define ALTERA_UART_EOP_MSK (0xFF) +#define ALTERA_UART_EOP_OFST (0) + +void serial_setbrg(void) +{ + unsigned div; + + div = (CONFIG_SYS_UART_FREQ / gd->baudrate) - 1; + writel(div, CONFIG_SYS_UART_BASE + ALTERA_UART_DIVISOR_REG); + return; +} + +int serial_init(void) +{ + serial_setbrg(); + return 0; +} + +void serial_putc(char c) +{ + if (c == '\n') + serial_putc('\r'); + while ((readl(CONFIG_SYS_UART_BASE + ALTERA_UART_STATUS_REG) + & ALTERA_UART_CONTROL_TRDY_MSK) == 0) + WATCHDOG_RESET(); + writel((unsigned char)c, CONFIG_SYS_UART_BASE + ALTERA_UART_TXDATA_REG); +} + +void serial_puts(const char *s) +{ + while (*s != 0) + serial_putc(*s++); +} + +int serial_tstc(void) +{ + return readl(CONFIG_SYS_UART_BASE + ALTERA_UART_STATUS_REG) + & ALTERA_UART_STATUS_RRDY_MSK; +} + +int serial_getc(void) +{ + while (serial_tstc() == 0) + WATCHDOG_RESET(); + return readl(CONFIG_SYS_UART_BASE + ALTERA_UART_RXDATA_REG) & 0x00ff; +} -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 04/28] serial: move altera jtaguart driver to drivers/serial 2010-03-19 7:43 ` [U-Boot] [PATCH 03/28] serial: move altera uart driver to drivers/serial Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 05/28] serial: move yanu " Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This patch moves the altera jtaguart driver from cpu/nios2/serial.c to drivers/serial/altera_jtaguart.c. The registers access is changed from "volatile struct" to readl()/ writel(). This is consistent with Altera HAL and Linux. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- drivers/serial/Makefile | 1 + drivers/serial/altera_jtaguart.c | 107 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/altera_jtaguart.c diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 7ce920d..a7278ae 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libserial.a +COBJS-$(CONFIG_ALTERA_JTAGUART) += altera_jtaguart.o COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o COBJS-$(CONFIG_AT91RM9200_USART) += at91rm9200_usart.o diff --git a/drivers/serial/altera_jtaguart.c b/drivers/serial/altera_jtaguart.c new file mode 100644 index 0000000..de58356 --- /dev/null +++ b/drivers/serial/altera_jtaguart.c @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * (C) Copyright 2008, Thomas Chou <thomas@wytron.com.tw> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Altera JTAG UART register definitions according to the Altera JTAG UART + * datasheet: http://www.altera.com/literature/hb/nios2/n2cpu_nii51009.pdf + */ + +#define ALTERA_JTAGUART_SIZE 8 + +#define ALTERA_JTAGUART_DATA_REG 0 + +#define ALTERA_JTAGUART_DATA_DATA_MSK 0x000000FF +#define ALTERA_JTAGUART_DATA_RVALID_MSK 0x00008000 +#define ALTERA_JTAGUART_DATA_RAVAIL_MSK 0xFFFF0000 +#define ALTERA_JTAGUART_DATA_RAVAIL_OFF 16 + +#define ALTERA_JTAGUART_CONTROL_REG 4 + +#define ALTERA_JTAGUART_CONTROL_RE_MSK 0x00000001 +#define ALTERA_JTAGUART_CONTROL_WE_MSK 0x00000002 +#define ALTERA_JTAGUART_CONTROL_RI_MSK 0x00000100 +#define ALTERA_JTAGUART_CONTROL_RI_OFF 8 +#define ALTERA_JTAGUART_CONTROL_WI_MSK 0x00000200 +#define ALTERA_JTAGUART_CONTROL_AC_MSK 0x00000400 +#define ALTERA_JTAGUART_CONTROL_RRDY_MSK 0x00001000 +#define ALTERA_JTAGUART_CONTROL_WSPACE_MSK 0xFFFF0000 +#define ALTERA_JTAGUART_CONTROL_WSPACE_OFF 16 + +void serial_setbrg(void) +{ +} + +int serial_init(void) +{ + serial_setbrg(); + return 0; +} + +void serial_putc(char c) +{ + unsigned status; + while (((status = + readl(CONFIG_SYS_JTAGUART_BASE + ALTERA_JTAGUART_CONTROL_REG)) + & ALTERA_JTAGUART_CONTROL_WSPACE_MSK) == 0) { + if ((status & ALTERA_JTAGUART_CONTROL_AC_MSK) == 0) + return; /* no connection, bypass */ + WATCHDOG_RESET(); + } + writel((unsigned char)c, + CONFIG_SYS_JTAGUART_BASE + ALTERA_JTAGUART_DATA_REG); +} + +void serial_puts(const char *s) +{ + while (*s != 0) + serial_putc(*s++); +} + +int serial_tstc(void) +{ + return readl(CONFIG_SYS_JTAGUART_BASE + ALTERA_JTAGUART_CONTROL_REG) + & ALTERA_JTAGUART_CONTROL_RRDY_MSK; +} + +int serial_getc(void) +{ + int c; + unsigned val; + + while (1) { + WATCHDOG_RESET(); + val = + readl(CONFIG_SYS_JTAGUART_BASE + ALTERA_JTAGUART_DATA_REG); + if (val & ALTERA_JTAGUART_DATA_RVALID_MSK) + break; + } + c = val & 0x0ff; + return c; +} -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 05/28] serial: move yanu driver to drivers/serial 2010-03-19 7:43 ` [U-Boot] [PATCH 04/28] serial: move altera jtaguart " Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 06/28] spi: add altera spi controller support Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This patch moves the opencore yanu serial driver to the drivers/serial directory. The nios2-yanu.h header is moved to drivers/serial/yanu.h. The args of writel() are changed to writel(val, port). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- drivers/serial/Makefile | 1 + drivers/serial/yanu.c | 187 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/serial/yanu.h | 120 ++++++++++++++++++++++++++++++ 3 files changed, 308 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/yanu.c create mode 100644 drivers/serial/yanu.h diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index a7278ae..6d0f9c8 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -55,6 +55,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_USB_TTY) += usbtty.o +COBJS-$(CONFIG_YANU) += yanu.o COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) diff --git a/drivers/serial/yanu.c b/drivers/serial/yanu.c new file mode 100644 index 0000000..ca71395 --- /dev/null +++ b/drivers/serial/yanu.c @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * YANU Support: + * Copyright 2010, Renato Andreola <renato.andreola@imagos.it> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> +#include "yanu.h" + +DECLARE_GLOBAL_DATA_PTR; + +static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_YANU_BASE; + +#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) + +/* Everything's already setup for fixed-baud PTF assignment*/ + +void serial_setbrg(void) +{ + int n, k; + const unsigned max_uns = 0xFFFFFFFF; + unsigned best_n, best_m, baud; + + /* compute best N and M couple */ + best_n = YANU_MAX_PRESCALER_N; + for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { + if ((unsigned)CONFIG_SYS_YANU_FREQ / (1 << (n + 4)) >= + (unsigned)CONFIG_BAUDRATE) { + best_n = n; + break; + } + } + for (k = 0;; k++) { + if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k))) + break; + } + best_m = + ((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) / + ((unsigned)CONFIG_SYS_YANU_FREQ >> k); + + baud = best_m + best_n * YANU_BAUDE; + writel(baud, &uart->baud); + + return; +} + +#else + +void serial_setbrg(void) +{ + int n, k; + const unsigned max_uns = 0xFFFFFFFF; + unsigned best_n, best_m, baud; + + /* compute best N and M couple */ + best_n = YANU_MAX_PRESCALER_N; + for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { + if ((unsigned)CONFIG_SYS_YANU_FREQ / (1 << (n + 4)) >= + gd->baudrate) { + best_n = n; + break; + } + } + for (k = 0;; k++) { + if (gd->baudrate <= (max_uns >> (15+n-k))) + break; + } + best_m = + (gd->baudrate * (1 << (15 + n - k))) / + ((unsigned)CONFIG_SYS_YANU_FREQ >> k); + + baud = best_m + best_n * YANU_BAUDE; + writel(baud, &uart->baud); + + return; +} + + +#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ + +int serial_init(void) +{ + unsigned action, control; + + /* status register cleanup */ + action = YANU_ACTION_RRRDY | + YANU_ACTION_RTRDY | + YANU_ACTION_ROE | + YANU_ACTION_RBRK | + YANU_ACTION_RFE | + YANU_ACTION_RPE | + YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR; + + writel(action, &uart->action); + + /* control register cleanup */ + /* no interrupts enabled */ + /* one stop bit */ + /* hardware flow control disabled */ + /* 8 bits */ + control = (0x7 << YANU_CONTROL_BITS_POS); + /* enven parity just to be clean */ + control |= YANU_CONTROL_PAREVEN; + /* we set threshold for fifo */ + control |= YANU_CONTROL_RDYDLY * YANU_RXFIFO_DLY; + control |= YANU_CONTROL_TXTHR * YANU_TXFIFO_THR; + + writel(control, &uart->control); + + /* to set baud rate */ + serial_setbrg(); + + return 0; +} + + +/*----------------------------------------------------------------------- + * YANU CONSOLE + *---------------------------------------------------------------------*/ +void serial_putc(char c) +{ + int tx_chars; + unsigned status; + + if (c == '\n') + serial_putc('\r'); + + while (1) { + status = readl(&uart->status); + tx_chars = (status>>YANU_TFIFO_CHARS_POS) + & ((1<<YANU_TFIFO_CHARS_N)-1); + if (tx_chars < YANU_TXFIFO_SIZE-1) + break; + WATCHDOG_RESET(); + } + + writel((unsigned char)c, &uart->data); +} + +void serial_puts(const char *s) +{ + while (*s != 0) + serial_putc(*s++); +} + + +int serial_tstc(void) +{ + unsigned status ; + + status = readl(&uart->status); + return (((status >> YANU_RFIFO_CHARS_POS) & + ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0); +} + +int serial_getc(void) +{ + while (serial_tstc() == 0) + WATCHDOG_RESET(); + + /* first we pull the char */ + writel(YANU_ACTION_RFIFO_PULL, &uart->action); + + return readl(&uart->data) & YANU_DATA_CHAR_MASK; +} diff --git a/drivers/serial/yanu.h b/drivers/serial/yanu.h new file mode 100644 index 0000000..bcaa895 --- /dev/null +++ b/drivers/serial/yanu.h @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2006, Imagos S.a.s <www.imagos.it> + * Renato Andreola <renato.andreola@imagos.it> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * Altera NiosII YANU serial interface by Imagos + * please see http://www.opencores.org/project,yanu for + * information/downloads + ************************************************************************/ + +#ifndef __NIOS2_YANU_H__ +#define __NIOS2_YANU_H__ + +#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */ +#define YANU_MAX_PRESCALER_M ((1 << 11) - 1) /* 2047 */ +#define YANU_FIFO_SIZE (16) +#define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE) +#define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE) + +#define YANU_RXFIFO_DLY (10*11) +#define YANU_TXFIFO_THR (10) +#define YANU_DATA_CHAR_MASK (0xFF) + +/* data register */ +#define YANU_DATA_OFFSET (0) /* data register offset */ + +#define YANU_CONTROL_OFFSET (4) /* control register offset */ +/* interrupt enable */ +#define YANU_CONTROL_IE_RRDY (1<<0) /* ie on received character ready */ +#define YANU_CONTROL_IE_OE (1<<1) /* ie on rx overrun */ +#define YANU_CONTROL_IE_BRK (1<<2) /* ie on break detect */ +#define YANU_CONTROL_IE_FE (1<<3) /* ie on framing error */ +#define YANU_CONTROL_IE_PE (1<<4) /* ie on parity error */ +#define YANU_CONTROL_IE_TRDY (1<<5) /* ie interrupt on tranmitter ready */ +/* control bits */ +#define YANU_CONTROL_BITS_POS (6) /* bits number pos */ +#define YANU_CONTROL_BITS (1<<YANU_CONTROL_BITS_POS) +/* number of rx/tx bits per word. 3 bit unsigned integer */ +#define YANU_CONTROL_BITS_N (3) /* ... its bit filed length */ +#define YANU_CONTROL_PARENA (1<<9) /* enable parity bit */ +#define YANU_CONTROL_PAREVEN (1<<10) /* parity even */ +#define YANU_CONTROL_STOPS (1<<11) /* number of stop bits */ +#define YANU_CONTROL_HHENA (1<<12) /* Harware Handshake enable... */ +#define YANU_CONTROL_FORCEBRK (1<<13) /* if set than txd = active (0) */ +/* tuning part */ +#define YANU_CONTROL_RDYDLY (1<<14) /* delay before setting rrdy (in bit) */ +#define YANU_CONTROL_RDYDLY_N (8) /* ... its bit filed length */ +#define YANU_CONTROL_TXTHR (1<<22) +/* tx interrupt threshold: the trdy set if txfifo_chars<= txthr (chars) */ +#define YANU_CONTROL_TXTHR_N (4) /* ... its bit field length */ + +#define YANU_BAUD_OFFSET (8) /* baud register offset */ +#define YANU_BAUDM (1<<0) /* baud mantissa lsb */ +#define YANU_BAUDM_N (12) /* ...its bit filed length */ +#define YANU_BAUDE (1<<12) /* baud exponent lsb */ +#define YANU_BAUDE_N (4) /* ...its bit field length */ + +#define YANU_ACTION_OFFSET (12) /* action register... write only */ +#define YANU_ACTION_RRRDY (1<<0) /* reset rrdy */ +#define YANU_ACTION_ROE (1<<1) /* reset oe */ +#define YANU_ACTION_RBRK (1<<2) /* reset brk */ +#define YANU_ACTION_RFE (1<<3) /* reset fe */ +#define YANU_ACTION_RPE (1<<4) /* reset pe */ +#define YANU_ACTION_SRRDY (1<<5) /* set rrdy */ +#define YANU_ACTION_SOE (1<<6) /* set oe */ +#define YANU_ACTION_SBRK (1<<7) /* set brk */ +#define YANU_ACTION_SFE (1<<8) /* set fe */ +#define YANU_ACTION_SPE (1<<9) /* set pe */ +#define YANU_ACTION_RFIFO_PULL (1<<10) +/* pull a char from rx fifo we MUST do it before taking a char */ +#define YANU_ACTION_RFIFO_CLEAR (1<<11) /* clear rx fifo */ +#define YANU_ACTION_TFIFO_CLEAR (1<<12) /* clear tx fifo */ +#define YANU_ACTION_RTRDY (1<<13) /* clear trdy */ +#define YANU_ACTION_STRDY (1<<14) /* set trdy */ + +#define YANU_STATUS_OFFSET (16) +#define YANU_STATUS_RRDY (1<<0) /* rxrdy flag */ +#define YANU_STATUS_TRDY (1<<1) /* txrdy flag */ +#define YANU_STATUS_OE (1<<2) /* rx overrun error */ +#define YANU_STATUS_BRK (1<<3) /* rx break detect flag */ +#define YANU_STATUS_FE (1<<4) /* rx framing error flag */ +#define YANU_STATUS_PE (1<<5) /* rx parity erro flag */ +#define YANU_RFIFO_CHARS_POS (6) +#define YANU_RFIFO_CHARS (1<<RFIFO_CHAR_POS) +/* number of chars into rx fifo */ +#define YANU_RFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */ +#define YANU_TFIFO_CHARS_POS (11) +#define YANU_TFIFO_CHARS (1<<TFIFO_CHAR_POS) +/* number of chars into tx fifo */ +#define YANU_TFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */ + +typedef volatile struct yanu_uart_t { + volatile unsigned data; + volatile unsigned control; /* control register (RW) 32-bit */ + volatile unsigned baud; /* baud/prescaler register (RW) 32-bit */ + volatile unsigned action; /* action register (W) 32-bit */ + volatile unsigned status; /* status register (R) 32-bit */ + volatile unsigned magic; /* magic register (R) 32-bit */ +} yanu_uart_t; + +#endif -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 06/28] spi: add altera spi controller support 2010-03-19 7:43 ` [U-Boot] [PATCH 05/28] serial: move yanu " Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 07/28] net: add opencore 10/100 ethernet mac support Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This patch adds the driver of altera spi controller, which is also used as epcs/spi flash controller. With the spi_flash driver, they can replace the epcs driver at cpu/nios2/epcs.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- drivers/spi/Makefile | 1 + drivers/spi/altera_spi.c | 103 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/altera_spi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index f112ed0..dfcbb8b 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libspi.a +COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c new file mode 100644 index 0000000..72097a6 --- /dev/null +++ b/drivers/spi/altera_spi.c @@ -0,0 +1,103 @@ +/* + * Altera SPI driver + * + * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <spi.h> + +#define ALTERA_SPI_RXDATA 0 +#define ALTERA_SPI_TXDATA 4 +#define ALTERA_SPI_STATUS 8 +#define ALTERA_SPI_CONTROL 12 +#define ALTERA_SPI_SLAVE_SEL 20 + +#define ALTERA_SPI_STATUS_ROE_MSK (0x8) +#define ALTERA_SPI_STATUS_TOE_MSK (0x10) +#define ALTERA_SPI_STATUS_TMT_MSK (0x20) +#define ALTERA_SPI_STATUS_TRDY_MSK (0x40) +#define ALTERA_SPI_STATUS_RRDY_MSK (0x80) +#define ALTERA_SPI_STATUS_E_MSK (0x100) + +#define ALTERA_SPI_CONTROL_IROE_MSK (0x8) +#define ALTERA_SPI_CONTROL_ITOE_MSK (0x10) +#define ALTERA_SPI_CONTROL_ITRDY_MSK (0x40) +#define ALTERA_SPI_CONTROL_IRRDY_MSK (0x80) +#define ALTERA_SPI_CONTROL_IE_MSK (0x100) +#define ALTERA_SPI_CONTROL_SSO_MSK (0x400) + +void spi_init(void) +{ + /* empty read buffer */ + if (readl(CONFIG_SYS_SPI_BASE + ALTERA_SPI_STATUS) & + ALTERA_SPI_STATUS_RRDY_MSK) + readl(CONFIG_SYS_SPI_BASE + ALTERA_SPI_RXDATA); + return; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct spi_slave *slave; + + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + slave->bus = bus; + slave->cs = cs; + + return slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + return; +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + int i, iter = bitlen >> 3; + const uchar *txp = dout; + uchar *rxp = din; + uchar d; + + if (flags & SPI_XFER_BEGIN) { + writel(1 << slave->cs, + CONFIG_SYS_SPI_BASE + ALTERA_SPI_SLAVE_SEL); + writel(ALTERA_SPI_CONTROL_SSO_MSK, + CONFIG_SYS_SPI_BASE + ALTERA_SPI_CONTROL); + } + + for (i = 0; i < iter; i++) { + writel(txp ? txp[i] : 0, + CONFIG_SYS_SPI_BASE + ALTERA_SPI_TXDATA); + while (!(readl(CONFIG_SYS_SPI_BASE + ALTERA_SPI_STATUS) & + ALTERA_SPI_STATUS_RRDY_MSK)) + ; + d = readl(CONFIG_SYS_SPI_BASE + ALTERA_SPI_RXDATA); + if (rxp) + rxp[i] = d; + } + if (flags & SPI_XFER_END) + writel(0, CONFIG_SYS_SPI_BASE + ALTERA_SPI_CONTROL); + + return 0; +} -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 07/28] net: add opencore 10/100 ethernet mac support 2010-03-19 7:43 ` [U-Boot] [PATCH 06/28] spi: add altera spi controller support Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 08/28] net: add altera triple speeds " Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This driver supports the opencore 10/100 ethernet mac. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- drivers/net/Makefile | 1 + drivers/net/ethoc.c | 536 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 537 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ethoc.c diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 1ec0ba1..0e68e52 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_E1000) += e1000.o COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o COBJS-$(CONFIG_EP93XX) += ep93xx_eth.o +COBJS-$(CONFIG_ETHOC) += ethoc.o COBJS-$(CONFIG_FEC_MXC) += fec_mxc.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o COBJS-$(CONFIG_FTMAC100) += ftmac100.o diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c new file mode 100644 index 0000000..3f7c5cd --- /dev/null +++ b/drivers/net/ethoc.c @@ -0,0 +1,536 @@ +/* + * Opencore 10/100 ethernet mac driver + * + * Copyright (C) 2007-2008 Avionic Design Development GmbH + * Copyright (C) 2008-2009 Avionic Design GmbH + * Thierry Reding <thierry.reding@avionic-design.de> + * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <net.h> +#include <miiphy.h> +#include <asm/io.h> +#include <asm/cache.h> + +/* register offsets */ +#define MODER 0x00 +#define INT_SOURCE 0x04 +#define INT_MASK 0x08 +#define IPGT 0x0c +#define IPGR1 0x10 +#define IPGR2 0x14 +#define PACKETLEN 0x18 +#define COLLCONF 0x1c +#define TX_BD_NUM 0x20 +#define CTRLMODER 0x24 +#define MIIMODER 0x28 +#define MIICOMMAND 0x2c +#define MIIADDRESS 0x30 +#define MIITX_DATA 0x34 +#define MIIRX_DATA 0x38 +#define MIISTATUS 0x3c +#define MAC_ADDR0 0x40 +#define MAC_ADDR1 0x44 +#define ETH_HASH0 0x48 +#define ETH_HASH1 0x4c +#define ETH_TXCTRL 0x50 + +/* mode register */ +#define MODER_RXEN (1 << 0) /* receive enable */ +#define MODER_TXEN (1 << 1) /* transmit enable */ +#define MODER_NOPRE (1 << 2) /* no preamble */ +#define MODER_BRO (1 << 3) /* broadcast address */ +#define MODER_IAM (1 << 4) /* individual address mode */ +#define MODER_PRO (1 << 5) /* promiscuous mode */ +#define MODER_IFG (1 << 6) /* interframe gap for incoming frames */ +#define MODER_LOOP (1 << 7) /* loopback */ +#define MODER_NBO (1 << 8) /* no back-off */ +#define MODER_EDE (1 << 9) /* excess defer enable */ +#define MODER_FULLD (1 << 10) /* full duplex */ +#define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */ +#define MODER_DCRC (1 << 12) /* delayed CRC enable */ +#define MODER_CRC (1 << 13) /* CRC enable */ +#define MODER_HUGE (1 << 14) /* huge packets enable */ +#define MODER_PAD (1 << 15) /* padding enabled */ +#define MODER_RSM (1 << 16) /* receive small packets */ + +/* interrupt source and mask registers */ +#define INT_MASK_TXF (1 << 0) /* transmit frame */ +#define INT_MASK_TXE (1 << 1) /* transmit error */ +#define INT_MASK_RXF (1 << 2) /* receive frame */ +#define INT_MASK_RXE (1 << 3) /* receive error */ +#define INT_MASK_BUSY (1 << 4) +#define INT_MASK_TXC (1 << 5) /* transmit control frame */ +#define INT_MASK_RXC (1 << 6) /* receive control frame */ + +#define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE) +#define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE) + +#define INT_MASK_ALL ( \ + INT_MASK_TXF | INT_MASK_TXE | \ + INT_MASK_RXF | INT_MASK_RXE | \ + INT_MASK_TXC | INT_MASK_RXC | \ + INT_MASK_BUSY \ + ) + +/* packet length register */ +#define PACKETLEN_MIN(min) (((min) & 0xffff) << 16) +#define PACKETLEN_MAX(max) (((max) & 0xffff) << 0) +#define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \ + PACKETLEN_MAX(max)) + +/* transmit buffer number register */ +#define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80) + +/* control module mode register */ +#define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */ +#define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */ +#define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */ + +/* MII mode register */ +#define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */ +#define MIIMODER_NOPRE (1 << 8) /* no preamble */ + +/* MII command register */ +#define MIICOMMAND_SCAN (1 << 0) /* scan status */ +#define MIICOMMAND_READ (1 << 1) /* read status */ +#define MIICOMMAND_WRITE (1 << 2) /* write control data */ + +/* MII address register */ +#define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0) +#define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8) +#define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \ + MIIADDRESS_RGAD(reg)) + +/* MII transmit data register */ +#define MIITX_DATA_VAL(x) ((x) & 0xffff) + +/* MII receive data register */ +#define MIIRX_DATA_VAL(x) ((x) & 0xffff) + +/* MII status register */ +#define MIISTATUS_LINKFAIL (1 << 0) +#define MIISTATUS_BUSY (1 << 1) +#define MIISTATUS_INVALID (1 << 2) + +/* TX buffer descriptor */ +#define TX_BD_CS (1 << 0) /* carrier sense lost */ +#define TX_BD_DF (1 << 1) /* defer indication */ +#define TX_BD_LC (1 << 2) /* late collision */ +#define TX_BD_RL (1 << 3) /* retransmission limit */ +#define TX_BD_RETRY_MASK (0x00f0) +#define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4) +#define TX_BD_UR (1 << 8) /* transmitter underrun */ +#define TX_BD_CRC (1 << 11) /* TX CRC enable */ +#define TX_BD_PAD (1 << 12) /* pad enable */ +#define TX_BD_WRAP (1 << 13) +#define TX_BD_IRQ (1 << 14) /* interrupt request enable */ +#define TX_BD_READY (1 << 15) /* TX buffer ready */ +#define TX_BD_LEN(x) (((x) & 0xffff) << 16) +#define TX_BD_LEN_MASK (0xffff << 16) + +#define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \ + TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR) + +/* RX buffer descriptor */ +#define RX_BD_LC (1 << 0) /* late collision */ +#define RX_BD_CRC (1 << 1) /* RX CRC error */ +#define RX_BD_SF (1 << 2) /* short frame */ +#define RX_BD_TL (1 << 3) /* too long */ +#define RX_BD_DN (1 << 4) /* dribble nibble */ +#define RX_BD_IS (1 << 5) /* invalid symbol */ +#define RX_BD_OR (1 << 6) /* receiver overrun */ +#define RX_BD_MISS (1 << 7) +#define RX_BD_CF (1 << 8) /* control frame */ +#define RX_BD_WRAP (1 << 13) +#define RX_BD_IRQ (1 << 14) /* interrupt request enable */ +#define RX_BD_EMPTY (1 << 15) +#define RX_BD_LEN(x) (((x) & 0xffff) << 16) + +#define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \ + RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS) + +#define ETHOC_BUFSIZ 1536 +#define ETHOC_ZLEN 64 +#define ETHOC_BD_BASE 0x400 +#define ETHOC_TIMEOUT (HZ / 2) +#define ETHOC_MII_TIMEOUT (1 + (HZ / 5)) + +/** + * struct ethoc - driver-private device structure + * @iobase: pointer to I/O memory region + * @membase: pointer to buffer memory region + * @dma_alloc: dma allocated buffer size + * @num_tx: number of send buffers + * @cur_tx: last send buffer written + * @dty_tx: last buffer actually sent + * @num_rx: number of receive buffers + * @cur_rx: current receive buffer + * @netdev: pointer to network device structure + * @napi: NAPI structure + * @stats: network device statistics + * @msg_enable: device state flags + * @rx_lock: receive lock + * @lock: device lock + * @phy: attached PHY + * @mdio: MDIO bus for PHY access + * @phy_id: address of attached PHY + */ +struct ethoc { + void *iobase; + + unsigned int num_tx; + unsigned int cur_tx; + unsigned int dty_tx; + + unsigned int num_rx; + unsigned int cur_rx; + + u32 msg_enable; + + s8 phy_id; +}; + +/** + * struct ethoc_bd - buffer descriptor + * @stat: buffer statistics + * @addr: physical memory address + */ +struct ethoc_bd { + u32 stat; + u32 addr; +}; + +static inline u32 ethoc_read(struct ethoc *dev, loff_t offset) +{ + return readl(dev->iobase + offset); +} + +static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data) +{ + writel(data, dev->iobase + offset); +} + +static inline void ethoc_read_bd(struct ethoc *dev, int index, + struct ethoc_bd *bd) +{ + loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); + bd->stat = ethoc_read(dev, offset + 0); + bd->addr = ethoc_read(dev, offset + 4); +} + +static inline void ethoc_write_bd(struct ethoc *dev, int index, + const struct ethoc_bd *bd) +{ + loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); + ethoc_write(dev, offset + 0, bd->stat); + ethoc_write(dev, offset + 4, bd->addr); +} + +static int ethoc_set_mac_address(struct eth_device *dev, void *addr) +{ + struct ethoc *priv = (void *)dev->priv; + u8 *mac = (u8 *) addr; + + ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | + (mac[4] << 8) | (mac[5] << 0)); + ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); + + return 0; +} + +static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask) +{ + ethoc_write(dev, INT_SOURCE, mask); +} + +static inline void ethoc_enable_rx_and_tx(struct ethoc *dev) +{ + u32 mode = ethoc_read(dev, MODER); + mode |= MODER_RXEN | MODER_TXEN; + ethoc_write(dev, MODER, mode); +} + +static inline void ethoc_disable_rx_and_tx(struct ethoc *dev) +{ + u32 mode = ethoc_read(dev, MODER); + mode &= ~(MODER_RXEN | MODER_TXEN); + ethoc_write(dev, MODER, mode); +} + +static int ethoc_init_ring(struct ethoc *dev) +{ + struct ethoc_bd bd; + int i; + + dev->cur_tx = 0; + dev->dty_tx = 0; + dev->cur_rx = 0; + + /* setup transmission buffers */ + bd.stat = TX_BD_IRQ | TX_BD_CRC; + + for (i = 0; i < dev->num_tx; i++) { + if (i == dev->num_tx - 1) + bd.stat |= TX_BD_WRAP; + + ethoc_write_bd(dev, i, &bd); + } + + bd.stat = RX_BD_EMPTY | RX_BD_IRQ; + + for (i = 0; i < dev->num_rx; i++) { + bd.addr = NetRxPackets[i]; + if (i == dev->num_rx - 1) + bd.stat |= RX_BD_WRAP; + + flush_dcache(bd.addr, PKTSIZE_ALIGN); + ethoc_write_bd(dev, dev->num_tx + i, &bd); + } + + return 0; +} + +static int ethoc_reset(struct ethoc *dev) +{ + u32 mode; + + /* TODO: reset controller? */ + + ethoc_disable_rx_and_tx(dev); + + /* TODO: setup registers */ + + /* enable FCS generation and automatic padding */ + mode = ethoc_read(dev, MODER); + mode |= MODER_CRC | MODER_PAD; + ethoc_write(dev, MODER, mode); + + /* set full-duplex mode */ + mode = ethoc_read(dev, MODER); + mode |= MODER_FULLD; + ethoc_write(dev, MODER, mode); + ethoc_write(dev, IPGT, 0x15); + + ethoc_ack_irq(dev, INT_MASK_ALL); + ethoc_enable_rx_and_tx(dev); + return 0; +} + +static int ethoc_init(struct eth_device *dev, bd_t * bd) +{ + struct ethoc *priv = (void *)dev->priv; + printf("ethoc\n"); + + eth_getenv_enetaddr("ethaddr", dev->enetaddr); + ethoc_set_mac_address(dev, dev->enetaddr); + + priv->num_tx = 1; + priv->num_rx = PKTBUFSRX; + ethoc_write(priv, TX_BD_NUM, priv->num_tx); + ethoc_init_ring(priv); + ethoc_reset(priv); + + return 0; +} + +static unsigned int ethoc_update_rx_stats(struct ethoc *dev, + struct ethoc_bd *bd) +{ + unsigned int ret = 0; + + if (bd->stat & RX_BD_TL) { + debug("ETHOC: " "RX: frame too long\n"); + ret++; + } + + if (bd->stat & RX_BD_SF) { + debug("ETHOC: " "RX: frame too short\n"); + ret++; + } + + if (bd->stat & RX_BD_DN) + debug("ETHOC: " "RX: dribble nibble\n"); + + if (bd->stat & RX_BD_CRC) { + debug("ETHOC: " "RX: wrong CRC\n"); + ret++; + } + + if (bd->stat & RX_BD_OR) { + debug("ETHOC: " "RX: overrun\n"); + ret++; + } + + if (bd->stat & RX_BD_LC) { + debug("ETHOC: " "RX: late collision\n"); + ret++; + } + + return ret; +} + +static int ethoc_rx(struct eth_device *dev, int limit) +{ + struct ethoc *priv = (void *)dev->priv; + int count; + + for (count = 0; count < limit; ++count) { + unsigned int entry; + struct ethoc_bd bd; + + entry = priv->num_tx + (priv->cur_rx % priv->num_rx); + ethoc_read_bd(priv, entry, &bd); + if (bd.stat & RX_BD_EMPTY) + break; + + debug("%s(): RX buffer %d, %x received\n", + __func__, priv->cur_rx, bd.stat); + if (ethoc_update_rx_stats(priv, &bd) == 0) { + int size = bd.stat >> 16; + size -= 4; /* strip the CRC */ + NetReceive(bd.addr, size); + } + + /* clear the buffer descriptor so it can be reused */ + flush_dcache(bd.addr, PKTSIZE_ALIGN); + bd.stat &= ~RX_BD_STATS; + bd.stat |= RX_BD_EMPTY; + ethoc_write_bd(priv, entry, &bd); + priv->cur_rx++; + } + + return count; +} + +static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd) +{ + if (bd->stat & TX_BD_LC) + debug("ETHOC: " "TX: late collision\n"); + + if (bd->stat & TX_BD_RL) + debug("ETHOC: " "TX: retransmit limit\n"); + + if (bd->stat & TX_BD_UR) + debug("ETHOC: " "TX: underrun\n"); + + if (bd->stat & TX_BD_CS) + debug("ETHOC: " "TX: carrier sense lost\n"); + + return 0; +} + +static void ethoc_tx(struct eth_device *dev) +{ + struct ethoc *priv = (void *)dev->priv; + unsigned int entry = priv->dty_tx % priv->num_tx; + struct ethoc_bd bd; + + ethoc_read_bd(priv, entry, &bd); + if ((bd.stat & TX_BD_READY) == 0) + (void)ethoc_update_tx_stats(priv, &bd); +} + +static int ethoc_send(struct eth_device *dev, volatile void *packet, int length) +{ + struct ethoc *priv = (void *)dev->priv; + struct ethoc_bd bd; + unsigned int entry; + u32 pending; + int tmo; + + entry = priv->cur_tx % priv->num_tx; + ethoc_read_bd(priv, entry, &bd); + if (unlikely(length < ETHOC_ZLEN)) + bd.stat |= TX_BD_PAD; + else + bd.stat &= ~TX_BD_PAD; + bd.addr = packet; + + flush_dcache(bd.addr, length); + bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK); + bd.stat |= TX_BD_LEN(length); + ethoc_write_bd(priv, entry, &bd); + + /* start transmit */ + bd.stat |= TX_BD_READY; + ethoc_write_bd(priv, entry, &bd); + + /* wait for transfer to succeed */ + tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; + while (1) { + pending = ethoc_read(priv, INT_SOURCE); + ethoc_ack_irq(priv, pending & ~INT_MASK_RX); + if (pending & INT_MASK_BUSY) + debug("%s(): packet dropped\n", __func__); + + if (pending & INT_MASK_TX) { + ethoc_tx(dev); + break; + } + if (get_timer(0) >= tmo) { + debug("%s(): timed out\n", __func__); + return -1; + } + } + + debug("%s(): packet sent\n", __func__); + return 0; +} + +static void ethoc_halt(struct eth_device *dev) +{ + struct ethoc *priv = (void *)dev->priv; + ethoc_disable_rx_and_tx(priv); +} + +static int ethoc_recv(struct eth_device *dev) +{ + struct ethoc *priv = (void *)dev->priv; + u32 pending; + + pending = ethoc_read(priv, INT_SOURCE); + ethoc_ack_irq(priv, pending); + if (pending & INT_MASK_BUSY) + debug("%s(): packet dropped\n", __func__); + if (pending & INT_MASK_RX) { + debug("%s(): rx irq\n", __func__); + ethoc_rx(dev, PKTBUFSRX); + } + + return 0; +} + +int ethoc_initialize(u8 dev_num, int base_addr) +{ + struct ethoc *priv; + struct eth_device *dev; + + priv = malloc(sizeof(*priv)); + if (!priv) + return 0; + dev = malloc(sizeof(*dev)); + if (!dev) { + free(priv); + return 0; + } + + memset(dev, 0, sizeof(*dev)); + dev->priv = priv; + priv->iobase = base_addr; + dev->init = ethoc_init; + dev->halt = ethoc_halt; + dev->send = ethoc_send; + dev->recv = ethoc_recv; + sprintf(dev->name, "%s-%hu", "ETHOC", dev_num); + + eth_register(dev); + return 1; +} -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 08/28] net: add altera triple speeds ethernet mac support 2010-03-19 7:43 ` [U-Boot] [PATCH 07/28] net: add opencore 10/100 ethernet mac support Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 09/28] nios2: change asm-nios2/io.h to compatible with nios2 linux Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This driver supports the altera triple speeds 10/100/1000 ethernet mac. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- drivers/net/Makefile | 1 + drivers/net/altera_tse.c | 969 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/altera_tse.h | 500 ++++++++++++++++++++++++ 3 files changed, 1470 insertions(+), 0 deletions(-) create mode 100644 drivers/net/altera_tse.c create mode 100644 drivers/net/altera_tse.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 0e68e52..b75c02f 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libnet.a COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o +COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c new file mode 100644 index 0000000..7d14a01 --- /dev/null +++ b/drivers/net/altera_tse.c @@ -0,0 +1,969 @@ +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <net.h> +#include <command.h> +#include <asm/cache.h> +#include <asm/dma-mapping.h> +#include <miiphy.h> +#include "altera_tse.h" + +static int tse_eth_send(struct eth_device *dev, volatile void *packet, + int length); +static int tse_eth_rx(struct eth_device *dev); +static void tse_eth_halt(struct eth_device *dev); +static void tse_eth_reset(struct eth_device *dev); +static int tse_eth_init(struct eth_device *dev, bd_t *bd); + +static int tse_mdio_read(struct altera_tse_priv *priv, unsigned int regnum); +static int tse_mdio_write(struct altera_tse_priv *priv, unsigned int regnum, + unsigned int value); +#define read_phy_reg(priv, regnum) tse_mdio_read(priv, regnum) +#define write_phy_reg(priv, regnum, value) tse_mdio_write(priv, regnum, value) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) +static int altera_tse_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +static int altera_tse_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +#endif + +static int tse_adjust_link(struct altera_tse_priv *priv); + +static uint mii_parse_88E1011_psr(uint mii_reg, struct altera_tse_priv *priv); +static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv); +static uint mii_m88e1111s_setmode_sr(uint mii_reg, + struct altera_tse_priv *priv); +static uint mii_m88e1111s_setmode_cr(uint mii_reg, + struct altera_tse_priv *priv); +static uint mii_cr_init(uint mii_reg, struct altera_tse_priv *priv); + +static struct phy_info *get_phy_info(struct eth_device *dev); +static void phy_run_commands(struct altera_tse_priv *priv, struct phy_cmd *cmd); +static int init_phy(struct eth_device *dev); + +/* sgdma debug - print descriptor */ +static void alt_sgdma_print_desc(volatile struct alt_sgdma_descriptor *desc) +{ + debug("SGDMA DEBUG :\n"); + debug("desc->source : 0x%x \n", (unsigned int)desc->source); + debug("desc->destination : 0x%x \n", (unsigned int)desc->destination); + debug("desc->next : 0x%x \n", (unsigned int)desc->next); + debug("desc->source_pad : 0x%x \n", (unsigned int)desc->source_pad); + debug("desc->destination_pad : 0x%x \n", + (unsigned int)desc->destination_pad); + debug("desc->next_pad : 0x%x \n", (unsigned int)desc->next_pad); + debug("desc->bytes_to_transfer : 0x%x \n", + (unsigned int)desc->bytes_to_transfer); + debug("desc->actual_bytes_transferred : 0x%x \n", + (unsigned int)desc->actual_bytes_transferred); + debug("desc->descriptor_status : 0x%x \n", + (unsigned int)desc->descriptor_status); + debug("desc->descriptor_control : 0x%x \n", + (unsigned int)desc->descriptor_control); + +} + +/* This is a generic routine that the SGDMA mode-specific routines + * call to populate a descriptor. + * arg1 :pointer to first SGDMA descriptor. + * arg2 :pointer to next SGDMA descriptor. + * arg3 :Address to where data to be written. + * arg4 :Address from where data to be read. + * arg5 :no of byte to transaction. + * arg6 :variable indicating to generate start of packet or not + * arg7 :read fixed + * arg8 :write fixed + * arg9 :read burst + * arg10 :write burst + * arg11 :atlantic_channel number + */ +static void alt_sgdma_construct_descriptor_burst( + volatile struct alt_sgdma_descriptor *desc, + volatile struct alt_sgdma_descriptor *next, + unsigned int *read_addr, + unsigned int *write_addr, + unsigned short length_or_eop, + int generate_eop, + int read_fixed, + int write_fixed_or_sop, + int read_burst, + int write_burst, + unsigned char atlantic_channel) +{ + /* + * Mark the "next" descriptor as "not" owned by hardware. This prevents + * The SGDMA controller from continuing to process the chain. This is + * done as a single IO write to bypass cache, without flushing + * the entire descriptor, since only the 8-bit descriptor status must + * be flushed. + */ + if (!next) + debug("Next descriptor not defined!!\n"); + + next->descriptor_control = (next->descriptor_control & + ~ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK); + + desc->source = (unsigned int *)((unsigned int)read_addr & 0x1FFFFFFF); + desc->destination = + (unsigned int *)((unsigned int)write_addr & 0x1FFFFFFF); + desc->next = (unsigned int *)((unsigned int)next & 0x1FFFFFFF); + desc->source_pad = 0x0; + desc->destination_pad = 0x0; + desc->next_pad = 0x0; + desc->bytes_to_transfer = length_or_eop; + desc->actual_bytes_transferred = 0; + desc->descriptor_status = 0x0; + + /* SGDMA burst not currently supported */ + desc->read_burst = 0; + desc->write_burst = 0; + + /* + * Set the descriptor control block as follows: + * - Set "owned by hardware" bit + * - Optionally set "generate EOP" bit + * - Optionally set the "read from fixed address" bit + * - Optionally set the "write to fixed address bit (which serves + * serves as a "generate SOP" control bit in memory-to-stream mode). + * - Set the 4-bit atlantic channel, if specified + * + * Note that this step is performed after all other descriptor information + * has been filled out so that, if the controller already happens to be + * pointing at this descriptor, it will not run (via the "owned by + * hardware" bit) until all other descriptor information has been set up. + */ + + desc->descriptor_control = + ((ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK) | + (generate_eop ? + ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK : 0x0) | + (read_fixed ? + ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK : 0x0) | + (write_fixed_or_sop ? + ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK : 0x0) | + (atlantic_channel ? ((atlantic_channel & 0x0F) << 3) : 0) + ); + +} + +static int alt_sgdma_do_sync_transfer(volatile struct alt_sgdma_registers *dev, + volatile struct alt_sgdma_descriptor *desc) +{ + unsigned int status; + int counter = 0; + + /* Wait for any pending transfers to complete */ + status = dev->status; + + counter = 0; + while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) { + if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + debug("Timeout waiting sgdma in do sync!\n"); + + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + dev->status = 0xFF; + + /* Point the controller at the descriptor */ + dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF; + debug("next desc in sgdma 0x%x\n", + (unsigned int)dev->next_descriptor_pointer); + + /* + * Set up SGDMA controller to: + * - Disable interrupt generation + * - Run once a valid descriptor is written to controller + * - Stop on an error with any particular descriptor + */ + dev->control = (ALT_SGDMA_CONTROL_RUN_MSK | + ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK); + + /* Wait for the descriptor (chain) to complete */ + status = dev->status; + debug("wait for sgdma...."); + while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) + ; + debug("done\n"); + + /* Clear Run */ + dev->control = (dev->control & (~ALT_SGDMA_CONTROL_RUN_MSK)); + + /* Get & clear status register contents */ + status = dev->status; + dev->status = 0xFF; + + /* we really should check if the transfer completes properly */ + debug("tx sgdma status = 0x%x", status); + return 0; +} + +static int alt_sgdma_do_async_transfer(volatile struct alt_sgdma_registers *dev, + volatile struct alt_sgdma_descriptor *desc) +{ + unsigned int status; + int counter = 0; + + /* Wait for any pending transfers to complete */ + status = dev->status; + + counter = 0; + while (dev->status & ALT_SGDMA_STATUS_BUSY_MSK) { + if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + debug("Timeout waiting sgdma in do async!\n"); + + /* + * Clear any (previous) status register information + * that might occlude our error checking later. + */ + dev->status = 0xFF; + + /* Point the controller at the descriptor */ + dev->next_descriptor_pointer = (unsigned int)desc & 0x1FFFFFFF; + + /* + * Set up SGDMA controller to: + * - Disable interrupt generation + * - Run once a valid descriptor is written to controller + * - Stop on an error with any particular descriptor + */ + dev->control = (ALT_SGDMA_CONTROL_RUN_MSK | + ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK); + + /* we really should check if the transfer completes properly */ + + return 0; +} + +/* TSE init code */ +int altera_tse_init(bd_t *bis, int num_tses) +{ + struct altera_tse_priv *priv; + struct eth_device *dev; + struct alt_sgdma_descriptor *rx_desc; + struct alt_sgdma_descriptor *tx_desc; + int num, i; + unsigned long dma_handle; + + puts("Altera TSE\n"); + + for (num = 0; num < num_tses; num++) { + dev = (struct eth_device *)malloc(sizeof *dev); + + if (NULL == dev) + return 0; + + memset(dev, 0, sizeof *dev); + + priv = (struct altera_tse_priv *)malloc(sizeof(*priv)); + + if (NULL == priv) + return 0; +#if CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM + tx_desc = (void *)CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE; +#else + tx_desc = + dma_alloc_coherent(sizeof(*tx_desc) * (3 + PKTBUFSRX), + &dma_handle); +#endif + rx_desc = tx_desc + 2; + debug("tx desc: address = 0x%x\n", (unsigned int)tx_desc); + debug("rx desc: address = 0x%x\n", (unsigned int)rx_desc); + + if (NULL == rx_desc || NULL == tx_desc) + return 0; + memset(rx_desc, 0, (sizeof *rx_desc) * (PKTBUFSRX + 1)); + memset(tx_desc, 0, (sizeof *tx_desc) * 2); + + /* initialize tse priv */ + SET_ALTERA_TSE_INFO(priv, 0); + priv->rx_desc = rx_desc; + priv->tx_desc = tx_desc; + + /* init eth structure */ + sprintf(dev->name, priv->devname); + dev->iobase = 0; + dev->priv = priv; + dev->init = tse_eth_init; + dev->halt = tse_eth_halt; + dev->send = tse_eth_send; + dev->recv = tse_eth_rx; + + /* Tell u-boot to get the addr from the env */ + for (i = 0; i < 6; i++) + dev->enetaddr[i] = 0; + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) + miiphy_register(dev->name, altera_tse_miiphy_read, + altera_tse_miiphy_write); +#endif + + init_phy(dev); + } + + return 1; +} + +/* u-boot interface */ +static int tse_adjust_link(struct altera_tse_priv *priv) +{ + unsigned int refvar; + alt_tse_mac *mac_dev = priv->mac_dev; + + refvar = mac_dev->command_config.image; + + if (!(priv->duplexity)) + refvar |= ALTERA_TSE_CMD_HD_ENA_MSK; + else + refvar &= ~ALTERA_TSE_CMD_HD_ENA_MSK; + + switch (priv->speed) { + case 1000: + refvar |= ALTERA_TSE_CMD_ETH_SPEED_MSK; + refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; + break; + case 100: + refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; + refvar &= ~ALTERA_TSE_CMD_ENA_10_MSK; + break; + case 10: + refvar &= ~ALTERA_TSE_CMD_ETH_SPEED_MSK; + refvar |= ALTERA_TSE_CMD_ENA_10_MSK; + break; + } + mac_dev->command_config.image = refvar; + + return 0; +} + +static int tse_eth_send(struct eth_device *dev, + volatile void *packet, int length) +{ + struct altera_tse_priv *priv = dev->priv; + struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; + volatile struct alt_sgdma_descriptor *tx_desc = + (volatile struct alt_sgdma_descriptor *)priv->tx_desc; + + volatile struct alt_sgdma_descriptor *tx_desc_cur = + (volatile struct alt_sgdma_descriptor *)&tx_desc[0]; + + flush_dcache((unsigned long)packet, length); + alt_sgdma_construct_descriptor_burst( + (volatile struct alt_sgdma_descriptor *)&tx_desc[0], + (volatile struct alt_sgdma_descriptor *)&tx_desc[1], + (unsigned int *)packet, /* read addr */ + (unsigned int *)0, + length, /* length or EOP ,will change for each tx */ + 0x1, /* gen eop */ + 0x0, /* read fixed */ + 0x1, /* write fixed or sop */ + 0x0, /* read burst */ + 0x0, /* write burst */ + 0x0 /* channel */ + ); + debug("TX Packet @ 0x%x,0x%x bytes", (unsigned int)packet, length); + + /* send the packet */ + debug("sending packet\n"); + alt_sgdma_do_sync_transfer(tx_sgdma, tx_desc_cur); + debug("sent %d bytes\n", tx_desc_cur->actual_bytes_transferred); + return tx_desc_cur->actual_bytes_transferred; +} + +static int tse_eth_rx(struct eth_device *dev) +{ + int packet_length = 0; + struct altera_tse_priv *priv = dev->priv; + volatile struct alt_sgdma_descriptor *rx_desc = + (volatile struct alt_sgdma_descriptor *)priv->rx_desc; + volatile struct alt_sgdma_descriptor *rx_desc_cur = &rx_desc[0]; + debug("eth_rx: sgdma status = 0x%x\n", rx_sgdma->status); + debug("eth_rx: sgdma control = 0x%x\n", rx_sgdma->control); + debug("mac rx errors : %d\n", mac_dev->ifInErrors); + + if (rx_desc_cur->descriptor_status & + ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK) { + debug("got packet\n"); + packet_length = rx_desc->actual_bytes_transferred; + NetReceive(NetRxPackets[0], packet_length); + + /* start descriptor again */ + flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); + alt_sgdma_construct_descriptor_burst( + (volatile struct alt_sgdma_descriptor *)&rx_desc[0], + (volatile struct alt_sgdma_descriptor *)&rx_desc[1], + (unsigned int)0x0, /* read addr */ + (unsigned int *)NetRxPackets[0], + 0x0, /* length or EOP */ + 0x0, /* gen eop */ + 0x0, /* read fixed */ + 0x0, /* write fixed or sop */ + 0x0, /* read burst */ + 0x0, /* write burst */ + 0x0 /* channel */ + ); + + /* setup the sgdma */ + alt_sgdma_do_async_transfer(priv->sgdma_rx, &rx_desc[0]); + } + + return -1; +} + +static void tse_eth_halt(struct eth_device *dev) +{ + /* don't do anything! */ + /* this gets called after each uboot */ + /* network command. don't need to reset the thing all of the time */ +} + +static void tse_eth_reset(struct eth_device *dev) +{ + /* stop sgdmas, disable tse receive */ + struct altera_tse_priv *priv = dev->priv; + alt_tse_mac *mac_dev = priv->mac_dev; + struct alt_sgdma_registers *rx_sgdma = priv->sgdma_rx; + struct alt_sgdma_registers *tx_sgdma = priv->sgdma_tx; + int counter; + volatile struct alt_sgdma_descriptor *rx_desc = + (volatile struct alt_sgdma_descriptor *)&priv->rx_desc[0]; + + /* clear rx desc & wait for sgdma to complete */ + rx_desc->descriptor_control = 0; + rx_sgdma->control = 0; + counter = 0; + while (rx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) { + if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { + debug("Timeout waiting for rx sgdma!\n"); + rx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + rx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + } + + counter = 0; + tx_sgdma->control = 0; + while (tx_sgdma->status & ALT_SGDMA_STATUS_BUSY_MSK) { + if (counter++ > ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR) { + debug("Timeout waiting for tx sgdma!\n"); + tx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + tx_sgdma->control &= ALT_SGDMA_CONTROL_SOFTWARERESET_MSK; + } + /* reset the mac */ + mac_dev->command_config.bits.transmit_enable = 1; + mac_dev->command_config.bits.receive_enable = 1; + mac_dev->command_config.bits.software_reset = 1; + + counter = 0; + while (mac_dev->command_config.bits.software_reset) { + if (counter++ > ALT_TSE_SW_RESET_WATCHDOG_CNTR) + break; + } + + if (counter >= ALT_TSE_SW_RESET_WATCHDOG_CNTR) + debug("TSEMAC SW reset bit never cleared!\n"); + +} + +static int tse_eth_init(struct eth_device *dev, bd_t * bd) +{ + int dat; + struct altera_tse_priv *priv = dev->priv; + alt_tse_mac *mac_dev = priv->mac_dev; + volatile struct alt_sgdma_descriptor *tx_desc = priv->tx_desc; + volatile struct alt_sgdma_descriptor *rx_desc = priv->rx_desc; + volatile struct alt_sgdma_descriptor *rx_desc_cur = + (volatile struct alt_sgdma_descriptor *)&rx_desc[0]; + + /* stop controller */ + debug("Reseting TSE & SGDMAs\n"); + tse_eth_reset(dev); + + /* start the phy */ + debug("Configuring PHY\n"); + phy_run_commands(priv, priv->phyinfo->startup); + + /* need to create sgdma */ + debug("Configuring tx desc\n"); + alt_sgdma_construct_descriptor_burst( + (volatile struct alt_sgdma_descriptor *)&tx_desc[0], + (volatile struct alt_sgdma_descriptor *)&tx_desc[1], + (unsigned int *)NULL, /* read addr */ + (unsigned int *)0, + 0, /* length or EOP ,will change for each tx */ + 0x1, /* gen eop */ + 0x0, /* read fixed */ + 0x1, /* write fixed or sop */ + 0x0, /* read burst */ + 0x0, /* write burst */ + 0x0 /* channel */ + ); + debug("Configuring rx desc\n"); + flush_dcache((unsigned long)(NetRxPackets[0]), PKTSIZE_ALIGN); + alt_sgdma_construct_descriptor_burst( + (volatile struct alt_sgdma_descriptor *)&rx_desc[0], + (volatile struct alt_sgdma_descriptor *)&rx_desc[1], + (unsigned int)0x0, /* read addr */ + (unsigned int *)NetRxPackets[0], + 0x0, /* length or EOP */ + 0x0, /* gen eop */ + 0x0, /* read fixed */ + 0x0, /* write fixed or sop */ + 0x0, /* read burst */ + 0x0, /* write burst */ + 0x0 /* channel */ + ); + /* start rx async transfer */ + debug("Starting rx sgdma\n"); + alt_sgdma_do_async_transfer(priv->sgdma_rx, rx_desc_cur); + + /* start TSE */ + debug("Configuring TSE Mac\n"); + /* Initialize MAC registers */ + mac_dev->max_frame_length = PKTSIZE_ALIGN; + mac_dev->rx_almost_empty_threshold = 8; + mac_dev->rx_almost_full_threshold = 8; + mac_dev->tx_almost_empty_threshold = 8; + mac_dev->tx_almost_full_threshold = 3; + mac_dev->tx_sel_empty_threshold = + CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH - 16; + mac_dev->tx_sel_full_threshold = 0; + mac_dev->rx_sel_empty_threshold = + CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH - 16; + mac_dev->rx_sel_full_threshold = 0; + + /* NO Shift */ + mac_dev->rx_cmd_stat.bits.rx_shift16 = 0; + mac_dev->tx_cmd_stat.bits.tx_shift16 = 0; + + /* enable MAC */ + dat = 0; + dat = ALTERA_TSE_CMD_TX_ENA_MSK | ALTERA_TSE_CMD_RX_ENA_MSK; + + mac_dev->command_config.image = dat; + + /* Set the MAC address */ + debug("Setting MAC address to 0x%x%x%x%x%x%x\n", + dev->enetaddr[5], dev->enetaddr[4], + dev->enetaddr[3], dev->enetaddr[2], + dev->enetaddr[1], dev->enetaddr[0]); + mac_dev->mac_addr_0 = ((dev->enetaddr[3]) << 24 | + (dev->enetaddr[2]) << 16 | + (dev->enetaddr[1]) << 8 | (dev->enetaddr[0])); + + mac_dev->mac_addr_1 = ((dev->enetaddr[5] << 8 | + (dev->enetaddr[4])) & 0xFFFF); + + /* Set the MAC address */ + mac_dev->supp_mac_addr_0_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_0_1 = mac_dev->mac_addr_1; + + /* Set the MAC address */ + mac_dev->supp_mac_addr_1_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_1_1 = mac_dev->mac_addr_1; + + /* Set the MAC address */ + mac_dev->supp_mac_addr_2_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_2_1 = mac_dev->mac_addr_1; + + /* Set the MAC address */ + mac_dev->supp_mac_addr_3_0 = mac_dev->mac_addr_0; + mac_dev->supp_mac_addr_3_1 = mac_dev->mac_addr_1; + + /* configure the TSE core */ + /* -- output clocks, */ + /* -- and later config stuff for SGMII */ + if (priv->link) { + debug("Adjusting TSE to link speed\n"); + tse_adjust_link(priv); + } + + return priv->link ? 0 : -1; +} + +/* + * PHY & MDIO code + * Need to add SGMII stuff + * + */ + +static struct phy_info phy_info_M88E1111S = { + 0x01410cc, + "Marvell 88E1111S", + 4, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_88E1111_PHY_EXT_SR, 0x848f, + &mii_m88e1111s_setmode_sr}, + /* Delay RGMII TX and RX */ + {MIIM_88E1111_PHY_EXT_CR, 0x0cd2, + &mii_m88e1111s_setmode_cr}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, +}; + +/* a generic flavor. */ +static struct phy_info phy_info_generic = { + 0, + "Unknown/Generic PHY", + 32, + (struct phy_cmd[]){ /* config */ + {PHY_BMCR, PHY_BMCR_RESET, NULL}, + {PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG, NULL}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + {PHY_BMSR, miim_read, NULL}, + {PHY_BMSR, miim_read, &mii_parse_sr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + } +}; + +static struct phy_info *phy_info[] = { + &phy_info_M88E1111S, + NULL +}; + + /* Grab the identifier of the device's PHY, and search through + * all of the known PHYs to see if one matches. If so, return + * it, if not, return NULL + */ +static struct phy_info *get_phy_info(struct eth_device *dev) +{ + struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv; + uint phy_reg, phy_ID; + int i; + struct phy_info *theInfo = NULL; + + /* Grab the bits from PHYIR1, and put them in the upper half */ + phy_reg = tse_mdio_read(priv, MIIM_PHYIR1); + phy_ID = (phy_reg & 0xffff) << 16; + + /* Grab the bits from PHYIR2, and put them in the lower half */ + phy_reg = tse_mdio_read(priv, MIIM_PHYIR2); + phy_ID |= (phy_reg & 0xffff); + + /* loop through all the known PHY types, and find one that */ + /* matches the ID we read from the PHY. */ + for (i = 0; phy_info[i]; i++) { + if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) { + theInfo = phy_info[i]; + break; + } + } + + if (theInfo == NULL) { + theInfo = &phy_info_generic; + debug("%s: No support for PHY id %x; assuming generic\n", + dev->name, phy_ID); + } else + debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID); + + return theInfo; +} + +/* Execute the given series of commands on the given device's + * PHY, running functions as necessary + */ +static void phy_run_commands(struct altera_tse_priv *priv, struct phy_cmd *cmd) +{ + int i; + uint result; + + for (i = 0; cmd->mii_reg != miim_end; i++) { + if (cmd->mii_data == miim_read) { + result = tse_mdio_read(priv, cmd->mii_reg); + + if (cmd->funct != NULL) + (*(cmd->funct)) (result, priv); + + } else { + if (cmd->funct != NULL) + result = (*(cmd->funct)) (cmd->mii_reg, priv); + else + result = cmd->mii_data; + + tse_mdio_write(priv, cmd->mii_reg, result); + + } + cmd++; + } +} + +/* Phy init code */ +static int init_phy(struct eth_device *dev) +{ + struct altera_tse_priv *priv = (struct altera_tse_priv *)dev->priv; + struct phy_info *curphy; + + /* Get the cmd structure corresponding to the attached + * PHY */ + curphy = get_phy_info(dev); + + if (curphy == NULL) { + priv->phyinfo = NULL; + printf("%s: No PHY found\n", dev->name); + + return 0; + } else + printf("%s found\n", curphy->name); + priv->phyinfo = curphy; + + phy_run_commands(priv, priv->phyinfo->config); + + return 1; +} + +/* + * Also copied from tsec.c + */ +/* Parse the status register for link, and then do + * auto-negotiation + */ +static uint mii_parse_sr(uint mii_reg, struct altera_tse_priv *priv) +{ + /* + * Wait if the link is up, and autonegotiation is in progress + * (ie - we're capable and it's not done) + */ + mii_reg = tse_mdio_read(priv, MIIM_STATUS); + + if (!(mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) + && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + int i = 0; + + puts("Waiting for PHY auto negotiation to complete"); + while (!(mii_reg & PHY_BMSR_AUTN_COMP)) { + /* + * Timeout reached ? + */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + priv->link = 0; + return 0; + } + + if ((i++ % 1000) == 0) + putc('.'); + udelay(1000); /* 1 ms */ + mii_reg = tse_mdio_read(priv, MIIM_STATUS); + } + puts(" done\n"); + priv->link = 1; + udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & MIIM_STATUS_LINK) { + debug("Link is up\n"); + priv->link = 1; + } else { + debug("Link is down\n"); + priv->link = 0; + } + } + + return 0; +} + +/* Parse the 88E1011's status register for speed and duplex + * information + */ +static uint mii_parse_88E1011_psr(uint mii_reg, struct altera_tse_priv *priv) +{ + uint speed; + + mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS); + + if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) && + !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { + int i = 0; + + puts("Waiting for PHY realtime link"); + while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) { + /* Timeout reached ? */ + if (i > PHY_AUTONEGOTIATE_TIMEOUT) { + puts(" TIMEOUT !\n"); + priv->link = 0; + break; + } + + if ((i++ == 1000) == 0) { + i = 0; + puts("."); + } + udelay(1000); /* 1 ms */ + mii_reg = tse_mdio_read(priv, MIIM_88E1011_PHY_STATUS); + } + puts(" done\n"); + udelay(500000); /* another 500 ms (results in faster booting) */ + } else { + if (mii_reg & MIIM_88E1011_PHYSTAT_LINK) + priv->link = 1; + else + priv->link = 0; + } + + if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX) + priv->duplexity = 1; + else + priv->duplexity = 0; + + speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED); + + switch (speed) { + case MIIM_88E1011_PHYSTAT_GBIT: + priv->speed = 1000; + debug("PHY Speed is 1000Mbit\n"); + break; + case MIIM_88E1011_PHYSTAT_100: + debug("PHY Speed is 100Mbit\n"); + priv->speed = 100; + break; + default: + debug("PHY Speed is 10Mbit\n"); + priv->speed = 10; + } + + return 0; +} + +static uint mii_m88e1111s_setmode_sr(uint mii_reg, struct altera_tse_priv *priv) +{ + uint mii_data = tse_mdio_read(priv, mii_reg); + mii_data &= 0xfff0; + mii_data |= 0xb; + return mii_data; +} + +static uint mii_m88e1111s_setmode_cr(uint mii_reg, struct altera_tse_priv *priv) +{ + uint mii_data = tse_mdio_read(priv, mii_reg); + mii_data &= ~0x82; + mii_data |= 0x82; + return mii_data; +} + +/* + * Returns which value to write to the control register. + * For 10/100, the value is slightly different + */ +static uint mii_cr_init(uint mii_reg, struct altera_tse_priv *priv) +{ + return MIIM_CONTROL_INIT; +} + +static int tse_mdio_read(struct altera_tse_priv *priv, unsigned int regnum) +{ + alt_tse_mac *mac_dev; + unsigned int *mdio_regs; + unsigned int data; + u16 value; + + mac_dev = priv->mac_dev; + + /* set mdio address */ + mac_dev->mdio_phy1_addr = priv->phyaddr; + mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; + + /* get the data */ + data = mdio_regs[regnum]; + + value = data & 0xffff; + + return value; +} + +static int tse_mdio_write(struct altera_tse_priv *priv, unsigned int regnum, + unsigned int value) +{ + alt_tse_mac *mac_dev; + unsigned int *mdio_regs; + unsigned int data; + + mac_dev = priv->mac_dev; + + /* set mdio address */ + mac_dev->mdio_phy1_addr = priv->phyaddr; + mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; + + /* get the data */ + data = (unsigned int)value; + + mdio_regs[regnum] = data; + + return 0; +} + +/* MDIO access to phy */ +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII) +static int altera_tse_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + struct eth_device *dev; + struct altera_tse_priv *priv; + dev = eth_get_dev_by_name(devname); + priv = dev->priv; + + tse_mdio_write(priv, (uint) reg, (uint) value); + + return 0; +} + +static int altera_tse_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) +{ + struct eth_device *dev; + struct altera_tse_priv *priv; + alt_tse_mac *mac_dev; + unsigned int *mdio_regs; + + dev = eth_get_dev_by_name(devname); + priv = dev->priv; + + mac_dev = priv->mac_dev; + mac_dev->mdio_phy1_addr = (int)addr; + mdio_regs = (unsigned int *)&mac_dev->mdio_phy1; + + *value = 0xffff & mdio_regs[reg]; + + return 0; + +} +#endif diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h new file mode 100644 index 0000000..e966c99 --- /dev/null +++ b/drivers/net/altera_tse.h @@ -0,0 +1,500 @@ + +#define __packed_1_ __attribute__ ((packed, aligned(1))) + +/* PHY Stuff */ +#define miim_end -2 +#define miim_read -1 + +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ + +#ifndef CONFIG_SYS_TBIPA_VALUE +#define CONFIG_SYS_TBIPA_VALUE 0x1f +#endif +#define MIIMCFG_INIT_VALUE 0x00000003 +#define MIIMCFG_RESET 0x80000000 + +#define MIIMIND_BUSY 0x00000001 +#define MIIMIND_NOTVALID 0x00000004 + +#define MIIM_CONTROL 0x00 +#define MIIM_CONTROL_RESET 0x00009140 +#define MIIM_CONTROL_INIT 0x00001140 +#define MIIM_CONTROL_RESTART 0x00001340 +#define MIIM_ANEN 0x00001000 + +#define MIIM_CR 0x00 +#define MIIM_CR_RST 0x00008000 +#define MIIM_CR_INIT 0x00001000 + +#define MIIM_STATUS 0x1 +#define MIIM_STATUS_AN_DONE 0x00000020 +#define MIIM_STATUS_LINK 0x0004 +#define PHY_BMSR_AUTN_ABLE 0x0008 +#define PHY_BMSR_AUTN_COMP 0x0020 + +#define MIIM_PHYIR1 0x2 +#define MIIM_PHYIR2 0x3 + +#define MIIM_ANAR 0x4 +#define MIIM_ANAR_INIT 0x1e1 + +#define MIIM_TBI_ANLPBPA 0x5 +#define MIIM_TBI_ANLPBPA_HALF 0x00000040 +#define MIIM_TBI_ANLPBPA_FULL 0x00000020 + +#define MIIM_TBI_ANEX 0x6 +#define MIIM_TBI_ANEX_NP 0x00000004 +#define MIIM_TBI_ANEX_PRX 0x00000002 + +#define MIIM_GBIT_CONTROL 0x9 +#define MIIM_GBIT_CONTROL_INIT 0xe00 + +#define MIIM_EXT_PAGE_ACCESS 0x1f + +/* 88E1011 PHY Status Register */ +#define MIIM_88E1011_PHY_STATUS 0x11 +#define MIIM_88E1011_PHYSTAT_SPEED 0xc000 +#define MIIM_88E1011_PHYSTAT_GBIT 0x8000 +#define MIIM_88E1011_PHYSTAT_100 0x4000 +#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 +#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 +#define MIIM_88E1011_PHYSTAT_LINK 0x0400 + +#define MIIM_88E1011_PHY_SCR 0x10 +#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 + +#define MIIM_88E1111_PHY_EXT_CR 0x14 +#define MIIM_88E1111_PHY_EXT_SR 0x1b + +/* 88E1111 PHY LED Control Register */ +#define MIIM_88E1111_PHY_LED_CONTROL 24 +#define MIIM_88E1111_PHY_LED_DIRECT 0x4100 +#define MIIM_88E1111_PHY_LED_COMBINE 0x411C + +#define MIIM_READ_COMMAND 0x00000001 + +/* struct phy_info: a structure which defines attributes for a PHY + * id will contain a number which represents the PHY. During + * startup, the driver will poll the PHY to find out what its + * UID--as defined by registers 2 and 3--is. The 32-bit result + * gotten from the PHY will be shifted right by "shift" bits to + * discard any bits which may change based on revision numbers + * unimportant to functionality + * + * The struct phy_cmd entries represent pointers to an arrays of + * commands which tell the driver what to do to the PHY. + */ +struct phy_info { + uint id; + char *name; + uint shift; + /* Called to configure the PHY, and modify the controller + * based on the results */ + struct phy_cmd *config; + + /* Called when starting up the controller */ + struct phy_cmd *startup; + + /* Called when bringing down the controller */ + struct phy_cmd *shutdown; +}; + +/* SGDMA Stuff */ +#define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001) +#define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002) +#define ALT_SGDMA_STATUS_DESC_COMPLETED_MSK (0x00000004) +#define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008) +#define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010) + +#define ALT_SGDMA_CONTROL_IE_ERROR_MSK (0x00000001) +#define ALT_SGDMA_CONTROL_IE_EOP_ENCOUNTERED_MSK (0x00000002) +#define ALT_SGDMA_CONTROL_IE_DESC_COMPLETED_MSK (0x00000004) +#define ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK (0x00000008) +#define ALT_SGDMA_CONTROL_IE_GLOBAL_MSK (0x00000010) +#define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020) +#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040) +#define ALT_SGDMA_CONTROL_IE_MAX_DESC_PROCESSED_MSK (0x00000080) +#define ALT_SGDMA_CONTROL_MAX_DESC_PROCESSED_MSK (0x0000FF00) +#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000) +#define ALT_SGDMA_CONTROL_PARK_MSK (0x00020000) +#define ALT_SGDMA_CONTROL_CLEAR_INTERRUPT_MSK (0x80000000) + +#define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \ + | ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \ + | ALT_SGDMA_CONTROL_IE_GLOBAL_MSK) + +/* + * Descriptor control bit masks & offsets + * + * Note: The control byte physically occupies bits [31:24] in memory. + * The following bit-offsets are expressed relative to the LSB of + * the control register bitfield. + */ +#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x00000008) +#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080) + +/* + * Descriptor status bit masks & offsets + * + * Note: The status byte physically occupies bits [23:16] in memory. + * The following bit-offsets are expressed relative to the LSB of + * the status register bitfield. + */ +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x00000001) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x00000002) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x00000004) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x00000008) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x00000010) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x00000020) +#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x00000040) +#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080) +#define ALT_SGDMA_DESCRIPTOR_STATUS_ERROR_MSK (0x0000007F) + +/* + * The SGDMA controller buffer descriptor allocates + * 64 bits for each address. To support ANSI C, the + * struct implementing a descriptor places 32-bits + * of padding directly above each address; each pad must + * be cleared when initializing a descriptor. + */ + +/* + * Buffer Descriptor data structure + * + */ +struct alt_sgdma_descriptor { + unsigned int *source; /* the address of data to be read. */ + unsigned int source_pad; + + unsigned int *destination; /* the address to write data */ + unsigned int destination_pad; + + unsigned int *next; /* the next descriptor in the list. */ + unsigned int next_pad; + + unsigned short bytes_to_transfer; /* the number of bytes to transfer */ + unsigned char read_burst; + unsigned char write_burst; + + unsigned short actual_bytes_transferred;/* bytes transferred by DMA */ + unsigned char descriptor_status; + unsigned char descriptor_control; + +} __packed_1_; + +/* SG-DMA Control/Status Slave registers map */ + +struct alt_sgdma_registers { + unsigned int status; + unsigned int status_pad[3]; + unsigned int control; + unsigned int control_pad[3]; + unsigned int next_descriptor_pointer; + unsigned int descriptor_pad[3]; +}; + +/* TSE Stuff */ +#define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001) +#define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002) +#define ALTERA_TSE_CMD_XON_GEN_MSK (0x00000004) +#define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008) +#define ALTERA_TSE_CMD_PROMIS_EN_MSK (0x00000010) +#define ALTERA_TSE_CMD_PAD_EN_MSK (0x00000020) +#define ALTERA_TSE_CMD_CRC_FWD_MSK (0x00000040) +#define ALTERA_TSE_CMD_PAUSE_FWD_MSK (0x00000080) +#define ALTERA_TSE_CMD_PAUSE_IGNORE_MSK (0x00000100) +#define ALTERA_TSE_CMD_TX_ADDR_INS_MSK (0x00000200) +#define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400) +#define ALTERA_TSE_CMD_EXCESS_COL_MSK (0x00000800) +#define ALTERA_TSE_CMD_LATE_COL_MSK (0x00001000) +#define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000) +#define ALTERA_TSE_CMD_MHASH_SEL_MSK (0x00004000) +#define ALTERA_TSE_CMD_LOOPBACK_MSK (0x00008000) +/* Bits (18:16) = address select */ +#define ALTERA_TSE_CMD_TX_ADDR_SEL_MSK (0x00070000) +#define ALTERA_TSE_CMD_MAGIC_ENA_MSK (0x00080000) +#define ALTERA_TSE_CMD_SLEEP_MSK (0x00100000) +#define ALTERA_TSE_CMD_WAKEUP_MSK (0x00200000) +#define ALTERA_TSE_CMD_XOFF_GEN_MSK (0x00400000) +#define ALTERA_TSE_CMD_CNTL_FRM_ENA_MSK (0x00800000) +#define ALTERA_TSE_CMD_NO_LENGTH_CHECK_MSK (0x01000000) +#define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000) +#define ALTERA_TSE_CMD_RX_ERR_DISC_MSK (0x04000000) +/* Bits (30..27) reserved */ +#define ALTERA_TSE_CMD_CNT_RESET_MSK (0x80000000) + +#define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 (0x00040000) +#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC (0x00020000) + +#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000) + +#define ALT_TSE_SW_RESET_WATCHDOG_CNTR 10000 +#define ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR 90000000 + +#define SET_ALTERA_TSE_INFO(x, num) \ +{ \ + sprintf(x->devname, CONFIG_SYS_ALTERA_TSE_##num##_NAME); \ + x->mac_dev = (alt_tse_mac *) CONFIG_SYS_ALTERA_TSE_##num##_BASE; \ + x->sgdma_rx = (struct alt_sgdma_registers *) \ + CONFIG_SYS_ALTERA_TSE_##num##_SGDMA_RX_BASE; \ + x->sgdma_tx = (struct alt_sgdma_registers *) \ + CONFIG_SYS_ALTERA_TSE_##num##_SGDMA_TX_BASE; \ + x->rx_sgdma_irq = (unsigned int) \ + CONFIG_SYS_ALTERA_TSE_##num##_SGDMA_RX_IRQ; \ + x->tx_sgdma_irq = (unsigned int) \ + CONFIG_SYS_ALTERA_TSE_##num##_SGDMA_TX_IRQ; \ + x->has_descriptor_mem = (unsigned int) \ + CONFIG_SYS_ALTERA_TSE_##num##_HAS_DESC_MEM; \ + x->descriptor_mem_base = (unsigned int) \ + CONFIG_SYS_ALTERA_TSE_##num##_DESC_MEM_BASE; \ + x->descriptor_mem_size = (unsigned int) \ + CONFIG_SYS_ALTERA_TSE_##num##_DESC_MEM_SPAN; \ + x->phyaddr = (unsigned int) CONFIG_SYS_ALTERA_TSE_##num##_PHY_ADDR; \ + x->flags = (unsigned int) CONFIG_SYS_ALTERA_TSE_##num##_FLAGS; \ + x->link = (unsigned int) 0; \ + x->duplexity = (unsigned int) 0; \ + x->speed = (unsigned int) 0; \ +} + +/* Command_Config Register Bit Definitions */ + +typedef volatile union __alt_tse_command_config { + unsigned int image; + struct { + unsigned int + transmit_enable:1, /* bit 0 */ + receive_enable:1, /* bit 1 */ + pause_frame_xon_gen:1, /* bit 2 */ + ethernet_speed:1, /* bit 3 */ + promiscuous_enable:1, /* bit 4 */ + pad_enable:1, /* bit 5 */ + crc_forward:1, /* bit 6 */ + pause_frame_forward:1, /* bit 7 */ + pause_frame_ignore:1, /* bit 8 */ + set_mac_address_on_tx:1, /* bit 9 */ + halfduplex_enable:1, /* bit 10 */ + excessive_collision:1, /* bit 11 */ + late_collision:1, /* bit 12 */ + software_reset:1, /* bit 13 */ + multicast_hash_mode_sel:1, /* bit 14 */ + loopback_enable:1, /* bit 15 */ + src_mac_addr_sel_on_tx:3, /* bit 18:16 */ + magic_packet_detect:1, /* bit 19 */ + sleep_mode_enable:1, /* bit 20 */ + wake_up_request:1, /* bit 21 */ + pause_frame_xoff_gen:1, /* bit 22 */ + control_frame_enable:1, /* bit 23 */ + payload_len_chk_disable:1, /* bit 24 */ + enable_10mbps_intf:1, /* bit 25 */ + rx_error_discard_enable:1, /* bit 26 */ + reserved_bits:4, /* bit 30:27 */ + self_clear_counter_reset:1; /* bit 31 */ + } __packed_1_ bits; +} __packed_1_ alt_tse_command_config; + +/* Tx_Cmd_Stat Register Bit Definitions */ + +typedef volatile union __alt_tse_tx_cmd_stat { + unsigned int image; + struct { + unsigned int reserved_lsbs:17, /* bit 16:0 */ + omit_crc:1, /* bit 17 */ + tx_shift16:1, /* bit 18 */ + reserved_msbs:13; /* bit 31:19 */ + + } __packed_1_ bits; +} alt_tse_tx_cmd_stat; + +/* Rx_Cmd_Stat Register Bit Definitions */ + +typedef volatile union __alt_tse_rx_cmd_stat { + unsigned int image; + struct { + unsigned int reserved_lsbs:25, /* bit 24:0 */ + rx_shift16:1, /* bit 25 */ + reserved_msbs:6; /* bit 31:26 */ + + } __packed_1_ bits; +} alt_tse_rx_cmd_stat; + +struct alt_tse_mdio { + unsigned int control; /*PHY device operation control register */ + unsigned int status; /*PHY device operation status register */ + unsigned int phy_id1; /*Bits 31:16 of PHY identifier. */ + unsigned int phy_id2; /*Bits 15:0 of PHY identifier. */ + unsigned int auto_negotiation_advertisement; + unsigned int remote_partner_base_page_ability; + + unsigned int reg6; + unsigned int reg7; + unsigned int reg8; + unsigned int reg9; + unsigned int rega; + unsigned int regb; + unsigned int regc; + unsigned int regd; + unsigned int rege; + unsigned int regf; + unsigned int reg10; + unsigned int reg11; + unsigned int reg12; + unsigned int reg13; + unsigned int reg14; + unsigned int reg15; + unsigned int reg16; + unsigned int reg17; + unsigned int reg18; + unsigned int reg19; + unsigned int reg1a; + unsigned int reg1b; + unsigned int reg1c; + unsigned int reg1d; + unsigned int reg1e; + unsigned int reg1f; + +}; + +/* MAC register Space */ + +typedef volatile struct { + unsigned int megacore_revision; + unsigned int scratch_pad; + alt_tse_command_config command_config; + unsigned int mac_addr_0; + unsigned int mac_addr_1; + unsigned int max_frame_length; + unsigned int pause_quanta; + unsigned int rx_sel_empty_threshold; + unsigned int rx_sel_full_threshold; + unsigned int tx_sel_empty_threshold; + unsigned int tx_sel_full_threshold; + unsigned int rx_almost_empty_threshold; + unsigned int rx_almost_full_threshold; + unsigned int tx_almost_empty_threshold; + unsigned int tx_almost_full_threshold; + unsigned int mdio_phy0_addr; + unsigned int mdio_phy1_addr; + + /* only if 100/1000 BaseX PCS, reserved otherwise */ + unsigned int reservedx44[5]; + + unsigned int reg_read_access_status; + unsigned int min_tx_ipg_length; + + /* IEEE 802.3 oEntity Managed Object Support */ + unsigned int aMACID_1; /*The MAC addresses */ + unsigned int aMACID_2; + unsigned int aFramesTransmittedOK; + unsigned int aFramesReceivedOK; + unsigned int aFramesCheckSequenceErrors; + unsigned int aAlignmentErrors; + unsigned int aOctetsTransmittedOK; + unsigned int aOctetsReceivedOK; + + /* IEEE 802.3 oPausedEntity Managed Object Support */ + unsigned int aTxPAUSEMACCtrlFrames; + unsigned int aRxPAUSEMACCtrlFrames; + + /* IETF MIB (MIB-II) Object Support */ + unsigned int ifInErrors; + unsigned int ifOutErrors; + unsigned int ifInUcastPkts; + unsigned int ifInMulticastPkts; + unsigned int ifInBroadcastPkts; + unsigned int ifOutDiscards; + unsigned int ifOutUcastPkts; + unsigned int ifOutMulticastPkts; + unsigned int ifOutBroadcastPkts; + + /* IETF RMON MIB Object Support */ + unsigned int etherStatsDropEvent; + unsigned int etherStatsOctets; + unsigned int etherStatsPkts; + unsigned int etherStatsUndersizePkts; + unsigned int etherStatsOversizePkts; + unsigned int etherStatsPkts64Octets; + unsigned int etherStatsPkts65to127Octets; + unsigned int etherStatsPkts128to255Octets; + unsigned int etherStatsPkts256to511Octets; + unsigned int etherStatsPkts512to1023Octets; + unsigned int etherStatsPkts1024to1518Octets; + + unsigned int etherStatsPkts1519toXOctets; + unsigned int etherStatsJabbers; + unsigned int etherStatsFragments; + + unsigned int reservedxE4; + + /*FIFO control register. */ + alt_tse_tx_cmd_stat tx_cmd_stat; + alt_tse_rx_cmd_stat rx_cmd_stat; + + unsigned int ipaccTxConf; + unsigned int ipaccRxConf; + unsigned int ipaccRxStat; + unsigned int ipaccRxStatSum; + + /*Multicast address resolution table */ + unsigned int hash_table[64]; + + /*Registers 0 to 31 within PHY device 0/1 */ + struct alt_tse_mdio mdio_phy0; + struct alt_tse_mdio mdio_phy1; + + /*4 Supplemental MAC Addresses */ + unsigned int supp_mac_addr_0_0; + unsigned int supp_mac_addr_0_1; + unsigned int supp_mac_addr_1_0; + unsigned int supp_mac_addr_1_1; + unsigned int supp_mac_addr_2_0; + unsigned int supp_mac_addr_2_1; + unsigned int supp_mac_addr_3_0; + unsigned int supp_mac_addr_3_1; + + unsigned int reservedx320[56]; +} alt_tse_mac; + +struct altera_tse_priv { + char devname[16]; + alt_tse_mac *mac_dev; + struct alt_sgdma_registers *sgdma_rx; + struct alt_sgdma_registers *sgdma_tx; + unsigned int rx_sgdma_irq; + unsigned int tx_sgdma_irq; + unsigned int has_descriptor_mem; + unsigned int descriptor_mem_base; + unsigned int descriptor_mem_size; + volatile struct alt_sgdma_descriptor *rx_desc; + volatile struct alt_sgdma_descriptor *tx_desc; + volatile unsigned char *rx_buf; + struct phy_info *phyinfo; + unsigned int phyaddr; + unsigned int flags; + unsigned int link; + unsigned int duplexity; + unsigned int speed; +}; + +/* Phy stuff continued */ +/* + * struct phy_cmd: A command for reading or writing a PHY register + * + * mii_reg: The register to read or write + * + * mii_data: For writes, the value to put in the register. + * A value of -1 indicates this is a read. + * + * funct: A function pointer which is invoked for each command. + * For reads, this function will be passed the value read + * from the PHY, and process it. + * For writes, the result of this function will be written + * to the PHY register + */ +struct phy_cmd { + uint mii_reg; + uint mii_data; + uint(*funct) (uint mii_reg, struct altera_tse_priv *priv); +}; -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 09/28] nios2: change asm-nios2/io.h to compatible with nios2 linux 2010-03-19 7:43 ` [U-Boot] [PATCH 08/28] net: add altera triple speeds " Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 10/28] nios2: add asm-nios2/errno.h Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot The port address should be mapped to uncached (bypass) io region before calling these writel()/readl() functions. Similar to the ioremap() of Linux. The uncached address mapping is (phyaddr | IO_REGION). here IO_REGION is 0x80000000 for NOMMU, 0xe0000000 for MMU. The cache bypass asm macros, ldwio/stwio, are removed. Mixing physical address and uncached virtual address in the config file is confusing. We shall use uncached virtual address for all devices except the main memory (sdram), which should be cached. The args to writel() is changed to (val,port), which is consistent with other archs. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- include/asm-nios2/io.h | 59 +++++++++++++++++++---------------------------- 1 files changed, 24 insertions(+), 35 deletions(-) diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h index 01d11ef..11f59ea 100644 --- a/include/asm-nios2/io.h +++ b/include/asm-nios2/io.h @@ -58,41 +58,30 @@ static inline phys_addr_t virt_to_phys(void * vaddr) return (phys_addr_t)(vaddr); } -extern unsigned char inb (unsigned char *port); -extern unsigned short inw (unsigned short *port); -extern unsigned inl (unsigned port); - -#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#define __raw_readb(a) (*(volatile unsigned char *)(a)) -#define __raw_readw(a) (*(volatile unsigned short *)(a)) -#define __raw_readl(a) (*(volatile unsigned int *)(a)) - -#define readb(addr)\ - ({unsigned char val;\ - asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) -#define readw(addr)\ - ({unsigned short val;\ - asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) -#define readl(addr)\ - ({unsigned long val;\ - asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) - -#define writeb(addr,val)\ - asm volatile ("stbio %1, 0(%0)" : : "r" (addr), "r" (val)) -#define writew(addr,val)\ - asm volatile ("sthio %1, 0(%0)" : : "r" (addr), "r" (val)) -#define writel(addr,val)\ - asm volatile ("stwio %1, 0(%0)" : : "r" (addr), "r" (val)) - -#define inb(addr) readb(addr) -#define inw(addr) readw(addr) -#define inl(addr) readl(addr) -#define outb(addr,val) writeb(addr,val) -#define outw(addr,val) writew(addr,val) -#define outl(addr,val) writel(addr,val) +#define readb(addr) \ + ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; }) +#define readw(addr) \ + ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; }) +#define readl(addr) \ + ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; }) + +#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b)) + +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +#define inb(addr) readb(addr) +#define inw(addr) readw(addr) +#define inl(addr) readl(addr) +#define outb(x, addr) ((void) writeb(x, addr)) +#define outw(x, addr) ((void) writew(x, addr)) +#define outl(x, addr) ((void) writel(x, addr)) static inline void insb (unsigned long port, void *dst, unsigned long count) { -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 10/28] nios2: add asm-nios2/errno.h 2010-03-19 7:43 ` [U-Boot] [PATCH 09/28] nios2: change asm-nios2/io.h to compatible with nios2 linux Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 11/28] nios2: add local_irq_enable/disable to asm-nios2/system.h Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot Just pull in asm-generic. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- include/asm-nios2/errno.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) create mode 100644 include/asm-nios2/errno.h diff --git a/include/asm-nios2/errno.h b/include/asm-nios2/errno.h new file mode 100644 index 0000000..4c82b50 --- /dev/null +++ b/include/asm-nios2/errno.h @@ -0,0 +1 @@ +#include <asm-generic/errno.h> -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 11/28] nios2: add local_irq_enable/disable to asm-nios2/system.h 2010-03-19 7:43 ` [U-Boot] [PATCH 10/28] nios2: add asm-nios2/errno.h Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 12/28] nios2: use bitops from linux-2.6 asm-generic Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot Copy from linux header. This is needed for generic bitops. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- include/asm-nios2/system.h | 33 +++++++++++++++++++++++++++++++++ 1 files changed, 33 insertions(+), 0 deletions(-) diff --git a/include/asm-nios2/system.h b/include/asm-nios2/system.h index ec84f59..bb03ca5 100644 --- a/include/asm-nios2/system.h +++ b/include/asm-nios2/system.h @@ -23,4 +23,37 @@ #ifndef __ASM_NIOS2_SYSTEM_H_ #define __ASM_NIOS2_SYSTEM_H_ +#define local_irq_enable() __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "ori r8, r8, 1\n" \ + "wrctl status, r8\n" \ + : : : "r8") + +#define local_irq_disable() __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "andi r8, r8, 0xfffe\n" \ + "wrctl status, r8\n" \ + : : : "r8") + +#define local_save_flags(x) __asm__ __volatile__ ( \ + "rdctl r8, status\n" \ + "mov %0, r8\n" \ + : "=r" (x) : : "r8", "memory") + +#define local_irq_restore(x) __asm__ __volatile__ ( \ + "mov r8, %0\n" \ + "wrctl status, r8\n" \ + : : "r" (x) : "r8", "memory") + +/* For spinlocks etc */ +#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } \ + while (0) + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + local_save_flags(flags); \ + ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \ +}) + #endif /* __ASM_NIOS2_SYSTEM_H */ -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 12/28] nios2: use bitops from linux-2.6 asm-generic 2010-03-19 7:43 ` [U-Boot] [PATCH 11/28] nios2: add local_irq_enable/disable to asm-nios2/system.h Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 13/28] nios2: fix __fswab64 link error with asm-nios2/byteorder.h Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot These are needed to use ubi/ubifs. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- include/asm-nios2/bitops.h | 14 +-- include/asm-nios2/bitops/atomic.h | 189 +++++++++++++++++++++++++++++++++ include/asm-nios2/bitops/ffs.h | 41 +++++++ include/asm-nios2/bitops/non-atomic.h | 108 +++++++++++++++++++ 4 files changed, 342 insertions(+), 10 deletions(-) create mode 100644 include/asm-nios2/bitops/atomic.h create mode 100644 include/asm-nios2/bitops/ffs.h create mode 100644 include/asm-nios2/bitops/non-atomic.h diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h index 5776bda..cf48ff7 100644 --- a/include/asm-nios2/bitops.h +++ b/include/asm-nios2/bitops.h @@ -24,15 +24,9 @@ #ifndef __ASM_NIOS2_BITOPS_H_ #define __ASM_NIOS2_BITOPS_H_ - -extern void set_bit(int nr, volatile void * a); -extern void clear_bit(int nr, volatile void * a); -extern int test_and_clear_bit(int nr, volatile void * a); -extern void change_bit(unsigned long nr, volatile void *addr); -extern int test_and_set_bit(int nr, volatile void * a); -extern int test_and_change_bit(int nr, volatile void * addr); -extern int test_bit(int nr, volatile void * a); -extern int ffs(int i); -#define PLATFORM_FFS +/* copied from linux-2.6/include/asm-generic/bitops */ +#include <asm/bitops/atomic.h> +#include <asm/bitops/non-atomic.h> +#include <asm/bitops/ffs.h> #endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/include/asm-nios2/bitops/atomic.h b/include/asm-nios2/bitops/atomic.h new file mode 100644 index 0000000..c894646 --- /dev/null +++ b/include/asm-nios2/bitops/atomic.h @@ -0,0 +1,189 @@ +#ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_ +#define _ASM_GENERIC_BITOPS_ATOMIC_H_ + +#include <asm/types.h> +#include <asm/system.h> + +#ifdef CONFIG_SMP +#include <asm/spinlock.h> +#include <asm/cache.h> /* we use L1_CACHE_BYTES */ + +/* Use an array of spinlocks for our atomic_ts. + * Hash function to index into a different SPINLOCK. + * Since "a" is usually an address, use one spinlock per cacheline. + */ +# define ATOMIC_HASH_SIZE 4 +# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) + +extern raw_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; + +/* Can't use raw_spin_lock_irq because of #include problems, so + * this is the substitute */ +#define _atomic_spin_lock_irqsave(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + local_irq_save(f); \ + __raw_spin_lock(s); \ +} while(0) + +#define _atomic_spin_unlock_irqrestore(l,f) do { \ + raw_spinlock_t *s = ATOMIC_HASH(l); \ + __raw_spin_unlock(s); \ + local_irq_restore(f); \ +} while(0) + + +#else +# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) +# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) +#endif + +/* + * NMI events can occur at any time, including when interrupts have been + * disabled by *_irqsave(). So you can get NMI events occurring while a + * *_bit function is holding a spin lock. If the NMI handler also wants + * to do bit manipulation (and they do) then you can get a deadlock + * between the original caller of *_bit() and the NMI handler. + * + * by Keith Owens + */ + +/** + * set_bit - Atomically set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * This function is atomic and may not be reordered. See __set_bit() + * if you do not require the atomic guarantees. + * + * Note: there are no guarantees that this function will not be reordered + * on non x86 architectures, so if you are writing portable code, + * make sure not to rely on its reordering guarantees. + * + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p |= mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * clear_bit - Clears a bit in memory + * @nr: Bit to clear + * @addr: Address to start counting from + * + * clear_bit() is atomic and may not be reordered. However, it does + * not contain a memory barrier, so if it is used for locking purposes, + * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() + * in order to ensure changes are visible on other processors. + */ +static inline void clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p &= ~mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * change_bit - Toggle a bit in memory + * @nr: Bit to change + * @addr: Address to start counting from + * + * change_bit() is atomic and may not be reordered. It may be + * reordered on other architectures than x86. + * Note that @nr may be almost arbitrarily large; this function is not + * restricted to acting on a single-word quantity. + */ +static inline void change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + *p ^= mask; + _atomic_spin_unlock_irqrestore(p, flags); +} + +/** + * test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It may be reordered on other architectures than x86. + * It also implies a memory barrier. + */ +static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old | mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +/** + * test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It can be reorderdered on other architectures other than x86. + * It also implies a memory barrier. + */ +static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old & ~mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +/** + * test_and_change_bit - Change a bit and return its old value + * @nr: Bit to change + * @addr: Address to count from + * + * This operation is atomic and cannot be reordered. + * It also implies a memory barrier. + */ +static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old; + unsigned long flags; + + _atomic_spin_lock_irqsave(p, flags); + old = *p; + *p = old ^ mask; + _atomic_spin_unlock_irqrestore(p, flags); + + return (old & mask) != 0; +} + +#endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */ diff --git a/include/asm-nios2/bitops/ffs.h b/include/asm-nios2/bitops/ffs.h new file mode 100644 index 0000000..fbbb43a --- /dev/null +++ b/include/asm-nios2/bitops/ffs.h @@ -0,0 +1,41 @@ +#ifndef _ASM_GENERIC_BITOPS_FFS_H_ +#define _ASM_GENERIC_BITOPS_FFS_H_ + +/** + * ffs - find first bit set + * @x: the word to search + * + * This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +static inline int ffs(int x) +{ + int r = 1; + + if (!x) + return 0; + if (!(x & 0xffff)) { + x >>= 16; + r += 16; + } + if (!(x & 0xff)) { + x >>= 8; + r += 8; + } + if (!(x & 0xf)) { + x >>= 4; + r += 4; + } + if (!(x & 3)) { + x >>= 2; + r += 2; + } + if (!(x & 1)) { + x >>= 1; + r += 1; + } + return r; +} + +#endif /* _ASM_GENERIC_BITOPS_FFS_H_ */ diff --git a/include/asm-nios2/bitops/non-atomic.h b/include/asm-nios2/bitops/non-atomic.h new file mode 100644 index 0000000..697cc2b --- /dev/null +++ b/include/asm-nios2/bitops/non-atomic.h @@ -0,0 +1,108 @@ +#ifndef _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ +#define _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ + +#include <asm/types.h> + +/** + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p |= mask; +} + +static inline void __clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p &= ~mask; +} + +/** + * __change_bit - Toggle a bit in memory + * @nr: the bit to change + * @addr: the address to start counting from + * + * Unlike change_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void __change_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p ^= mask; +} + +/** + * __test_and_set_bit - Set a bit and return its old value + * @nr: Bit to set + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old | mask; + return (old & mask) != 0; +} + +/** + * __test_and_clear_bit - Clear a bit and return its old value + * @nr: Bit to clear + * @addr: Address to count from + * + * This operation is non-atomic and can be reordered. + * If two examples of this operation race, one can appear to succeed + * but actually fail. You must protect multiple accesses with a lock. + */ +static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old & ~mask; + return (old & mask) != 0; +} + +/* WARNING: non atomic and it can be reordered! */ +static inline int __test_and_change_bit(int nr, + volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; + + *p = old ^ mask; + return (old & mask) != 0; +} + +/** + * test_bit - Determine whether a bit is set + * @nr: bit number to test + * @addr: Address to start counting from + */ +static inline int test_bit(int nr, const volatile unsigned long *addr) +{ + return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); +} + +#endif /* _ASM_GENERIC_BITOPS_NON_ATOMIC_H_ */ -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 13/28] nios2: fix __fswab64 link error with asm-nios2/byteorder.h 2010-03-19 7:43 ` [U-Boot] [PATCH 12/28] nios2: use bitops from linux-2.6 asm-generic Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 14/28] nios2: add dma_alloc_coherent with asm-nios2/dma-mapping.h Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- include/asm-nios2/byteorder.h | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/include/asm-nios2/byteorder.h b/include/asm-nios2/byteorder.h index 495c823..dbee62e 100644 --- a/include/asm-nios2/byteorder.h +++ b/include/asm-nios2/byteorder.h @@ -25,6 +25,11 @@ #define __ASM_NIOS2_BYTEORDER_H_ #include <asm/types.h> +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + #include <linux/byteorder/little_endian.h> #endif /* __ASM_NIOS2_BYTEORDER_H_ */ -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 14/28] nios2: add dma_alloc_coherent with asm-nios2/dma-mapping.h 2010-03-19 7:43 ` [U-Boot] [PATCH 13/28] nios2: fix __fswab64 link error with asm-nios2/byteorder.h Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 15/28] nios2: add gpio support with asm-nios2/gpio.h Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This function return cache-line aligned allocation which is mapped to uncached io region. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- include/asm-nios2/dma-mapping.h | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) create mode 100644 include/asm-nios2/dma-mapping.h diff --git a/include/asm-nios2/dma-mapping.h b/include/asm-nios2/dma-mapping.h new file mode 100644 index 0000000..69d2cc6 --- /dev/null +++ b/include/asm-nios2/dma-mapping.h @@ -0,0 +1,14 @@ +#ifndef __ASM_NIOS2_DMA_MAPPING_H +#define __ASM_NIOS2_DMA_MAPPING_H + +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + void *addr = malloc(len + CONFIG_SYS_DCACHELINE_SIZE); + flush_dcache((unsigned long)addr, len + CONFIG_SYS_DCACHELINE_SIZE); + *handle = ((unsigned long)addr + + (CONFIG_SYS_DCACHELINE_SIZE - 1)) & + ~(CONFIG_SYS_DCACHELINE_SIZE - 1) & ~(IO_REGION_BASE); + return (void *)(*handle | IO_REGION_BASE); +} + +#endif /* __ASM_NIOS2_DMA_MAPPING_H */ -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 15/28] nios2: add gpio support with asm-nios2/gpio.h 2010-03-19 7:43 ` [U-Boot] [PATCH 14/28] nios2: add dma_alloc_coherent with asm-nios2/dma-mapping.h Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 16/28] nios2: move timer handler from interrupt.c to timer.c Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This gpio core is described in http://nioswiki.com/GPIO. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- include/asm-nios2/gpio.h | 72 ++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 72 insertions(+), 0 deletions(-) create mode 100644 include/asm-nios2/gpio.h diff --git a/include/asm-nios2/gpio.h b/include/asm-nios2/gpio.h new file mode 100644 index 0000000..3a98a0d --- /dev/null +++ b/include/asm-nios2/gpio.h @@ -0,0 +1,72 @@ +/* + * Altera GPIO driver + * + * The gpio core and usage is described in http://nioswiki.com/GPIO + * + * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _ASM_NIOS2_GPIO_H_ +#define _ASM_NIOS2_GPIO_H_ 1 + +#include <asm/io.h> + +#define AVALON_GPIO_PORT(p) (CONFIG_SYS_GPIO_BASE + ((p) << 2)) + +static inline int gpio_is_valid(int number) +{ + return 1; +} + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + +static inline int gpio_direction_input(unsigned gpio) +{ + writel(1, AVALON_GPIO_PORT(gpio)); + return 0; +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + writel(value ? 3 : 2, AVALON_GPIO_PORT(gpio)); + return 0; +} + +static inline int gpio_get_value(unsigned gpio) +{ + return readl(AVALON_GPIO_PORT(gpio)); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + writel(value ? 3 : 2, AVALON_GPIO_PORT(gpio)); +} + +static inline int gpio_cansleep(unsigned gpio) +{ + return 0; +} + +static inline int gpio_get_value_cansleep(unsigned gpio) +{ + return gpio_get_value(gpio); +} + +static inline void gpio_set_value_cansleep(unsigned gpio, int value) +{ + gpio_set_value(gpio, value); +} + +#undef AVALON_GPIO_PORT +#endif /* _ASM_NIOS2_GPIO_H_ */ -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 16/28] nios2: move timer handler from interrupt.c to timer.c 2010-03-19 7:43 ` [U-Boot] [PATCH 15/28] nios2: add gpio support with asm-nios2/gpio.h Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 17/28] nios2: define text_base in start.S for linker script Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This patch move the timer handler from interrupt.c to timer.c. It will be cleaner to seperate time management from interrupt management. The registers access is changed from "volatile struct" to readl()/ writel(). This is consistent with Altera HAL and Linux. The cpu/nios2/Makefile is updated with the removal of serial.c and epcs.c, as the serial drivers are moved to drivers/serial/ and the epcs flash is supported with altera_spi and spi_flash drivers. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- cpu/nios2/Makefile | 2 +- cpu/nios2/interrupts.c | 64 +------------------------------ cpu/nios2/timer.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+), 63 deletions(-) create mode 100644 cpu/nios2/timer.c diff --git a/cpu/nios2/Makefile b/cpu/nios2/Makefile index 75f30b4..9ced9dd 100644 --- a/cpu/nios2/Makefile +++ b/cpu/nios2/Makefile @@ -27,7 +27,7 @@ LIB = $(obj)lib$(CPU).a START = start.o SOBJS = exceptions.o -COBJS = cpu.o interrupts.o serial.o sysid.o traps.o epcs.o +COBJS = cpu.o interrupts.o sysid.o traps.o timer.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/nios2/interrupts.c b/cpu/nios2/interrupts.c index 1c3566e..8becf09 100644 --- a/cpu/nios2/interrupts.c +++ b/cpu/nios2/interrupts.c @@ -37,10 +37,6 @@ #include <status_led.h> #endif -#if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ) -#error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation) -#endif - /****************************************************************************/ struct irq_action { @@ -52,62 +48,6 @@ struct irq_action { static struct irq_action vecs[32]; /*************************************************************************/ -volatile ulong timestamp = 0; - -void reset_timer (void) -{ - timestamp = 0; -} - -ulong get_timer (ulong base) -{ - WATCHDOG_RESET (); - return (timestamp - base); -} - -void set_timer (ulong t) -{ - timestamp = t; -} - - -/* The board must handle this interrupt if a timer is not - * provided. - */ -#if defined(CONFIG_SYS_NIOS_TMRBASE) -void tmr_isr (void *arg) -{ - nios_timer_t *tmr = (nios_timer_t *)arg; - /* Interrupt is cleared by writing anything to the - * status register. - */ - writel (&tmr->status, 0); - timestamp += CONFIG_SYS_NIOS_TMRMS; -#ifdef CONFIG_STATUS_LED - status_led_tick(timestamp); -#endif -} - -static void tmr_init (void) -{ - nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE; - - writel (&tmr->status, 0); - writel (&tmr->control, 0); - writel (&tmr->control, NIOS_TIMER_STOP); - -#if defined(CONFIG_SYS_NIOS_TMRCNT) - writel (&tmr->periodl, CONFIG_SYS_NIOS_TMRCNT & 0xffff); - writel (&tmr->periodh, (CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff); -#endif - writel (&tmr->control, NIOS_TIMER_ITO | NIOS_TIMER_CONT | - NIOS_TIMER_START ); - irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr); -} - -#endif /* CONFIG_SYS_NIOS_TMRBASE */ - -/*************************************************************************/ int disable_interrupts (void) { int val = rdctl (CTL_STATUS); @@ -195,8 +135,8 @@ int interrupt_init (void) vecs[i].count = 0; } -#if defined(CONFIG_SYS_NIOS_TMRBASE) - tmr_init (); +#if defined(CONFIG_SYS_TIMER_BASE) + timer_init (); #endif enable_interrupts (); diff --git a/cpu/nios2/timer.c b/cpu/nios2/timer.c new file mode 100644 index 0000000..354da51 --- /dev/null +++ b/cpu/nios2/timer.c @@ -0,0 +1,98 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd at denx.de. + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/io.h> + +#define ALTERA_TIMER_PERIOD ((CONFIG_SYS_TIMER_FREQ / CONFIG_SYS_HZ) - 1) + +#define ALTERA_TIMER_STATUS_REG 0 +#define ALTERA_TIMER_CONTROL_REG 4 +#define ALTERA_TIMER_PERIODL_REG 8 +#define ALTERA_TIMER_PERIODH_REG 12 +#define ALTERA_TIMER_SNAPL_REG 16 +#define ALTERA_TIMER_SNAPH_REG 20 + +#define ALTERA_TIMER_CONTROL_ITO_MSK (0x1) +#define ALTERA_TIMER_CONTROL_CONT_MSK (0x2) +#define ALTERA_TIMER_CONTROL_START_MSK (0x4) +#define ALTERA_TIMER_CONTROL_STOP_MSK (0x8) + +static volatile ulong timestamp; + +void reset_timer(void) +{ + timestamp = 0; +} + +ulong get_timer(ulong base) +{ + WATCHDOG_RESET(); + return timestamp - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +/* The board must handle this interrupt if a timer is not + * provided. + */ +#if defined(CONFIG_SYS_TIMER_BASE) + +static void timer_isr(void *arg) +{ + /* Interrupt is cleared by writing anything to the + * status register. + */ + writew(0, CONFIG_SYS_TIMER_BASE + ALTERA_TIMER_STATUS_REG); + timestamp++; +#ifdef CONFIG_STATUS_LED + status_led_tick(timestamp); +#endif +} + +void timer_init(void) +{ + writew(ALTERA_TIMER_CONTROL_STOP_MSK, + CONFIG_SYS_TIMER_BASE + ALTERA_TIMER_CONTROL_REG); + writew(0, CONFIG_SYS_TIMER_BASE + ALTERA_TIMER_STATUS_REG); + /* set timer period */ + writew(ALTERA_TIMER_PERIOD, + CONFIG_SYS_TIMER_BASE + ALTERA_TIMER_PERIODL_REG); + writew(ALTERA_TIMER_PERIOD >> 16, + CONFIG_SYS_TIMER_BASE + ALTERA_TIMER_PERIODH_REG); + /* interrupt enable + continuous + start */ + writew(ALTERA_TIMER_CONTROL_ITO_MSK | ALTERA_TIMER_CONTROL_CONT_MSK | + ALTERA_TIMER_CONTROL_START_MSK, + CONFIG_SYS_TIMER_BASE + ALTERA_TIMER_CONTROL_REG); + + irq_install_handler(CONFIG_SYS_TIMER_IRQ, timer_isr, NULL); +} + +#endif /* CONFIG_SYS_TIMER_BASE */ -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 17/28] nios2: define text_base in start.S for linker script 2010-03-19 7:43 ` [U-Boot] [PATCH 16/28] nios2: move timer handler from interrupt.c to timer.c Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 18/28] nios2: pass command line and initrd to linux Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot We will remove the TEXT_BASE def in board config.mk. And compute the text base in board config header file. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- cpu/nios2/start.S | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/cpu/nios2/start.S b/cpu/nios2/start.S index 31cd5b0..4b4c560 100644 --- a/cpu/nios2/start.S +++ b/cpu/nios2/start.S @@ -26,6 +26,12 @@ #include <timestamp.h> #include <version.h> +#ifdef CONFIG_SYS_TEXT_BASE + /* text base used in link script u-boot.lds */ + .global text_base + .equ text_base,CONFIG_SYS_TEXT_BASE +#endif + /************************************************************************* * RESTART ************************************************************************/ -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 18/28] nios2: pass command line and initrd to linux 2010-03-19 7:43 ` [U-Boot] [PATCH 17/28] nios2: define text_base in start.S for linker script Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 19/28] nios2: board init for eth, no flash, nand and mmc Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot The bootargs passing to nios2 linux is enabled with 'NIOS' magic as the first argument. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- lib_nios2/bootm.c | 19 ++++++++++++------- 1 files changed, 12 insertions(+), 7 deletions(-) diff --git a/lib_nios2/bootm.c b/lib_nios2/bootm.c index 675bfac..302f709 100644 --- a/lib_nios2/bootm.c +++ b/lib_nios2/bootm.c @@ -26,21 +26,26 @@ #include <asm/byteorder.h> #include <asm/cache.h> +#define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */ + int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { - void (*kernel)(void) = (void (*)(void))images->ep; + void (*kernel)(int, int, int, char *) = (void (*)(void))images->ep; + char *commandline = getenv("bootargs"); + ulong initrd_start = images->rd_start; + ulong initrd_end = images->rd_end; if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; /* flushes data and instruction caches before calling the kernel */ - flush_dcache (0,CONFIG_SYS_DCACHE_SIZE); - flush_icache (0,CONFIG_SYS_ICACHE_SIZE); + disable_interrupts(); + flush_dcache((unsigned long) kernel, CONFIG_SYS_DCACHE_SIZE); + flush_icache((unsigned long) kernel, CONFIG_SYS_ICACHE_SIZE); - /* For now we assume the Microtronix linux ... which only - * needs to be called ;-) - */ - kernel (); + printf("bootargs=%s @ 0x%x\n", commandline, &commandline); + printf("initrd=0x%x-0x%x\n", initrd_start, initrd_end); + kernel(NIOS_MAGIC, initrd_start, initrd_end, commandline); /* does not return */ return 1; -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 19/28] nios2: board init for eth, no flash, nand and mmc 2010-03-19 7:43 ` [U-Boot] [PATCH 18/28] nios2: pass command line and initrd to linux Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 20/28] nios2: fix writel in board/altera/common/epled.c Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This patch adds various initializations for eth, flash protection, no flash, nand flash and mmc. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- lib_nios2/board.c | 33 +++++++++++++++++++++++++++++++++ 1 files changed, 33 insertions(+), 0 deletions(-) diff --git a/lib_nios2/board.c b/lib_nios2/board.c index 41d3297..34d811e 100644 --- a/lib_nios2/board.c +++ b/lib_nios2/board.c @@ -38,6 +38,8 @@ DECLARE_GLOBAL_DATA_PTR; +unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; + /* * All attempts to come up with a "common" initialization sequence * that works for all boards and architectures failed: some of the @@ -78,6 +80,21 @@ init_fnc_t *init_sequence[] = { }; +static void board_net_init_r(bd_t *bd) +{ +#ifdef CONFIG_CMD_NET + char *s = getenv("bootfile"); + + if (s != NULL) + copy_filename(BootFile, s, sizeof(BootFile)); + + bd->bi_ip_addr = getenv_IPaddr("ipaddr"); + + printf("Net: "); + eth_initialize(gd->bd); +#endif +} + /***********************************************************************/ void board_init (void) { @@ -100,7 +117,9 @@ void board_init (void) bd = gd->bd; bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; +#ifndef CONFIG_SYS_NO_FLASH bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; +#endif #if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE) bd->bi_sramstart= CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; @@ -119,8 +138,20 @@ void board_init (void) /* The Malloc area is immediately below the monitor copy in RAM */ mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN); +#ifndef CONFIG_SYS_NO_FLASH WATCHDOG_RESET (); bd->bi_flashsize = flash_init(); +#endif + +#ifdef CONFIG_CMD_NAND + puts("NAND: "); + nand_init(); /* go init the NAND */ +#endif + +#ifdef CONFIG_GENERIC_MMC + puts("MMC: "); + mmc_initialize(bd); +#endif WATCHDOG_RESET (); env_relocate(); @@ -135,6 +166,8 @@ void board_init (void) WATCHDOG_RESET (); interrupt_init (); + board_net_init_r(bd); + #if defined(CONFIG_BOARD_LATE_INIT) board_late_init (); #endif -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 20/28] nios2: fix writel in board/altera/common/epled.c 2010-03-19 7:43 ` [U-Boot] [PATCH 19/28] nios2: board init for eth, no flash, nand and mmc Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 21/28] nios2: add cf ide init and reset handler Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot The args to writel() is changed to (val,port). The base address is renamed to CONFIG_SYS_LED_PIO_BASE, which is consistent with the name used in altera example designs. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- board/altera/common/epled.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c index e5e7705..d092011 100644 --- a/board/altera/common/epled.c +++ b/board/altera/common/epled.c @@ -33,30 +33,30 @@ static led_id_t val = 0; void __led_init (led_id_t mask, int state) { - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; + nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LED_PIO_BASE; if (state == STATUS_LED_ON) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_set (led_id_t mask, int state) { - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; + nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LED_PIO_BASE; if (state == STATUS_LED_ON) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_toggle (led_id_t mask) { - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; + nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LED_PIO_BASE; val ^= mask; - writel (&pio->data, val); + writel (val, &pio->data); } -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 21/28] nios2: add cf ide init and reset handler 2010-03-19 7:43 ` [U-Boot] [PATCH 20/28] nios2: fix writel in board/altera/common/epled.c Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 22/28] nios2: add gpio led driver Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This patch adds the init and reset of cf card controllers. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- board/altera/common/cfide.c | 79 +++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 79 insertions(+), 0 deletions(-) create mode 100644 board/altera/common/cfide.c diff --git a/board/altera/common/cfide.c b/board/altera/common/cfide.c new file mode 100644 index 0000000..acd1e1d --- /dev/null +++ b/board/altera/common/cfide.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <nios2-io.h> + +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_SYS_CF_CTL_BASE) +/* ide_set_reset for Altera CF interface */ +#define ALTERA_CF_CTL_STATUS 0 +#define ALTERA_CF_IDE_CTL 4 +#define ALTERA_CF_CTL_STATUS_PRESENT_MSK (0x1) +#define ALTERA_CF_CTL_STATUS_POWER_MSK (0x2) +#define ALTERA_CF_CTL_STATUS_RESET_MSK (0x4) +#define ALTERA_CF_CTL_STATUS_IRQ_EN_MSK (0x8) +#define ALTERA_CF_IDE_CTL_IRQ_EN_MSK (0x1) + +void ide_set_reset(int idereset) +{ + if (idereset) { + writel(0, /* disable ide irq */ + CONFIG_SYS_CF_CTL_BASE + ALTERA_CF_IDE_CTL); + writel(ALTERA_CF_CTL_STATUS_RESET_MSK, /* power down */ + CONFIG_SYS_CF_CTL_BASE + ALTERA_CF_CTL_STATUS); + udelay(500 * 1000); /* 0.5 sec delay */ + writel(ALTERA_CF_CTL_STATUS_POWER_MSK, /* power up */ + CONFIG_SYS_CF_CTL_BASE + ALTERA_CF_CTL_STATUS); + udelay(500 * 1000); /* 0.5 sec delay */ + } +} +#endif + +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_SYS_CF_PRESENT) +/* ide_preinit for PK1C20 */ +int ide_preinit(void) +{ + nios_pio_t *present = (nios_pio_t *) CONFIG_SYS_CF_PRESENT; + nios_pio_t *power = (nios_pio_t *) CONFIG_SYS_CF_POWER; + nios_pio_t *atasel = (nios_pio_t *) CONFIG_SYS_CF_ATASEL; + + /* setup data direction registers */ + present->direction = NIOS_PIO_IN; + power->direction = NIOS_PIO_OUT; + atasel->direction = NIOS_PIO_OUT; + + /* Check for presence of card */ + if (present->data) + return 1; + printf("Ok\n"); + + /* Finish setup */ + power->data = 1; /* Turn on power FET */ + atasel->data = 0; /* Put in ATA mode */ + + return 0; +} +#endif -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 22/28] nios2: add gpio led driver 2010-03-19 7:43 ` [U-Boot] [PATCH 21/28] nios2: add cf ide init and reset handler Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 23/28] nios2: convert ep1c20 board to use cfi flash and spi flash Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot Ths patch adds status led driver based on gpio interface. The STATUS_LED_BIT specifies the gpio pin number. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- board/altera/common/gpioled.c | 31 +++++++++++++++++++++++++++++++ 1 files changed, 31 insertions(+), 0 deletions(-) create mode 100644 board/altera/common/gpioled.c diff --git a/board/altera/common/gpioled.c b/board/altera/common/gpioled.c new file mode 100644 index 0000000..13e0032 --- /dev/null +++ b/board/altera/common/gpioled.c @@ -0,0 +1,31 @@ +/* + * LED driver based on gpio + * + * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <common.h> +#include <status_led.h> +#include <asm/io.h> +#include <asm/gpio.h> + +/* assume led is active low */ + +void __led_init(led_id_t mask, int state) +{ + gpio_direction_output(mask, (state == STATUS_LED_ON) ? 0 : 1); +} + +void __led_set(led_id_t mask, int state) +{ + gpio_set_value(mask, (state == STATUS_LED_ON) ? 0 : 1); +} + +void __led_toggle(led_id_t mask) +{ + gpio_set_value(mask, !gpio_get_value(mask)); +} -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 23/28] nios2: convert ep1c20 board to use cfi flash and spi flash 2010-03-19 7:43 ` [U-Boot] [PATCH 22/28] nios2: add gpio led driver Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 24/28] nios2: convert ep1s10 board to use cfi flash Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot The patch converts the ep1c20 board to use the common cfi flash and spi driver. The addressing of devices is changed to virtual address. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- board/altera/ep1c20/Makefile | 2 +- board/altera/ep1c20/config.mk | 2 +- board/altera/ep1c20/u-boot.lds | 1 + include/configs/EP1C20.h | 60 ++++++++++++++++++++++++++------------- 4 files changed, 43 insertions(+), 22 deletions(-) diff --git a/board/altera/ep1c20/Makefile b/board/altera/ep1c20/Makefile index acad2aa..c57ef1a 100644 --- a/board/altera/ep1c20/Makefile +++ b/board/altera/ep1c20/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).a -COMOBJS := ../common/AMDLV065D.o ../common/epled.o +COMOBJS := ../common/epled.o COBJS := $(BOARD).o $(COMOBJS) diff --git a/board/altera/ep1c20/config.mk b/board/altera/ep1c20/config.mk index dab2740..6cb9629 100644 --- a/board/altera/ep1c20/config.mk +++ b/board/altera/ep1c20/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x01fc0000 +#TEXT_BASE = 0x01fc0000 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include diff --git a/board/altera/ep1c20/u-boot.lds b/board/altera/ep1c20/u-boot.lds index e2eb3aa..fa7ed30 100644 --- a/board/altera/ep1c20/u-boot.lds +++ b/board/altera/ep1c20/u-boot.lds @@ -28,6 +28,7 @@ ENTRY(_start) SECTIONS { + . = text_base; .text : { cpu/nios2/start.o (.text) diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h index 61d8e20..cf6960a 100644 --- a/include/configs/EP1C20.h +++ b/include/configs/EP1C20.h @@ -24,6 +24,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_BOARD_NAME "EP1C20" +#define IO_REGION_BASE 0x80000000 + /*------------------------------------------------------------------------ * BOARD/CPU *----------------------------------------------------------------------*/ @@ -32,7 +35,7 @@ #define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ #define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ +#define CONFIG_SYS_NIOS_SYSID_BASE 0x821208b8 /* System id address */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ /*------------------------------------------------------------------------ @@ -47,7 +50,7 @@ /*------------------------------------------------------------------------ * MEMORY BASE ADDRESSES *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ +#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH base addr */ #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ #define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ #define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ @@ -61,23 +64,29 @@ * -Global data is placed below the heap. * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */ +#define CONFIG_SYS_TEXT_LEN (256 * 1024) /* Reserve 256k */ +#define CONFIG_SYS_TEXT_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_TEXT_LEN) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_RESET_ADDR | IO_REGION_BASE) +#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_TEXT_LEN #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET /*------------------------------------------------------------------------ * FLASH (AM29LV065D) *----------------------------------------------------------------------*/ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix nios2 flash timing issue in amd toggle*/ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ /*------------------------------------------------------------------------ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above @@ -95,13 +104,16 @@ * CONSOLE *----------------------------------------------------------------------*/ #if defined(CONFIG_CONSOLE_JTAG) -#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ +#define CONFIG_ALTERA_JTAGUART #else -#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ +#define CONFIG_ALTERA_UART #endif -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CONFIG_SYS_JTAGUART_BASE 0x821208b0 /* JTAG UART base addr */ +#define CONFIG_SYS_UART_BASE 0x82120840 /* UART base addr */ + +#define CONFIG_SYS_UART_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ #define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ @@ -112,7 +124,15 @@ * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. * The register base is currently at offset 0x600 from the memory base. *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */ +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_ALTERA_SPI + +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SYS_SPI_BASE 0x82100200 /* EPCS register base */ /*------------------------------------------------------------------------ * DEBUG @@ -126,23 +146,23 @@ * registers, we can slow it down to 10 msec using TMRCNT. If the default * period is acceptable, TMRCNT can be left undefined. *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_TIMER_BASE 0x82120820 /* Tick timer base addr */ +#define CONFIG_SYS_TIMER_IRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_TIMER_FREQ CONFIG_SYS_CLK_FREQ /* Timer input freq */ +#define CONFIG_SYS_HZ 1000 /* should be 1000 for flash timing */ /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board * must implement its own led routines -- leds are, after all, * board-specific, no? *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ +#define CONFIG_SYS_LED_PIO_BASE 0x82120870 /* LED PIO base addr */ +#define CONFIG_EPLED /* Enable LED PIO driver */ #define CONFIG_STATUS_LED /* Enable status driver */ #define STATUS_LED_BIT 1 /* Bit-0 on PIO */ #define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* Every 500 msec */ /*------------------------------------------------------------------------ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 24/28] nios2: convert ep1s10 board to use cfi flash 2010-03-19 7:43 ` [U-Boot] [PATCH 23/28] nios2: convert ep1c20 board to use cfi flash and spi flash Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 25/28] nios2: convert ep1s40 " Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot The patch converts the ep1s10 board to use the common cfi flash driver. The addressing of devices is changed to virtual address. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- board/altera/ep1s10/Makefile | 2 +- board/altera/ep1s10/config.mk | 2 +- board/altera/ep1s10/u-boot.lds | 1 + include/configs/EP1S10.h | 58 ++++++++++++++++++++++++---------------- 4 files changed, 38 insertions(+), 25 deletions(-) diff --git a/board/altera/ep1s10/Makefile b/board/altera/ep1s10/Makefile index acad2aa..c57ef1a 100644 --- a/board/altera/ep1s10/Makefile +++ b/board/altera/ep1s10/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).a -COMOBJS := ../common/AMDLV065D.o ../common/epled.o +COMOBJS := ../common/epled.o COBJS := $(BOARD).o $(COMOBJS) diff --git a/board/altera/ep1s10/config.mk b/board/altera/ep1s10/config.mk index dab2740..6cb9629 100644 --- a/board/altera/ep1s10/config.mk +++ b/board/altera/ep1s10/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x01fc0000 +#TEXT_BASE = 0x01fc0000 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include diff --git a/board/altera/ep1s10/u-boot.lds b/board/altera/ep1s10/u-boot.lds index e2eb3aa..fa7ed30 100644 --- a/board/altera/ep1s10/u-boot.lds +++ b/board/altera/ep1s10/u-boot.lds @@ -28,6 +28,7 @@ ENTRY(_start) SECTIONS { + . = text_base; .text : { cpu/nios2/start.o (.text) diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 41e64e6..38320f3 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -24,6 +24,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_BOARD_NAME "EP1S10" +#define IO_REGION_BASE 0x80000000 + /*------------------------------------------------------------------------ * BOARD/CPU *----------------------------------------------------------------------*/ @@ -32,7 +35,7 @@ #define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ #define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ +#define CONFIG_SYS_NIOS_SYSID_BASE 0x821208b8 /* System id address */ /*------------------------------------------------------------------------ * CACHE -- the following will support II/s and II/f. The II/s does not @@ -46,12 +49,12 @@ /*------------------------------------------------------------------------ * MEMORY BASE ADDRESSES *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ +#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH base addr */ #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ #define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ #define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ #define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB */ +#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ /*------------------------------------------------------------------------ * MEMORY ORGANIZATION @@ -60,46 +63,56 @@ * -Global data is placed below the heap. * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ +#define CONFIG_SYS_TEXT_LEN (256 * 1024) /* Reserve 256k */ +#define CONFIG_SYS_TEXT_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_TEXT_LEN) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_RESET_ADDR | IO_REGION_BASE) +#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_TEXT_LEN #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) /* 256k heap */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET /*------------------------------------------------------------------------ * FLASH (AM29LV065D) *----------------------------------------------------------------------*/ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix nios2 flash timing issue in amd toggle*/ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ /*------------------------------------------------------------------------ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom - * of flash memory. This will keep the environment in user region + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region * of flash. NOTE: the monitor length must be multiple of sector size * (which is common practice). *----------------------------------------------------------------------*/ #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ #define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ #define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN) /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ #if defined(CONFIG_CONSOLE_JTAG) -#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ +#define CONFIG_ALTERA_JTAGUART #else -#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ +#define CONFIG_ALTERA_UART #endif -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CONFIG_SYS_JTAGUART_BASE 0x821208b0 /* JTAG UART base addr */ +#define CONFIG_SYS_UART_BASE 0x82120840 /* UART base addr */ + +#define CONFIG_SYS_UART_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ #define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ @@ -107,7 +120,6 @@ /*------------------------------------------------------------------------ * EPCS Device -- None for stratix. *----------------------------------------------------------------------*/ -#undef CONFIG_SYS_NIOS_EPCSBASE /*------------------------------------------------------------------------ * DEBUG @@ -121,22 +133,22 @@ * registers, we can slow it down to 10 msec using TMRCNT. If the default * period is acceptable, TMRCNT can be left undefined. *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_TIMER_BASE 0x82120820 /* Tick timer base addr */ +#define CONFIG_SYS_TIMER_IRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_TIMER_FREQ CONFIG_SYS_CLK_FREQ /* Timer input freq */ +#define CONFIG_SYS_HZ 1000 /* should be 1000 for flash timing */ /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board * must implement its own led routines -- since leds are board-specific. *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ +#define CONFIG_SYS_LED_PIO_BASE 0x82120870 /* LED PIO base addr */ +#define CONFIG_EPLED /* Enable LED PIO driver */ #define CONFIG_STATUS_LED /* Enable status driver */ #define STATUS_LED_BIT 1 /* Bit-0 on PIO */ #define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* Every 500 msec */ /*------------------------------------------------------------------------ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 25/28] nios2: convert ep1s40 board to use cfi flash 2010-03-19 7:43 ` [U-Boot] [PATCH 24/28] nios2: convert ep1s10 board to use cfi flash Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 26/28] nios2: convert pci5441 " Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot The patch converts the ep1s40 board to use the common cfi flash driver. The addressing of devices is changed to virtual address. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- board/altera/ep1s40/Makefile | 2 +- board/altera/ep1s40/config.mk | 2 +- board/altera/ep1s40/u-boot.lds | 1 + include/configs/EP1S40.h | 54 ++++++++++++++++++++++++--------------- 4 files changed, 36 insertions(+), 23 deletions(-) diff --git a/board/altera/ep1s40/Makefile b/board/altera/ep1s40/Makefile index acad2aa..c57ef1a 100644 --- a/board/altera/ep1s40/Makefile +++ b/board/altera/ep1s40/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).a -COMOBJS := ../common/AMDLV065D.o ../common/epled.o +COMOBJS := ../common/epled.o COBJS := $(BOARD).o $(COMOBJS) diff --git a/board/altera/ep1s40/config.mk b/board/altera/ep1s40/config.mk index dab2740..6cb9629 100644 --- a/board/altera/ep1s40/config.mk +++ b/board/altera/ep1s40/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x01fc0000 +#TEXT_BASE = 0x01fc0000 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include diff --git a/board/altera/ep1s40/u-boot.lds b/board/altera/ep1s40/u-boot.lds index e2eb3aa..fa7ed30 100644 --- a/board/altera/ep1s40/u-boot.lds +++ b/board/altera/ep1s40/u-boot.lds @@ -28,6 +28,7 @@ ENTRY(_start) SECTIONS { + . = text_base; .text : { cpu/nios2/start.o (.text) diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 5b332e4..07a0cca 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -24,6 +24,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_BOARD_NAME "EP1S40" +#define IO_REGION_BASE 0x80000000 + /*------------------------------------------------------------------------ * BOARD/CPU *----------------------------------------------------------------------*/ @@ -32,7 +35,7 @@ #define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ #define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ +#define CONFIG_SYS_NIOS_SYSID_BASE 0x821208b8 /* System id address */ /*------------------------------------------------------------------------ * CACHE -- the following will support II/s and II/f. The II/s does not @@ -46,12 +49,12 @@ /*------------------------------------------------------------------------ * MEMORY BASE ADDRESSES *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ +#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH base addr */ #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ #define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ #define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ #define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */ -#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB */ +#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ /*------------------------------------------------------------------------ * MEMORY ORGANIZATION @@ -60,22 +63,29 @@ * -Global data is placed below the heap. * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256k */ +#define CONFIG_SYS_TEXT_LEN (256 * 1024) /* Reserve 256k */ +#define CONFIG_SYS_TEXT_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_TEXT_LEN) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_RESET_ADDR | IO_REGION_BASE) +#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_TEXT_LEN #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024) /* 256k heap */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET /*------------------------------------------------------------------------ * FLASH (AM29LV065D) *----------------------------------------------------------------------*/ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix nios2 flash timing issue in amd toggle*/ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ /*------------------------------------------------------------------------ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above @@ -87,19 +97,22 @@ #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ #define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ #define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN) /*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/ #if defined(CONFIG_CONSOLE_JTAG) -#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ +#define CONFIG_ALTERA_JTAGUART #else -#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ +#define CONFIG_ALTERA_UART #endif -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CONFIG_SYS_JTAGUART_BASE 0x821208b0 /* JTAG UART base addr */ +#define CONFIG_SYS_UART_BASE 0x82120840 /* UART base addr */ + +#define CONFIG_SYS_UART_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ #define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ @@ -107,7 +120,6 @@ /*------------------------------------------------------------------------ * EPCS Device -- None for stratix. *----------------------------------------------------------------------*/ -#undef CONFIG_SYS_NIOS_EPCSBASE /*------------------------------------------------------------------------ * DEBUG @@ -121,22 +133,22 @@ * registers, we can slow it down to 10 msec using TMRCNT. If the default * period is acceptable, TMRCNT can be left undefined. *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_TIMER_BASE 0x82120820 /* Tick timer base addr */ +#define CONFIG_SYS_TIMER_IRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_TIMER_FREQ CONFIG_SYS_CLK_FREQ /* Timer input freq */ +#define CONFIG_SYS_HZ 1000 /* should be 1000 for flash timing */ /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board * must implement its own led routines -- since leds are board-specific. *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ +#define CONFIG_SYS_LED_PIO_BASE 0x82120870 /* LED PIO base addr */ +#define CONFIG_EPLED /* Enable LED PIO driver */ #define CONFIG_STATUS_LED /* Enable status driver */ #define STATUS_LED_BIT 1 /* Bit-0 on PIO */ #define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* Every 500 msec */ /*------------------------------------------------------------------------ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 26/28] nios2: convert pci5441 board to use cfi flash 2010-03-19 7:43 ` [U-Boot] [PATCH 25/28] nios2: convert ep1s40 " Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 27/28] nios2: convert pk1c20 board to use cfi flash and spi flash Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot The patch converts the pci5441 board to use the common cfi flash driver. The addressing of devices is changed to virtual address. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- board/psyent/pci5441/Makefile | 2 +- board/psyent/pci5441/config.mk | 2 +- board/psyent/pci5441/u-boot.lds | 1 + include/configs/PCI5441.h | 44 +++++++++++++++++++++++--------------- 4 files changed, 30 insertions(+), 19 deletions(-) diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile index 301b4a0..18f2f55 100644 --- a/board/psyent/pci5441/Makefile +++ b/board/psyent/pci5441/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).a -COMOBJS := ../common/AMDLV065D.o +COMOBJS := COBJS := $(BOARD).o $(COMOBJS) diff --git a/board/psyent/pci5441/config.mk b/board/psyent/pci5441/config.mk index d72bcee..9c67ec3 100644 --- a/board/psyent/pci5441/config.mk +++ b/board/psyent/pci5441/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x018e0000 +#TEXT_BASE = 0x018e0000 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include diff --git a/board/psyent/pci5441/u-boot.lds b/board/psyent/pci5441/u-boot.lds index b2d88a5..5c26351 100644 --- a/board/psyent/pci5441/u-boot.lds +++ b/board/psyent/pci5441/u-boot.lds @@ -28,6 +28,7 @@ ENTRY(_start) SECTIONS { + . = text_base; .text : { cpu/nios2/start.o (.text) diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index 831a60d..d193aa8 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -24,6 +24,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_BOARD_NAME "Psyent PCI5441" +#define IO_REGION_BASE 0x80000000 + /*------------------------------------------------------------------------ * BOARD/CPU *----------------------------------------------------------------------*/ @@ -32,7 +35,7 @@ #define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ #define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x00920828 /* System id address */ +#define CONFIG_SYS_NIOS_SYSID_BASE 0x80920828 /* System id address */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ /*------------------------------------------------------------------------ @@ -47,7 +50,7 @@ /*------------------------------------------------------------------------ * MEMORY BASE ADDRESSES *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ +#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH base addr */ #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ #define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ #define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ @@ -59,23 +62,28 @@ * -Global data is placed below the heap. * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128k */ +#define CONFIG_SYS_TEXT_LEN (128 * 1024) /* Reserve 128k */ +#define CONFIG_SYS_TEXT_BASE 0x018e0000 +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_RESET_ADDR | IO_REGION_BASE) +#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_TEXT_LEN #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET /*------------------------------------------------------------------------ * FLASH (AM29LV065D) *----------------------------------------------------------------------*/ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix nios2 flash timing issue in amd toggle*/ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ /*------------------------------------------------------------------------ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above @@ -93,13 +101,16 @@ * CONSOLE *----------------------------------------------------------------------*/ #if defined(CONFIG_CONSOLE_JTAG) -#define CONFIG_SYS_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */ +#define CONFIG_ALTERA_JTAGUART #else -#define CONFIG_SYS_NIOS_CONSOLE 0x009208a0 /* UART base addr */ +#define CONFIG_ALTERA_UART #endif -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CONFIG_SYS_JTAGUART_BASE 0x80920820 /* JTAG UART base addr */ +#define CONFIG_SYS_UART_BASE 0x809208a0 /* UART base addr */ + +#define CONFIG_SYS_UART_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ #define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ @@ -116,11 +127,10 @@ * registers, we can slow it down to 10 msec using TMRCNT. If the default * period is acceptable, TMRCNT can be left undefined. *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_TIMER_BASE 0x80920860 /* Tick timer base addr */ +#define CONFIG_SYS_TIMER_IRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_TIMER_FREQ CONFIG_SYS_CLK_FREQ /* Timer input freq */ +#define CONFIG_SYS_HZ 1000 /* should be 1000 for flash timing */ /* -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 27/28] nios2: convert pk1c20 board to use cfi flash and spi flash 2010-03-19 7:43 ` [U-Boot] [PATCH 26/28] nios2: convert pci5441 " Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 28/28] nios2: add struct stat support in linux/stat.h Thomas Chou 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot The patch converts the pk1c20 board to use the common cfi flash and spi driver. The addressing of devices is changed to virtual address. The args to writel() is changed to (val,port) in led.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- board/psyent/pk1c20/Makefile | 2 +- board/psyent/pk1c20/config.mk | 2 +- board/psyent/pk1c20/led.c | 12 +++--- board/psyent/pk1c20/u-boot.lds | 1 + include/configs/PK1C20.h | 68 ++++++++++++++++++++++++++-------------- 5 files changed, 53 insertions(+), 32 deletions(-) diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile index e23a17b..84db953 100644 --- a/board/psyent/pk1c20/Makefile +++ b/board/psyent/pk1c20/Makefile @@ -28,7 +28,7 @@ endif LIB = $(obj)lib$(BOARD).a -COMOBJS := ../common/AMDLV065D.o +COMOBJS := COBJS := $(BOARD).o led.o $(COMOBJS) diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk index d65780d..ff49287 100644 --- a/board/psyent/pk1c20/config.mk +++ b/board/psyent/pk1c20/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -TEXT_BASE = 0x01fc0000 +#TEXT_BASE = 0x01fc0000 PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c index e5e7705..d092011 100644 --- a/board/psyent/pk1c20/led.c +++ b/board/psyent/pk1c20/led.c @@ -33,30 +33,30 @@ static led_id_t val = 0; void __led_init (led_id_t mask, int state) { - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; + nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LED_PIO_BASE; if (state == STATUS_LED_ON) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_set (led_id_t mask, int state) { - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; + nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LED_PIO_BASE; if (state == STATUS_LED_ON) val &= ~mask; else val |= mask; - writel (&pio->data, val); + writel (val, &pio->data); } void __led_toggle (led_id_t mask) { - nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR; + nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LED_PIO_BASE; val ^= mask; - writel (&pio->data, val); + writel (val, &pio->data); } diff --git a/board/psyent/pk1c20/u-boot.lds b/board/psyent/pk1c20/u-boot.lds index b2d88a5..5c26351 100644 --- a/board/psyent/pk1c20/u-boot.lds +++ b/board/psyent/pk1c20/u-boot.lds @@ -28,6 +28,7 @@ ENTRY(_start) SECTIONS { + . = text_base; .text : { cpu/nios2/start.o (.text) diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index cf6f7a9..3cd0806 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -24,6 +24,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_BOARD_NAME "Psyent PK1C20" +#define IO_REGION_BASE 0x80000000 + /*------------------------------------------------------------------------ * BOARD/CPU *----------------------------------------------------------------------*/ @@ -32,7 +35,7 @@ #define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ #define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ -#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ +#define CONFIG_SYS_NIOS_SYSID_BASE 0x821208b8 /* System id address */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ /*------------------------------------------------------------------------ @@ -47,7 +50,7 @@ /*------------------------------------------------------------------------ * MEMORY BASE ADDRESSES *----------------------------------------------------------------------*/ -#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ +#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH base addr */ #define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ #define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ #define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ @@ -61,23 +64,29 @@ * -Global data is placed below the heap. * -The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */ +#define CONFIG_SYS_TEXT_LEN (256 * 1024) /* Reserve 256k */ +#define CONFIG_SYS_TEXT_BASE (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_TEXT_LEN) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_RESET_ADDR | IO_REGION_BASE) +#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_TEXT_LEN #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET /*------------------------------------------------------------------------ * FLASH (AM29LV065D) *----------------------------------------------------------------------*/ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix nios2 flash timing issue in amd toggle*/ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ /*------------------------------------------------------------------------ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above @@ -95,13 +104,16 @@ * CONSOLE *----------------------------------------------------------------------*/ #if defined(CONFIG_CONSOLE_JTAG) -#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ +#define CONFIG_ALTERA_JTAGUART #else -#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ +#define CONFIG_ALTERA_UART #endif -#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ -#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CONFIG_SYS_JTAGUART_BASE 0x821208b0 /* JTAG UART base addr */ +#define CONFIG_SYS_UART_BASE 0x82120840 /* UART base addr */ + +#define CONFIG_SYS_UART_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ #define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ @@ -112,7 +124,15 @@ * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. * The register base is currently at offset 0x600 from the memory base. *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */ +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_ALTERA_SPI + +#define CONFIG_ENV_SPI_MAX_HZ 30000000 +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SYS_SPI_BASE 0x82100200 /* EPCS register base */ /*------------------------------------------------------------------------ * DEBUG @@ -126,23 +146,23 @@ * registers, we can slow it down to 10 msec using TMRCNT. If the default * period is acceptable, TMRCNT can be left undefined. *----------------------------------------------------------------------*/ -#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ -#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ -#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ -#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) -#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) +#define CONFIG_SYS_TIMER_BASE 0x82120820 /* Tick timer base addr */ +#define CONFIG_SYS_TIMER_IRQ 3 /* Timer IRQ num */ +#define CONFIG_SYS_TIMER_FREQ CONFIG_SYS_CLK_FREQ /* Timer input freq */ +#define CONFIG_SYS_HZ 1000 /* should be 1000 for flash timing */ /*------------------------------------------------------------------------ * STATUS LED -- Provides a simple blinking led. For Nios2 each board * must implement its own led routines -- leds are, after all, * board-specific, no? *----------------------------------------------------------------------*/ -#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ +#define CONFIG_SYS_LED_PIO_BASE 0x82120870 /* LED PIO base addr */ +#define CONFIG_EPLED /* Enable LED PIO driver */ #define CONFIG_STATUS_LED /* Enable status driver */ #define STATUS_LED_BIT 1 /* Bit-0 on PIO */ #define STATUS_LED_STATE 1 /* Blinking */ -#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* Every 500 msec */ /*------------------------------------------------------------------------ * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... @@ -200,7 +220,7 @@ #define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ #define CONFIG_SYS_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ -#define CONFIG_SYS_ATA_BASE_ADDR 0x00900800 /* ATA base addr */ +#define CONFIG_SYS_ATA_BASE_ADDR 0x80900800 /* ATA base addr */ #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ #define CONFIG_SYS_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ #define CONFIG_SYS_ATA_REG_OFFSET 0x0040 /* Register offset */ @@ -209,9 +229,9 @@ #define CONFIG_DOS_PARTITION /* Board-specific cf regs */ -#define CONFIG_SYS_CF_PRESENT 0x00900880 /* CF Present PIO base */ -#define CONFIG_SYS_CF_POWER 0x00900890 /* CF Power FET PIO base*/ -#define CONFIG_SYS_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */ +#define CONFIG_SYS_CF_PRESENT 0x80900880 /* CF Present PIO base */ +#define CONFIG_SYS_CF_POWER 0x80900890 /* CF Power FET PIO base*/ +#define CONFIG_SYS_CF_ATASEL 0x809008a0 /* CF ATASEL PIO base */ #endif -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 28/28] nios2: add struct stat support in linux/stat.h 2010-03-19 7:43 ` [U-Boot] [PATCH 27/28] nios2: convert pk1c20 board to use cfi flash and spi flash Thomas Chou @ 2010-03-19 7:43 ` Thomas Chou 0 siblings, 0 replies; 40+ messages in thread From: Thomas Chou @ 2010-03-19 7:43 UTC (permalink / raw) To: u-boot This is needed for jffs2 support. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> --- include/linux/stat.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/linux/stat.h b/include/linux/stat.h index 2ce1c25..cef6369 100644 --- a/include/linux/stat.h +++ b/include/linux/stat.h @@ -68,7 +68,7 @@ struct stat { #endif /* __PPC__ */ #if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__bfin__) ||\ - defined (__microblaze__) + defined (__microblaze__) || defined (__nios2__) struct stat { unsigned short st_dev; -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 01/28] nios2: add nios2-generic board 2010-03-19 7:43 ` [U-Boot] [PATCH 01/28] nios2: add nios2-generic board Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 02/28] cfi flash: add status polling method for amd flash Thomas Chou @ 2010-04-05 5:36 ` Ben Warren 2010-04-07 3:19 ` Thomas Chou 1 sibling, 1 reply; 40+ messages in thread From: Ben Warren @ 2010-04-05 5:36 UTC (permalink / raw) To: u-boot Hi Thomas, On 3/19/2010 12:43 AM, Thomas Chou wrote: > This is a generic approach to port u-boot for nios2 boards. > It uses a new set of device drivers, such as the cfi flash, spi > lash, nand flash and new ethernet drivers. > > <snip> > +#ifdef CONFIG_CMD_NET > +int board_eth_init(bd_t *bis) > +{ > + int rc = 0; > +#ifdef CONFIG_SMC91111 > + rc = smc91111_initialize(bis, CONFIG_SMC91111_BASE); > +#endif > + > +#ifdef CONFIG_DRIVER_DM9000 > + rc = dm9000_initialize(bis); > +#endif > + > +#ifdef CONFIG_ALTERA_TSE > + altera_tse_init(bis, CONFIG_SYS_NUM_TSE_MACS); > +#endif > + > +#ifdef CONFIG_ETHOC > + rc = ethoc_initialize(bis, CONFIG_SYS_ETHOC_BASE); > +#endif > + return rc; > +} > Please clean up the return code handling. The drivers are not mutually exclusive. <snip> > + > +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b > +#define CONFIG_NETMASK 255.255.255.0 > +#define CONFIG_IPADDR 192.168.2.21 > +#define CONFIG_SERVERIP 192.168.2.16 > + > Please remove these definitions regards, Ben ^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 01/28] nios2: add nios2-generic board 2010-04-05 5:36 ` [U-Boot] [PATCH 01/28] nios2: add nios2-generic board Ben Warren @ 2010-04-07 3:19 ` Thomas Chou 2010-04-07 17:23 ` Ben Warren 0 siblings, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-04-07 3:19 UTC (permalink / raw) To: u-boot On 04/05/2010 01:36 PM, Ben Warren wrote: > Hi Thomas, > > On 3/19/2010 12:43 AM, Thomas Chou wrote: >> This is a generic approach to port u-boot for nios2 boards. >> It uses a new set of device drivers, such as the cfi flash, spi >> lash, nand flash and new ethernet drivers. >> > <snip> >> +#ifdef CONFIG_CMD_NET >> +int board_eth_init(bd_t *bis) >> +{ >> + int rc = 0; >> +#ifdef CONFIG_SMC91111 >> + rc = smc91111_initialize(bis, CONFIG_SMC91111_BASE); >> +#endif >> + >> +#ifdef CONFIG_DRIVER_DM9000 >> + rc = dm9000_initialize(bis); >> +#endif >> + >> +#ifdef CONFIG_ALTERA_TSE >> + altera_tse_init(bis, CONFIG_SYS_NUM_TSE_MACS); >> +#endif >> + >> +#ifdef CONFIG_ETHOC >> + rc = ethoc_initialize(bis, CONFIG_SYS_ETHOC_BASE); >> +#endif >> + return rc; >> +} > Please clean up the return code handling. The drivers are not > mutually exclusive. Hi Ben, Does it make sense to return 0 always, as we don't have cpu_eth_init()? > > <snip> >> + >> +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b >> +#define CONFIG_NETMASK 255.255.255.0 >> +#define CONFIG_IPADDR 192.168.2.21 >> +#define CONFIG_SERVERIP 192.168.2.16 >> + > Please remove these definitions OK. Best regards, Thomas ^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 01/28] nios2: add nios2-generic board 2010-04-07 3:19 ` Thomas Chou @ 2010-04-07 17:23 ` Ben Warren 0 siblings, 0 replies; 40+ messages in thread From: Ben Warren @ 2010-04-07 17:23 UTC (permalink / raw) To: u-boot On 4/6/2010 8:19 PM, Thomas Chou wrote: > On 04/05/2010 01:36 PM, Ben Warren wrote: >> Hi Thomas, >> >> On 3/19/2010 12:43 AM, Thomas Chou wrote: >>> This is a generic approach to port u-boot for nios2 boards. >>> It uses a new set of device drivers, such as the cfi flash, spi >>> lash, nand flash and new ethernet drivers. >>> >> <snip> >>> +#ifdef CONFIG_CMD_NET >>> +int board_eth_init(bd_t *bis) >>> +{ >>> + int rc = 0; >>> +#ifdef CONFIG_SMC91111 >>> + rc = smc91111_initialize(bis, CONFIG_SMC91111_BASE); >>> +#endif >>> + >>> +#ifdef CONFIG_DRIVER_DM9000 >>> + rc = dm9000_initialize(bis); >>> +#endif >>> + >>> +#ifdef CONFIG_ALTERA_TSE >>> + altera_tse_init(bis, CONFIG_SYS_NUM_TSE_MACS); >>> +#endif >>> + >>> +#ifdef CONFIG_ETHOC >>> + rc = ethoc_initialize(bis, CONFIG_SYS_ETHOC_BASE); >>> +#endif >>> + return rc; >>> +} >> Please clean up the return code handling. The drivers are not >> mutually exclusive. > Hi Ben, > > Does it make sense to return 0 always, as we don't have cpu_eth_init()? > No, it should return the number of interfaces initialized. I realize that the caller doesn't currently do anything with this number, and intend to make a return code of -1 be interpreted as an error, but that's currently not the case. If there's an error in board_eth_init(), return 0 and print an error message. > >> >> <snip> >>> + >>> +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b >>> +#define CONFIG_NETMASK 255.255.255.0 >>> +#define CONFIG_IPADDR 192.168.2.21 >>> +#define CONFIG_SERVERIP 192.168.2.16 >>> + >> Please remove these definitions > OK. > > Best regards, > Thomas regards, Ben ^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch 2010-03-19 7:43 [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 01/28] nios2: add nios2-generic board Thomas Chou @ 2010-03-19 14:41 ` Thomas Chou 2010-03-19 14:55 ` Peter Tyser 1 sibling, 1 reply; 40+ messages in thread From: Thomas Chou @ 2010-03-19 14:41 UTC (permalink / raw) To: u-boot On 03/19/2010 03:43 PM, Thomas Chou wrote: > These patches are for next u-boot release. I udnerstand the merge window is > not opened yet. But there are quite a few things to review, so please > allow me submit them early. > > This is a generic approach to port u-boot for nios2 boards. We try to ease > the porting of a new nios2 design. We will rely on tools generated header > file which contains the devices base address, instead of entering the hex > numbers by hand. > Please disregard these patches. I will resubmit after reorganization. - Thomas ^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch 2010-03-19 14:41 ` [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch Thomas Chou @ 2010-03-19 14:55 ` Peter Tyser 2010-03-19 15:23 ` Thomas Chou 2010-03-19 18:40 ` Wolfgang Denk 0 siblings, 2 replies; 40+ messages in thread From: Peter Tyser @ 2010-03-19 14:55 UTC (permalink / raw) To: u-boot On Fri, 2010-03-19 at 22:41 +0800, Thomas Chou wrote: > On 03/19/2010 03:43 PM, Thomas Chou wrote: > > These patches are for next u-boot release. I udnerstand the merge window is > > not opened yet. But there are quite a few things to review, so please > > allow me submit them early. > > > > This is a generic approach to port u-boot for nios2 boards. We try to ease > > the porting of a new nios2 design. We will rely on tools generated header > > file which contains the devices base address, instead of entering the hex > > numbers by hand. > > > Please disregard these patches. I will resubmit after reorganization. Hi Thomas, When you resubmit, please use the "--no-chain-reply-to" option for git send-email. It will properly thread your patch series to prevent the later patches from creeping off the right side of everyone's email clients. Best, Peter ^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch 2010-03-19 14:55 ` Peter Tyser @ 2010-03-19 15:23 ` Thomas Chou 2010-03-19 18:40 ` Wolfgang Denk 1 sibling, 0 replies; 40+ messages in thread From: Thomas Chou @ 2010-03-19 15:23 UTC (permalink / raw) To: u-boot On 03/19/2010 10:55 PM, Peter Tyser wrote: >> >> Please disregard these patches. I will resubmit after reorganization. >> > Hi Thomas, > When you resubmit, please use the "--no-chain-reply-to" option for git > send-email. It will properly thread your patch series to prevent the > later patches from creeping off the right side of everyone's email > clients. > OK. I added it using git config. Cheers, Thomas ^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch 2010-03-19 14:55 ` Peter Tyser 2010-03-19 15:23 ` Thomas Chou @ 2010-03-19 18:40 ` Wolfgang Denk 2010-03-19 18:56 ` Scott Wood 1 sibling, 1 reply; 40+ messages in thread From: Wolfgang Denk @ 2010-03-19 18:40 UTC (permalink / raw) To: u-boot Dear Peter Tyser, In message <1269010558.3376.5270.camel@localhost.localdomain> you wrote: > > When you resubmit, please use the "--no-chain-reply-to" option for git > send-email. It will properly thread your patch series to prevent the > later patches from creeping off the right side of everyone's email > clients. No, don't! Peter, I strongly disagree here. If your mailer cannot handle (long) threads correctly, then this is your local problem. To me it makes perfect sense that a patch series is threaded - some people forget to number the patches, and quite often patch arrive out of order. It is much easier to have these threded correctly. Thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Time is an illusion perpetrated by the manufacturers of space. ^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch 2010-03-19 18:40 ` Wolfgang Denk @ 2010-03-19 18:56 ` Scott Wood 2010-03-19 19:59 ` Wolfgang Denk 0 siblings, 1 reply; 40+ messages in thread From: Scott Wood @ 2010-03-19 18:56 UTC (permalink / raw) To: u-boot Wolfgang Denk wrote: > Dear Peter Tyser, > > In message <1269010558.3376.5270.camel@localhost.localdomain> you wrote: >> When you resubmit, please use the "--no-chain-reply-to" option for git >> send-email. It will properly thread your patch series to prevent the >> later patches from creeping off the right side of everyone's email >> clients. > > No, don't! > > Peter, I strongly disagree here. If your mailer cannot handle (long) > threads correctly, then this is your local problem. It is not a local problem, it is a common problem. Some people might claim that us not wanting to see HTML on the mailing list is a local problem with our mail clients, too. :-) And I'm not entirely sure how you're proposing that a mail client *should* deal with such a thread. It's a tradeoff between displaying less of the subject text, or breaking the display of the thread structure earlier. Either one is going to be worse for certain inputs -- and given that in an actual discussion the subject doesn't often change, I'd rather see more of the thread structure. Even when they don't go off the right edge, chained patchsets are hard on the eyes IMHO. It's semantically a list, not a (fully unbalanced) tree. I'm used to lists going straight down, not diagonally. > To me it makes perfect sense that a patch series is threaded - some > people forget to number the patches, and quite often patch arrive out > of order. It is much easier to have these threded correctly. So why not insist on people numbering their patches rather than creating a huge reply-to chain? -Scott ^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch 2010-03-19 18:56 ` Scott Wood @ 2010-03-19 19:59 ` Wolfgang Denk 2010-03-19 21:07 ` Peter Tyser 0 siblings, 1 reply; 40+ messages in thread From: Wolfgang Denk @ 2010-03-19 19:59 UTC (permalink / raw) To: u-boot Dear Scott Wood, In message <4BA3C8F8.5090804@freescale.com> you wrote: > > And I'm not entirely sure how you're proposing that a mail client > *should* deal with such a thread. It's a tradeoff between displaying > less of the subject text, or breaking the display of the thread > structure earlier. Either one is going to be worse for certain inputs > -- and given that in an actual discussion the subject doesn't often > change, I'd rather see more of the thread structure. I'm not an expert in the design of MUAs, nor in user interfaces in general. I'm using an ancient MUA myself, which has far fromperfect threading capabilities, and usually I don;t even use a threaded display. But when reviewing patch series, I definitely want to see the threads of a series (and the replies to these postings) properly threaded, which includes the correct sequence of the patches. That means that patch N+1 must be marked as successor of patch N. The thread information may also be essential for any automatic tools that try to process such a thread series. > Even when they don't go off the right edge, chained patchsets are hard > on the eyes IMHO. It's semantically a list, not a (fully unbalanced) > tree. I'm used to lists going straight down, not diagonally. Agreed. But then, for the MUA there is probably no way to decide which message is the next message in the list (that should not get indented), and which is a follow-up to one of the the messages so it _should_ get indented. AFAICT mail headers don't carry that type of information. But "--no-chain-reply-to" means you have NO list of messages at all - just all messages hanging under the first one, without any before-after references. To me, this is les order and thus much worse. > > To me it makes perfect sense that a patch series is threaded - some > > people forget to number the patches, and quite often patch arrive out > > of order. It is much easier to have these threded correctly. > > So why not insist on people numbering their patches rather than creating > a huge reply-to chain? I think we should have _both_. People sometimes forget something - if you have both threading and numbering you still can reconstruct the intended sequence. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Anything free is worth what you pay for it. ^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch 2010-03-19 19:59 ` Wolfgang Denk @ 2010-03-19 21:07 ` Peter Tyser 2010-03-21 20:28 ` Wolfgang Denk 0 siblings, 1 reply; 40+ messages in thread From: Peter Tyser @ 2010-03-19 21:07 UTC (permalink / raw) To: u-boot Hi Wolfgang, > > And I'm not entirely sure how you're proposing that a mail client > > *should* deal with such a thread. It's a tradeoff between displaying > > less of the subject text, or breaking the display of the thread > > structure earlier. Either one is going to be worse for certain inputs > > -- and given that in an actual discussion the subject doesn't often > > change, I'd rather see more of the thread structure. > > I'm not an expert in the design of MUAs, nor in user interfaces in > general. I'm using an ancient MUA myself, which has far fromperfect > threading capabilities, and usually I don;t even use a threaded > display. But when reviewing patch series, I definitely want to see the > threads of a series (and the replies to these postings) properly > threaded, which includes the correct sequence of the patches. That > means that patch N+1 must be marked as successor of patch N. I personally think that looking at a "deep threaded" patch series with lots of responses is much harder to grasp than the "shallow threaded". As a basic example: http://article.gmane.org/gmane.comp.version-control.git/109790 I would guess that the majority of other users prefer the "shallow threaded" style too. <snip> > But then, for the MUA there is probably no way to decide which > message is the next message in the list (that should not get > indented), and which is a follow-up to one of the the messages so it > _should_ get indented. AFAICT mail headers don't carry that type of > information. I'm pretty sure in the --no-chain-reply-to case, git makes sure the email dates increment properly, and no 2 are the same. Thus any sane email client should order them properly when using shallow threading. > > > To me it makes perfect sense that a patch series is threaded - some > > > people forget to number the patches, and quite often patch arrive out > > > of order. It is much easier to have these threded correctly. > > > > So why not insist on people numbering their patches rather than creating > > a huge reply-to chain? > > I think we should have _both_. People sometimes forget something - if > you have both threading and numbering you still can reconstruct the > intended sequence. I believe the default behavior of git has also been changed to --no-chain-reply-to for what its worth. The fact that patch order can be determined by both timestamp and patch title (assuming proper generation) seems sufficient to me to use the --no-chain-reply-to option. Best, Peter ^ permalink raw reply [flat|nested] 40+ messages in thread
* [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch 2010-03-19 21:07 ` Peter Tyser @ 2010-03-21 20:28 ` Wolfgang Denk 0 siblings, 0 replies; 40+ messages in thread From: Wolfgang Denk @ 2010-03-21 20:28 UTC (permalink / raw) To: u-boot Dear Peter, In message <1269032821.7363.27.camel@ptyser-laptop> you wrote: > > I personally think that looking at a "deep threaded" patch series with > lots of responses is much harder to grasp than the "shallow threaded". > As a basic example: > http://article.gmane.org/gmane.comp.version-control.git/109790 Thanks for the link - I was not aware of this discussion. > I would guess that the majority of other users prefer the "shallow > threaded" style too. I can only guess that, too. But I know my own preferences :-) > I'm pretty sure in the --no-chain-reply-to case, git makes sure the > email dates increment properly, and no 2 are the same. Thus any sane > email client should order them properly when using shallow threading. IIRC git-send-email will indeed make sure to have at least second increments. > I believe the default behavior of git has also been changed to > --no-chain-reply-to for what its worth. The fact that patch order can > be determined by both timestamp and patch title (assuming proper > generation) seems sufficient to me to use the --no-chain-reply-to > option. Well, as the default behavior has been changed, it seems I'm overruled anyway, and there is no need to take additional action. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Never worry about theory as long as the machinery does what it's supposed to do. - R. A. Heinlein ^ permalink raw reply [flat|nested] 40+ messages in thread
end of thread, other threads:[~2010-04-07 17:23 UTC | newest] Thread overview: 40+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2010-03-19 7:43 [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 01/28] nios2: add nios2-generic board Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 02/28] cfi flash: add status polling method for amd flash Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 03/28] serial: move altera uart driver to drivers/serial Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 04/28] serial: move altera jtaguart " Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 05/28] serial: move yanu " Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 06/28] spi: add altera spi controller support Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 07/28] net: add opencore 10/100 ethernet mac support Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 08/28] net: add altera triple speeds " Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 09/28] nios2: change asm-nios2/io.h to compatible with nios2 linux Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 10/28] nios2: add asm-nios2/errno.h Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 11/28] nios2: add local_irq_enable/disable to asm-nios2/system.h Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 12/28] nios2: use bitops from linux-2.6 asm-generic Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 13/28] nios2: fix __fswab64 link error with asm-nios2/byteorder.h Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 14/28] nios2: add dma_alloc_coherent with asm-nios2/dma-mapping.h Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 15/28] nios2: add gpio support with asm-nios2/gpio.h Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 16/28] nios2: move timer handler from interrupt.c to timer.c Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 17/28] nios2: define text_base in start.S for linker script Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 18/28] nios2: pass command line and initrd to linux Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 19/28] nios2: board init for eth, no flash, nand and mmc Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 20/28] nios2: fix writel in board/altera/common/epled.c Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 21/28] nios2: add cf ide init and reset handler Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 22/28] nios2: add gpio led driver Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 23/28] nios2: convert ep1c20 board to use cfi flash and spi flash Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 24/28] nios2: convert ep1s10 board to use cfi flash Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 25/28] nios2: convert ep1s40 " Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 26/28] nios2: convert pci5441 " Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 27/28] nios2: convert pk1c20 board to use cfi flash and spi flash Thomas Chou 2010-03-19 7:43 ` [U-Boot] [PATCH 28/28] nios2: add struct stat support in linux/stat.h Thomas Chou 2010-04-05 5:36 ` [U-Boot] [PATCH 01/28] nios2: add nios2-generic board Ben Warren 2010-04-07 3:19 ` Thomas Chou 2010-04-07 17:23 ` Ben Warren 2010-03-19 14:41 ` [U-Boot] [PATCH 00/28] u-boot next: a generic approach for nios2 arch Thomas Chou 2010-03-19 14:55 ` Peter Tyser 2010-03-19 15:23 ` Thomas Chou 2010-03-19 18:40 ` Wolfgang Denk 2010-03-19 18:56 ` Scott Wood 2010-03-19 19:59 ` Wolfgang Denk 2010-03-19 21:07 ` Peter Tyser 2010-03-21 20:28 ` Wolfgang Denk
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