[U-Boot] [PATCH 0/3] Add support for MB86R0x SoCs

[U-Boot] [PATCH 0/3] Add support for MB86R0x SoCs

[Matthias Weisser]

This patchset adds support for MB86R0x SoC familiy from Fujitsu,
its built in lcd controller and a first board using the
MB86R01.

Matthias Weisser (3):
  arm: Add support for MB86R0x SoCs
  video: add support for display controller in MB86R0x SoCs
  arm: Add support for jadecpu board based on MB86R01 SoC

 MAINTAINERS                                  |    4 +
 MAKEALL                                      |    1 +
 Makefile                                     |    3 +
 arch/arm/cpu/arm926ejs/mb86r0x/Makefile      |   47 +++++
 arch/arm/cpu/arm926ejs/mb86r0x/reset.c       |   37 ++++
 arch/arm/cpu/arm926ejs/mb86r0x/timer.c       |  129 ++++++++++++
 arch/arm/include/asm/arch-mb86r0x/hardware.h |   31 +++
 arch/arm/include/asm/arch-mb86r0x/mb86r0x.h  |  170 ++++++++++++++++
 board/syteco/jadecpu/Makefile                |   55 +++++
 board/syteco/jadecpu/config.mk               |    1 +
 board/syteco/jadecpu/jadecpu.c               |  198 ++++++++++++++++++
 board/syteco/jadecpu/lowlevel_init.S         |  279 ++++++++++++++++++++++++++
 common/serial.c                              |    3 +-
 drivers/video/Makefile                       |    1 +
 drivers/video/cfb_console.c                  |    8 +
 drivers/video/mb86r0xgdc.c                   |  194 ++++++++++++++++++
 include/configs/jadecpu.h                    |  189 +++++++++++++++++
 include/serial.h                             |    3 +-
 tools/Makefile                               |    3 +
 tools/logos/syteco.bmp                       |  Bin 0 -> 11414 bytes
 20 files changed, 1354 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/Makefile
 create mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/reset.c
 create mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/timer.c
 create mode 100644 arch/arm/include/asm/arch-mb86r0x/hardware.h
 create mode 100644 arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
 create mode 100644 board/syteco/jadecpu/Makefile
 create mode 100644 board/syteco/jadecpu/config.mk
 create mode 100644 board/syteco/jadecpu/jadecpu.c
 create mode 100644 board/syteco/jadecpu/lowlevel_init.S
 create mode 100644 drivers/video/mb86r0xgdc.c
 create mode 100644 include/configs/jadecpu.h
 create mode 100644 tools/logos/syteco.bmp

[U-Boot] [PATCH 1/3] arm: Add support for MB86R0x SoCs

[Matthias Weisser]

This patch adds support for MB86R0x SoCs from Fujitsu

Signed-off-by: Matthias Weisser <weisserm@arcor.de>
---
 arch/arm/cpu/arm926ejs/mb86r0x/Makefile      |   47 +++++++
 arch/arm/cpu/arm926ejs/mb86r0x/reset.c       |   37 ++++++
 arch/arm/cpu/arm926ejs/mb86r0x/timer.c       |  129 +++++++++++++++++++
 arch/arm/include/asm/arch-mb86r0x/hardware.h |   31 +++++
 arch/arm/include/asm/arch-mb86r0x/mb86r0x.h  |  170 ++++++++++++++++++++++++++
 5 files changed, 414 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/Makefile
 create mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/reset.c
 create mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/timer.c
 create mode 100644 arch/arm/include/asm/arch-mb86r0x/hardware.h
 create mode 100644 arch/arm/include/asm/arch-mb86r0x/mb86r0x.h

diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
new file mode 100644
index 0000000..360f046
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	= timer.o reset.o
+SOBJS	=
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
new file mode 100644
index 0000000..6acb5bb
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * Reset the cpu by setting software reset request bit
+ */
+void reset_cpu(ulong ignored)
+{
+	writel(0x00000002, MB86R0x_CRG_PHYS_BASE + CRG_CRSR);
+	while (1)
+		/* NOP */;
+	/* Never reached */
+}
diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
new file mode 100644
index 0000000..640b80e
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#define TIMER_LOAD_VAL		0xffffffff
+#define TIMER_BASE		MB86R0x_TIMER_PHYS_BASE
+
+#define TIMER_REG_LOAD		(TIMER_BASE + 0)
+#define TIMER_REG_VALUE		(TIMER_BASE + 4)
+#define TIMER_REG_CONTROL	(TIMER_BASE + 8)
+
+#define TIMER_FREQ	(CONFIG_MB86R0x_IOCLK  / 16)
+
+static ulong timestamp;
+static ulong lastdec;
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, TIMER_FREQ);
+
+	return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+	usec *= TIMER_FREQ;
+	do_div(usec, 1000000);
+
+	return usec;
+}
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int timer_init(void)
+{
+	writel(TIMER_LOAD_VAL, TIMER_REG_LOAD);
+	writel(0x86, TIMER_REG_CONTROL);
+
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+unsigned long long get_ticks(void)
+{
+	ulong now = readl(TIMER_REG_VALUE);
+
+	if (now <= lastdec)	/* normal mode (non roll) */
+		/* move stamp forward with absolut diff ticks */
+		timestamp += (lastdec - now);
+	else			/* we have rollover of incrementer */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	lastdec = now;
+	return timestamp;
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	lastdec = readl(TIMER_REG_VALUE);
+	timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	return tick_to_time(get_ticks());
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = usec_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		/*NOP*/;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h
new file mode 100644
index 0000000..d1e57c0
--- /dev/null
+++ b/arch/arm/include/asm/arch-mb86r0x/hardware.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007
+ *
+ * Author : Carsten Schneider, mycable GmbH
+ *          <cs@mycable.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <asm/arch/mb86r0x.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
new file mode 100644
index 0000000..885960f
--- /dev/null
+++ b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2007
+ *
+ * mb86r0x definitions
+ *
+ * Author : Carsten Schneider, mycable GmbH
+ *          <cs@mycable.de>
+ *
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef MB86R0X_H
+#define MB86R0X_H
+
+#ifndef __ASSEMBLY__
+
+/* GPIO registers */
+struct mb86r0x_gpio {
+	uint32_t gpdr0;
+	uint32_t gpdr1;
+	uint32_t gpdr2;
+	uint32_t res;
+	uint32_t gpddr0;
+	uint32_t gpddr1;
+	uint32_t gpddr2;
+};
+
+/* PWM registers */
+struct mb86r0x_pwm {
+	uint32_t bcr;
+	uint32_t tpr;
+	uint32_t pr;
+	uint32_t dr;
+	uint32_t cr;
+	uint32_t sr;
+	uint32_t ccr;
+	uint32_t ir;
+};
+
+/* The mb86r0x chip control (CCNT) register set. */
+struct mb86r0x_ccnt {
+	uint32_t ccid;
+	uint32_t csrst;
+	uint32_t pad0[2];
+	uint32_t cist;
+	uint32_t cistm;
+	uint32_t cgpio_ist;
+	uint32_t cgpio_istm;
+	uint32_t cgpio_ip;
+	uint32_t cgpio_im;
+	uint32_t caxi_bw;
+	uint32_t caxi_ps;
+	uint32_t cmux_md;
+	uint32_t cex_pin_st;
+	uint32_t cmlb;
+	uint32_t pad1[1];
+	uint32_t cusb;
+	uint32_t pad2[41];
+	uint32_t cbsc;
+	uint32_t cdcrc;
+	uint32_t cmsr0;
+	uint32_t cmsr1;
+	uint32_t pad3[2];
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Physical Address Defines
+ */
+#define MB86R0x_DDR2C_PHYS_BASE		0xf3000000
+#define MB86R0x_GDC_PHYS_BASE		0xf1fc0000
+#define MB86R0x_GDC_DISP0_PHYS_BASE	0xf1fd0000
+#define MB86R0x_GDC_DISP1_PHYS_BASE	0xf1fd2000
+#define MB86R0x_CCNT_PHYS_BASE		0xfff42000
+#define MB86R0x_CAN0_PHYS_BASE		0xfff54000
+#define MB86R0x_CAN1_PHYS_BASE		0xfff55000
+#define MB86R0x_I2C0_PHYS_BASE		0xfff56000
+#define MB86R0x_I2C1_PHYS_BASE		0xfff57000
+#define MB86R0x_EHCI_PHYS_BASE		0xfff80000
+#define MB86R0x_OHCI_PHYS_BASE		0xfff81000
+#define MB86R0x_IRC1_PHYS_BASE		0xfffb0000
+#define MB86R0x_MEMC_PHYS_BASE		0xfffc0000
+#define MB86R0x_TIMER_PHYS_BASE		0xfffe0000
+#define MB86R0x_UART0_PHYS_BASE		0xfffe1000
+#define MB86R0x_UART1_PHYS_BASE		0xfffe2000
+#define MB86R0x_IRCE_PHYS_BASE		0xfffe4000
+#define MB86R0x_CRG_PHYS_BASE		0xfffe7000
+#define MB86R0x_IRC0_PHYS_BASE		0xfffe8000
+#define MB86R0x_GPIO_PHYS_BASE		0xfffe9000
+#define MB86R0x_PWM0_PHYS_BASE		0xfff41000
+#define MB86R0x_PWM1_PHYS_BASE		0xfff41100
+
+/*
+ * Offset definitions for DRAM controller
+ */
+#define DDR2C_DRIC		0x00
+#define DDR2C_DRIC1		0x02
+#define DDR2C_DRIC2		0x04
+#define DDR2C_DRCA		0x06
+#define DDR2C_DRCM		0x08
+#define DDR2C_DRCST1		0x0a
+#define DDR2C_DRCST2		0x0c
+#define DDR2C_DRCR		0x0e
+#define DDR2C_DRCF		0x20
+#define DDR2C_DRASR		0x30
+#define DDR2C_DRIMS		0x50
+#define DDR2C_DROS		0x60
+#define DDR2C_DRIBSLI		0x62
+#define DDR2C_DRIBSODT1		0x64
+#define DDR2C_DRIBSOCD		0x66
+#define DDR2C_DRIBSOCD2		0x68
+#define DDR2C_DROABA		0x70
+#define DDR2C_DROBV		0x80
+#define DDR2C_DROBS		0x84
+#define DDR2C_DROBSR1		0x86
+#define DDR2C_DROBSR2		0x88
+#define DDR2C_DROBSR3		0x8a
+#define DDR2C_DROBSR4		0x8c
+#define DDR2C_DRIMR1		0x90
+#define DDR2C_DRIMR2		0x92
+#define DDR2C_DRIMR3		0x94
+#define DDR2C_DRIMR4		0x96
+#define DDR2C_DROISR1		0x98
+#define DDR2C_DROISR2		0x9a
+
+/*
+ * Offset definitions Chip Control Module
+ */
+#define CCNT_CCID		0x00
+#define CCNT_CSRST		0x1c
+#define CCNT_CIST		0x20
+#define CCNT_CISTM		0x24
+#define CCNT_CMUX_MD		0x30
+#define CCNT_CDCRC		0xec
+
+/*
+ * Offset definitions clock reset generator
+ */
+#define CRG_CRPR		0x00
+#define CRG_CRWR		0x08
+#define CRG_CRSR		0x0c
+#define CRG_CRDA		0x10
+#define CRG_CRDB		0x14
+#define CRG_CRHA		0x18
+#define CRG_CRPA		0x1c
+#define CRG_CRPB		0x20
+#define CRG_CRHB		0x24
+#define CRG_CRAM		0x28
+
+#endif /* MB86R0X_H */
-- 
1.5.6.3

[U-Boot] [PATCH 2/3] video: add support for display controller in MB86R0x SoCs

[Matthias Weisser]

This patch adds support for the display controller in
the MB86R0x SoCs.

Signed-off-by: Matthias Weisser <weisserm@arcor.de>
---
 drivers/video/Makefile      |    1 +
 drivers/video/cfb_console.c |    8 ++
 drivers/video/mb86r0xgdc.c  |  194 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 203 insertions(+), 0 deletions(-)
 create mode 100644 drivers/video/mb86r0xgdc.c

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index a5e339a..1a60ec6 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -32,6 +32,7 @@ COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
 COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
 COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o
+COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o
 COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_SED156X) += sed156x.o
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index d1f47c9..4769cdb 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -153,6 +153,14 @@ CONFIG_VIDEO_HW_CURSOR:	     - Uses the hardware cursor capability of the
 #endif
 
 /*****************************************************************************/
+/* Defines for the MB86R0xGDC driver					     */
+/*****************************************************************************/
+#ifdef CONFIG_VIDEO_MB86R0xGDC
+
+#define VIDEO_FB_16BPP_WORD_SWAP
+#endif
+
+/*****************************************************************************/
 /* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc	     */
 /*****************************************************************************/
 #include <video_fb.h>
diff --git a/drivers/video/mb86r0xgdc.c b/drivers/video/mb86r0xgdc.c
new file mode 100644
index 0000000..9022730
--- /dev/null
+++ b/drivers/video/mb86r0xgdc.c
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * mb86r0x.c - Graphic interface for Fujitsu MB86R0x integrated graphic
+ * controller. Derived from mb862xx.c
+ */
+
+#include <common.h>
+
+#include <malloc.h>
+#include <mb862xx.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <video_fb.h>
+#include "videomodes.h"
+
+/*
+ * 4MB (at the end of system RAM)
+ */
+#define VIDEO_MEM_SIZE		0x400000
+
+/*
+ * Graphic Device
+ */
+static GraphicDevice mb86r0x;
+
+void *video_hw_init(void)
+{
+	GraphicDevice *pGD = &mb86r0x;
+	struct ctfb_res_modes var_mode[2];
+	unsigned long *vid;
+	unsigned long div;
+	unsigned long dspBase[2];
+	char *penv;
+	int bpp;
+	int i, j;
+
+	memset(pGD, 0, sizeof(GraphicDevice));
+
+	dspBase[0] = MB86R0x_GDC_DISP0_PHYS_BASE;
+	dspBase[1] = MB86R0x_GDC_DISP1_PHYS_BASE;
+
+	pGD->frameAdrs = MB86R0x_GDC_PHYS_BASE;
+	pGD->gdfIndex = GDF_15BIT_555RGB;
+	pGD->gdfBytesPP = 2;
+
+	pGD->memSize = VIDEO_MEM_SIZE;
+	pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
+	vid = (unsigned long *)pGD->frameAdrs;
+
+	for (i = 0; i < 2; i++) {
+		char varName[32];
+		u32 dcm1, dcm2, dcm3;
+		u16 htp, hdp, hdb, hsp, vtr, vsp, vdp;
+		u8 hsw, vsw;
+		u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1;
+		u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh;
+
+		sprintf(varName, "gs_dsp_%d_param", i);
+
+		penv = getenv(varName);
+		if (penv == NULL) {
+			penv = getenv("videomode");
+			if ((i == 1) || (penv == NULL))
+				continue;
+		}
+
+		bpp = 0;
+		bpp = video_get_params(&var_mode[i], penv);
+
+		if (bpp == 0) {
+			var_mode[i].xres = 640;
+			var_mode[i].yres = 480;
+			var_mode[i].pixclock = 39721;	/* 25MHz */
+			var_mode[i].left_margin = 48;
+			var_mode[i].right_margin = 16;
+			var_mode[i].upper_margin = 33;
+			var_mode[i].lower_margin = 10;
+			var_mode[i].hsync_len = 96;
+			var_mode[i].vsync_len = 2;
+			var_mode[i].sync = 0;
+			var_mode[i].vmode = 0;
+		}
+
+		for (j = 0; j < var_mode[i].xres * var_mode[i].yres / 2; j++)
+			*vid++ = 0xFFFFFFFF;
+
+		pGD->winSizeX = var_mode[i].xres;
+		pGD->winSizeY = var_mode[i].yres;
+
+		/* LCD base clock is ~ 660MHZ. We do calculations in kHz */
+		div = 660000 / (1000000000L / var_mode[i].pixclock);
+		if (div > 64)
+			div = 64;
+		if (0 == div)
+			div = 1;
+
+		dcm1 = (div - 1) << 8;
+		dcm2 = 0x00000000;
+		dcm3 = 0x00000000;
+
+		htp = var_mode[i].left_margin + var_mode[i].xres +
+			var_mode[i].hsync_len + var_mode[i].right_margin;
+		hdp = var_mode[i].xres;
+		hdb = var_mode[i].xres;
+		hsp = var_mode[i].xres + var_mode[i].right_margin;
+		hsw = var_mode[i].hsync_len;
+
+		vsw = var_mode[i].vsync_len;
+		vtr = var_mode[i].upper_margin + var_mode[i].yres +
+			var_mode[i].vsync_len + var_mode[i].lower_margin;
+		vsp = var_mode[i].yres + var_mode[i].lower_margin;
+		vdp = var_mode[i].yres;
+
+		l2m =	((var_mode[i].yres - 1) << (0)) |
+			(((var_mode[i].xres * 2) / 64) << (16)) |
+			((1) << (31));
+
+		l2em = (1 << 0) | (1 << 1);
+
+		l2oa0 = pGD->frameAdrs;
+		l2da0 = pGD->frameAdrs;
+		l2oa1 = pGD->frameAdrs;
+		l2da1 = pGD->frameAdrs;
+		l2dx = 0;
+		l2dy = 0;
+		l2wx = 0;
+		l2wy = 0;
+		l2ww = var_mode[i].xres;
+		l2wh = var_mode[i].yres - 1;
+
+		writel(dcm1, dspBase[i] + GC_DCM1);
+		writel(dcm2, dspBase[i] + GC_DCM2);
+		writel(dcm3, dspBase[i] + GC_DCM3);
+
+		writew(htp, dspBase[i] + GC_HTP);
+		writew(hdp, dspBase[i] + GC_HDP);
+		writew(hdb, dspBase[i] + GC_HDB);
+		writew(hsp, dspBase[i] + GC_HSP);
+		writeb(hsw, dspBase[i] + GC_HSW);
+
+		writeb(vsw, dspBase[i] + GC_VSW);
+		writew(vtr, dspBase[i] + GC_VTR);
+		writew(vsp, dspBase[i] + GC_VSP);
+		writew(vdp, dspBase[i] + GC_VDP);
+
+		writel(l2m, dspBase[i] + GC_L2M);
+		writel(l2em, dspBase[i] + GC_L2EM);
+		writel(l2oa0, dspBase[i] + GC_L2OA0);
+		writel(l2da0, dspBase[i] + GC_L2DA0);
+		writel(l2oa1, dspBase[i] + GC_L2OA1);
+		writel(l2da1, dspBase[i] + GC_L2DA1);
+		writew(l2dx, dspBase[i] + GC_L2DX);
+		writew(l2dy, dspBase[i] + GC_L2DY);
+		writew(l2wx, dspBase[i] + GC_L2WX);
+		writew(l2wy, dspBase[i] + GC_L2WY);
+		writew(l2ww, dspBase[i] + GC_L2WW);
+		writew(l2wh, dspBase[i] + GC_L2WH);
+
+		writel(dcm1 | (1 << 18) | (1 << 31), dspBase[i] + GC_DCM1);
+	}
+
+	return pGD;
+}
+
+/*
+ * Set a RGB color in the LUT
+ */
+void video_set_lut(unsigned int index, unsigned char r,
+					unsigned char g, unsigned char b)
+{
+
+}
-- 
1.5.6.3

[U-Boot] [PATCH 3/3] arm: Add support for jadecpu board based on MB86R01 SoC

[Matthias Weisser]

This patch adds support for the jadecpu board using the
MB86R01 'Jade' SoC from Fujitsu.

Signed-off-by: Matthias Weisser <weisserm@arcor.de>
---
 MAINTAINERS                          |    4 +
 MAKEALL                              |    1 +
 Makefile                             |    3 +
 board/syteco/jadecpu/Makefile        |   55 +++++++
 board/syteco/jadecpu/config.mk       |    1 +
 board/syteco/jadecpu/jadecpu.c       |  198 ++++++++++++++++++++++++
 board/syteco/jadecpu/lowlevel_init.S |  279 ++++++++++++++++++++++++++++++++++
 common/serial.c                      |    3 +-
 include/configs/jadecpu.h            |  189 +++++++++++++++++++++++
 include/serial.h                     |    3 +-
 tools/Makefile                       |    3 +
 tools/logos/syteco.bmp               |  Bin 0 -> 11414 bytes
 12 files changed, 737 insertions(+), 2 deletions(-)
 create mode 100644 board/syteco/jadecpu/Makefile
 create mode 100644 board/syteco/jadecpu/config.mk
 create mode 100644 board/syteco/jadecpu/jadecpu.c
 create mode 100644 board/syteco/jadecpu/lowlevel_init.S
 create mode 100644 include/configs/jadecpu.h
 create mode 100644 tools/logos/syteco.bmp

diff --git a/MAINTAINERS b/MAINTAINERS
index 04c8730..ac0ed62 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -776,6 +776,10 @@ Prafulla Wadaskar <prafulla@marvell.com>
 	rd6281a		ARM926EJS (Kirkwood SoC)
 	sheevaplug	ARM926EJS (Kirkwood SoC)
 
+Matthias Weisser <matthias.weisser@graf-syteco.de>
+
+	jadecpu		ARM926EJS (MB86R01 SoC)
+
 Richard Woodruff <r-woodruff2@ti.com>
 
 	omap2420h4	ARM1136EJS
diff --git a/MAKEALL b/MAKEALL
index fb1f7a3..5ee9678 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -561,6 +561,7 @@ LIST_ARM9="			\
 	edb9315			\
 	edb9315a		\
 	imx27lite		\
+	jadecpu			\
 	lpd7a400		\
 	mv88f6281gtw_ge		\
 	mx1ads			\
diff --git a/Makefile b/Makefile
index 0381c81..4fdd216 100644
--- a/Makefile
+++ b/Makefile
@@ -2834,6 +2834,9 @@ CPU9260_config	:	unconfig
 	@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
 	@$(MKCONFIG) -a cpu9260 arm arm926ejs cpu9260 eukrea at91
 
+jadecpu_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs jadecpu syteco mb86r0x
+
 meesc_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs meesc esd at91
 
diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile
new file mode 100644
index 0000000..87d2234
--- /dev/null
+++ b/board/syteco/jadecpu/Makefile
@@ -0,0 +1,55 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= jadecpu.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk
new file mode 100644
index 0000000..c661f0b
--- /dev/null
+++ b/board/syteco/jadecpu/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x46000000
diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c
new file mode 100644
index 0000000..ecc6742
--- /dev/null
+++ b/board/syteco/jadecpu/jadecpu.c
@@ -0,0 +1,198 @@
+/*
+ * (c) 2010 Graf-Syteco, Matthias Weisser
+ * <weisserm@arcor.de>
+ *
+ * (C) Copyright 2007, mycable GmbH
+ * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/arch/mb86r0x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress(int progress)
+{
+	printf("Boot reached stage %d\n", progress);
+}
+#endif
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
+					MB86R0x_CCNT_PHYS_BASE;
+
+	/* We select mode 0 for group 2 and mode 1 for group 4 */
+	writel(0x00000010, &ccnt->cmux_md);
+
+	gd->flags = 0;
+	gd->bd->bi_arch_number = MACH_TYPE_JADECPU;
+	gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
+
+	icache_enable();
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
+					MB86R0x_GPIO_PHYS_BASE;
+	struct mb86r0x_pwm *pwm;
+	uint32_t in_word;
+	const char *e;
+	const char *s;
+
+#ifdef CONFIG_VIDEO_MB86R0xGDC
+	/* Check if we have valid display settings and turn on power if so */
+	/* Display 0 */
+	if (getenv("gs_dsp_0_param") || getenv("videomode")) {
+		writel(readl(&gpio->gpdr2) | (1 << 3), &gpio->gpdr2);
+
+		e = getenv("gs_dsp_0_pwm");
+		if (e != NULL) {
+			uint32_t freq, init;
+
+			freq = 0;
+			init = 0;
+
+			s = strchr(e, 'f');
+			if (s != NULL)
+				freq = simple_strtol(s + 2, NULL, 0);
+
+			s = strchr(e, 'i');
+			if (s != NULL)
+				init = simple_strtol(s + 2, NULL, 0);
+
+			if (freq > 0) {
+				pwm = (struct mb86r0x_pwm *)
+					MB86R0x_PWM0_PHYS_BASE;
+
+				writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
+					&pwm->bcr);
+				writel(1002, &pwm->tpr);
+				writel(1, &pwm->pr);
+				writel(init * 10 + 1, &pwm->dr);
+				writel(1, &pwm->cr);
+				writel(1, &pwm->sr);
+			}
+		}
+	}
+	writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
+
+	/* Display 1 */
+	if (getenv("gs_dsp_1_param")) {
+		writel(readl(&gpio->gpdr2) | (1 << 4), &gpio->gpdr2);
+
+		e = getenv("gs_dsp_1_pwm");
+		if (e != NULL) {
+			uint32_t freq, init;
+
+			freq = 0;
+			init = 0;
+
+			s = strchr(e, 'f');
+			if (s != NULL)
+				freq = simple_strtol(s + 2, NULL, 0);
+
+			s = strchr(e, 'i');
+			if (s != NULL)
+				init = simple_strtol(s + 2, NULL, 0);
+
+			if (freq > 0) {
+				pwm = (struct mb86r0x_pwm *)
+					MB86R0x_PWM1_PHYS_BASE;
+
+				writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
+					&pwm->bcr);
+				writel(1002, &pwm->tpr);
+				writel(1, &pwm->pr);
+				writel(init * 10 + 1, &pwm->dr);
+				writel(1, &pwm->cr);
+				writel(1, &pwm->sr);
+			}
+		}
+	}
+	writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
+#endif /* CONFIG_VIDEO_MB86R0xGDC */
+
+	/* 5V enable */
+	writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
+	writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
+
+	/* We have special boot options if told by GPIOs */
+	in_word = readl(&gpio->gpdr1);
+
+	if ((in_word & 0xC0) == 0xC0) {
+		setenv("stdin", "serial");
+		setenv("stdout", "serial");
+		setenv("stderr", "serial");
+		setenv("bootdelay", "10");
+	} else if ((in_word & 0xC0) != 0) {
+		setenv("stdout", "vga");
+		setenv("bootcmd", "mw.l 0x40000000 0 1024; usb start;"
+			"fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;"
+			"bootelf 0x40000000; bootelf 0x10080000");
+		setenv("bootdelay", "5");
+	} else {
+		setenv("stdin", "serial");
+		setenv("stdout", "serial");
+		setenv("stderr", "serial");
+		if (getenv("gs_devel")) {
+			setenv("stdout", "vga");
+			setenv("bootdelay", "5");
+		} else {
+			setenv("bootdelay", "0");
+			setenv("bootcmd", "bootelf 0x10080000");
+		}
+	}
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+/*
+ * DRAM configuration
+ */
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
+
diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S
new file mode 100644
index 0000000..f7ba19a
--- /dev/null
+++ b/board/syteco/jadecpu/lowlevel_init.S
@@ -0,0 +1,279 @@
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2007, mycable GmbH
+ * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
+ *
+ * (C) Copyright 2007, mycable GmbH
+ * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
+ *
+ * (C) Copyright 2003, ARM Ltd.
+ * Philippe Robin, <philippe.robin@arm.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software/* you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation/* either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY/* without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program/* if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/macro.h>
+#include <asm/arch/mb86r0x.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+/*
+ * Initialize Clock Reset Generator (CRG)
+ */
+
+	ldr		r0, =MB86R0x_CRG_PHYS_BASE
+
+	/* Not change the initial value that is set by external pin.*/
+1:	ldr		r2, [r0, #CRG_CRPR]	/* Wait for PLLREADY */
+	tst		r2, #0x00000100
+	beq		1b
+
+	/* Set clock gate control */
+	ldr		r1, =0x0000ffff		/* Open */
+	str		r1, [r0, #CRG_CRHA]	/* CRHA: AHB clock */
+	ldr		r1, =0x0000ffff		/* Open */
+	str		r1, [r0, #CRG_CRPA]	/* CRPA: APB-A clock */
+	ldr		r1, =0xfffffffe		/* Close */
+	str		r1, [r0, #CRG_CRPB]	/* CRPA: APB-B clock */
+	ldr		r1, =0x0000ffff		/* Open */
+	str		r1, [r0, #CRG_CRHB]	/* CRHB: ExtAHB clock */
+	ldr		r1, =0xffffffef		/* Open ARM926EJ-S only */
+	str		r1, [r0, #CRG_CRAM]	/* CRAM: ARM core clock */
+
+/*
+ * Initialize External Bus Interface
+ */
+
+	ldr		r0, =MB86R0x_MEMC_PHYS_BASE
+
+	/*
+	 * SRAM/flash _mode_ registers (XCS4 is set by external pin)
+	 * XCS0: Ethernet Controller
+	 * XCS2: not used (?)
+	 * XCS4: Flash
+	 */
+	ldr		r1, =0x00000001		/* XCS0: 16bit */
+	str		r1, [r0, #0x00]
+	ldr		r1, =0x00000001		/* XCS2: 16bit */
+	str		r1, [r0, #0x08]
+	ldr		r1, =0x00000021		/* XCS4: 16bit, */
+	str		r1, [r0, #0x10]
+
+	/* SRAM/flash _timing_ registers (HCLK=83.3/80MHz) */
+	ldr		r1, =0x03061008		/* XCS0: FPGA*/
+	str		r1, [r0, #0x20]
+	ldr		r1, =0x03061008		/* XCS2: Ethernet */
+	str		r1, [r0, #0x28]
+	ldr		r1, =0x03061804		/* XCS4: FLASH ROM */
+	str		r1, [r0, #0x30]
+
+	/* SRAM/flash _area_ registers (address of XCS4 is set by hardware) */
+	ldr		r1, =0x000000c0		/* XCS0: 0x0c000000/1MB */
+	str		r1, [r0, #0x40]
+	ldr		r1, =0x00000020		/* XCS2: 0x02000000/1MB */
+	str		r1, [r0, #0x48]
+	ldr		r1, =0x001f0000		/* XCS4: 32 MB */
+	str		r1, [r0, #0x50]
+
+/*
+ * Initialize DDR2 Controller
+ */
+
+	/* Wait for PLL LOCK up time or more */
+	wait_timer	20
+
+	/*
+	 * (2) Initialize DDRIF
+	 */
+	ldr	r0, =MB86R0x_DDR2C_PHYS_BASE
+	ldr	r1, =0x5555
+	strh	r1, [r0, #DDR2C_DRIMS]
+
+	/*
+	 * (3) Wait for 20MCKPs(120nsec) or more
+	 */
+	wait_timer	20
+
+	/*
+	 * (4) IRESET/IUSRRST release
+	/*
+	ldr	r0, =MB86R0x_CCNT_PHYS_BASE
+	ldr	r1, =0x00000002
+	str	r1, [r0, #CCNT_CDCRC]
+
+	/*
+	 * (5) Wait for 20MCKPs(120nsec) or more
+	 */
+	wait_timer	20
+
+	/*
+	 * (6) IDLLRST release
+	 */
+	ldr	r0, =MB86R0x_CCNT_PHYS_BASE
+	ldr	r1, =0x00000003
+	str	r1, [r0, #CCNT_CDCRC]
+
+	/*
+	 * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
+	 */
+	wait_timer	33536
+
+	/*
+	 * (9) MCKE ON
+	 */
+	ldr	r0, =MB86R0x_DDR2C_PHYS_BASE
+	ldr	r1, =0x003f
+	strh	r1, [r0, #DDR2C_DRIC1]
+	ldr	r1, =0x0000
+	strh	r1, [r0, #DDR2C_DRIC2]
+	ldr	r1, =0xc124		/* 512Mbit DDR2SDRAM x 2 */
+	strh	r1, [r0, #DDR2C_DRCA]
+	ldr	r1, =0xc000
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	/*
+	 * (10) Initialize SDRAM
+	 */
+
+	ldr	r1, =0xc001		/* NOP Command */
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	wait_timer	67			/* 400ns wait */
+
+	ldr	r1, =0x0017		/* PALL Command */
+	strh	r1, [r0, #DDR2C_DRIC1]
+	ldr	r1, =0x0400
+	strh	r1, [r0, #DDR2C_DRIC2]
+	ldr	r1, =0xc001
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	ldr	r1, =0x0006		/* EMR(2) command */
+	strh	r1, [r0, #DDR2C_DRIC1]
+	ldr	r1, =0x0000
+	strh	r1, [r0, #DDR2C_DRIC2]
+	ldr	r1, =0xc001
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	ldr	r1, =0x0007		/* EMR(3) command */
+	strh	r1, [r0, #DDR2C_DRIC1]
+	ldr	r1, =0x0000
+	strh	r1, [r0, #DDR2C_DRIC2]
+	ldr	r1, =0xc001
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	ldr	r1, =0x0005		/* EMR(1) command */
+	strh	r1, [r0, #DDR2C_DRIC1]
+	ldr	r1, =0x0000		/* Extended Mode Register 1 clear*/
+	strh	r1, [r0, #DDR2C_DRIC2]
+	ldr	r1, =0xc001
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	ldr	r1, =0x0004		/* MRS command */
+	strh	r1, [r0, #DDR2C_DRIC1]
+	ldr	r1, =0x0532		/* Mode Register */
+	strh	r1, [r0, #DDR2C_DRIC2]
+	ldr	r1, =0xc001
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	wait_timer 200
+
+	ldr	r1, =0x0017		/* PALL command */
+	strh	r1, [r0, #DDR2C_DRIC1]
+	ldr	r1, =0x0400
+	strh	r1, [r0, #DDR2C_DRIC2]
+	ldr	r1, =0xc001
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	ldr	r1, =0x000f		/* REF command 1 */
+	strh	r1, [r0, #DDR2C_DRIC1]
+	ldr	r1, =0x0000		/* (changed) */
+	strh	r1, [r0, #DDR2C_DRIC2]
+	ldr	r1, =0xc001
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	wait_timer	18			/* 105ns wait */
+
+	ldr	r1, =0x0004		/* MRS command */
+	strh	r1, [r0, #DDR2C_DRIC1]
+	ldr	r1, =0x0432
+	strh	r1, [r0, #DDR2C_DRIC2]
+	ldr	r1, =0xc001
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	wait_timer	200			/* MRS to OCD: 200clock */
+
+	ldr	r1, =0x0005		/* EMR(1) command */
+	strh	r1, [r0, #DDR2C_DRIC1]
+	ldr	r1, =0x0380		/* Extended Mode Register 1 set OCD */
+	strh	r1, [r0, #DDR2C_DRIC2]
+	ldr	r1, =0xc001
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	ldr	r1, =0x0005		/* EMR(1) command */
+	strh	r1, [r0, #DDR2C_DRIC1]
+	/* ldr  r1, =0x0044 */
+	ldr	r1, =0x0002		/* EMR(1) set reduced strength */
+	strh	r1, [r0, #DDR2C_DRIC2]
+	ldr	r1, =0xc001
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	ldr	r1, =0x0032		/* Set BT, AL, CL, BL */
+	strh	r1, [r0, #DDR2C_DRCM]
+
+	ldr	r1, =0x3418		/* Set tRCD, tRAS, tRP, tRC */
+	strh	r1, [r0, #DDR2C_DRCST1]
+
+	/* ldr	r1, =0x2e22 */		/* Set tRFC, tRRD, tWR */
+	ldr	r1, =0x6e32
+	strh	r1, [r0, #DDR2C_DRCST2]
+
+	/* ldr	r1, =0x0051 */		/* Set CNTL, REF_CNT*/
+	ldr	r1, =0x0141		/* (changed) */
+	strh	r1, [r0, #DDR2C_DRCR]
+
+	ldr	r1, =0x0002		/* Set Address FIFO (8 steps) */
+	strh	r1, [r0, #DDR2C_DRCF]
+
+	ldr	r1, =0x0001		/* Enable AXI Cache */
+	strh	r1, [r0, #DDR2C_DRASR]
+
+	/*
+	 * (11) ODT setting
+	 */
+	ldr	r1, =0x0001
+	strh	r1, [r0, #DDR2C_DROBS]
+	ldr	r1, =0x0103		/* ODT auto adjustment on */
+	strh	r1, [r0, #DDR2C_DROABA]
+	ldr	r1, =0x003F		/* Set ODT to on 50/100 Ohm */
+	strh	r1, [r0, #DDR2C_DRIBSODT1]
+
+	/*
+	 * (12) Shift to ODTCONT ON (SDRAM side) and DDR2C usual operation mode
+	 */
+	ldr	r1, =0x0001
+	strh	r1, [r0, #DDR2C_DROS]
+	ldr	r1, =0x4000
+	strh	r1, [r0, #DDR2C_DRIC]
+
+	mov pc, lr
+
diff --git a/common/serial.c b/common/serial.c
index 5f9ffd7..3cc4d23 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -41,7 +41,8 @@ struct serial_device *__default_serial_console (void)
 #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
    || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
    || defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) \
-   || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+   || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
+   || defined(CONFIG_MB86R0x)
 #if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL)
 #if (CONFIG_CONS_INDEX==1)
 	return &eserial1_device;
diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h
new file mode 100644
index 0000000..03641eb
--- /dev/null
+++ b/include/configs/jadecpu.h
@@ -0,0 +1,189 @@
+/*
+ * (C) Copyright 2010
+ * Matthias Weisser <weisserm@arcor.de>
+ *
+ * Configuation settings for the jadecpu board
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MB86R0x
+#define CONFIG_MB86R0x_IOCLK		(41164767)
+#define CONFIG_SYS_HZ			(CONFIG_MB86R0x_IOCLK / 16)
+#define CONFIG_SYS_TIMERBASE	0xfffe0000
+
+#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
+#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
+
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG	1
+#define BOARD_LATE_INIT		1
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * Serial
+ */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE		(-4)
+#define CONFIG_SYS_NS16550_CLK			CONFIG_MB86R0x_IOCLK
+#define CONFIG_SYS_NS16550_COM1			0xfffe1000	/* UART 0 */
+#define CONFIG_SYS_NS16550_COM2			0xfff50000	/* UART 2 */
+#define CONFIG_SYS_NS16550_COM3			0xfff51000	/* UART 3 */
+#define CONFIG_SYS_NS16550_COM4			0xfff43000	/* UART 4 */
+
+#define CONFIG_CONS_INDEX	4
+
+/*
+ * Ethernet
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE	0x02000000
+#define CONFIG_SMC911X_16_BIT
+
+/*
+ * Video
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MB86R0xGDC
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (800*480 + 256*4 + 10*1024)
+#define VIDEO_KBD_INIT_FCT		0
+#define VIDEO_TSTC_FCT			serial_tstc
+#define VIDEO_GETC_FCT			serial_getc
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_CMD_IMI		1
+#define CONFIG_CMD_ELF		1
+#define CONFIG_CMD_PING		1
+#define CONFIG_CMD_DHCP		1
+#define CONFIG_CMD_BMP		1
+#define CONFIG_CMD_USB		1
+#define CONFIG_CMD_FAT		1
+
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* USB */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_REGS_BASE       0xFFF81000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME       "mb86r0x"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS  1
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM		0x40000000	/* Start address of DDRRAM */
+#define PHYS_SDRAM_SIZE	0x08000000	/* 128 megs */
+
+/*
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_FLASH_BASE		0x10000000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00040000)
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SECT_SIZE		(128 * 1024)
+#define CONFIG_ENV_SIZE		(128 * 1024)
+
+/*
+ * CFI FLASH driver setup
+ */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER	1
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1	/* ~10x faster */
+
+#define CONFIG_SYS_LOAD_ADDR		0x40000000	/* load address */
+
+#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM + (512*1024))
+#define CONFIG_SYS_MEMTEST_END		(PHYS_SDRAM + PHYS_SDRAM_SIZE)
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT	"jade> "
+#define CONFIG_SYS_CBSIZE	256
+#define CONFIG_SYS_MAXARGS	16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP	1
+#define CONFIG_CMDLINE_EDITING	1
+
+#define CONFIG_BOOTDELAY	2
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"delaygs"
+#define CONFIG_AUTOBOOT_STOP_STR	"stopgs"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(0x400000 - 0x8000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif	/* __CONFIG_H */
+
diff --git a/include/serial.h b/include/serial.h
index f2638ec..8802193 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -25,7 +25,8 @@ extern struct serial_device * default_serial_console (void);
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \
     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
     defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) || \
-    defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+    defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
+    defined(CONFIG_MB86R0x)
 extern struct serial_device serial0_device;
 extern struct serial_device serial1_device;
 #if defined(CONFIG_SYS_NS16550_SERIAL)
diff --git a/tools/Makefile b/tools/Makefile
index 749d994..b2e73b2 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -118,6 +118,9 @@ endif
 ifeq ($(VENDOR),ronetix)
 LOGO_BMP= logos/ronetix.bmp
 endif
+ifeq ($(VENDOR),syteco)
+LOGO_BMP= logos/syteco.bmp
+endif
 
 # now $(obj) is defined
 HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c))
diff --git a/tools/logos/syteco.bmp b/tools/logos/syteco.bmp
new file mode 100644
index 0000000000000000000000000000000000000000..9a994fe3e3812bdc2d63f7045d2740d931b2a42a
GIT binary patch
literal 11414
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zpTGaTJ70d>ocj*7zwrA7zc=^Q_v1f*zJ*`xcs`%*@pwS<xpm#${eIu-^Dz~e3QPqq
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z0>RTB%VAF#qXYSRB?sP6xgtpp8mxKWY_v`ft;lE&fTC{zc{EXkA}`|*TXPu)+dZQZ
zgA|@|G<1>F8VBm0_P&(XUdBNj6{-<geK6xd-7}#_!8sX@ZYD<%W$HnK1FD!>u)I1x
zeAfRI96^!S>k$<B3>>J)NRItNOh05iELAIfp)pd)w*{-%RbN;>-EZcML*E7Dy$EK2
z$8j8R?b=?CzP9E7ul#}*K<eLK&t!U_dGEEL2fqGb5W%s56gg}Vs-k}7Y>(s!AY~2{
zgq at kJTQ#USJV*tH0RpQ?tSVR84!UwXYWVjRRoIBr5JVzIL=MTiRfCLU2dUx^iU^FJ
z{1KDSt&W3%NQ^#?xSH;Z($MZ;!O at pbG0K9I29A9yiP6K5&8&OnTX<urac$YB3XG_%
zc4_xmAdMW7Ahd0F>0Se*g#-Qz+~i0*OpRzmO&p8Kk#d&nS0HU1i=ju(U3yG{baTYZ
zbK0dnB0zdMFzwrpO1&JUlOuePN-phj2GYk7Fh(fS#St;if{=@D566LV9^}}v+N=(L
v-!AOjQj8HG2a<6m=FVaZmJGf;QwXdp^U*bbS~I1ozV-x>`b|atPencepjJ52

literal 0
HcmV?d00001

-- 
1.5.6.3

[U-Boot] [PATCH 1/3] arm: Add support for MB86R0x SoCs

[Wolfgang Denk]

Dear Matthias Weisser,

In message <1271932257-14618-2-git-send-email-weisserm@arcor.de> you wrote:
> This patch adds support for MB86R0x SoCs from Fujitsu
> 
> Signed-off-by: Matthias Weisser <weisserm@arcor.de>
...
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
...
> +void reset_cpu(ulong ignored)
> +{
> +	writel(0x00000002, MB86R0x_CRG_PHYS_BASE + CRG_CRSR);

Please define some symbolic name for the magic constant 0x00000002

Also, we do not accept code based on a "base + offset" notation.
Please use C structures instead. [Please fix globally.]


> +#define TIMER_LOAD_VAL		0xffffffff
> +#define TIMER_BASE		MB86R0x_TIMER_PHYS_BASE
> +
> +#define TIMER_REG_LOAD		(TIMER_BASE + 0)
> +#define TIMER_REG_VALUE		(TIMER_BASE + 4)
> +#define TIMER_REG_CONTROL	(TIMER_BASE + 8)

Create a proper C struct, please!


> +/*
> + * Offset definitions for DRAM controller
> + */
> +#define DDR2C_DRIC		0x00
> +#define DDR2C_DRIC1		0x02
> +#define DDR2C_DRIC2		0x04
> +#define DDR2C_DRCA		0x06
> +#define DDR2C_DRCM		0x08
> +#define DDR2C_DRCST1		0x0a
> +#define DDR2C_DRCST2		0x0c
> +#define DDR2C_DRCR		0x0e
> +#define DDR2C_DRCF		0x20
> +#define DDR2C_DRASR		0x30
> +#define DDR2C_DRIMS		0x50
> +#define DDR2C_DROS		0x60
> +#define DDR2C_DRIBSLI		0x62
> +#define DDR2C_DRIBSODT1		0x64
> +#define DDR2C_DRIBSOCD		0x66
> +#define DDR2C_DRIBSOCD2		0x68
> +#define DDR2C_DROABA		0x70
> +#define DDR2C_DROBV		0x80
> +#define DDR2C_DROBS		0x84
> +#define DDR2C_DROBSR1		0x86
> +#define DDR2C_DROBSR2		0x88
> +#define DDR2C_DROBSR3		0x8a
> +#define DDR2C_DROBSR4		0x8c
> +#define DDR2C_DRIMR1		0x90
> +#define DDR2C_DRIMR2		0x92
> +#define DDR2C_DRIMR3		0x94
> +#define DDR2C_DRIMR4		0x96
> +#define DDR2C_DROISR1		0x98
> +#define DDR2C_DROISR2		0x9a

C struct, please.

> +/*
> + * Offset definitions Chip Control Module
> + */
> +#define CCNT_CCID		0x00
> +#define CCNT_CSRST		0x1c
> +#define CCNT_CIST		0x20
> +#define CCNT_CISTM		0x24
> +#define CCNT_CMUX_MD		0x30
> +#define CCNT_CDCRC		0xec

Ditto.

> +/*
> + * Offset definitions clock reset generator
> + */
> +#define CRG_CRPR		0x00
> +#define CRG_CRWR		0x08
> +#define CRG_CRSR		0x0c
> +#define CRG_CRDA		0x10
> +#define CRG_CRDB		0x14
> +#define CRG_CRHA		0x18
> +#define CRG_CRPA		0x1c
> +#define CRG_CRPB		0x20
> +#define CRG_CRHB		0x24
> +#define CRG_CRAM		0x28

Ditto.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Consistency requires you to be as ignorant today as you were a  year
ago."                                              - Bernard Berenson

[U-Boot] [PATCH 2/3] video: add support for display controller in MB86R0x SoCs

[Wolfgang Denk]

Dear Matthias Weisser,

In message <1271932257-14618-3-git-send-email-weisserm@arcor.de> you wrote:
> This patch adds support for the display controller in
> the MB86R0x SoCs.
> 
> Signed-off-by: Matthias Weisser <weisserm@arcor.de>
...
> +	pGD->memSize = VIDEO_MEM_SIZE;
> +	pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;

Please pay attention to the global memory map requirements. PRAM might
go first.


> +		writel(dcm1, dspBase[i] + GC_DCM1);
> +		writel(dcm2, dspBase[i] + GC_DCM2);
> +		writel(dcm3, dspBase[i] + GC_DCM3);
> +
> +		writew(htp, dspBase[i] + GC_HTP);
> +		writew(hdp, dspBase[i] + GC_HDP);
> +		writew(hdb, dspBase[i] + GC_HDB);
> +		writew(hsp, dspBase[i] + GC_HSP);
> +		writeb(hsw, dspBase[i] + GC_HSW);
> +
> +		writeb(vsw, dspBase[i] + GC_VSW);
> +		writew(vtr, dspBase[i] + GC_VTR);
> +		writew(vsp, dspBase[i] + GC_VSP);
> +		writew(vdp, dspBase[i] + GC_VDP);
> +
> +		writel(l2m, dspBase[i] + GC_L2M);
> +		writel(l2em, dspBase[i] + GC_L2EM);
> +		writel(l2oa0, dspBase[i] + GC_L2OA0);
> +		writel(l2da0, dspBase[i] + GC_L2DA0);
> +		writel(l2oa1, dspBase[i] + GC_L2OA1);
> +		writel(l2da1, dspBase[i] + GC_L2DA1);
> +		writew(l2dx, dspBase[i] + GC_L2DX);
> +		writew(l2dy, dspBase[i] + GC_L2DY);
> +		writew(l2wx, dspBase[i] + GC_L2WX);
> +		writew(l2wy, dspBase[i] + GC_L2WY);
> +		writew(l2ww, dspBase[i] + GC_L2WW);
> +		writew(l2wh, dspBase[i] + GC_L2WH);
> +
> +		writel(dcm1 | (1 << 18) | (1 << 31), dspBase[i] + GC_DCM1);

Please use a C struct instead.

> +/*
> + * Set a RGB color in the LUT
> + */
> +void video_set_lut(unsigned int index, unsigned char r,
> +					unsigned char g, unsigned char b)
> +{
> +
> +}

Code seems to be missing?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The more we disagree, the more chance there is that at least  one  of
us is right.

[U-Boot] [PATCH 3/3] arm: Add support for jadecpu board based on MB86R01 SoC

[Wolfgang Denk]

Dear Matthias Weisser,

In message <1271932257-14618-4-git-send-email-weisserm@arcor.de> you wrote:
> This patch adds support for the jadecpu board using the
> MB86R01 'Jade' SoC from Fujitsu.
> 
> Signed-off-by: Matthias Weisser <weisserm@arcor.de>
> ---
>  MAINTAINERS                          |    4 +
>  MAKEALL                              |    1 +
>  Makefile                             |    3 +
>  board/syteco/jadecpu/Makefile        |   55 +++++++
>  board/syteco/jadecpu/config.mk       |    1 +
>  board/syteco/jadecpu/jadecpu.c       |  198 ++++++++++++++++++++++++
>  board/syteco/jadecpu/lowlevel_init.S |  279 ++++++++++++++++++++++++++++++++++
>  common/serial.c                      |    3 +-
>  include/configs/jadecpu.h            |  189 +++++++++++++++++++++++
>  include/serial.h                     |    3 +-
>  tools/Makefile                       |    3 +
>  tools/logos/syteco.bmp               |  Bin 0 -> 11414 bytes
>  12 files changed, 737 insertions(+), 2 deletions(-)
>  create mode 100644 board/syteco/jadecpu/Makefile
>  create mode 100644 board/syteco/jadecpu/config.mk
>  create mode 100644 board/syteco/jadecpu/jadecpu.c
>  create mode 100644 board/syteco/jadecpu/lowlevel_init.S
>  create mode 100644 include/configs/jadecpu.h
>  create mode 100644 tools/logos/syteco.bmp
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 04c8730..ac0ed62 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -776,6 +776,10 @@ Prafulla Wadaskar <prafulla@marvell.com>
>  	rd6281a		ARM926EJS (Kirkwood SoC)
>  	sheevaplug	ARM926EJS (Kirkwood SoC)
>  
> +Matthias Weisser <matthias.weisser@graf-syteco.de>
> +
> +	jadecpu		ARM926EJS (MB86R01 SoC)
> +
>  Richard Woodruff <r-woodruff2@ti.com>
>  
>  	omap2420h4	ARM1136EJS
> diff --git a/MAKEALL b/MAKEALL
> index fb1f7a3..5ee9678 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -561,6 +561,7 @@ LIST_ARM9="			\
>  	edb9315			\
>  	edb9315a		\
>  	imx27lite		\
> +	jadecpu			\
>  	lpd7a400		\
>  	mv88f6281gtw_ge		\
>  	mx1ads			\
> diff --git a/Makefile b/Makefile
> index 0381c81..4fdd216 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -2834,6 +2834,9 @@ CPU9260_config	:	unconfig
>  	@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
>  	@$(MKCONFIG) -a cpu9260 arm arm926ejs cpu9260 eukrea at91
>  
> +jadecpu_config	:	unconfig
> +	@$(MKCONFIG) $(@:_config=) arm arm926ejs jadecpu syteco mb86r0x
> +
>  meesc_config	:	unconfig
>  	@$(MKCONFIG) $(@:_config=) arm arm926ejs meesc esd at91
>  
> diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile
> new file mode 100644
> index 0000000..87d2234
> --- /dev/null
> +++ b/board/syteco/jadecpu/Makefile
> @@ -0,0 +1,55 @@
> +#
> +# (C) Copyright 2003-2008
> +# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> +#
> +# (C) Copyright 2008
> +# Stelian Pop <stelian.pop@leadtechdesign.com>
> +# Lead Tech Design <www.leadtechdesign.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> +# MA 02111-1307 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB	= $(obj)lib$(BOARD).a
> +
> +COBJS-y	+= jadecpu.o
> +SOBJS	:= lowlevel_init.o
> +
> +SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
> +OBJS	:= $(addprefix $(obj),$(COBJS-y))
> +SOBJS	:= $(addprefix $(obj),$(SOBJS))
> +
> +$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
> +	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
> +
> +clean:
> +	rm -f $(SOBJS) $(OBJS)
> +
> +distclean:	clean
> +	rm -f $(LIB) core *.bak $(obj).depend
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk
> new file mode 100644
> index 0000000..c661f0b
> --- /dev/null
> +++ b/board/syteco/jadecpu/config.mk
> @@ -0,0 +1 @@
> +TEXT_BASE = 0x46000000
> diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c
> new file mode 100644
> index 0000000..ecc6742
> --- /dev/null
> +++ b/board/syteco/jadecpu/jadecpu.c
> @@ -0,0 +1,198 @@
> +/*
> + * (c) 2010 Graf-Syteco, Matthias Weisser
> + * <weisserm@arcor.de>
> + *
> + * (C) Copyright 2007, mycable GmbH
> + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +#include <asm/io.h>
> +#include <asm/arch/mb86r0x.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#if defined(CONFIG_SHOW_BOOT_PROGRESS)
> +void show_boot_progress(int progress)
> +{
> +	printf("Boot reached stage %d\n", progress);
> +}
> +#endif
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +int board_init(void)
> +{
> +	struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
> +					MB86R0x_CCNT_PHYS_BASE;
> +
> +	/* We select mode 0 for group 2 and mode 1 for group 4 */
> +	writel(0x00000010, &ccnt->cmux_md);
> +
> +	gd->flags = 0;
> +	gd->bd->bi_arch_number = MACH_TYPE_JADECPU;
> +	gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
> +
> +	icache_enable();
> +
> +	return 0;
> +}
> +
> +int board_late_init(void)
> +{
> +	struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
> +					MB86R0x_GPIO_PHYS_BASE;
> +	struct mb86r0x_pwm *pwm;
> +	uint32_t in_word;
> +	const char *e;
> +	const char *s;
> +
> +#ifdef CONFIG_VIDEO_MB86R0xGDC
> +	/* Check if we have valid display settings and turn on power if so */
> +	/* Display 0 */
> +	if (getenv("gs_dsp_0_param") || getenv("videomode")) {
> +		writel(readl(&gpio->gpdr2) | (1 << 3), &gpio->gpdr2);
> +
> +		e = getenv("gs_dsp_0_pwm");
> +		if (e != NULL) {
> +			uint32_t freq, init;
> +
> +			freq = 0;
> +			init = 0;
> +
> +			s = strchr(e, 'f');
> +			if (s != NULL)
> +				freq = simple_strtol(s + 2, NULL, 0);
> +
> +			s = strchr(e, 'i');
> +			if (s != NULL)
> +				init = simple_strtol(s + 2, NULL, 0);
> +
> +			if (freq > 0) {
> +				pwm = (struct mb86r0x_pwm *)
> +					MB86R0x_PWM0_PHYS_BASE;
> +
> +				writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
> +					&pwm->bcr);
> +				writel(1002, &pwm->tpr);
> +				writel(1, &pwm->pr);
> +				writel(init * 10 + 1, &pwm->dr);
> +				writel(1, &pwm->cr);
> +				writel(1, &pwm->sr);
> +			}
> +		}
> +	}
> +	writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
> +
> +	/* Display 1 */
> +	if (getenv("gs_dsp_1_param")) {
> +		writel(readl(&gpio->gpdr2) | (1 << 4), &gpio->gpdr2);
> +
> +		e = getenv("gs_dsp_1_pwm");
> +		if (e != NULL) {
> +			uint32_t freq, init;
> +
> +			freq = 0;
> +			init = 0;
> +
> +			s = strchr(e, 'f');
> +			if (s != NULL)
> +				freq = simple_strtol(s + 2, NULL, 0);
> +
> +			s = strchr(e, 'i');
> +			if (s != NULL)
> +				init = simple_strtol(s + 2, NULL, 0);
> +
> +			if (freq > 0) {
> +				pwm = (struct mb86r0x_pwm *)
> +					MB86R0x_PWM1_PHYS_BASE;
> +
> +				writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
> +					&pwm->bcr);
> +				writel(1002, &pwm->tpr);
> +				writel(1, &pwm->pr);
> +				writel(init * 10 + 1, &pwm->dr);
> +				writel(1, &pwm->cr);
> +				writel(1, &pwm->sr);

Instead of repeating the code, use a function with an argument.

> +	if ((in_word & 0xC0) == 0xC0) {
> +		setenv("stdin", "serial");
> +		setenv("stdout", "serial");
> +		setenv("stderr", "serial");
> +		setenv("bootdelay", "10");
> +	} else if ((in_word & 0xC0) != 0) {
> +		setenv("stdout", "vga");
> +		setenv("bootcmd", "mw.l 0x40000000 0 1024; usb start;"
> +			"fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;"
> +			"bootelf 0x40000000; bootelf 0x10080000");
> +		setenv("bootdelay", "5");

I consider such mandatory settings of behaviour-critical variables as
"bootcmd" and "bootdelay" bad style.  I recommend to use oither
variables instead, and to use these as defaults, so the user still has
a choice to define his own "bootcmd" which does not get overwritten at
each boot.

> diff --git a/common/serial.c b/common/serial.c
> index 5f9ffd7..3cc4d23 100644
> --- a/common/serial.c
> +++ b/common/serial.c
> @@ -41,7 +41,8 @@ struct serial_device *__default_serial_console (void)
>  #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \
>     || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \
>     || defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) \
> -   || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
> +   || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
> +   || defined(CONFIG_MB86R0x)

Please keep list sorted.

...
> +#define CONFIG_MB86R0x
> +#define CONFIG_MB86R0x_IOCLK		(41164767)
> +#define CONFIG_SYS_HZ			(CONFIG_MB86R0x_IOCLK / 16)

NAK.  CONFIG_SYS_HZ must always be 1000.

> diff --git a/include/serial.h b/include/serial.h
> index f2638ec..8802193 100644
> --- a/include/serial.h
> +++ b/include/serial.h
> @@ -25,7 +25,8 @@ extern struct serial_device * default_serial_console (void);
>  #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \
>      defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
>      defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) || \
> -    defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
> +    defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
> +    defined(CONFIG_MB86R0x)

Please keep list sorted.

>  extern struct serial_device serial0_device;
>  extern struct serial_device serial1_device;
>  #if defined(CONFIG_SYS_NS16550_SERIAL)
> diff --git a/tools/Makefile b/tools/Makefile
> index 749d994..b2e73b2 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -118,6 +118,9 @@ endif
>  ifeq ($(VENDOR),ronetix)
>  LOGO_BMP= logos/ronetix.bmp
>  endif
> +ifeq ($(VENDOR),syteco)
> +LOGO_BMP= logos/syteco.bmp
> +endif

Please keep list sorted.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Program maintenance is an entropy-increasing process,  and  even  its
most skilfull execution only delays the subsidence of the system into
unfixable obsolescence.       - Fred Brooks, "The Mythical Man Month"

[U-Boot] [PATCH 2/3] video: add support for display controller in MB86R0x SoCs

[Matthias Weißer]

Am 22.04.2010 14:41, schrieb Wolfgang Denk:
> Dear Matthias Weisser,
>
> In message<1271932257-14618-3-git-send-email-weisserm@arcor.de>  you wrote:
>> This patch adds support for the display controller in
>> the MB86R0x SoCs.
>>
>> Signed-off-by: Matthias Weisser<weisserm@arcor.de>
> ...
>> +	pGD->memSize = VIDEO_MEM_SIZE;
>> +	pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
>
> Please pay attention to the global memory map requirements. PRAM might
> go first.
>
>
>> +		writel(dcm1, dspBase[i] + GC_DCM1);
>> +		writel(dcm2, dspBase[i] + GC_DCM2);
>> +		writel(dcm3, dspBase[i] + GC_DCM3);
>> +
>> +		writew(htp, dspBase[i] + GC_HTP);
>> +		writew(hdp, dspBase[i] + GC_HDP);
>> +		writew(hdb, dspBase[i] + GC_HDB);
>> +		writew(hsp, dspBase[i] + GC_HSP);
>> +		writeb(hsw, dspBase[i] + GC_HSW);
>> +
>> +		writeb(vsw, dspBase[i] + GC_VSW);
>> +		writew(vtr, dspBase[i] + GC_VTR);
>> +		writew(vsp, dspBase[i] + GC_VSP);
>> +		writew(vdp, dspBase[i] + GC_VDP);
>> +
>> +		writel(l2m, dspBase[i] + GC_L2M);
>> +		writel(l2em, dspBase[i] + GC_L2EM);
>> +		writel(l2oa0, dspBase[i] + GC_L2OA0);
>> +		writel(l2da0, dspBase[i] + GC_L2DA0);
>> +		writel(l2oa1, dspBase[i] + GC_L2OA1);
>> +		writel(l2da1, dspBase[i] + GC_L2DA1);
>> +		writew(l2dx, dspBase[i] + GC_L2DX);
>> +		writew(l2dy, dspBase[i] + GC_L2DY);
>> +		writew(l2wx, dspBase[i] + GC_L2WX);
>> +		writew(l2wy, dspBase[i] + GC_L2WY);
>> +		writew(l2ww, dspBase[i] + GC_L2WW);
>> +		writew(l2wh, dspBase[i] + GC_L2WH);
>> +
>> +		writel(dcm1 | (1<<  18) | (1<<  31), dspBase[i] + GC_DCM1);
>
> Please use a C struct instead.

This driver is mainly copied from mb862xx (sharing the header as offsets 
are the same) and that was the approach used there. I will add the 
structures and use them.

>> +/*
>> + * Set a RGB color in the LUT
>> + */
>> +void video_set_lut(unsigned int index, unsigned char r,
>> +					unsigned char g, unsigned char b)
>> +{
>> +
>> +}
>
> Code seems to be missing?

The driver doesn't support palletized color format at the moment but 
removing this function leads to a linker error.

Maybe we should add a config option to disable palletized color format 
or add a weak function somewhere. Maybe Anatolij can comment on this 
issue also.

Regards,
Matthias

[U-Boot] [PATCH 3/3] arm: Add support for jadecpu board based on MB86R01 SoC

[Matthias Weißer]

Am 22.04.2010 14:51, schrieb Wolfgang Denk:
>> +	if ((in_word&  0xC0) == 0xC0) {
>> +		setenv("stdin", "serial");
>> +		setenv("stdout", "serial");
>> +		setenv("stderr", "serial");
>> +		setenv("bootdelay", "10");
>> +	} else if ((in_word&  0xC0) != 0) {
>> +		setenv("stdout", "vga");
>> +		setenv("bootcmd", "mw.l 0x40000000 0 1024; usb start;"
>> +			"fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;"
>> +			"bootelf 0x40000000; bootelf 0x10080000");
>> +		setenv("bootdelay", "5");
>
> I consider such mandatory settings of behaviour-critical variables as
> "bootcmd" and "bootdelay" bad style.  I recommend to use oither
> variables instead, and to use these as defaults, so the user still has
> a choice to define his own "bootcmd" which does not get overwritten at
> each boot.

OK. I think this will be the approach you mentioned:

setenv bootcmd '${gs_bootcmd}'
setenv gs_bootcmd bootelf 0x...

Is the redirection of the console OK as it is done in the above code?

Regards,
Matthias

[U-Boot] [PATCH 3/3] arm: Add support for jadecpu board based on MB86R01 SoC

[Wolfgang Denk]

Dear =?ISO-8859-1?Q?Matthias_Wei=DFer?=,

In message <4BD04C64.20000@arcor.de> you wrote:
> Am 22.04.2010 14:51, schrieb Wolfgang Denk:
> >> +	if ((in_word&  0xC0) == 0xC0) {
> >> +		setenv("stdin", "serial");
> >> +		setenv("stdout", "serial");
> >> +		setenv("stderr", "serial");
> >> +		setenv("bootdelay", "10");
> >> +	} else if ((in_word&  0xC0) != 0) {
> >> +		setenv("stdout", "vga");
> >> +		setenv("bootcmd", "mw.l 0x40000000 0 1024; usb start;"
> >> +			"fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;"
> >> +			"bootelf 0x40000000; bootelf 0x10080000");
> >> +		setenv("bootdelay", "5");
> >
> > I consider such mandatory settings of behaviour-critical variables as
> > "bootcmd" and "bootdelay" bad style.  I recommend to use oither
> > variables instead, and to use these as defaults, so the user still has
> > a choice to define his own "bootcmd" which does not get overwritten at
> > each boot.
> 
> OK. I think this will be the approach you mentioned:
> 
> setenv bootcmd '${gs_bootcmd}'
> setenv gs_bootcmd bootelf 0x...

Right.

> Is the redirection of the console OK as it is done in the above code?

I have to admit that I don't exactly like it (because you will never
know which exact state the system is in, especially if it's not
working - I prefer static states and manual, permanent switching),
but I will not object here.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"An organization dries up if you don't challenge it with growth."
       - Mark Shepherd, former President and CEO of Texas Instruments

[U-Boot] [PATCH 1/3] arm: Add support for MB86R0x SoCs

[Matthias Weißer]

Am 22.04.2010 14:34, schrieb Wolfgang Denk:
 > Dear Matthias Weisser,
 >
 > In message<1271932257-14618-2-git-send-email-weisserm@arcor.de>  you 
wrote:
 >> This patch adds support for MB86R0x SoCs from Fujitsu
 >>
 >> Signed-off-by: Matthias Weisser<weisserm@arcor.de>
 > ...
 >> --- /dev/null
 >> +++ b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c
 > ...
 >> +void reset_cpu(ulong ignored)
 >> +{
 >> +    writel(0x00000002, MB86R0x_CRG_PHYS_BASE + CRG_CRSR);
 >
 > Please define some symbolic name for the magic constant 0x00000002
 >
 > Also, we do not accept code based on a "base + offset" notation.
 > Please use C structures instead. [Please fix globally.]

I will fix this

 >> +#define TIMER_LOAD_VAL        0xffffffff
 >> +#define TIMER_BASE        MB86R0x_TIMER_PHYS_BASE
 >> +
 >> +#define TIMER_REG_LOAD        (TIMER_BASE + 0)
 >> +#define TIMER_REG_VALUE        (TIMER_BASE + 4)
 >> +#define TIMER_REG_CONTROL    (TIMER_BASE + 8)
 >
 > Create a proper C struct, please!

and this

 >> +/*
 >> + * Offset definitions for DRAM controller
 >> + */
 >> +#define DDR2C_DRIC        0x00
 >> +#define DDR2C_DRIC1        0x02
 >> +#define DDR2C_DRIC2        0x04
 >> +#define DDR2C_DRCA        0x06
 >> +#define DDR2C_DRCM        0x08
 >> +#define DDR2C_DRCST1        0x0a
 >> +#define DDR2C_DRCST2        0x0c
 >> +#define DDR2C_DRCR        0x0e
 >> +#define DDR2C_DRCF        0x20
 >> +#define DDR2C_DRASR        0x30
 >> +#define DDR2C_DRIMS        0x50
 >> +#define DDR2C_DROS        0x60
 >> +#define DDR2C_DRIBSLI        0x62
 >> +#define DDR2C_DRIBSODT1        0x64
 >> +#define DDR2C_DRIBSOCD        0x66
 >> +#define DDR2C_DRIBSOCD2        0x68
 >> +#define DDR2C_DROABA        0x70
 >> +#define DDR2C_DROBV        0x80
 >> +#define DDR2C_DROBS        0x84
 >> +#define DDR2C_DROBSR1        0x86
 >> +#define DDR2C_DROBSR2        0x88
 >> +#define DDR2C_DROBSR3        0x8a
 >> +#define DDR2C_DROBSR4        0x8c
 >> +#define DDR2C_DRIMR1        0x90
 >> +#define DDR2C_DRIMR2        0x92
 >> +#define DDR2C_DRIMR3        0x94
 >> +#define DDR2C_DRIMR4        0x96
 >> +#define DDR2C_DROISR1        0x98
 >> +#define DDR2C_DROISR2        0x9a
 >
 > C struct, please.
 >
 >> +/*
 >> + * Offset definitions Chip Control Module
 >> + */
 >> +#define CCNT_CCID        0x00
 >> +#define CCNT_CSRST        0x1c
 >> +#define CCNT_CIST        0x20
 >> +#define CCNT_CISTM        0x24
 >> +#define CCNT_CMUX_MD        0x30
 >> +#define CCNT_CDCRC        0xec
 >
 > Ditto.
 >
 >> +/*
 >> + * Offset definitions clock reset generator
 >> + */
 >> +#define CRG_CRPR        0x00
 >> +#define CRG_CRWR        0x08
 >> +#define CRG_CRSR        0x0c
 >> +#define CRG_CRDA        0x10
 >> +#define CRG_CRDB        0x14
 >> +#define CRG_CRHA        0x18
 >> +#define CRG_CRPA        0x1c
 >> +#define CRG_CRPB        0x20
 >> +#define CRG_CRHB        0x24
 >> +#define CRG_CRAM        0x28
 >
 > Ditto.

Well, the above three modules are used in assembler code only 
(lowlevel_init.S) and I didn't found a way to use C structs here. What 
would be the right approach in this case? Defining all these registers
as absolute addresses?

I have a also a couple of magic values in the mentioned .S file. Do I 
have to move them also to some symbolic constants?

Thanks for the quick review.

Regards,
Matthias

[U-Boot] [PATCH 2/3] video: add support for display controller in MB86R0x SoCs

[Matthias Weißer]

Am 22.04.2010 14:41, schrieb Wolfgang Denk:
> Dear Matthias Weisser,
>
> In message<1271932257-14618-3-git-send-email-weisserm@arcor.de>  you wrote:
>> This patch adds support for the display controller in
>> the MB86R0x SoCs.
>>
>> Signed-off-by: Matthias Weisser<weisserm@arcor.de>
> ...
>> +	pGD->memSize = VIDEO_MEM_SIZE;
>> +	pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
>
> Please pay attention to the global memory map requirements. PRAM might
> go first.

Can you please explain this a bit more in detail? I checked the source 
and README for CONFIG_PRAM and it seems to be reserving some space at 
the end of RAM. But I have only found reference to it in ppc and m68k code.

What would be the correct way to reserve some 2MB-4MB at the end of 
system RAM as a framebuffer for the integrated graphics device?

Thanks in advance

Matthias

[U-Boot] [PATCH 2/3] video: add support for display controller in MB86R0x SoCs

[Wolfgang Denk]

Dear Matthias,

in message <4BD7D5DD.6080701@arcor.de> you wrote:
>
> >> +	pGD->memSize = VIDEO_MEM_SIZE;
> >> +	pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
> >
> > Please pay attention to the global memory map requirements. PRAM might
> > go first.
> 
> Can you please explain this a bit more in detail? I checked the source 
> and README for CONFIG_PRAM and it seems to be reserving some space at 
> the end of RAM. But I have only found reference to it in ppc and m68k code.

Right. But there is a chance that the ARM implementation might be
reworked soon, and then it will follow the documented approach as
well, so better start correctly from the beginning so you don;t run
into conflicts soon.

> What would be the correct way to reserve some 2MB-4MB at the end of 
> system RAM as a framebuffer for the integrated graphics device?

See the PPC implementation for reference.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Shakespeare's Law of Prototyping: (Hamlet III, iv, 156-160)
        O, throw away the worser part of it,
        And live the purer with the other half.

[U-Boot] [PATCH 2/3] video: add support for display controller in MB86R0x SoCs

[Matthias Weißer]

Am 28.04.2010 08:44, schrieb Wolfgang Denk:
> Dear Matthias,

>
> in message<4BD7D5DD.6080701@arcor.de>  you wrote:
>>
>>>> +	pGD->memSize = VIDEO_MEM_SIZE;
>>>> +	pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE;
>>>
>>> Please pay attention to the global memory map requirements. PRAM might
>>> go first.
>>
>> Can you please explain this a bit more in detail? I checked the source
>> and README for CONFIG_PRAM and it seems to be reserving some space at
>> the end of RAM. But I have only found reference to it in ppc and m68k code.
>
> Right. But there is a chance that the ARM implementation might be
> reworked soon, and then it will follow the documented approach as
> well, so better start correctly from the beginning so you don;t run
> into conflicts soon.

I totally agree with you, but...

>> What would be the correct way to reserve some 2MB-4MB at the end of
>> system RAM as a framebuffer for the integrated graphics device?
>
> See the PPC implementation for reference.

I had a look into the PPC code and its clear to me how it is done there. 
But I currently do not see how this can be done on ARM without a couple 
of changes to arch/arm/lib/board.c

Another question regarding the video driver:
I have seen some video drivers in driver/video/... and some are in 
arch/.../cpu/...

What would be the right place for mine? As it is integrated into the SoC 
I tend to put it in arch/arm/cpu/arm/arm926ejs/mb86r0x and not into 
drivers/video. On the other hand there is a imx31 related video driver 
in drivers/video.

Thanks for you patience
Matthias

[U-Boot] [PATCH 2/3] video: add support for display controller in MB86R0x SoCs

[Anatolij Gustschin]

Dear Matthias,

On Thu, 22 Apr 2010 12:30:56 +0200
Matthias Weisser <weisserm@arcor.de> wrote:
...
> diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
> index d1f47c9..4769cdb 100644
> --- a/drivers/video/cfb_console.c
> +++ b/drivers/video/cfb_console.c
> @@ -153,6 +153,14 @@ CONFIG_VIDEO_HW_CURSOR:	     - Uses the hardware cursor capability of the
>  #endif
>  
>  /*****************************************************************************/
> +/* Defines for the MB86R0xGDC driver					     */
> +/*****************************************************************************/
> +#ifdef CONFIG_VIDEO_MB86R0xGDC
> +
> +#define VIDEO_FB_16BPP_WORD_SWAP
> +#endif

Please do not add VIDEO_FB_16BPP_WORD_SWAP #define here.
Add it into your include/configs/jadecpu.h file in the video
related section like other boards do. Thanks!

Best regards,
Anatolij

[U-Boot] [PATCH 2/3] video: add support for display controller in MB86R0x SoCs

[Anatolij Gustschin]

Dear Matthias,

On Thu, 22 Apr 2010 15:03:55 +0200
Matthias Wei?er <weisserm@arcor.de> wrote:
...
> >> +/*
> >> + * Set a RGB color in the LUT
> >> + */
> >> +void video_set_lut(unsigned int index, unsigned char r,
> >> +					unsigned char g, unsigned char b)
> >> +{
> >> +
> >> +}
> >
> > Code seems to be missing?
> 
> The driver doesn't support palletized color format at the moment but 
> removing this function leads to a linker error.
> 
> Maybe we should add a config option to disable palletized color format 
> or add a weak function somewhere. Maybe Anatolij can comment on this 
> issue also.

I will send a patch adding weak default video_set_lut() to cfb_console
driver. You can remove empty function then.

Best regards,
Anatolij

[U-Boot] [PATCH] video: cfb_console: add weak default video_set_lut()

[Anatolij Gustschin]

Do not enforce drivers to provide empty video_set_lut()
if they do not implement indexed color (8 bpp) frame
buffer support. Add default function to the cfb_console
driver and remove empty video_set_lut() functions.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
 arch/powerpc/cpu/mpc512x/diu.c                |   14 --------------
 board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c |    9 ---------
 drivers/video/cfb_console.c                   |   12 ++++++++++++
 drivers/video/sm501.c                         |   13 -------------
 4 files changed, 12 insertions(+), 36 deletions(-)

diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c
index f8d19a0..1cce6a2 100644
--- a/arch/powerpc/cpu/mpc512x/diu.c
+++ b/arch/powerpc/cpu/mpc512x/diu.c
@@ -179,18 +179,4 @@ void *video_hw_init(void)
 	return (void *)pGD;
 }
 
-/**
-  * Set the LUT
-  *
-  * @index: color number
-  * @r: red
-  * @b: blue
-  * @g: green
-  */
-void video_set_lut
-	(unsigned int index, unsigned char r, unsigned char g, unsigned char b)
-{
-	return;
-}
-
 #endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
index 94fb1eb..a7b7f45 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -183,15 +183,6 @@ void *video_hw_init(void)
 	return (void *)pGD;
 }
 
-void video_set_lut (unsigned int index,	/* color number */
-		    unsigned char r,	/* red */
-		    unsigned char g,	/* green */
-		    unsigned char b	/* blue */
-		    )
-{
-	return;
-}
-
 #endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
 
 #endif /* CONFIG_FSL_DIU_FB */
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index dbc6d1d..e89b155 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -803,6 +803,18 @@ static void inline fill_555rgb_pswap(uchar *fb, int x,
 #endif
 
 /*
+ * Do not enforce drivers (or board code) to provide empty
+ * video_set_lut() if they do not support 8 bpp format.
+ * Implement weak default function instead.
+ */
+void __video_set_lut (unsigned int index, unsigned char r,
+		      unsigned char g, unsigned char b)
+{
+}
+void video_set_lut (unsigned int, unsigned char, unsigned char, unsigned char)
+			__attribute__((weak, alias("__video_set_lut")));
+
+/*
  * RLE8 bitmap support
  */
 
diff --git a/drivers/video/sm501.c b/drivers/video/sm501.c
index 283d2d9..8c96316 100644
--- a/drivers/video/sm501.c
+++ b/drivers/video/sm501.c
@@ -131,16 +131,3 @@ void *video_hw_init (void)
 
 	return (&sm501);
 }
-
-/*-----------------------------------------------------------------------------
- * video_set_lut --
- *-----------------------------------------------------------------------------
- */
-void video_set_lut (
-	unsigned int index,           /* color number */
-	unsigned char r,              /* red */
-	unsigned char g,              /* green */
-	unsigned char b               /* blue */
-	)
-{
-}
-- 
1.6.3.3

[U-Boot] [PATCH 3/3] arm: Add support for jadecpu board based on MB86R01 SoC

[Matthias Weißer]

Hallo Wolfgang

Am 22.04.2010 14:51, schrieb Wolfgang Denk:
>>   extern struct serial_device serial0_device;
>>   extern struct serial_device serial1_device;
>>   #if defined(CONFIG_SYS_NS16550_SERIAL)
>> diff --git a/tools/Makefile b/tools/Makefile
>> index 749d994..b2e73b2 100644
>> --- a/tools/Makefile
>> +++ b/tools/Makefile
>> @@ -118,6 +118,9 @@ endif
>>   ifeq ($(VENDOR),ronetix)
>>   LOGO_BMP= logos/ronetix.bmp
>>   endif
>> +ifeq ($(VENDOR),syteco)
>> +LOGO_BMP= logos/syteco.bmp
>> +endif
>
> Please keep list sorted.

S is behind R in alphabet as you know for sure. So, can you explain 
which list should be kept sorted?

Regards,
Matthias

[U-Boot] [PATCH 3/3] arm: Add support for jadecpu board based on MB86R01 SoC

[Wolfgang Denk]

Dear =?ISO-8859-1?Q?Matthias_Wei=DFer?=,

In message <4BDEB5B1.6000200@arcor.de> you wrote:
> 
> Am 22.04.2010 14:51, schrieb Wolfgang Denk:
> >>   extern struct serial_device serial0_device;
> >>   extern struct serial_device serial1_device;
> >>   #if defined(CONFIG_SYS_NS16550_SERIAL)
> >> diff --git a/tools/Makefile b/tools/Makefile
> >> index 749d994..b2e73b2 100644
> >> --- a/tools/Makefile
> >> +++ b/tools/Makefile
> >> @@ -118,6 +118,9 @@ endif
> >>   ifeq ($(VENDOR),ronetix)
> >>   LOGO_BMP= logos/ronetix.bmp
> >>   endif
> >> +ifeq ($(VENDOR),syteco)
> >> +LOGO_BMP= logos/syteco.bmp
> >> +endif
> >
> > Please keep list sorted.
> 
> S is behind R in alphabet as you know for sure. So, can you explain 
> which list should be kept sorted?

Braino on my side. Please ignore this part of the comments.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"One planet is all you get."

[U-Boot] [PATCH 1/3] arm: Add support for MB86R0x SoCs

[Wolfgang Denk]

Dear =?ISO-8859-1?Q?Matthias_Wei=DFer?=,

In message <4BD538D8.2040007@arcor.de> you wrote:
>
>  > C struct, please.
...
>  > Ditto.
...
>  > Ditto.
> 
> Well, the above three modules are used in assembler code only 
> (lowlevel_init.S) and I didn't found a way to use C structs here. What 
> would be the right approach in this case? Defining all these registers
> as absolute addresses?

Mode these definitions (and only these) to a separate asm-offsets.h
header file, please.

Or, if you have the time, adapt the Linux code to auto-generate
asm-offsets.h from normal header files.

> I have a also a couple of magic values in the mentioned .S file. Do I 
> have to move them also to some symbolic constants?

Yes, please.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Man is the best computer we can put aboard a spacecraft ...  and  the
only one that can be mass produced with unskilled labor.
                                                 -- Wernher von Braun

[U-Boot] [PATCH v2] video: cfb_console: add weak default video_set_lut()

[Anatolij Gustschin]

Do not enforce drivers to provide empty video_set_lut()
if they do not implement indexed color (8 bpp) frame
buffer support. Add default function to the cfb_console
driver and remove empty video_set_lut() functions.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
---
v2: - unfortunately in the first patch video_set_lut()
      definition was misplaced and so dependent on
      CONFIG_CMD_BMP or CONFIG_SPLASH_SCREEN. Now,
      make the function definition unconditional.

 arch/powerpc/cpu/mpc512x/diu.c                |   14 --------------
 board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c |    9 ---------
 drivers/video/cfb_console.c                   |   12 ++++++++++++
 drivers/video/sm501.c                         |   13 -------------
 4 files changed, 12 insertions(+), 36 deletions(-)

diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c
index f8d19a0..1cce6a2 100644
--- a/arch/powerpc/cpu/mpc512x/diu.c
+++ b/arch/powerpc/cpu/mpc512x/diu.c
@@ -179,18 +179,4 @@ void *video_hw_init(void)
 	return (void *)pGD;
 }
 
-/**
-  * Set the LUT
-  *
-  * @index: color number
-  * @r: red
-  * @b: blue
-  * @g: green
-  */
-void video_set_lut
-	(unsigned int index, unsigned char r, unsigned char g, unsigned char b)
-{
-	return;
-}
-
 #endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
index 94fb1eb..a7b7f45 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -183,15 +183,6 @@ void *video_hw_init(void)
 	return (void *)pGD;
 }
 
-void video_set_lut (unsigned int index,	/* color number */
-		    unsigned char r,	/* red */
-		    unsigned char g,	/* green */
-		    unsigned char b	/* blue */
-		    )
-{
-	return;
-}
-
 #endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
 
 #endif /* CONFIG_FSL_DIU_FB */
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index d1f47c9..96d52fb 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -749,6 +749,18 @@ void video_puts (const char *s)
 
 /*****************************************************************************/
 
+/*
+ * Do not enforce drivers (or board code) to provide empty
+ * video_set_lut() if they do not support 8 bpp format.
+ * Implement weak default function instead.
+ */
+void __video_set_lut (unsigned int index, unsigned char r,
+		      unsigned char g, unsigned char b)
+{
+}
+void video_set_lut (unsigned int, unsigned char, unsigned char, unsigned char)
+			__attribute__((weak, alias("__video_set_lut")));
+
 #if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
 
 #define FILL_8BIT_332RGB(r,g,b)	{			\
diff --git a/drivers/video/sm501.c b/drivers/video/sm501.c
index 283d2d9..8c96316 100644
--- a/drivers/video/sm501.c
+++ b/drivers/video/sm501.c
@@ -131,16 +131,3 @@ void *video_hw_init (void)
 
 	return (&sm501);
 }
-
-/*-----------------------------------------------------------------------------
- * video_set_lut --
- *-----------------------------------------------------------------------------
- */
-void video_set_lut (
-	unsigned int index,           /* color number */
-	unsigned char r,              /* red */
-	unsigned char g,              /* green */
-	unsigned char b               /* blue */
-	)
-{
-}
-- 
1.6.3.3

[U-Boot] [PATCH v2] video: cfb_console: add weak default video_set_lut()

[Anatolij Gustschin]

On Sat, 12 Jun 2010 10:20:06 +0200
Anatolij Gustschin <agust@denx.de> wrote:

> Do not enforce drivers to provide empty video_set_lut()
> if they do not implement indexed color (8 bpp) frame
> buffer support. Add default function to the cfb_console
> driver and remove empty video_set_lut() functions.
> 
> Signed-off-by: Anatolij Gustschin <agust@denx.de>
> ---
> v2: - unfortunately in the first patch video_set_lut()
>       definition was misplaced and so dependent on
>       CONFIG_CMD_BMP or CONFIG_SPLASH_SCREEN. Now,
>       make the function definition unconditional.
> 
>  arch/powerpc/cpu/mpc512x/diu.c                |   14 --------------
>  board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c |    9 ---------
>  drivers/video/cfb_console.c                   |   12 ++++++++++++
>  drivers/video/sm501.c                         |   13 -------------
>  4 files changed, 12 insertions(+), 36 deletions(-)

Applied to u-boot-video/next.

Anatolij