From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tom Rix Date: Wed, 28 Apr 2010 15:23:31 -0500 Subject: [U-Boot] [PATCH] at91: define matrix registers bit fields In-Reply-To: <1271668996-8854-1-git-send-email-dimov@ronetix.at> References: <1271668996-8854-1-git-send-email-dimov@ronetix.at> Message-ID: <4BD89943.9070600@bumblecow.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Asen Dimov wrote: > Signed-off-by: Asen Dimov > --- > arch/arm/include/asm/arch-at91/at91_matrix.h | 138 ++++++++++++++++++++++++++ > 1 files changed, 138 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/include/asm/arch-at91/at91_matrix.h b/arch/arm/include/asm/arch-at91/at91_matrix.h > index 981ec20..60fd75b 100644 > --- a/arch/arm/include/asm/arch-at91/at91_matrix.h > +++ b/arch/arm/include/asm/arch-at91/at91_matrix.h > @@ -113,4 +113,142 @@ typedef struct at91_matrix { > > #define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008 > > +#if defined(CONFIG_AT91SAM9261) > +/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ > +#define AT91_MATRIX_MCFG_RCB0 (1 << 0) A space after #define is preferred to a 'tab' Fix globally > +/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ > +#define AT91_MATRIX_MCFG_RCB1 (1 << 1) > +#endif > + > +/* Undefined Length Burst Type */ > +#if defiled(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ 'defiled' is a typo Fix globally Running MAKEALL arm will find this type of error. Tom > + defined(CONFIG_AT91SAM9G45) > +#define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000 > +#define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001 > +#define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002 > +#define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003 > +#define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004 > +#endif > +#if defined(CONFIG_AT91SAM9G45) > +#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005 > +#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006 > +#define AT91_MATRIX_MCFG_ULBT_128 0x00000007 > +#endif > + > +/* Default Master Type */ > +#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000 > +#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000 > +#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000 > + > +/* Fixed Index of Default Master */ > +#if defiled(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) > +#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18) > +#elif defiled(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260) > +#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18) > +#endif > + > +/* Maximum Number of Allowed Cycles for a Burst */ > +#if defiled(CONFIG_AT91SAM9G45) > +#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0) > +#elif defiled(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ > + defined(CONFIG_AT91SAM9G45) > +#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0) > +#endif > + > +/* Arbitration Type */ > +#if defiled(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) > +#define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000 > +#define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000 > +#endif > + > +/* Master Remap Control Register */ > +#elif defiled(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ > + defined(CONFIG_AT91SAM9G45) > +/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ > +#define AT91_MATRIX_MRCR_RCB0 (1 << 0) > +/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ > +#define AT91_MATRIX_MRCR_RCB1 (1 << 1) > +#endif > +#if defiled(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) > +#define AT91_MATRIX_MRCR_RCB2 0x00000004 > +#define AT91_MATRIX_MRCR_RCB3 0x00000008 > +#define AT91_MATRIX_MRCR_RCB4 0x00000010 > +#define AT91_MATRIX_MRCR_RCB5 0x00000020 > +#define AT91_MATRIX_MRCR_RCB6 0x00000040 > +#define AT91_MATRIX_MRCR_RCB7 0x00000080 > +#define AT91_MATRIX_MRCR_RCB8 0x00000100 > +#endif > +#if defiled(CONFIG_AT91SAM9G45) > +#define AT91_MATRIX_MRCR_RCB9 0x00000200 > +#define AT91_MATRIX_MRCR_RCB10 0x00000400 > +#define AT91_MATRIX_MRCR_RCB11 0x00000800 > +#endif > + > +/* TCM Configuration Register */ > +#if defiled(CONFIG_AT91SAM9G45) > +/* Size of ITCM enabled memory block */ > +#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 > +#define AT91_MATRIX_TCMR_ITCM_32 0x00000040 > +/* Size of DTCM enabled memory block */ > +#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 > +#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 > +#define AT91_MATRIX_TCMR_DTCM_64 0x00000070 > +/* Wait state TCM register */ > +#define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000 > +#define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800 > +#endif > +#if defiled(CONFIG_AT91SAM9263) > +/* Size of ITCM enabled memory block */ > +#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 > +#define AT91_MATRIX_TCMR_ITCM_16 0x00000005 > +#define AT91_MATRIX_TCMR_ITCM_32 0x00000006 > +/* Size of DTCM enabled memory block */ > +#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 > +#define AT91_MATRIX_TCMR_DTCM_16 0x00000050 > +#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 > +#endif > +#if defiled(CONFIG_AT91SAM9261) > +/* Size of ITCM enabled memory block */ > +#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 > +#define AT91_MATRIX_TCMR_ITCM_16 0x00000005 > +#define AT91_MATRIX_TCMR_ITCM_32 0x00000006 > +#define AT91_MATRIX_TCMR_ITCM_64 0x00000007 > +/* Size of DTCM enabled memory block */ > +#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 > +#define AT91_MATRIX_TCMR_DTCM_16 0x00000050 > +#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 > +#define AT91_MATRIX_TCMR_DTCM_64 0x00000070 > +#endif > + > +#if defiled(CONFIG_AT91SAM9G45) > +/* Video Mode Configuration Register */ > +#define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000 > +#define AT91C_MATRIX_VDEC_SEL_ON 0x00000001 > +/* Write Protect Mode Register */ > +#define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000 > +#define AT91_MATRIX_WPMR_WP_WPEN 0x00000001 > +#define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */ > +/* Write Protect Status Register */ > +#define AT91_MATRIX_WPSR_NO_WPV 0x00000000 > +#define AT91_MATRIX_WPSR_WPV 0x00000001 > +#define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */ > +#endif > + > +/* USB Pad Pull-Up Control Register */ > +#if defiled(CONFIG_AT91SAM9261) > +#define AT91_MATRIX_USBPUCR_PUON 0x40000000 > +#endif > + > +#define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/ > +#define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/ > +#define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/ > +#define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/ > +#define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/ > +#define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/ > +#define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/ > +#define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/ > +#define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */ > +#define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */ > +#define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */ > + > #endif