From mboxrd@z Thu Jan  1 00:00:00 1970
From: Dirk Behme <dirk.behme@googlemail.com>
Date: Mon, 10 May 2010 16:02:40 +0200
Subject: [U-Boot] [PATCH] ARM1136: Fix cache_flush() error and correct
 cpu_init_crit() comments
In-Reply-To: <1273093774-10836-1-git-send-email-gdavis@mvista.com>
References: <1273093774-10836-1-git-send-email-gdavis@mvista.com>
Message-ID: <4BE81200.7070700@googlemail.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

Hi George,

On 05.05.2010 23:09, George G. Davis wrote:
> The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
> instruction which means "Invalidate Both Caches

... Also flushes the branch target cache"

> " when in fact the intent
> is to "Clean and Invalidate Entire Data Cache".

Why don't we have to invalidate/flush the I- and BT-Cache here? I.e. 
why is it sufficient to clean & invalidate the D-Cache here, only, and 
remove the existing I- and BT-Cache invalidation/flushing?

What's about just adding an additional clean of the data cache before 
the 'invalidate all':

+ asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i));  /* clean entire data 
cache */
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));  /* invalidate both 
caches and flush btb */
asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync 
things */

?

Thanks for finding this and best regards

Dirk