From mboxrd@z Thu Jan 1 00:00:00 1970 From: Timur Tabi Date: Fri, 21 May 2010 13:40:28 -0500 Subject: [U-Boot] [PATCH] mpc85xx: add function prototypes for sys and ddr clocks to speed.c In-Reply-To: <4BF6D2BF.20709@freescale.com> References: <1274465254-9002-1-git-send-email-timur@freescale.com> <4BF6CCE6.1080109@freescale.com> <4BF6CE65.5060307@freescale.com> <4BF6D21A.5090502@freescale.com> <4BF6D2BF.20709@freescale.com> Message-ID: <4BF6D39C.8050701@freescale.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Timur Tabi wrote: > Well, you'll have to convince Wolfgang of that, not me. He won't accept my > P1022DS board patch until I fix this "problem". Actually, if you look at Kumar's ICS307 patch, you'll see he fixes this problem for any board that uses the ICS307: > -#ifndef __ASSEMBLY__ > -extern unsigned long calculate_board_sys_clk(unsigned long dummy); > -extern unsigned long calculate_board_ddr_clk(unsigned long dummy); > -/* extern unsigned long get_board_sys_clk(unsigned long dummy); */ > -/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */ > -#endif > -#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */ > -#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */ > +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ > +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ > #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ > -#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq > - from ICS307 instead of switches */ -- Timur Tabi Linux kernel developer at Freescale