[U-Boot] [PATCH] OpenRD: Bring PCIe endpoint out of reset

[U-Boot] [PATCH] OpenRD: Bring PCIe endpoint out of reset

[Tanmay Upadhyay]

There exists PCIe endpoints(not all) that remains in reset state till
PERST# line (A11 on the PCIe connector) is hold low. They come out of
reset only when this line is high.

In case of OpenRD, this line was in tri-state. So, some of the PCIe
devices would never appear on the PCIe bus. This patch makes PERST#
line high while booting to bring such PCIe devices out of reset.

XGI Vollari Z11 GPU and Intel WiFi 4965 are the ones who doesn't care
about this line. Where as Broadcom's BCM970012 won't appear on the PCIe
bus until PERST# is high. With this patch both kinds of device would
appear on the PCIe bus.

Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
Signed-off-by: Dhaval Vasa <dhaval.vasa@einfochips.com>
---
 board/Marvell/openrd_base/openrd_base.h |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/Marvell/openrd_base/openrd_base.h b/board/Marvell/openrd_base/openrd_base.h
index f3daf17..965bd50 100644
--- a/board/Marvell/openrd_base/openrd_base.h
+++ b/board/Marvell/openrd_base/openrd_base.h
@@ -30,10 +30,10 @@
 #ifndef __OPENRD_BASE_H
 #define __OPENRD_BASE_H
 
-#define OPENRD_OE_LOW		(~(1<<28))        /* RS232 / RS485 */
-#define OPENRD_OE_HIGH		(~(1<<2))         /* SD / UART1 */
-#define OPENRD_OE_VAL_LOW		(0)       /* Sel RS232 */
-#define OPENRD_OE_VAL_HIGH		(1 << 2)  /* Sel SD */
+#define OPENRD_OE_LOW		(~((1<<28) | (1<<7)))  /* RS232 / RS485 */
+#define OPENRD_OE_HIGH		(~(1<<2))              /* SD / UART1 */
+#define OPENRD_OE_VAL_LOW		(1<<7)         /* Sel RS232 */
+#define OPENRD_OE_VAL_HIGH		(1 << 2)       /* Sel SD */
 
 /* PHY related */
 #define MV88E1116_LED_FCTRL_REG		10
-- 
1.6.6.1

-- 
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[U-Boot] [PATCH] OpenRD: Bring PCIe endpoint out of reset

[Tanmay Upadhyay]

There exists PCIe endpoints(not all) that remains in reset state till
PERST# line (A11 on the PCIe connector) is hold low. They come out of
reset only when this line is high.

In case of OpenRD, this line was in tri-state. So, some of the PCIe
devices would never appear on the PCIe bus. This patch makes PERST#
line high while booting to bring such PCIe devices out of reset.

XGI Vollari Z11 GPU and Intel WiFi 4965 are the ones who doesn't care
about this line. Where as Broadcom's BCM970012 won't appear on the PCIe
bus until PERST# is high. With this patch both kinds of device would
appear on the PCIe bus.

Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
Signed-off-by: Dhaval Vasa <dhaval.vasa@einfochips.com>
---
 board/Marvell/openrd_base/openrd_base.h |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/Marvell/openrd_base/openrd_base.h b/board/Marvell/openrd_base/openrd_base.h
index f3daf17..bf75fc6 100644
--- a/board/Marvell/openrd_base/openrd_base.h
+++ b/board/Marvell/openrd_base/openrd_base.h
@@ -30,10 +30,10 @@
 #ifndef __OPENRD_BASE_H
 #define __OPENRD_BASE_H
 
-#define OPENRD_OE_LOW		(~(1<<28))        /* RS232 / RS485 */
-#define OPENRD_OE_HIGH		(~(1<<2))         /* SD / UART1 */
-#define OPENRD_OE_VAL_LOW		(0)       /* Sel RS232 */
-#define OPENRD_OE_VAL_HIGH		(1 << 2)  /* Sel SD */
+#define OPENRD_OE_LOW		(~((1<<28) | (1<<7)))  /* RS232 / RS485, PCIe */
+#define OPENRD_OE_HIGH		(~(1<<2))              /* SD / UART1 */
+#define OPENRD_OE_VAL_LOW	(1<<7)        /* Sel RS232, PCIe out of reset */
+#define OPENRD_OE_VAL_HIGH	(1 << 2)      /* Sel SD */
 
 /* PHY related */
 #define MV88E1116_LED_FCTRL_REG		10
-- 
1.6.6.1

-- 
_____________________________________________________________________
Disclaimer: This e-mail message and all attachments transmitted with it
are intended solely for the use of the addressee and may contain legally
privileged and confidential information. If the reader of this message
is not the intended recipient, or an employee or agent responsible for
delivering this message to the intended recipient, you are hereby
notified that any dissemination, distribution, copying, or other use of
this message or its attachments is strictly prohibited. If you have
received this message in error, please notify the sender immediately by
replying to this message and please delete it from your computer. Any
views expressed in this message are those of the individual sender
unless otherwise stated.Company has taken enough precautions to prevent
the spread of viruses. However the company accepts no liability for any
damage caused by any virus transmitted by this email.
_____________________________________________________________________
 

[U-Boot] [PATCH] OpenRD: Bring PCIe endpoint out of reset

[Prafulla Wadaskar]

 

> -----Original Message-----
> From: Tanmay Upadhyay [mailto:tanmay.upadhyay at einfochips.com] 
> Sent: Tuesday, April 20, 2010 11:21 AM
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de; Tanmay Upadhyay; Dhaval Vasa
> Subject: [PATCH] OpenRD: Bring PCIe endpoint out of reset
> 
> There exists PCIe endpoints(not all) that remains in reset state till
> PERST# line (A11 on the PCIe connector) is hold low. They come out of
> reset only when this line is high.
> 
> In case of OpenRD, this line was in tri-state. So, some of the PCIe
> devices would never appear on the PCIe bus. This patch makes PERST#
> line high while booting to bring such PCIe devices out of reset.
> 
> XGI Vollari Z11 GPU and Intel WiFi 4965 are the ones who doesn't care
> about this line. Where as Broadcom's BCM970012 won't appear 
> on the PCIe
> bus until PERST# is high. With this patch both kinds of device would
> appear on the PCIe bus.

Well, there is some problem indeed on OpenRD board regarding PCIe.
This patch did not helped me to test the hardware that I have.

I have Matrox 550 graphics card on PCIe,
I have enabled respective support in the kernel and tried to bring it up.
This patch did not helped me for successful bring up.

Whereas, if I use u-boot from official release (that comes with board) everything works fine.
And that does not have this patch.

So I think this is not perfect resolution for this problem.
We need to dig more into the issue.

Copying Simon..

Regards..
Prafulla . .

[U-Boot] [PATCH] OpenRD: Reset PCIe endpoint while boot-up through PERST#

[Tanmay Upadhyay]

As per PCIe specifications PERST# line (A11 on the PCIe connector)
should be asserted for minimum 100us. PCIe endpoint comes out of
reset when this line is high.

In case of OpenRD, this line was in tri-state. This might prevent
PCIe devices to appear on the PCIe bus. This patch holds PERST#
line low for 100 us and then sets high while booting.

XGI Vollari Z11 GPU and Intel WiFi 4965 works fine without this fix.
Where as Broadcom's BCM970012 doesn't appear on the PCIe bus without
the fix. There might be few other devices as well which require this.

Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
Signed-off-by: Dhaval Vasa <dhaval.vasa@einfochips.com>
---
 board/Marvell/openrd_base/openrd_base.c |    4 ++++
 board/Marvell/openrd_base/openrd_base.h |    8 ++++----
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c
index c00a08a..b76047a 100644
--- a/board/Marvell/openrd_base/openrd_base.c
+++ b/board/Marvell/openrd_base/openrd_base.c
@@ -103,6 +103,10 @@ int board_init(void)
 
 	kirkwood_mpp_conf(kwmpp_config);
 
+	/* PERST# should be asserted for at least 100 us */
+	udelay(100);
+	writel(readl(KW_GPIO0_BASE) | (1<<7), KW_GPIO0_BASE);
+
 	/*
 	 * arch number of board
 	 */
diff --git a/board/Marvell/openrd_base/openrd_base.h b/board/Marvell/openrd_base/openrd_base.h
index f3daf17..1655c12 100644
--- a/board/Marvell/openrd_base/openrd_base.h
+++ b/board/Marvell/openrd_base/openrd_base.h
@@ -30,10 +30,10 @@
 #ifndef __OPENRD_BASE_H
 #define __OPENRD_BASE_H
 
-#define OPENRD_OE_LOW		(~(1<<28))        /* RS232 / RS485 */
-#define OPENRD_OE_HIGH		(~(1<<2))         /* SD / UART1 */
-#define OPENRD_OE_VAL_LOW		(0)       /* Sel RS232 */
-#define OPENRD_OE_VAL_HIGH		(1 << 2)  /* Sel SD */
+#define OPENRD_OE_LOW		(~((1<<28) | (1<<7)))  /* RS232 / RS485, PCIe */
+#define OPENRD_OE_HIGH		(~(1<<2))              /* SD / UART1 */
+#define OPENRD_OE_VAL_LOW	0             /* Sel RS232, PCIe reset */
+#define OPENRD_OE_VAL_HIGH	(1 << 2)      /* Sel SD */
 
 /* PHY related */
 #define MV88E1116_LED_FCTRL_REG		10
-- 
1.6.6.1

[U-Boot] [PATCH] ARM: Kirkwood: Add support for OpenRD-Client & OpenRD-Ultimate

[Tanmay Upadhyay]

This patch modifies existing OpenRD-Base support to deal with all
the three OpenRD boards (OpenRD-Base, OpenRD-Client & OpenRD-Ultimate).

Signed-off-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
---
 Makefile                                |    9 +-
 arch/arm/include/asm/mach-types.h       |   13 ++
 board/Marvell/openrd/Makefile           |   65 +++++++++
 board/Marvell/openrd/config.mk          |   33 +++++
 board/Marvell/openrd/kwbimage.cfg       |  168 +++++++++++++++++++++++
 board/Marvell/openrd/openrd.c           |  180 +++++++++++++++++++++++++
 board/Marvell/openrd/openrd.h           |   67 ++++++++++
 board/Marvell/openrd_base/Makefile      |   56 --------
 board/Marvell/openrd_base/config.mk     |   33 -----
 board/Marvell/openrd_base/kwbimage.cfg  |  168 -----------------------
 board/Marvell/openrd_base/openrd_base.c |  160 ----------------------
 board/Marvell/openrd_base/openrd_base.h |   46 -------
 include/configs/openrd_client.h         |  219 +++++++++++++++++++++++++++++++
 include/configs/openrd_ultimate.h       |  219 +++++++++++++++++++++++++++++++
 14 files changed, 972 insertions(+), 464 deletions(-)
 create mode 100644 board/Marvell/openrd/Makefile
 create mode 100644 board/Marvell/openrd/config.mk
 create mode 100644 board/Marvell/openrd/kwbimage.cfg
 create mode 100644 board/Marvell/openrd/openrd.c
 create mode 100644 board/Marvell/openrd/openrd.h
 delete mode 100644 board/Marvell/openrd_base/Makefile
 delete mode 100644 board/Marvell/openrd_base/config.mk
 delete mode 100644 board/Marvell/openrd_base/kwbimage.cfg
 delete mode 100644 board/Marvell/openrd_base/openrd_base.c
 delete mode 100644 board/Marvell/openrd_base/openrd_base.h
 create mode 100644 include/configs/openrd_client.h
 create mode 100644 include/configs/openrd_ultimate.h

diff --git a/Makefile b/Makefile
index c26e491..f12214b 100644
--- a/Makefile
+++ b/Makefile
@@ -3007,8 +3007,15 @@ omap1610h2_cs_autoboot_config:	unconfig
 omap5912osk_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk ti omap
 
+openrd_ultimate_config \
+openrd_client_config \
 openrd_base_config: unconfig
-	@$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) Marvell kirkwood
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs openrd Marvell kirkwood
+ifneq ($(SRCTREE),$(OBJTREE))
+	@echo "VARIANT= $(@:_config=)" >> $(OBJTREE)/include/config.mk
+else
+	@echo "VARIANT= $(@:_config=)" >> ./include/config.mk
+endif
 
 xtract_omap730p2 = $(subst _cs0boot,,$(subst _cs3boot,, $(subst _config,,$1)))
 
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index 940d814..19114b0 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -2862,6 +2862,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_MATRIX518            2879
 #define MACH_TYPE_TINY_GURNARD         2880
 #define MACH_TYPE_SPEAR1310            2881
+#define MACH_TYPE_OPENRD_ULTIMATE      2884
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -37063,6 +37064,18 @@ extern unsigned int __machine_arch_type;
 # define machine_is_spear1310()	(0)
 #endif
 
+#ifdef CONFIG_MACH_OPENRD_ULTIMATE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OPENRD_ULTIMATE
+# endif
+# define machine_is_openrd_ultimate()	(machine_arch_type == MACH_TYPE_OPENRD_ULTIMATE)
+#else
+# define machine_is_openrd_ultimate()	(0)
+#endif
+
 /*
  * These have not yet been registered
  */
diff --git a/board/Marvell/openrd/Makefile b/board/Marvell/openrd/Makefile
new file mode 100644
index 0000000..96328e7
--- /dev/null
+++ b/board/Marvell/openrd/Makefile
@@ -0,0 +1,65 @@
+#
+# (C) Copyright 2009
+# Net Insight <www.netinsight.net>
+# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+#
+# Based on sheevaplug:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+# Get the board variant (base/client/ultimate) from the .mk file
+ifneq ($(SRCTREE),$(OBJTREE))
+include $(OBJTREE)/include/config.mk
+else
+include $(TOPDIR)/include/config.mk
+endif
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= openrd.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+CFLAGS  += -D$(VARIANT)
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/openrd/config.mk b/board/Marvell/openrd/config.mk
new file mode 100644
index 0000000..8ae355e
--- /dev/null
+++ b/board/Marvell/openrd/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2009
+# Net Insight <www.netinsight.net>
+# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+#
+# Based on sheevaplug:
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x00600000
+
+# Kirkwood Boot Image configuration file
+KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/openrd/kwbimage.cfg b/board/Marvell/openrd/kwbimage.cfg
new file mode 100644
index 0000000..757eb28
--- /dev/null
+++ b/board/Marvell/openrd/kwbimage.cfg
@@ -0,0 +1,168 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM	nand
+NAND_ECC_MODE	default
+NAND_PAGE_SIZE	0x0800
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000c30	# DDR Configuration register
+# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
+# bit 4:    0=addr/cmd in smame cycle
+# bit 5:    0=clk is driven during self refresh, we don't care for APX
+# bit 6:    0=use recommended falling edge of clk for addr/cmd
+# bit14:    0=input buffer always powered up
+# bit18:    1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
+# bit30-28: 3 required
+# bit31:    0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
+# bit3-0:   TRAS lsbs
+# bit7-4:   TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:    TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
+# bit6-0:   TRFC
+# bit8-7:   TR2R
+# bit10-9:  TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+DATA 0xFFD01410 0x000000cc	#  DDR Address Control
+# bit1-0:   00, Cs0width=x8
+# bit3-2:   11, Cs0size=1Gb
+# bit5-4:   00, Cs1width=x8
+# bit7-6:   11, Cs1size=1Gb
+# bit9-8:   00, Cs2width=nonexistent
+# bit11-10: 00, Cs2size =nonexistent
+# bit13-12: 00, Cs3width=nonexistent
+# bit15-14: 00, Cs3size =nonexistent
+# bit16:    0,  Cs0AddrSel
+# bit17:    0,  Cs1AddrSel
+# bit18:    0,  Cs2AddrSel
+# bit19:    0,  Cs3AddrSel
+# bit31-20: 0 required
+
+DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
+# bit0:    0,  OpenPage enabled
+# bit31-1: 0 required
+
+DATA 0xFFD01418 0x00000000	#  DDR Operation
+# bit3-0:   0x0, DDR cmd
+# bit31-4:  0 required
+
+DATA 0xFFD0141C 0x00000C52	#  DDR Mode
+# bit2-0:   2, BurstLen=2 required
+# bit3:     0, BurstType=0 required
+# bit6-4:   4, CL=5
+# bit7:     0, TestMode=0 normal
+# bit8:     0, DLL reset=0 normal
+# bit11-9:  6, auto-precharge write recovery ????????????
+# bit12:    0, PD must be zero
+# bit31-13: 0 required
+
+DATA 0xFFD01420 0x00000042	#  DDR Extended Mode
+# bit0:    0,  DDR DLL enabled
+# bit1:    1,  DDR drive strength reduced
+# bit2:    0,  DDR ODT control lsd (disabled)
+# bit5-3:  000, required
+# bit6:    1,  DDR ODT control msb, (disabled)
+# bit9-7:  000, required
+# bit10:   0,  differential DQS enabled
+# bit11:   0, required
+# bit12:   0, DDR output buffer enabled
+# bit31-13: 0 required
+
+DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
+# bit2-0:  111, required
+# bit3  :  1  , MBUS Burst Chop disabled
+# bit6-4:  111, required
+# bit7  :  0
+# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
+# bit9  :  0  , no half clock cycle addition to dataout
+# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
+# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
+# bit15-12: 1111 required
+# bit31-16: 0    required
+
+DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
+DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
+
+DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
+DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
+# bit0:    1,  Window enabled
+# bit1:    0,  Write Protect disabled
+# bit3-2:  00, CS0 hit selected
+# bit23-4: ones, required
+# bit31-24: 0x0F, Size (i.e. 256MB)
+
+DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
+DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
+
+DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
+DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
+
+DATA 0xFFD01494 0x00120012	#  DDR ODT Control (Low)
+# bit3-0:   0010, (read) M_ODT[0] is asserted during read from DRAM CS1
+# bit7-4:   0001, (read) M_ODT[1] is asserted during read from DRAM CS0
+# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
+# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
+DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
+
+DATA 0xFFD0149C 0x0000E40f	# CPU ODT Control
+# bit3-0:    1111, internal ODT is asserted during read from DRAM bank 0-3
+# bit11-10:    01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
+# bit13-12:    10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
+# bit14:        1, M_STARTBURST_IN ODT: Enabled
+# bit15:        1, DDR IO ODT Unit: Use ODT block
+DATA 0xFFD01480 0x00000001	# DDR Initialization Control
+#bit0=1, enable DDR init upon this register write
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c
new file mode 100644
index 0000000..0630947
--- /dev/null
+++ b/board/Marvell/openrd/openrd.c
@@ -0,0 +1,180 @@
+/*
+ * Modified Simon's work to deal with all the three variants of
+ * OpenRD boards (OpenRD-Base, OpenRD-Client & OpenRD-Ultimate)
+ *
+ * eInfochips <www.einfochips.com>
+ * Modified-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
+ *
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.c:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/kirkwood.h>
+#include <asm/arch/mpp.h>
+#include "openrd.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	/*
+	 * default gpio configuration
+	 * There are maximum 64 gpios controlled through 2 sets of registers
+	 * the  below configuration configures mainly initial LED status
+	 */
+	kw_config_gpio(OPENRD_OE_VAL_LOW,
+			OPENRD_OE_VAL_HIGH,
+			OPENRD_OE_LOW, OPENRD_OE_HIGH);
+
+	/* Multi-Purpose Pins Functionality configuration */
+	u32 kwmpp_config[] = {
+		MPP0_NF_IO2,
+		MPP1_NF_IO3,
+		MPP2_NF_IO4,
+		MPP3_NF_IO5,
+		MPP4_NF_IO6,
+		MPP5_NF_IO7,
+		MPP6_SYSRST_OUTn,
+		MPP7_GPO,
+		MPP8_TW_SDA,
+		MPP9_TW_SCK,
+		MPP10_UART0_TXD,
+		MPP11_UART0_RXD,
+		MPP12_SD_CLK,
+		MPP13_SD_CMD, /* Alt UART1_TXD */
+		MPP14_SD_D0,  /* Alt UART1_RXD */
+		MPP15_SD_D1,
+		MPP16_SD_D2,
+		MPP17_SD_D3,
+		MPP18_NF_IO0,
+		MPP19_NF_IO1,
+		MPP20_GE1_0,
+		MPP21_GE1_1,
+		MPP22_GE1_2,
+		MPP23_GE1_3,
+		MPP24_GE1_4,
+		MPP25_GE1_5,
+		MPP26_GE1_6,
+		MPP27_GE1_7,
+		MPP28_GPIO,
+		MPP29_TSMP9,
+		MPP30_GE1_10,
+		MPP31_GE1_11,
+		MPP32_GE1_12,
+		MPP33_GE1_13,
+		MPP34_GPIO,   /* UART1 / SD sel */
+		MPP35_TDM_CH0_TX_QL,
+		MPP36_TDM_SPI_CS1,
+		MPP37_TDM_CH2_TX_QL,
+		MPP38_TDM_CH2_RX_QL,
+		MPP39_AUDIO_I2SBCLK,
+		MPP40_AUDIO_I2SDO,
+		MPP41_AUDIO_I2SLRC,
+		MPP42_AUDIO_I2SMCLK,
+		MPP43_AUDIO_I2SDI,
+		MPP44_AUDIO_EXTCLK,
+		MPP45_TDM_PCLK,
+		MPP46_TDM_FS,
+		MPP47_TDM_DRX,
+		MPP48_TDM_DTX,
+		MPP49_TDM_CH0_RX_QL,
+		0
+	};
+
+	kirkwood_mpp_conf(kwmpp_config);
+
+	/*
+	 * arch number of board
+	 */
+	gd->bd->bi_arch_number = MACH_TYPE_OPENRD;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
+	return 0;
+}
+
+int dram_init(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
+		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
+	}
+	return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and enable MV88E1116/MV88E1121 PHY */
+void mv_phy_init(char *name)
+{
+	u16 reg;
+	u16 devadr;
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n", __func__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, PGADR_REG, 2);
+	miiphy_read(name, devadr, MAC_CTRL_REG, &reg);
+	reg |= (RGMII_RXTM_CTRL | RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, PGADR_REG, 0);
+
+	/* reset the phy */
+	if (!miiphy_reset(name, devadr))
+		printf("%s Initialized on %s\n", PHY_NO, name);
+}
+
+void reset_phy(void)
+{
+	mv_phy_init("egiga0");
+
+#ifdef openrd_client
+	/* Kirkwood ethernet driver is written with the assumption that in case
+	 * of multiple PHYs, their addresses are consecutive. But unfortunately
+	 * in case of OpenRD-Client, PHY addresses are not consecutive.*/
+	miiphy_write("egiga1", 0xEE, 0xEE, 24);
+#endif
+
+#if defined(openrd_client) || defined(openrd_ultimate)
+	/* configure and initialize both PHY's */
+	mv_phy_init("egiga1");
+#endif
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/openrd/openrd.h b/board/Marvell/openrd/openrd.h
new file mode 100644
index 0000000..8b0cbf8
--- /dev/null
+++ b/board/Marvell/openrd/openrd.h
@@ -0,0 +1,67 @@
+/*
+ * Modified Simon's work to deal with all the three variants of
+ * OpenRD boards (OpenRD-Base, OpenRD-Client & OpenRD-Ultimate)
+ *
+ * eInfochips <www.einfochips.com>
+ * Modified-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
+ *
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __OPENRD_H
+#define __OPENRD_H
+
+#define OPENRD_OE_LOW		(~(1<<28))        /* RS232 / RS485 */
+#define OPENRD_OE_HIGH		(~(1<<2))         /* SD / UART1 */
+#define OPENRD_OE_VAL_LOW		(0)       /* Sel RS232 */
+#define OPENRD_OE_VAL_HIGH		(1 << 2)  /* Sel SD */
+
+/* PHY related */
+#define MAC_CTRL_REG		21
+#define PGADR_REG		22
+#define RGMII_TXTM_CTRL		(1 << 4)
+#define RGMII_RXTM_CTRL		(1 << 5)
+
+#ifdef openrd_base
+#define MACH_TYPE_OPENRD MACH_TYPE_OPENRD_BASE
+#endif
+
+#ifdef openrd_client
+#define MACH_TYPE_OPENRD MACH_TYPE_OPENRD_CLIENT
+#endif
+
+#ifdef openrd_ultimate
+#define MACH_TYPE_OPENRD MACH_TYPE_OPENRD_ULTIMATE
+/* OpenRD-Ultimate uses 88E1121 PHY */
+#define PHY_NO          "88E1121"
+#else
+/* OpenRD-Base & OpenRD-Client uses 88E1116 PHY */
+#define PHY_NO          "88E1116"
+#endif
+
+#endif /* __OPENRD_H */
diff --git a/board/Marvell/openrd_base/Makefile b/board/Marvell/openrd_base/Makefile
deleted file mode 100644
index 3ef0b9b..0000000
--- a/board/Marvell/openrd_base/Makefile
+++ /dev/null
@@ -1,56 +0,0 @@
-#
-# (C) Copyright 2009
-# Net Insight <www.netinsight.net>
-# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
-#
-# Based on sheevaplug:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS	:= openrd_base.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/Marvell/openrd_base/config.mk b/board/Marvell/openrd_base/config.mk
deleted file mode 100644
index 8ae355e..0000000
--- a/board/Marvell/openrd_base/config.mk
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2009
-# Net Insight <www.netinsight.net>
-# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
-#
-# Based on sheevaplug:
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-TEXT_BASE = 0x00600000
-
-# Kirkwood Boot Image configuration file
-KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
diff --git a/board/Marvell/openrd_base/kwbimage.cfg b/board/Marvell/openrd_base/kwbimage.cfg
deleted file mode 100644
index 757eb28..0000000
--- a/board/Marvell/openrd_base/kwbimage.cfg
+++ /dev/null
@@ -1,168 +0,0 @@
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-# Refer docs/README.kwimage for more details about how-to configure
-# and create kirkwood boot image
-#
-
-# Boot Media configurations
-BOOT_FROM	nand
-NAND_ECC_MODE	default
-NAND_PAGE_SIZE	0x0800
-
-# SOC registers configuration using bootrom header extension
-# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
-
-# Configure RGMII-0 interface pad voltage to 1.8V
-DATA 0xFFD100e0 0x1b1b1b9b
-
-#Dram initalization for SINGLE x16 CL=5 @ 400MHz
-DATA 0xFFD01400 0x43000c30	# DDR Configuration register
-# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
-# bit23-14: zero
-# bit24: 1= enable exit self refresh mode on DDR access
-# bit25: 1 required
-# bit29-26: zero
-# bit31-30: 01
-
-DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
-# bit 4:    0=addr/cmd in smame cycle
-# bit 5:    0=clk is driven during self refresh, we don't care for APX
-# bit 6:    0=use recommended falling edge of clk for addr/cmd
-# bit14:    0=input buffer always powered up
-# bit18:    1=cpu lock transaction enabled
-# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
-# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
-# bit30-28: 3 required
-# bit31:    0=no additional STARTBURST delay
-
-DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
-# bit3-0:   TRAS lsbs
-# bit7-4:   TRCD
-# bit11- 8: TRP
-# bit15-12: TWR
-# bit19-16: TWTR
-# bit20:    TRAS msb
-# bit23-21: 0x0
-# bit27-24: TRRD
-# bit31-28: TRTP
-
-DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
-# bit6-0:   TRFC
-# bit8-7:   TR2R
-# bit10-9:  TR2W
-# bit12-11: TW2W
-# bit31-13: zero required
-
-DATA 0xFFD01410 0x000000cc	#  DDR Address Control
-# bit1-0:   00, Cs0width=x8
-# bit3-2:   11, Cs0size=1Gb
-# bit5-4:   00, Cs1width=x8
-# bit7-6:   11, Cs1size=1Gb
-# bit9-8:   00, Cs2width=nonexistent
-# bit11-10: 00, Cs2size =nonexistent
-# bit13-12: 00, Cs3width=nonexistent
-# bit15-14: 00, Cs3size =nonexistent
-# bit16:    0,  Cs0AddrSel
-# bit17:    0,  Cs1AddrSel
-# bit18:    0,  Cs2AddrSel
-# bit19:    0,  Cs3AddrSel
-# bit31-20: 0 required
-
-DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
-# bit0:    0,  OpenPage enabled
-# bit31-1: 0 required
-
-DATA 0xFFD01418 0x00000000	#  DDR Operation
-# bit3-0:   0x0, DDR cmd
-# bit31-4:  0 required
-
-DATA 0xFFD0141C 0x00000C52	#  DDR Mode
-# bit2-0:   2, BurstLen=2 required
-# bit3:     0, BurstType=0 required
-# bit6-4:   4, CL=5
-# bit7:     0, TestMode=0 normal
-# bit8:     0, DLL reset=0 normal
-# bit11-9:  6, auto-precharge write recovery ????????????
-# bit12:    0, PD must be zero
-# bit31-13: 0 required
-
-DATA 0xFFD01420 0x00000042	#  DDR Extended Mode
-# bit0:    0,  DDR DLL enabled
-# bit1:    1,  DDR drive strength reduced
-# bit2:    0,  DDR ODT control lsd (disabled)
-# bit5-3:  000, required
-# bit6:    1,  DDR ODT control msb, (disabled)
-# bit9-7:  000, required
-# bit10:   0,  differential DQS enabled
-# bit11:   0, required
-# bit12:   0, DDR output buffer enabled
-# bit31-13: 0 required
-
-DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
-# bit2-0:  111, required
-# bit3  :  1  , MBUS Burst Chop disabled
-# bit6-4:  111, required
-# bit7  :  0
-# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
-# bit9  :  0  , no half clock cycle addition to dataout
-# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
-# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
-# bit15-12: 1111 required
-# bit31-16: 0    required
-
-DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
-DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)
-
-DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
-DATA 0xFFD01504 0x0FFFFFF1	# CS[0]n Size
-# bit0:    1,  Window enabled
-# bit1:    0,  Write Protect disabled
-# bit3-2:  00, CS0 hit selected
-# bit23-4: ones, required
-# bit31-24: 0x0F, Size (i.e. 256MB)
-
-DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
-DATA 0xFFD0150C 0x0FFFFFF5	# CS[1]n Size 256Mb Window enabled for CS1
-
-DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
-DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled
-
-DATA 0xFFD01494 0x00120012	#  DDR ODT Control (Low)
-# bit3-0:   0010, (read) M_ODT[0] is asserted during read from DRAM CS1
-# bit7-4:   0001, (read) M_ODT[1] is asserted during read from DRAM CS0
-# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
-# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
-DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
-
-DATA 0xFFD0149C 0x0000E40f	# CPU ODT Control
-# bit3-0:    1111, internal ODT is asserted during read from DRAM bank 0-3
-# bit11-10:    01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
-# bit13-12:    10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
-# bit14:        1, M_STARTBURST_IN ODT: Enabled
-# bit15:        1, DDR IO ODT Unit: Use ODT block
-DATA 0xFFD01480 0x00000001	# DDR Initialization Control
-#bit0=1, enable DDR init upon this register write
-
-# End of Header extension
-DATA 0x0 0x0
diff --git a/board/Marvell/openrd_base/openrd_base.c b/board/Marvell/openrd_base/openrd_base.c
deleted file mode 100644
index c00a08a..0000000
--- a/board/Marvell/openrd_base/openrd_base.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * (C) Copyright 2009
- * Net Insight <www.netinsight.net>
- * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
- *
- * Based on sheevaplug.c:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <common.h>
-#include <miiphy.h>
-#include <asm/arch/kirkwood.h>
-#include <asm/arch/mpp.h>
-#include "openrd_base.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init(void)
-{
-	/*
-	 * default gpio configuration
-	 * There are maximum 64 gpios controlled through 2 sets of registers
-	 * the  below configuration configures mainly initial LED status
-	 */
-	kw_config_gpio(OPENRD_OE_VAL_LOW,
-			OPENRD_OE_VAL_HIGH,
-			OPENRD_OE_LOW, OPENRD_OE_HIGH);
-
-	/* Multi-Purpose Pins Functionality configuration */
-	u32 kwmpp_config[] = {
-		MPP0_NF_IO2,
-		MPP1_NF_IO3,
-		MPP2_NF_IO4,
-		MPP3_NF_IO5,
-		MPP4_NF_IO6,
-		MPP5_NF_IO7,
-		MPP6_SYSRST_OUTn,
-		MPP7_GPO,
-		MPP8_TW_SDA,
-		MPP9_TW_SCK,
-		MPP10_UART0_TXD,
-		MPP11_UART0_RXD,
-		MPP12_SD_CLK,
-		MPP13_SD_CMD, /* Alt UART1_TXD */
-		MPP14_SD_D0,  /* Alt UART1_RXD */
-		MPP15_SD_D1,
-		MPP16_SD_D2,
-		MPP17_SD_D3,
-		MPP18_NF_IO0,
-		MPP19_NF_IO1,
-		MPP20_GE1_0,
-		MPP21_GE1_1,
-		MPP22_GE1_2,
-		MPP23_GE1_3,
-		MPP24_GE1_4,
-		MPP25_GE1_5,
-		MPP26_GE1_6,
-		MPP27_GE1_7,
-		MPP28_GPIO,
-		MPP29_TSMP9,
-		MPP30_GE1_10,
-		MPP31_GE1_11,
-		MPP32_GE1_12,
-		MPP33_GE1_13,
-		MPP34_GPIO,   /* UART1 / SD sel */
-		MPP35_TDM_CH0_TX_QL,
-		MPP36_TDM_SPI_CS1,
-		MPP37_TDM_CH2_TX_QL,
-		MPP38_TDM_CH2_RX_QL,
-		MPP39_AUDIO_I2SBCLK,
-		MPP40_AUDIO_I2SDO,
-		MPP41_AUDIO_I2SLRC,
-		MPP42_AUDIO_I2SMCLK,
-		MPP43_AUDIO_I2SDI,
-		MPP44_AUDIO_EXTCLK,
-		MPP45_TDM_PCLK,
-		MPP46_TDM_FS,
-		MPP47_TDM_DRX,
-		MPP48_TDM_DTX,
-		MPP49_TDM_CH0_RX_QL,
-		0
-	};
-
-	kirkwood_mpp_conf(kwmpp_config);
-
-	/*
-	 * arch number of board
-	 */
-	gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
-	return 0;
-}
-
-int dram_init(void)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
-		gd->bd->bi_dram[i].start = kw_sdram_bar(i);
-		gd->bd->bi_dram[i].size = kw_sdram_bs(i);
-	}
-	return 0;
-}
-
-#ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
-{
-	u16 reg;
-	u16 devadr;
-	char *name = "egiga0";
-
-	if (miiphy_set_current_dev(name))
-		return;
-
-	/* command to read PHY dev address */
-	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
-		printf("Err..%s could not read PHY dev address\n",
-			__FUNCTION__);
-		return;
-	}
-
-	/*
-	 * Enable RGMII delay on Tx and Rx for CPU port
-	 * Ref: sec 4.7.2 of chip datasheet
-	 */
-	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
-	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
-	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
-	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
-	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
-
-	/* reset the phy */
-	miiphy_reset(name, devadr);
-
-	printf("88E1116 Initialized on %s\n", name);
-}
-#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/Marvell/openrd_base/openrd_base.h b/board/Marvell/openrd_base/openrd_base.h
deleted file mode 100644
index f3daf17..0000000
--- a/board/Marvell/openrd_base/openrd_base.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2009
- * Net Insight <www.netinsight.net>
- * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
- *
- * Based on sheevaplug.h:
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __OPENRD_BASE_H
-#define __OPENRD_BASE_H
-
-#define OPENRD_OE_LOW		(~(1<<28))        /* RS232 / RS485 */
-#define OPENRD_OE_HIGH		(~(1<<2))         /* SD / UART1 */
-#define OPENRD_OE_VAL_LOW		(0)       /* Sel RS232 */
-#define OPENRD_OE_VAL_HIGH		(1 << 2)  /* Sel SD */
-
-/* PHY related */
-#define MV88E1116_LED_FCTRL_REG		10
-#define MV88E1116_CPRSP_CR3_REG		21
-#define MV88E1116_MAC_CTRL_REG		21
-#define MV88E1116_PGADR_REG		22
-#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
-#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
-
-#endif /* __OPENRD_BASE_H */
diff --git a/include/configs/openrd_client.h b/include/configs/openrd_client.h
new file mode 100644
index 0000000..d936ffa
--- /dev/null
+++ b/include/configs/openrd_client.h
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_OPENRD_CLIENT_H
+#define _CONFIG_OPENRD_CLIENT_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nOpenRD-Client"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL		1
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+#define CONFIG_SHEEVA_88SV131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_MACH_OPENRD_CLIENT	/* Machine type */
+
+#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */
+
+/*
+ * CLKs configurations
+ */
+#define CONFIG_SYS_HZ		1000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/*Console on UART0 */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
+					  115200, 230400, 460800, 921600 }
+/* auto boot */
+#define CONFIG_BOOTDELAY	3	/* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */
+
+#define	CONFIG_SYS_PROMPT	"Marvell>> "	/* Command Prompt */
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
+#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
+		+sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print Buff */
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_SYS_NAND_BASE		0xD8000000	/* KW_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL		1
+#endif
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0x60000
+#define CONFIG_ENV_OFFSET		0x60000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"${x_bootcmd_kernel}; "	\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define MTDIDS_DEFAULT		"nand0=nand_mtd"
+#define MTDPARTS_DEFAULT	"mtdparts=nand_mtd:0x100000 at 0x000000(uboot),"\
+	"0x400000 at 0x100000(uImage),"\
+	"0x1fb00000 at 0x500000(rootfs)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"x_bootargs=console"		\
+	"=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0"		\
+	"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0"	\
+	"x_bootcmd_usb=usb start\0"					\
+	"x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0"		\
+	"mtdids="MTDIDS_DEFAULT"\0"					\
+	"mtdparts="MTDPARTS_DEFAULT"\0"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024) /* 1MiB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_ARCH_CPU_INIT	/* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT	/* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO	/* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS	4
+#define CONFIG_STACKSIZE	0x00100000	/* regular stack- 1M */
+#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
+#define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_NET_MULTI	/* specify more that one ports available */
+#define	CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA	/* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS	{1, 1}
+#define CONFIG_PHY_BASE_ADR	0x8
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_KIRKWOOD	/* on Kirkwood platform	*/
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_OPENRD_CLIENT_H */
diff --git a/include/configs/openrd_ultimate.h b/include/configs/openrd_ultimate.h
new file mode 100644
index 0000000..a0e0417
--- /dev/null
+++ b/include/configs/openrd_ultimate.h
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_OPENRD_ULTIMATE_H
+#define _CONFIG_OPENRD_ULTIMATE_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nOpenRD-Ultimate"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_MARVELL		1
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+#define CONFIG_SHEEVA_88SV131	1	/* CPU Core subversion */
+#define CONFIG_KIRKWOOD		1	/* SOC Family Name */
+#define CONFIG_KW88F6281	1	/* SOC Name */
+#define CONFIG_MACH_OPENRD_ULTIMATE	/* Machine type */
+
+#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */
+
+/*
+ * CLKs configurations
+ */
+#define CONFIG_SYS_HZ		1000
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1		KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX	1	/*Console on UART0 */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, \
+					  115200, 230400, 460800, 921600 }
+/* auto boot */
+#define CONFIG_BOOTDELAY	3	/* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
+#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */
+
+#define	CONFIG_SYS_PROMPT	"Marvell>> "	/* Command Prompt */
+#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
+#define	CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
+		+sizeof(CONFIG_SYS_PROMPT) + 16)	/* Print Buff */
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_USB
+
+/*
+ * NAND configuration
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_KIRKWOOD
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_SYS_NAND_BASE		0xD8000000	/* KW_DEFADR_NANDF */
+#define NAND_ALLOW_ERASE_ALL		1
+#endif
+
+/*
+ *  Environment variables configurations
+ */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_ENV_IS_IN_NAND		1
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K */
+#else
+#define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
+#endif
+/*
+ * max 4k env size is enough, but in case of nand
+ * it has to be rounded to sector size
+ */
+#define CONFIG_ENV_SIZE			0x20000	/* 128k */
+#define CONFIG_ENV_ADDR			0x60000
+#define CONFIG_ENV_OFFSET		0x60000	/* env starts here */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_BOOTCOMMAND		"${x_bootcmd_kernel}; "	\
+	"setenv bootargs ${x_bootargs} ${x_bootargs_root}; "	\
+	"${x_bootcmd_usb}; bootm 0x6400000;"
+
+#define MTDIDS_DEFAULT		"nand0=nand_mtd"
+#define MTDPARTS_DEFAULT	"mtdparts=nand_mtd:0x100000 at 0x000000(uboot),"\
+	"0x400000 at 0x100000(uImage),"\
+	"0x1fb00000 at 0x500000(rootfs)"
+
+#define CONFIG_EXTRA_ENV_SETTINGS	"x_bootargs=console"		\
+	"=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0"		\
+	"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0"	\
+	"x_bootcmd_usb=usb start\0"					\
+	"x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0"		\
+	"mtdids="MTDIDS_DEFAULT"\0"					\
+	"mtdparts="MTDPARTS_DEFAULT"\0"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024) /* 1MiB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_ARCH_CPU_INIT	/* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT	/* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO	/* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS	4
+#define CONFIG_STACKSIZE	0x00100000	/* regular stack- 1M */
+#define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
+#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
+#define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_NET_MULTI	/* specify more that one ports available */
+#define	CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_KIRKWOOD_EGIGA	/* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_KIRKWOOD_EGIGA_PORTS	{1, 1}
+#define CONFIG_PHY_BASE_ADR	0
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * USB/EHCI
+ */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_KIRKWOOD	/* on Kirkwood platform	*/
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#endif /* CONFIG_CMD_USB */
+
+/*
+ * File system
+ */
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_LZO
+
+#endif /* _CONFIG_OPENRD_ULTIMATE_H */
-- 
1.6.6.1

[U-Boot] [PATCH] ARM: Kirkwood: Add support for OpenRD-Client & OpenRD-Ultimate

[Simon Kagstrom]

On Thu, 10 Jun 2010 14:42:24 +0530
Tanmay Upadhyay <tanmay.upadhyay@einfochips.com> wrote:

> This patch modifies existing OpenRD-Base support to deal with all
> the three OpenRD boards (OpenRD-Base, OpenRD-Client & OpenRD-Ultimate).

Yes, that's a good change!

> diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
> index 940d814..19114b0 100644
> --- a/arch/arm/include/asm/mach-types.h
> +++ b/arch/arm/include/asm/mach-types.h
> @@ -2862,6 +2862,7 @@ extern unsigned int __machine_arch_type;
>  #define MACH_TYPE_MATRIX518            2879
>  #define MACH_TYPE_TINY_GURNARD         2880
>  #define MACH_TYPE_SPEAR1310            2881
> +#define MACH_TYPE_OPENRD_ULTIMATE      2884

I don't think this file is supposed to be edited in patches, but rather
synched from arm-linux by Wolfgang from time to time.

> diff --git a/include/configs/openrd_client.h b/include/configs/openrd_client.h
> new file mode 100644
> index 0000000..d936ffa

Perhaps common parts of this...

> diff --git a/include/configs/openrd_ultimate.h b/include/configs/openrd_ultimate.h
> new file mode 100644
> index 0000000..a0e0417

and this and openrd_base.h can be merged into a common file. Most stuff
should be identical, right?

// Simon

[U-Boot] [PATCH] ARM: Kirkwood: Add support for OpenRD-Client & OpenRD-Ultimate

[Tanmay Upadhyay]

On 06/10/2010 02:46 PM, Simon Kagstrom wrote:
> On Thu, 10 Jun 2010 14:42:24 +0530
> Tanmay Upadhyay<tanmay.upadhyay@einfochips.com>  wrote:
>
>    
>> This patch modifies existing OpenRD-Base support to deal with all
>> the three OpenRD boards (OpenRD-Base, OpenRD-Client&  OpenRD-Ultimate).
>>      
> Yes, that's a good change!
>
>    
>> diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
>> index 940d814..19114b0 100644
>> --- a/arch/arm/include/asm/mach-types.h
>> +++ b/arch/arm/include/asm/mach-types.h
>> @@ -2862,6 +2862,7 @@ extern unsigned int __machine_arch_type;
>>   #define MACH_TYPE_MATRIX518            2879
>>   #define MACH_TYPE_TINY_GURNARD         2880
>>   #define MACH_TYPE_SPEAR1310            2881
>> +#define MACH_TYPE_OPENRD_ULTIMATE      2884
>>      
> I don't think this file is supposed to be edited in patches, but rather
> synched from arm-linux by Wolfgang from time to time.
>
>    
Sorry, I didn't know about that. However, as the number is already 
registered, is that ok to have it here?
>> diff --git a/include/configs/openrd_client.h b/include/configs/openrd_client.h
>> new file mode 100644
>> index 0000000..d936ffa
>>      
> Perhaps common parts of this...
>
>    
>> diff --git a/include/configs/openrd_ultimate.h b/include/configs/openrd_ultimate.h
>> new file mode 100644
>> index 0000000..a0e0417
>>      
> and this and openrd_base.h can be merged into a common file. Most stuff
> should be identical, right?
>    
I agree with you. But auto-generated 'config.h' file includes 
<board_name.h>. So there has to be one for each board. However, there 
could be one 'openrd.h'  in the configs and three board specific files 
include it. This will increase the number of files, but would decrease 
LOC. What do you think?

Thanks,

Tanmay
> // Simon
>
>
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>
> ____________________________________________________________________________________
> Disclaimer: This e-mail message and all attachments transmitted with it are intended solely for the use of the addressee and may contain legally privileged and confidential information. If the reader of this message is not the intended recipient, or an employee or agent responsible for delivering this message to the intended recipient, you are hereby notified that any dissemination, distribution, copying, or other use of this message or its attachments is strictly prohibited. If you have received this message in error, please notify the sender immediately by replying to this message and please delete it from your computer. Any views expressed in this message are those of the individual sender unless otherwise stated.Company has taken enough precautions to prevent the spread of viruses. However the company accepts no liability for any damage caused by any virus transmitted by this email.
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>    

[U-Boot] [PATCH] ARM: Kirkwood: Add support for OpenRD-Client & OpenRD-Ultimate

[Simon Kagstrom]

On Thu, 10 Jun 2010 15:08:00 +0530
Tanmay Upadhyay <tanmay.upadhyay@einfochips.com> wrote:

> >> +#define MACH_TYPE_OPENRD_ULTIMATE      2884
> >>      
> > I don't think this file is supposed to be edited in patches, but rather
> > synched from arm-linux by Wolfgang from time to time.
>
> Sorry, I didn't know about that. However, as the number is already 
> registered, is that ok to have it here?

Probably Wolfgang or Tom Rix (the ARM maintainer) can synch it if you
ask them to.

> I agree with you. But auto-generated 'config.h' file includes 
> <board_name.h>. So there has to be one for each board. However, there 
> could be one 'openrd.h'  in the configs and three board specific files 
> include it. This will increase the number of files, but would decrease 
> LOC. What do you think?

Personally I'd prefer to keep the common parts in a common file, so I'd
vote for that solution.

// Simon

[U-Boot] [PATCH] ARM: Kirkwood: Add support for OpenRD-Client & OpenRD-Ultimate

[Prafulla Wadaskar]

 

> -----Original Message-----
> From: Simon Kagstrom [mailto:simon.kagstrom at netinsight.net] 
> Sent: Thursday, June 10, 2010 3:56 PM
> To: Tanmay Upadhyay
> Cc: Prafulla Wadaskar; u-boot at lists.denx.de
> Subject: Re: [PATCH] ARM: Kirkwood: Add support for 
> OpenRD-Client & OpenRD-Ultimate
> 
> On Thu, 10 Jun 2010 15:08:00 +0530
> Tanmay Upadhyay <tanmay.upadhyay@einfochips.com> wrote:
> 
> > >> +#define MACH_TYPE_OPENRD_ULTIMATE      2884
> > >>      
> > > I don't think this file is supposed to be edited in 
> patches, but rather
> > > synched from arm-linux by Wolfgang from time to time.
> >
> > Sorry, I didn't know about that. However, as the number is already 
> > registered, is that ok to have it here?
> 
> Probably Wolfgang or Tom Rix (the ARM maintainer) can synch it if you
> ask them to.

Tom Does this frequently, Hi Tom, can you pls do the needful?

> 
> > I agree with you. But auto-generated 'config.h' file includes 
> > <board_name.h>. So there has to be one for each board. 

Yes, This is correct approach, lets have three files for three boards (like other added)
Abstract common part in openrd.h and include it in respective board config header files.

> However, there 
> > could be one 'openrd.h'  in the configs and three board 
> specific files 
> > include it. This will increase the number of files, but 
> would decrease 
> > LOC. What do you think?

As suggested above, let's keep code clean and simple.
Adding new board support in future to the same family will keep on increasing code complexity.
I prefer adding few files instead of modifying existing.
Secondly kwimage.cfg in your port may have common settings for all three board which may not be the case always.
And file parsing does not support conditional code for this file.

So I suggest, you should keep common code under openrd.c/h, and board specific in <board_name>.c/h
Even I don't mind keeping existing openrd_base board support as it is and adding new board support for two other boards.

Regards..
Prafulla . .

[U-Boot] [PATCH] ARM: Kirkwood: Add support for OpenRD-Client & OpenRD-Ultimate

[Albert ARIBAUD]

Le 10/06/2010 11:12, Tanmay Upadhyay a ?crit :

> This patch modifies existing OpenRD-Base support to deal with all
> the three OpenRD boards (OpenRD-Base, OpenRD-Client&  OpenRD-Ultimate).

Probably small detail: this patch replaces the @ by an <at> in the 
e-mail addresses (not only the patch author's). Is it a policy for 
submitting patches to u-boot that all e-mail addresses should be 
'obfuscated' so?

More important: I've tried running the resulting u-boot on my 
OpenRD-Client by TFTPing it to RAM (the default OpenRD-Client config has 
CONFIG_SKIP_LOWLEVEL_INIT defined and CONFIG_SKIP_RELACATION undefined). 
Doing a 'go' to the load address causes no visible output on the console 
and no sign of life at all -- I have to reset the board to get back to 
the FLASH u-boot. Anyone here had better luck with the OpenRD client config?

Amicalement,
-- 
Albert.

[U-Boot] [PATCH] ARM: Kirkwood: Add support for OpenRD-Client & OpenRD-Ultimate

[Wolfgang Denk]

Dear Albert ARIBAUD,

In message <4C14C6A9.6000407@free.fr> you wrote:
> Le 10/06/2010 11:12, Tanmay Upadhyay a =E9crit :
> 
> > This patch modifies existing OpenRD-Base support to deal with all
> > the three OpenRD boards (OpenRD-Base, OpenRD-Client&  OpenRD-Ultimate).
> 
> Probably small detail: this patch replaces the @ by an <at> in the >
> e-mail addresses (not only the patch author's). Is it a policy for >
> submitting patches to u-boot that all e-mail addresses should be >
> 'obfuscated' so?

This is not only NOT policy, but it is a strict NO-NO. Do NOT do that.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
When a child is taught ... its programmed with simple instructions --
and at some point, if its mind develops properly, it exceeds the  sum
of what it was taught, thinks independently.
	-- Dr. Richard Daystrom, "The Ultimate Computer",
	   stardate 4731.3.

[U-Boot] [PATCH] ARM: Kirkwood: Add support for OpenRD-Client & OpenRD-Ultimate

[Wolfgang Denk]

Dear Albert ARIBAUD,

In message <4C14C6A9.6000407@free.fr> you wrote:
>
> > This patch modifies existing OpenRD-Base support to deal with all
> > the three OpenRD boards (OpenRD-Base, OpenRD-Client&  OpenRD-Ultimate).
>
> Probably small detail: this patch replaces the @ by an <at> in the >
> e-mail addresses (not only the patch author's). Is it a policy for >
> submitting patches to u-boot that all e-mail addresses should be >
> 'obfuscated' so?

Hm... I cannot find any such change in the original patch. Did you
receive the original mail through the mailing list, or are you
reviewing the patch in some mailing list archive?

Note that many mailing list setups auto-obfuscate mail addresses.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
War isn't a good life, but it's life.
	-- Kirk, "A Private Little War", stardate 4211.8

[U-Boot] [PATCH] ARM: Kirkwood: Add support for OpenRD-Client & OpenRD-Ultimate

[Albert ARIBAUD]

Hi Wolfgang,

Le 13/06/2010 14:51, Wolfgang Denk a ?crit :

>> Probably small detail: this patch replaces the @ by an<at>  in the>
>> e-mail addresses (not only the patch author's). Is it a policy for>
>> submitting patches to u-boot that all e-mail addresses should be>
>> 'obfuscated' so?
>
> Hm... I cannot find any such change in the original patch. Did you
> receive the original mail through the mailing list, or are you
> reviewing the patch in some mailing list archive?

Indeed, I used the web u-boot archives, and yes, that's what turned the 
@s into <at>s; going through the NNTP server instead solved this point.

Sorry for the noise.

Amicalement,
-- 
Albert.

[U-Boot] [PATCH] ARM: Kirkwood: Add support for OpenRD-Client & OpenRD-Ultimate

[Tanmay Upadhyay]

On 06/11/2010 12:33 AM, Prafulla Wadaskar wrote:
>
>
>    
>> -----Original Message-----
>> From: Simon Kagstrom [mailto:simon.kagstrom at netinsight.net]
>> Sent: Thursday, June 10, 2010 3:56 PM
>> To: Tanmay Upadhyay
>> Cc: Prafulla Wadaskar; u-boot at lists.denx.de
>> Subject: Re: [PATCH] ARM: Kirkwood: Add support for
>> OpenRD-Client&  OpenRD-Ultimate
>>
>> On Thu, 10 Jun 2010 15:08:00 +0530
>> Tanmay Upadhyay<tanmay.upadhyay@einfochips.com>  wrote:
>>
>>      
>>>>> +#define MACH_TYPE_OPENRD_ULTIMATE      2884
>>>>>
>>>>>            
>>>> I don't think this file is supposed to be edited in
>>>>          
>> patches, but rather
>>      
>>>> synched from arm-linux by Wolfgang from time to time.
>>>>          
>>> Sorry, I didn't know about that. However, as the number is already
>>> registered, is that ok to have it here?
>>>        
>> Probably Wolfgang or Tom Rix (the ARM maintainer) can synch it if you
>> ask them to.
>>      
> Tom Does this frequently, Hi Tom, can you pls do the needful?
>    
Tom has synched it, but unfortunately the code for ultimate hasn't been 
in yet. It's stuck somewhere 
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/017535.html.

Shall I wait for this patch to get into the kernel before I send mine 
for u-boot? Otherwise my patch won't get compiled. However, I can send 
my patch for review. I have operd.h, openrd_base.h, openrd_client.h & 
openrd_ultimate.h in 'include/configs' as suggested.

Please suggest.

Thanks,

Tanmay
>    
>>      
>>> I agree with you. But auto-generated 'config.h' file includes
>>> <board_name.h>. So there has to be one for each board.
>>>        
> Yes, This is correct approach, lets have three files for three boards (like other added)
> Abstract common part in openrd.h and include it in respective board config header files.
>
>    
>> However, there
>>      
>>> could be one 'openrd.h'  in the configs and three board
>>>        
>> specific files
>>      
>>> include it. This will increase the number of files, but
>>>        
>> would decrease
>>      
>>> LOC. What do you think?
>>>        
> As suggested above, let's keep code clean and simple.
> Adding new board support in future to the same family will keep on increasing code complexity.
> I prefer adding few files instead of modifying existing.
> Secondly kwimage.cfg in your port may have common settings for all three board which may not be the case always.
> And file parsing does not support conditional code for this file.
>
> So I suggest, you should keep common code under openrd.c/h, and board specific in<board_name>.c/h
> Even I don't mind keeping existing openrd_base board support as it is and adding new board support for two other boards.
>
> Regards..
> Prafulla . .
>
>
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>
> ____________________________________________________________________________________
> Disclaimer: This e-mail message and all attachments transmitted with it are intended solely for the use of the addressee and may contain legally privileged and confidential information. If the reader of this message is not the intended recipient, or an employee or agent responsible for delivering this message to the intended recipient, you are hereby notified that any dissemination, distribution, copying, or other use of this message or its attachments is strictly prohibited. If you have received this message in error, please notify the sender immediately by replying to this message and please delete it from your computer. Any views expressed in this message are those of the individual sender unless otherwise stated.Company has taken enough precautions to prevent the spread of viruses. However the company accepts no liability for any damage caused by any virus transmitted by this email.
> ____________________________________________________________________________________
>
>    

[U-Boot] [PATCH v2] Armada100: Add Board Support for Marvell GuruPlug-Display

[Ajay Bhargav]

This patch adds basic board support with DRAM and UART functionality

v2 - Updated MAINTAINERS file as suggested by Prafulla.

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
Acked-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
---
 MAINTAINERS                               |    4 +
 MAKEALL                                   |    1 +
 arch/arm/include/asm/arch-armada100/mfp.h |    4 +-
 board/Marvell/gplugd/Makefile             |   57 +++++++++++++++++++
 board/Marvell/gplugd/gplugd.c             |   62 ++++++++++++++++++++
 boards.cfg                                |    1 +
 include/configs/gplugd.h                  |   87 +++++++++++++++++++++++++++++
 7 files changed, 214 insertions(+), 2 deletions(-)
 create mode 100644 board/Marvell/gplugd/Makefile
 create mode 100644 board/Marvell/gplugd/gplugd.c
 create mode 100644 include/configs/gplugd.h

diff --git a/MAINTAINERS b/MAINTAINERS
index e2c48a8..0b0c53d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -590,6 +590,10 @@ Eric Benard <eric@eukrea.com>
 	cpu9260		ARM926EJS (AT91SAM9260 SoC)
 	cpu9G20		ARM926EJS (AT91SAM9G20 SoC)
 
+Ajay Bhargav <ajay.bhargav@einfochips.com>
+
+	gplugd		ARM926EJS (ARMADA100 88AP168 SoC)
+
 Rishi Bhattacharya <rishi@ti.com>
 
 	omap5912osk	ARM926EJS
diff --git a/MAKEALL b/MAKEALL
index d592374..259da84 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -388,6 +388,7 @@ LIST_ARM9="			\
 	davinci_dm355leopard	\
 	davinci_dm365evm	\
 	davinci_dm6467evm	\
+	gplugd			\
 "
 
 #########################################################################
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h
index 73783a7..d6e0494 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -57,8 +57,8 @@
 #define MFP89_UART2_TXD		(MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM)
 
 /* UART3 */
-#define MFPO8_UART3_RXD		(MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
-#define MFPO9_UART3_TXD		(MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFPO8_UART3_TXD		(MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MFPO9_UART3_RXD		(MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
 
 /* I2c */
 #define MFP105_CI2C_SDA		(MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
diff --git a/board/Marvell/gplugd/Makefile b/board/Marvell/gplugd/Makefile
new file mode 100644
index 0000000..2d8bba0
--- /dev/null
+++ b/board/Marvell/gplugd/Makefile
@@ -0,0 +1,57 @@
+#
+# (C) Copyright 2011
+# eInfochips Ltd. <www.einfochips.com>
+# Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+#
+# Based on Aspenite:
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Contributor: Mahavir Jain <mjain@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB     = $(obj)lib$(BOARD).o
+
+COBJS	:= gplugd.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
new file mode 100644
index 0000000..dc7d89d
--- /dev/null
+++ b/board/Marvell/gplugd/gplugd.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * Based on Aspenite:
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* I2C */
+		MFP105_CI2C_SDA,
+		MFP106_CI2C_SCL,
+
+		/* Enable Console on UART3 */
+		MFPO8_UART3_TXD,
+		MFPO9_UART3_RXD,
+		MFP_EOC		/*End of configuration*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of Board */
+	gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 9f2b118..014d86b 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -72,6 +72,7 @@ netstar                      arm         arm925t
 voiceblue                    arm         arm925t
 omap1510inn                  arm         arm925t     -                   ti
 aspenite                     arm         arm926ejs   -                   Marvell        armada100
+gplugd                       arm         arm926ejs   -                   Marvell        armada100
 afeb9260                     arm         arm926ejs   -                   -              at91
 at91cap9adk                  arm         arm926ejs   -                   atmel          at91
 snapper9260                  arm         arm926ejs   -                   bluewater      at91        snapper9260:AT91SAM9260
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
new file mode 100644
index 0000000..cc14f49
--- /dev/null
+++ b/include/configs/gplugd.h
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * Based on Aspenite:
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_GPLUGD_H
+#define __CONFIG_GPLUGD_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-gplugD"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV331xV5	1	/* CPU Core subversion */
+#define CONFIG_ARMADA100		1	/* SOC Family Name */
+#define CONFIG_ARMADA168		1	/* SOC Used on this Board */
+#define CONFIG_MACH_SHEEVAD			/* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+#define	CONFIG_SYS_TEXT_BASE	0x00f00000
+
+/*
+ * There is no internal RAM in ARMADA100, using DRAM
+ * TBD: dcache to be used for this
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - 0x00200000)
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_ARCH_MISC_INIT
+
+#ifdef CONFIG_SYS_NS16550_COM1
+#undef CONFIG_SYS_NS16550_COM1
+#endif /* CONFIG_SYS_NS16550_COM1 */
+
+#define CONFIG_SYS_NS16550_COM1 ARMD1_UART3_BASE
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE	1	/* if env in SDRAM */
+#define CONFIG_ENV_SIZE	0x20000		/* 64k */
+
+#endif	/* __CONFIG_GPLUGD_H */
-- 
1.7.0.4

[U-Boot] [PATCH v2] Armada100: Add Board Support for Marvell GuruPlug-Display

[Prafulla Wadaskar]

> -----Original Message-----
> From: Ajay Bhargav [mailto:ajay.bhargav at einfochips.com]
> Sent: Tuesday, July 05, 2011 12:47 PM
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de; Ajay Bhargav
> Subject: [PATCH v2] Armada100: Add Board Support for Marvell GuruPlug-
> Display
> 
> This patch adds basic board support with DRAM and UART functionality
> 
> v2 - Updated MAINTAINERS file as suggested by Prafulla.
> 
> Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
> Acked-by: Tanmay Upadhyay <tanmay.upadhyay@einfochips.com>
> ---
>  MAINTAINERS                               |    4 +
>  MAKEALL                                   |    1 +
>  arch/arm/include/asm/arch-armada100/mfp.h |    4 +-

The change in this file is generic and not related to this board.
So please split the patch into two.

Rest everything looks okay to me.

Regards..
Prafulla . . 

[U-Boot] [Patch V2] mmc: mv_sdhci: Fix host version read for Armada100

[Ajay Bhargav]

sdhci_readw does not work for host version read in Armada100 series
SoCs. This patch fix this issue by making a sdhci_readl call to get host
version.

Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
---
Changes for v2:
	- Added quirk instead of #define (suggested by Marek)

 drivers/mmc/mv_sdhci.c |    5 ++++-
 include/sdhci.h        |    1 +
 2 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index f92caeb..c9b7079 100644
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -48,7 +48,10 @@ int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
 		mv_ops.write_b = mv_sdhci_writeb;
 	host->ops = &mv_ops;
 #endif
-	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+	if (quirks & SDHCI_QUIRK_REG32_RW)
+		host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
+	else
+		host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 	add_sdhci(host, max_clk, min_clk);
 	return 0;
 }
diff --git a/include/sdhci.h b/include/sdhci.h
index 0690938..800f9d9 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -215,6 +215,7 @@
  * quirks
  */
 #define SDHCI_QUIRK_32BIT_DMA_ADDR	(1 << 0)
+#define SDHCI_QUIRK_REG32_RW		(1 << 1)
 
 /* to make gcc happy */
 struct sdhci_host;
-- 
1.7.7.2

[U-Boot] [Patch V2] mmc: mv_sdhci: Fix host version read for Armada100

[Andy Fleming]

On Mon, Nov 14, 2011 at 3:43 AM, Ajay Bhargav
<ajay.bhargav@einfochips.com> wrote:
> sdhci_readw does not work for host version read in Armada100 series
> SoCs. This patch fix this issue by making a sdhci_readl call to get host
> version.
>
> Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>

Applied, thx