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* [U-Boot] IRQ in realmode and sleep()
@ 2010-06-29  8:03 Reinhard Arlt
  2010-06-29 18:44 ` Scott Wood
  0 siblings, 1 reply; 5+ messages in thread
From: Reinhard Arlt @ 2010-06-29  8:03 UTC (permalink / raw)
  To: u-boot

Hello,

the data cache is disabled on the CPCI750 board for the SDRAM by the 
DBAT entry for the SDRAM, but the data cache is enabled for most 
74xx_7xx boards in

cpu/74xx_7xx/start.S together with the translation.

The decrementer irq is executed in real mode with translation disabled.

Now in the irq routine, the processor writes the data into the cache, 
and the sleep() reads directly from RAM, and do not see the timer running.

A good solution would be to have translation on for the irq's too, but a 
simple solution is to put an '#if !(defined CPCI750)' around the 
routine, that enables the l1 data cache.

I am not shure, if the problem with the sleep() (and the missing 
timeouts in the networks stack) hits other boards too.

Reinhard

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [U-Boot] IRQ in realmode and sleep()
  2010-06-29  8:03 [U-Boot] IRQ in realmode and sleep() Reinhard Arlt
@ 2010-06-29 18:44 ` Scott Wood
  2010-06-30  7:02   ` Reinhard Arlt
  0 siblings, 1 reply; 5+ messages in thread
From: Scott Wood @ 2010-06-29 18:44 UTC (permalink / raw)
  To: u-boot

On Tue, Jun 29, 2010 at 10:03:53AM +0200, Reinhard Arlt wrote:
> Hello,
> 
> the data cache is disabled on the CPCI750 board for the SDRAM by the 
> DBAT entry for the SDRAM, but the data cache is enabled for most 
> 74xx_7xx boards in
> 
> cpu/74xx_7xx/start.S together with the translation.
> 
> The decrementer irq is executed in real mode with translation disabled.
> 
> Now in the irq routine, the processor writes the data into the cache, 
> and the sleep() reads directly from RAM, and do not see the timer running.
> 
> A good solution would be to have translation on for the irq's too, but a 
> simple solution is to put an '#if !(defined CPCI750)' around the 
> routine, that enables the l1 data cache.

Sounds like the right solution is to change the DBAT to be cacheable.

-Scott

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [U-Boot] IRQ in realmode and sleep()
  2010-06-29 18:44 ` Scott Wood
@ 2010-06-30  7:02   ` Reinhard Arlt
  2010-06-30  7:59     ` Wolfgang Denk
  0 siblings, 1 reply; 5+ messages in thread
From: Reinhard Arlt @ 2010-06-30  7:02 UTC (permalink / raw)
  To: u-boot

Hello,

Scott Wood wrote:
> On Tue, Jun 29, 2010 at 10:03:53AM +0200, Reinhard Arlt wrote:
>> Hello,
>>
>> the data cache is disabled on the CPCI750 board for the SDRAM by the
>> DBAT entry for the SDRAM, but the data cache is enabled for most
>> 74xx_7xx boards in
>>
>> cpu/74xx_7xx/start.S together with the translation.
>>
>> The decrementer irq is executed in real mode with translation disabled.
>>
>> Now in the irq routine, the processor writes the data into the cache,
>> and the sleep() reads directly from RAM, and do not see the timer running.
>>
>> A good solution would be to have translation on for the irq's too, but a
>> simple solution is to put an '#if !(defined CPCI750)' around the
>> routine, that enables the l1 data cache.
>
> Sounds like the right solution is to change the DBAT to be cacheable.
>
due to a bug in the MV64360, the data structures for the MPSC (serial 
port) must be in not cacheable ram. In operating systems, this is done 
by a page table entry, but i do not want to start with a page table in 
u-boot.

The question is: Is it O.K., that the irq routines run in real mode, 
with all your I/O locations are cacheable, for example.

> -Scott
>

Reinhard

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [U-Boot] IRQ in realmode and sleep()
  2010-06-30  7:02   ` Reinhard Arlt
@ 2010-06-30  7:59     ` Wolfgang Denk
  2010-07-01  8:14       ` Reinhard Arlt
  0 siblings, 1 reply; 5+ messages in thread
From: Wolfgang Denk @ 2010-06-30  7:59 UTC (permalink / raw)
  To: u-boot

Dear Reinhard Arlt,

In message <4C2AEC16.9080906@t-online.de> you wrote:
> 
> The question is: Is it O.K., that the irq routines run in real mode, 
> with all your I/O locations are cacheable, for example.

I expect to see problems when you enable data cache for I/O; there are
many drivers in U-Boot which are not prepared for such conditions.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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back.

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [U-Boot] IRQ in realmode and sleep()
  2010-06-30  7:59     ` Wolfgang Denk
@ 2010-07-01  8:14       ` Reinhard Arlt
  0 siblings, 0 replies; 5+ messages in thread
From: Reinhard Arlt @ 2010-07-01  8:14 UTC (permalink / raw)
  To: u-boot

Hello,

i is the other way round.

as there is no translation on (real mode) when executing the irq 
routine, the data caching always is on.

Best regards,

Reinhard Arlt

Wolfgang Denk wrote:
> Dear Reinhard Arlt,
>
> In message<4C2AEC16.9080906@t-online.de>  you wrote:
>>
>> The question is: Is it O.K., that the irq routines run in real mode,
>> with all your I/O locations are cacheable, for example.
>
> I expect to see problems when you enable data cache for I/O; there are
> many drivers in U-Boot which are not prepared for such conditions.
>
> Best regards,
>
> Wolfgang Denk
>

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2010-07-01  8:14 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-06-29  8:03 [U-Boot] IRQ in realmode and sleep() Reinhard Arlt
2010-06-29 18:44 ` Scott Wood
2010-06-30  7:02   ` Reinhard Arlt
2010-06-30  7:59     ` Wolfgang Denk
2010-07-01  8:14       ` Reinhard Arlt

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