From mboxrd@z Thu Jan 1 00:00:00 1970 From: Reinhard Arlt Date: Wed, 30 Jun 2010 09:02:46 +0200 Subject: [U-Boot] IRQ in realmode and sleep() In-Reply-To: <20100629184405.GC24215@schlenkerla.am.freescale.net> References: <4C29A8E9.9090504@t-online.de> <20100629184405.GC24215@schlenkerla.am.freescale.net> Message-ID: <4C2AEC16.9080906@t-online.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hello, Scott Wood wrote: > On Tue, Jun 29, 2010 at 10:03:53AM +0200, Reinhard Arlt wrote: >> Hello, >> >> the data cache is disabled on the CPCI750 board for the SDRAM by the >> DBAT entry for the SDRAM, but the data cache is enabled for most >> 74xx_7xx boards in >> >> cpu/74xx_7xx/start.S together with the translation. >> >> The decrementer irq is executed in real mode with translation disabled. >> >> Now in the irq routine, the processor writes the data into the cache, >> and the sleep() reads directly from RAM, and do not see the timer running. >> >> A good solution would be to have translation on for the irq's too, but a >> simple solution is to put an '#if !(defined CPCI750)' around the >> routine, that enables the l1 data cache. > > Sounds like the right solution is to change the DBAT to be cacheable. > due to a bug in the MV64360, the data structures for the MPSC (serial port) must be in not cacheable ram. In operating systems, this is done by a page table entry, but i do not want to start with a page table in u-boot. The question is: Is it O.K., that the irq routines run in real mode, with all your I/O locations are cacheable, for example. > -Scott > Reinhard