* [U-Boot] [PATCH v5 00/18] Network support for spear platforms and SPEAr1300
@ 2010-06-29 5:23 Vipin KUMAR
2010-06-29 5:23 ` [U-Boot] [PATCH v5 01/18] change_bit routine defined Vipin KUMAR
2010-06-30 13:35 ` [U-Boot] [PATCH v5 00/18] Network support for spear platforms and SPEAr1300 Armando VISCONTI
0 siblings, 2 replies; 23+ messages in thread
From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw)
To: u-boot
Dear Wolfgang, Tom,
The following set of patches is the fifth iteration of patches for the following
changes
-> Network device driver for synopsys designware peripheral
-> SPEAr1300 SoC support
-> A few other misc changes and bugfixes
These also include the feedbacks given by Tom and Ben
These set of patches are rebased on e5ed138a23923ebe61843244748d98d3dbc04777
Please include these changes in the mainline u-boot
Regards
Vipin
Vipin KUMAR (18):
change_bit routine defined
SPEAr : SMI erase and write timeouts increased
SPEAr : Placing ethaddr write and read within CONFIG_CMD_NET
SPEAr : Reducing the max RAM size to 128MB
SPEAr : Basic arch related support added for SPEAr SoCs
SPEAr : Network driver support added
SPEAr : Network support configured for spear SoCs
SPEAr : macb driver support added for spear310 and spear320
SPEAr : FSMC driver support added
SPEAr : Configuring FSMC driver for NAND interface
SPEAr : i2c driver moved completely into drivers/i2c
SPEAr : smi driver moved completely into drivers/mtd
SPEAr : USB Device Controller driver support added
SPEAr : Supporting various configurations for spear3xx and spear6xx
boards
SPEAr : Basic spear1300 architecture support added
SPEAr : spear1300 SoC support added
SPEAr : Removing extraneous code
SPEAr : USB device controller bugfixes
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 28 +-
arch/arm/cpu/arm926ejs/spear/Makefile | 3 +-
arch/arm/cpu/arm926ejs/spear/cpu.c | 78 +++
arch/arm/cpu/arm_cortexa8/spear13xx/Makefile | 52 ++
arch/arm/cpu/arm_cortexa8/spear13xx/cache.S | 114 +++++
arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c | 96 ++++
.../arm_cortexa8/spear13xx/reset.c} | 52 +--
arch/arm/cpu/arm_cortexa8/spear13xx/timer.c | 138 +++++
.../arm/include/asm/arch-spear/clk.h | 26 +-
arch/arm/include/asm/arch-spear/hardware.h | 16 +-
arch/arm/include/asm/arch-spear/spr_misc.h | 5 +
.../arm/include/asm/arch-spear13xx/hardware.h | 33 +-
arch/arm/include/asm/arch-spear13xx/spr_gpt.h | 85 ++++
arch/arm/include/asm/arch-spear13xx/spr_misc.h | 317 ++++++++++++
.../arm/include/asm/arch-spear13xx/sys_proto.h | 29 +-
arch/arm/include/asm/bitops.h | 11 +-
board/spear/common/Makefile | 10 +-
board/spear/common/spr_misc.c | 32 +-
board/spear/spear1300/Makefile | 51 ++
board/spear/spear1300/config.mk | 28 +
board/spear/spear1300/spear1300.c | 88 ++++
.../spear/spear1300/spr_lowlevel_init.S | 35 +-
board/spear/spear300/config.mk | 11 -
board/spear/spear300/spear300.c | 18 +-
board/spear/spear310/config.mk | 11 -
board/spear/spear310/spear310.c | 35 ++-
board/spear/spear320/config.mk | 11 -
board/spear/spear320/spear320.c | 23 +-
board/spear/spear600/config.mk | 11 -
board/spear/spear600/spear600.c | 18 +-
doc/README.designware_eth | 25 +
doc/README.spear | 46 ++-
drivers/i2c/Makefile | 2 +-
drivers/i2c/{spr_i2c.c => designware_i2c.c} | 4 +-
.../spr_i2c.h => drivers/i2c/designware_i2c.h | 6 +-
drivers/mtd/Makefile | 2 +-
drivers/mtd/nand/Makefile | 2 +-
drivers/mtd/nand/fsmc_nand.c | 366 ++++++++++++++
drivers/mtd/nand/spr_nand.c | 124 -----
drivers/mtd/{spr_smi.c => st_smi.c} | 59 ++-
.../arch-spear/spr_smi.h => drivers/mtd/st_smi.h | 8 +-
drivers/net/Makefile | 1 +
drivers/net/designware.c | 531 ++++++++++++++++++++
drivers/net/designware.h | 264 ++++++++++
drivers/serial/usbtty.h | 4 +-
drivers/usb/gadget/Makefile | 2 +-
drivers/usb/gadget/{spr_udc.c => designware_udc.c} | 116 +++--
include/configs/spear-common.h | 33 +-
include/configs/spear13xx_evb.h | 202 ++++++++
include/configs/{spear3xx.h => spear3xx_evb.h} | 30 ++
include/configs/{spear6xx.h => spear6xx_evb.h} | 13 +
include/linux/mtd/fsmc_nand.h | 104 ++++
include/netdev.h | 1 +
include/usb/{spr_udc.h => designware_udc.h} | 6 +-
56 files changed, 2997 insertions(+), 421 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/spear/cpu.c
create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/Makefile
create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/cache.S
create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c
rename arch/arm/{include/asm/arch-spear/spr_nand.h => cpu/arm_cortexa8/spear13xx/reset.c} (50%)
mode change 100644 => 100755
create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/timer.c
copy include/configs/spear6xx.h => arch/arm/include/asm/arch-spear/clk.h (64%)
copy include/configs/spear6xx.h => arch/arm/include/asm/arch-spear13xx/hardware.h (58%)
create mode 100644 arch/arm/include/asm/arch-spear13xx/spr_gpt.h
create mode 100644 arch/arm/include/asm/arch-spear13xx/spr_misc.h
copy include/configs/spear6xx.h => arch/arm/include/asm/arch-spear13xx/sys_proto.h (64%)
create mode 100644 board/spear/spear1300/Makefile
create mode 100644 board/spear/spear1300/config.mk
create mode 100644 board/spear/spear1300/spear1300.c
copy include/configs/spear6xx.h => board/spear/spear1300/spr_lowlevel_init.S (56%)
create mode 100644 doc/README.designware_eth
rename drivers/i2c/{spr_i2c.c => designware_i2c.c} (98%)
rename arch/arm/include/asm/arch-spear/spr_i2c.h => drivers/i2c/designware_i2c.h (98%)
create mode 100644 drivers/mtd/nand/fsmc_nand.c
delete mode 100644 drivers/mtd/nand/spr_nand.c
rename drivers/mtd/{spr_smi.c => st_smi.c} (94%)
rename arch/arm/include/asm/arch-spear/spr_smi.h => drivers/mtd/st_smi.h (96%)
create mode 100644 drivers/net/designware.c
create mode 100644 drivers/net/designware.h
rename drivers/usb/gadget/{spr_udc.c => designware_udc.c} (91%)
create mode 100644 include/configs/spear13xx_evb.h
rename include/configs/{spear3xx.h => spear3xx_evb.h} (85%)
rename include/configs/{spear6xx.h => spear6xx_evb.h} (82%)
create mode 100644 include/linux/mtd/fsmc_nand.h
rename include/usb/{spr_udc.h => designware_udc.h} (98%)
^ permalink raw reply [flat|nested] 23+ messages in thread* [U-Boot] [PATCH v5 01/18] change_bit routine defined 2010-06-29 5:23 [U-Boot] [PATCH v5 00/18] Network support for spear platforms and SPEAr1300 Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 02/18] SPEAr : SMI erase and write timeouts increased Vipin KUMAR 2010-06-30 13:35 ` [U-Boot] [PATCH v5 00/18] Network support for spear platforms and SPEAr1300 Armando VISCONTI 1 sibling, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> change_bit routine is left implementation dependent until now. This routine is now defined for arm platforms in asm-arm/bitops.h The Flexible Static memory controller driver, placed in mtd/nand/fsmc_nand.c needs this routine. FSMC is a memory controller peripheral from ST. The new driver implements the NAND interface part of the peripheral. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- arch/arm/include/asm/bitops.h | 11 +++++++++-- 1 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h index 270f163..435857b 100644 --- a/arch/arm/include/asm/bitops.h +++ b/arch/arm/include/asm/bitops.h @@ -29,8 +29,6 @@ extern void set_bit(int nr, volatile void * addr); extern void clear_bit(int nr, volatile void * addr); -extern void change_bit(int nr, volatile void * addr); - static inline void __change_bit(int nr, volatile void *addr) { unsigned long mask = BIT_MASK(nr); @@ -39,6 +37,15 @@ static inline void __change_bit(int nr, volatile void *addr) *p ^= mask; } +static inline void change_bit(int nr, volatile void *addr) +{ + unsigned long flags; + + local_irq_save(flags); + __change_bit(nr, addr); + local_irq_restore(flags); +} + static inline int __test_and_set_bit(int nr, volatile void *addr) { unsigned long mask = BIT_MASK(nr); -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 02/18] SPEAr : SMI erase and write timeouts increased 2010-06-29 5:23 ` [U-Boot] [PATCH v5 01/18] change_bit routine defined Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 03/18] SPEAr : Placing ethaddr write and read within CONFIG_CMD_NET Vipin KUMAR 0 siblings, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> SMI driver fails because of low timeout values. Increasing the write mode timeout and transfer timeouts to 15 ms Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- arch/arm/include/asm/arch-spear/spr_smi.h | 4 +- drivers/mtd/spr_smi.c | 57 ++++++++++++++++++----------- 2 files changed, 38 insertions(+), 23 deletions(-) diff --git a/arch/arm/include/asm/arch-spear/spr_smi.h b/arch/arm/include/asm/arch-spear/spr_smi.h index 06df745..0cca000 100644 --- a/arch/arm/include/asm/arch-spear/spr_smi.h +++ b/arch/arm/include/asm/arch-spear/spr_smi.h @@ -109,7 +109,7 @@ struct flash_dev { }; #define SFLASH_PAGE_SIZE 0x100 /* flash page size */ -#define XFER_FINISH_TOUT 2 /* xfer finish timeout */ -#define WMODE_TOUT 2 /* write enable timeout */ +#define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */ +#define WMODE_TOUT 15 /* write enable timeout(in ms) */ #endif diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/spr_smi.c index 9a70a19..c6ba951 100644 --- a/drivers/mtd/spr_smi.c +++ b/drivers/mtd/spr_smi.c @@ -58,13 +58,15 @@ static struct flash_dev flash_ids[] = { * * Wait until TFF is set in status register */ -static void smi_wait_xfer_finish(int timeout) +static int smi_wait_xfer_finish(int timeout) { - while (timeout--) { + do { if (readl(&smicntl->smi_sr) & TFF) - break; + return 0; udelay(1000); - } + } while (timeout--); + + return -1; } /* @@ -82,7 +84,9 @@ static unsigned int smi_read_id(flash_info_t *info, int banknum) writel(READ_ID, &smicntl->smi_tr); writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -EIO; value = (readl(&smicntl->smi_rr) & 0x00FFFFFF); @@ -104,11 +108,17 @@ static ulong flash_get_size(ulong base, int banknum) { flash_info_t *info = &flash_info[banknum]; struct flash_dev *dev; - unsigned int value; + int value; unsigned int density; int i; value = smi_read_id(info, banknum); + + if (value < 0) { + printf("Flash id could not be read\n"); + return 0; + } + density = (value >> 16) & 0xff; for (i = 0, dev = &flash_ids[0]; dev->density != 0x0; @@ -136,7 +146,7 @@ static ulong flash_get_size(ulong base, int banknum) * This routine will get the status register of the flash chip present at the * given bank */ -static unsigned int smi_read_sr(int bank) +static int smi_read_sr(int bank) { u32 ctrlreg1; @@ -150,7 +160,8 @@ static unsigned int smi_read_sr(int bank) /* Performing a RSR instruction in HW mode */ writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -1; /* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1); @@ -169,13 +180,11 @@ static unsigned int smi_read_sr(int bank) */ static int smi_wait_till_ready(int bank, int timeout) { - int count; - unsigned int sr; + int sr; /* One chip guarantees max 5 msec wait here after page writes, but potentially three seconds (!) after page erase. */ - for (count = 0; count < timeout; count++) { - + do { sr = smi_read_sr(bank); if (sr < 0) break; @@ -184,7 +193,8 @@ static int smi_wait_till_ready(int bank, int timeout) /* Try again after 1m-sec */ udelay(1000); - } + } while (timeout--); + printf("SMI controller is still in wait, timeout=%d\n", timeout); return -EIO; } @@ -200,6 +210,7 @@ static int smi_write_enable(int bank) { u32 ctrlreg1; int timeout = WMODE_TOUT; + int sr; /* Store the CTRL REG1 state */ ctrlreg1 = readl(&smicntl->smi_cr1); @@ -210,19 +221,22 @@ static int smi_write_enable(int bank) /* Give the Flash, Write Enable command */ writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -1; /* Restore the CTRL REG1 state */ writel(ctrlreg1, &smicntl->smi_cr1); - while (timeout--) { - if (smi_read_sr(bank) & (1 << (bank + WM_SHIFT))) + do { + sr = smi_read_sr(bank); + if (sr < 0) break; - udelay(1000); - } + else if (sr & (1 << (bank + WM_SHIFT))) + return 0; - if (timeout) - return 0; + /* Try again after 1m-sec */ + udelay(1000); + } while (timeout--); return -1; } @@ -291,7 +305,8 @@ static int smi_sector_erase(flash_info_t *info, unsigned int sector) writel(instruction, &smicntl->smi_tr); writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, &smicntl->smi_cr2); - smi_wait_xfer_finish(XFER_FINISH_TOUT); + if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) + return -EIO; if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) return -EBUSY; -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 03/18] SPEAr : Placing ethaddr write and read within CONFIG_CMD_NET 2010-06-29 5:23 ` [U-Boot] [PATCH v5 02/18] SPEAr : SMI erase and write timeouts increased Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 04/18] SPEAr : Reducing the max RAM size to 128MB Vipin KUMAR 0 siblings, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> ethaddr can be optionally read from i2c memory. So, chip_config command supports reading/writing hw mac id into i2c memory. Placing this code within CONFIG_CMD_NET as this would only be needed when network interface is configured Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- board/spear/common/spr_misc.c | 32 +++++++++++++++++++++++--------- doc/README.spear | 8 ++++++++ 2 files changed, 31 insertions(+), 9 deletions(-) diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index e356912..181e3b2 100644 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -38,6 +38,10 @@ DECLARE_GLOBAL_DATA_PTR; static struct chip_data chip_data; +#if defined(CONFIG_CMD_NET) +static int i2c_read_mac(uchar *buffer); +#endif + int dram_init(void) { struct xloader_table *xloader_tb = @@ -166,6 +170,7 @@ int spear_board_init(ulong mach_type) return 0; } +#if defined(CONFIG_CMD_NET) static int i2c_read_mac(uchar *buffer) { u8 buf[2]; @@ -198,22 +203,24 @@ static int write_mac(uchar *mac) /* check if valid MAC address is saved in I2C EEPROM or not? */ if ((buf[0] == MAGIC_BYTE0) && (buf[1] == MAGIC_BYTE1)) { i2c_write(CONFIG_I2C_CHIPADDRESS, MAC_OFF, 1, mac, MAC_LEN); - puts("I2C EEPROM written with mac address \n"); + puts("I2C EEPROM written with mac address\n"); return 0; } - puts("I2C EEPROM writing failed \n"); + puts("I2C EEPROM writing failed\n"); return -1; } +#endif int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { void (*sram_setfreq) (unsigned int, unsigned int); struct chip_data *chip = &chip_data; + unsigned int frequency; + +#if defined(CONFIG_CMD_NET) unsigned char mac[6]; - unsigned int reg, frequency; - char *s, *e; - char i2c_mac[20]; +#endif if ((argc > 3) || (argc < 2)) { cmd_usage(cmdtp); @@ -244,9 +251,12 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } return 0; + +#if defined(CONFIG_CMD_NET) } else if (!strcmp(argv[1], "ethaddr")) { - s = argv[2]; + u32 reg; + char *e, *s = argv[2]; for (reg = 0; reg < 6; ++reg) { mac[reg] = s ? simple_strtoul(s, &e, 16) : 0; if (s) @@ -255,6 +265,7 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) write_mac(mac); return 0; +#endif } else if (!strcmp(argv[1], "print")) { if (chip->cpufreq == -1) @@ -274,13 +285,13 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) else printf("DDR Type = Not Known\n"); +#if defined(CONFIG_CMD_NET) if (!i2c_read_mac(mac)) { - sprintf(i2c_mac, "%pM", mac); - printf("Ethaddr (from i2c mem) = %s\n", i2c_mac); + printf("Ethaddr (from i2c mem) = %pM\n", mac); } else { printf("Ethaddr (from i2c mem) = Not set\n"); } - +#endif printf("Xloader Rev = %s\n", chip->version); return 0; @@ -293,4 +304,7 @@ int do_chip_config(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(chip_config, 3, 1, do_chip_config, "configure chip", "chip_config cpufreq/ddrfreq frequency\n" +#if defined(CONFIG_CMD_NET) + "chip_config ethaddr XX:XX:XX:XX:XX:XX\n" +#endif "chip_config print"); diff --git a/doc/README.spear b/doc/README.spear index a8b1052..a6ff7fd 100644 --- a/doc/README.spear +++ b/doc/README.spear @@ -46,3 +46,11 @@ Further options make FLASH=PNOR (supported by SPEAr310 and SPEAr320) - This option generates a uboot image that supports emi controller for CFI compliant parallel NOR flash + +Mac id storage and retrieval in spear platforms + +Please read doc/README.enetaddr for the implementation guidelines for mac id +usage. Basically, environment has precedence over board specific storage. The +ethaddr beeing used for the network interface is always taken only from +environment variables. Although, we can check the mac id programmed in i2c +memory by using chip_config command -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 04/18] SPEAr : Reducing the max RAM size to 128MB 2010-06-29 5:23 ` [U-Boot] [PATCH v5 03/18] SPEAr : Placing ethaddr write and read within CONFIG_CMD_NET Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 05/18] SPEAr : Basic arch related support added for SPEAr SoCs Vipin KUMAR 0 siblings, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- include/configs/spear-common.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index cc52e39..b526558 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -208,6 +208,6 @@ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x00000000 -#define PHYS_SDRAM_1_MAXSIZE 0x40000000 +#define PHYS_SDRAM_1_MAXSIZE 0x08000000 #endif -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 05/18] SPEAr : Basic arch related support added for SPEAr SoCs 2010-06-29 5:23 ` [U-Boot] [PATCH v5 04/18] SPEAr : Reducing the max RAM size to 128MB Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 06/18] SPEAr : Network driver support added Vipin KUMAR 0 siblings, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> Adding CONFIG_DISPLAY_CPUINFO and CONFIG_ARCH_CPU_INIT support for SPEAr3xx and SPEAr6xx SoCs CONFIG_DISPLAY_CPUINFO includes the built CPU related information Earlier, architecture specific init code was mixed with board initialization code in board/spear/... CONFIG_ARCH_CPU_INIT includes the architecture specific initialisation code with in arch/arm/spear/cpu.c Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- arch/arm/cpu/arm926ejs/spear/Makefile | 3 +- arch/arm/cpu/arm926ejs/spear/cpu.c | 78 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-spear/spr_misc.h | 5 ++ include/configs/spear-common.h | 2 + 4 files changed, 87 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/spear/cpu.c diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile index bf8dfa8..6ca8c6e 100644 --- a/arch/arm/cpu/arm926ejs/spear/Makefile +++ b/arch/arm/cpu/arm926ejs/spear/Makefile @@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS := reset.o \ +COBJS := cpu.o \ + reset.o \ timer.o SOBJS := diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c new file mode 100644 index 0000000..0f66e05 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h> + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + struct misc_regs *const misc_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 periph1_clken; + + periph1_clken = readl(&misc_p->periph1_clken); + +#if defined(CONFIG_PL011_SERIAL) + periph1_clken |= MISC_UART0ENB; +#endif +#if defined(CONFIG_DESIGNWARE_ETH) + periph1_clken |= MISC_ETHENB; +#endif +#if defined(CONFIG_DW_UDC) + periph1_clken |= MISC_USBDENB; +#endif +#if defined(CONFIG_DW_I2C) + periph1_clken |= MISC_I2CENB; +#endif +#if defined(CONFIG_ST_SMI) + periph1_clken |= MISC_SMIENB; +#endif +#if defined(CONFIG_NAND_FSMC) + periph1_clken |= MISC_FSMCENB; +#endif + + writel(periph1_clken, &misc_p->periph1_clken); + return 0; +} +#endif + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ +#ifdef CONFIG_SPEAR300 + printf("CPU: SPEAr300\n"); +#elif defined(CONFIG_SPEAR310) + printf("CPU: SPEAr310\n"); +#elif defined(CONFIG_SPEAR320) + printf("CPU: SPEAr320\n"); +#elif defined(CONFIG_SPEAR600) + printf("CPU: SPEAr600\n"); +#else +#error CPU not supported in spear platform +#endif + return 0; +} +#endif diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h index 8b96d9b..045d2bb 100644 --- a/arch/arm/include/asm/arch-spear/spr_misc.h +++ b/arch/arm/include/asm/arch-spear/spr_misc.h @@ -126,5 +126,10 @@ struct misc_regs { /* PERIPH1_CLKEN, PERIPH1_RST value */ #define MISC_USBDENB 0x01000000 +#define MISC_ETHENB 0x00800000 +#define MISC_SMIENB 0x00200000 +#define MISC_FSMCENB 0x00000200 +#define MISC_I2CENB 0x00000080 +#define MISC_UART0ENB 0x00000008 #endif diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index b526558..10beef7 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -168,6 +168,8 @@ #define CONFIG_ENV_SIZE 0x02000 /* Miscellaneous configurable options */ +#define CONFIG_ARCH_CPU_INIT 1 +#define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 #define CONFIG_CMDLINE_TAG 1 #define CONFIG_SETUP_MEMORY_TAGS 1 -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 06/18] SPEAr : Network driver support added 2010-06-29 5:23 ` [U-Boot] [PATCH v5 05/18] SPEAr : Basic arch related support added for SPEAr SoCs Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 07/18] SPEAr : Network support configured for spear SoCs Vipin KUMAR 2010-07-12 7:07 ` [U-Boot] [PATCH v5 06/18] SPEAr : Network " Ben Warren 0 siblings, 2 replies; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> Designware network driver support added. This is a Synopsys ethernet controller Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- doc/README.designware_eth | 25 ++ drivers/net/Makefile | 1 + drivers/net/designware.c | 531 +++++++++++++++++++++++++++++++++++++++++++++ drivers/net/designware.h | 264 ++++++++++++++++++++++ include/netdev.h | 1 + 5 files changed, 822 insertions(+), 0 deletions(-) create mode 100644 doc/README.designware_eth create mode 100644 drivers/net/designware.c create mode 100644 drivers/net/designware.h diff --git a/doc/README.designware_eth b/doc/README.designware_eth new file mode 100644 index 0000000..25ec6bd --- /dev/null +++ b/doc/README.designware_eth @@ -0,0 +1,25 @@ +This driver supports Designware Ethernet Controller provided by Synopsis. + +The driver is enabled by CONFIG_DESIGNWARE_ETH. + +The driver has been developed and tested on SPEAr platforms. By default, the +MDIO interface works at 100/Full. #defining the below options in board +configuration file changes this behavior. + +Call an subroutine from respective board/.../board.c +designware_initialize(u32 id, ulong base_addr, u32 phy_addr); + +The various options suported by the driver are +1. CONFIG_DW_ALTDESCRIPTOR + Define this to use the Alternate/Enhanced Descriptor configurations. +1. CONFIG_DW_AUTONEG + Define this to autonegotiate with the host before proceeding with mac + level configuration. This obviates the definitions of CONFIG_DW_SPEED10M + and CONFIG_DW_DUPLEXHALF. +2. CONFIG_DW_SPEED10M + Define this to change the default behavior from 100Mbps to 10Mbps. +3. CONFIG_DW_DUPLEXHALF + Define this to change the default behavior from Full Duplex to Half. +4. CONFIG_DW_SEARCH_PHY + Define this to search the phy address. This would overwrite the value + passed as 3rd arg from designware_initialize routine. diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b75c02f..7a320fd 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o COBJS-$(CONFIG_CS8900) += cs8900.o COBJS-$(CONFIG_TULIP) += dc2114x.o +COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o COBJS-$(CONFIG_DNET) += dnet.o COBJS-$(CONFIG_E1000) += e1000.o diff --git a/drivers/net/designware.c b/drivers/net/designware.c new file mode 100644 index 0000000..d0d9827 --- /dev/null +++ b/drivers/net/designware.c @@ -0,0 +1,531 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Designware ethernet IP driver for u-boot + */ + +#include <common.h> +#include <miiphy.h> +#include <malloc.h> +#include <linux/err.h> +#include <asm/io.h> +#include "designware.h" + +static void tx_descs_init(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; + char *txbuffs = &priv->txbuffs[0]; + struct dmamacdescr *desc_p; + u32 idx; + + for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->dmamac_next = &desc_table_p[idx + 1]; + +#if defined(CONFIG_DW_ALTDESCRIPTOR) + desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | + DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \ + DESC_TXSTS_TXCHECKINSCTRL | \ + DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); + + desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; + desc_p->dmamac_cntl = 0; + desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); +#else + desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; + desc_p->txrx_status = 0; +#endif + } + + /* Correcting the last pointer of the chain */ + desc_p->dmamac_next = &desc_table_p[0]; + + writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); +} + +static void rx_descs_init(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; + char *rxbuffs = &priv->rxbuffs[0]; + struct dmamacdescr *desc_p; + u32 idx; + + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; + desc_p->dmamac_next = &desc_table_p[idx + 1]; + + desc_p->dmamac_cntl = + (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \ + DESC_RXCTRL_RXCHAIN; + + desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; + } + + /* Correcting the last pointer of the chain */ + desc_p->dmamac_next = &desc_table_p[0]; + + writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); +} + +static void descs_init(struct eth_device *dev) +{ + tx_descs_init(dev); + rx_descs_init(dev); +} + +static int mac_reset(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + + int timeout = CONFIG_MACRESET_TIMEOUT; + + writel(DMAMAC_SRST, &dma_p->busmode); + writel(MII_PORTSELECT, &mac_p->conf); + + do { + if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) + return 0; + udelay(1000); + } while (timeout--); + + return -1; +} + +static int dw_write_hwaddr(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 macid_lo, macid_hi; + u8 *mac_id = &dev->enetaddr[0]; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + \ + (mac_id[2] << 16) + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; +} + +static int dw_eth_init(struct eth_device *dev, bd_t *bis) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 conf; + + /* Reset ethernet hardware */ + if (mac_reset(dev) < 0) + return -1; + + writel(FIXEDBURST | PRIORXTX_41 | BURST_16, + &dma_p->busmode); + + writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode); + writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode); + + conf = FRAMEBURSTENABLE | DISABLERXOWN; + + if (priv->speed != SPEED_1000M) + conf |= MII_PORTSELECT; + + if (priv->duplex == FULL_DUPLEX) + conf |= FULLDPLXMODE; + + writel(conf, &mac_p->conf); + + descs_init(dev); + + /* + * Start/Enable xfer at dma as well as mac level + */ + writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); + writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); + + writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf); + writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf); + + return 0; +} + +static int dw_eth_send(struct eth_device *dev, volatile void *packet, + int length) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 desc_num = priv->tx_currdescnum; + struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; + + /* Check if the descriptor is owned by CPU */ + if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { + printf("CPU not owner of tx frame\n"); + return -1; + } + + memcpy((void *)desc_p->dmamac_addr, (void *)packet, length); + +#if defined(CONFIG_DW_ALTDESCRIPTOR) + desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; + desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ + DESC_TXCTRL_SIZE1MASK; + + desc_p->txrx_status &= ~(DESC_TXSTS_MSK); + desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; +#else + desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \ + DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \ + DESC_TXCTRL_TXFIRST; + + desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; +#endif + + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_TX_DESCR_NUM) + desc_num = 0; + + priv->tx_currdescnum = desc_num; + + /* Start the transmission */ + writel(POLL_DATA, &dma_p->txpolldemand); + + return 0; +} + +static int dw_eth_recv(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + u32 desc_num = priv->rx_currdescnum; + struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; + + u32 status = desc_p->txrx_status; + int length = 0; + + /* Check if the owner is the CPU */ + if (!(status & DESC_RXSTS_OWNBYDMA)) { + + length = (status & DESC_RXSTS_FRMLENMSK) >> \ + DESC_RXSTS_FRMLENSHFT; + + NetReceive(desc_p->dmamac_addr, length); + + /* + * Make the current descriptor valid again and go to + * the next one + */ + desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; + + /* Test the wrap-around condition. */ + if (++desc_num >= CONFIG_RX_DESCR_NUM) + desc_num = 0; + } + + priv->rx_currdescnum = desc_num; + + return length; +} + +static void dw_eth_halt(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + + mac_reset(dev); + priv->tx_currdescnum = priv->rx_currdescnum = 0; +} + +static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ + ((reg << MIIREGSHIFT) & MII_REGMSK); + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + do { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + *val = readl(&mac_p->miidata); + return 0; + } + udelay(1000); + } while (timeout--); + + return -1; +} + +static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) +{ + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 miiaddr; + int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; + u16 value; + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + do { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + ret = 0; + udelay(1000); + } while (timeout--); + + /* Needed as a fix for ST-Phy */ + eth_mdio_read(dev, addr, reg, &value); + + return ret; +} + +#if defined(CONFIG_DW_SEARCH_PHY) +static int find_phy(struct eth_device *dev) +{ + int phy_addr = 0; + u16 ctrl, oldctrl; + + do { + eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); + oldctrl = ctrl & PHY_BMCR_AUTON; + + ctrl ^= PHY_BMCR_AUTON; + eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl); + eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); + ctrl &= PHY_BMCR_AUTON; + + if (ctrl == oldctrl) { + phy_addr++; + } else { + ctrl ^= PHY_BMCR_AUTON; + eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl); + + return phy_addr; + } + } while (phy_addr < 32); + + return -1; +} +#endif + +static int dw_reset_phy(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + u16 ctrl; + int timeout = CONFIG_PHYRESET_TIMEOUT; + u32 phy_addr = priv->address; + + eth_mdio_write(dev, phy_addr, PHY_BMCR, PHY_BMCR_RESET); + do { + eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl); + if (!(ctrl & PHY_BMCR_RESET)) + break; + udelay(1000); + } while (timeout--); + + if (timeout < 0) + return -1; + +#ifdef CONFIG_PHY_RESET_DELAY + udelay(CONFIG_PHY_RESET_DELAY); +#endif + return 0; +} + +static int configure_phy(struct eth_device *dev) +{ + struct dw_eth_dev *priv = dev->priv; + int phy_addr; + u16 bmcr, ctrl; +#if defined(CONFIG_DW_AUTONEG) + u16 bmsr; + u32 timeout; + u16 anlpar, btsr; +#endif + +#if defined(CONFIG_DW_SEARCH_PHY) + phy_addr = find_phy(dev); + if (phy_addr > 0) + priv->address = phy_addr; + else + return -1; +#endif + if (dw_reset_phy(dev) < 0) + return -1; + +#if defined(CONFIG_DW_AUTONEG) + bmcr = PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | PHY_BMCR_100MB | \ + PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS; +#else + bmcr = PHY_BMCR_100MB | PHY_BMCR_DPLX; + +#if defined(CONFIG_DW_SPEED10M) + bmcr &= ~PHY_BMCR_100MB; +#endif +#if defined(CONFIG_DW_DUPLEXHALF) + bmcr &= ~PHY_BMCR_DPLX; +#endif +#endif + if (eth_mdio_write(dev, phy_addr, PHY_BMCR, bmcr) < 0) + return -1; + + /* Read the phy status register and populate priv structure */ +#if defined(CONFIG_DW_AUTONEG) + timeout = CONFIG_AUTONEG_TIMEOUT; + do { + eth_mdio_read(dev, phy_addr, PHY_BMSR, &bmsr); + if (bmsr & PHY_BMSR_AUTN_COMP) + break; + udelay(1000); + } while (timeout--); + + eth_mdio_read(dev, phy_addr, PHY_ANLPAR, &anlpar); + eth_mdio_read(dev, phy_addr, PHY_1000BTSR, &btsr); + + if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) { + priv->speed = SPEED_1000M; + if (btsr & PHY_1000BTSR_1000FD) + priv->duplex = FULL_DUPLEX; + else + priv->duplex = HALF_DUPLEX; + } else { + if (anlpar & PHY_ANLPAR_100) + priv->speed = SPEED_100M; + else + priv->speed = SPEED_10M; + + if (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) + priv->duplex = FULL_DUPLEX; + else + priv->duplex = HALF_DUPLEX; + } +#else + if (eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl) < 0) + return -1; + + if (ctrl & PHY_BMCR_DPLX) + priv->duplex = FULL_DUPLEX; + else + priv->duplex = HALF_DUPLEX; + + if (ctrl & PHY_BMCR_1000_MBPS) + priv->speed = SPEED_1000M; + else if (ctrl & PHY_BMCR_100_MBPS) + priv->speed = SPEED_100M; + else + priv->speed = SPEED_10M; +#endif + return 0; +} + +#if defined(CONFIG_MII) +static int dw_mii_read(char *devname, u8 addr, u8 reg, u16 *val) +{ + struct eth_device *dev; + + dev = eth_get_dev_by_name(devname); + if (dev) + eth_mdio_read(dev, addr, reg, val); + + return 0; +} + +static int dw_mii_write(char *devname, u8 addr, u8 reg, u16 val) +{ + struct eth_device *dev; + + dev = eth_get_dev_by_name(devname); + if (dev) + eth_mdio_write(dev, addr, reg, val); + + return 0; +} +#endif + +int designware_initialize(u32 id, ulong base_addr, u32 phy_addr) +{ + struct eth_device *dev; + struct dw_eth_dev *priv; + + dev = (struct eth_device *) malloc(sizeof(struct eth_device)); + if (!dev) + return -ENOMEM; + + /* + * Since the priv structure contains the descriptors which need a strict + * buswidth alignment, memalign is used to allocate memory + */ + priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev)); + if (!priv) { + free(dev); + return -ENOMEM; + } + + memset(dev, 0, sizeof(struct eth_device)); + memset(priv, 0, sizeof(struct dw_eth_dev)); + + sprintf(dev->name, "mii%d", id); + dev->iobase = (int)base_addr; + dev->priv = priv; + + eth_getenv_enetaddr_by_index(id, &dev->enetaddr[0]); + + priv->dev = dev; + priv->mac_regs_p = (struct eth_mac_regs *)base_addr; + priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + + DW_DMA_BASE_OFFSET); + priv->address = phy_addr; + + if (mac_reset(dev) < 0) + return -1; + + if (configure_phy(dev) < 0) { + printf("Phy could not be configured\n"); + return -1; + } + + dev->init = dw_eth_init; + dev->send = dw_eth_send; + dev->recv = dw_eth_recv; + dev->halt = dw_eth_halt; + dev->write_hwaddr = dw_write_hwaddr; + + eth_register(dev); + +#if defined(CONFIG_MII) + miiphy_register(dev->name, dw_mii_read, dw_mii_write); +#endif + return 1; +} diff --git a/drivers/net/designware.h b/drivers/net/designware.h new file mode 100644 index 0000000..e5828a6 --- /dev/null +++ b/drivers/net/designware.h @@ -0,0 +1,264 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DW_ETH_H +#define _DW_ETH_H + +#define CONFIG_TX_DESCR_NUM 16 +#define CONFIG_RX_DESCR_NUM 16 +#define CONFIG_ETH_BUFSIZE 2048 +#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) +#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) + +#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ) + +struct eth_mac_regs { + u32 conf; /* 0x00 */ + u32 framefilt; /* 0x04 */ + u32 hashtablehigh; /* 0x08 */ + u32 hashtablelow; /* 0x0c */ + u32 miiaddr; /* 0x10 */ + u32 miidata; /* 0x14 */ + u32 flowcontrol; /* 0x18 */ + u32 vlantag; /* 0x1c */ + u32 version; /* 0x20 */ + u8 reserved_1[20]; + u32 intreg; /* 0x38 */ + u32 intmask; /* 0x3c */ + u32 macaddr0hi; /* 0x40 */ + u32 macaddr0lo; /* 0x44 */ +}; + +/* MAC configuration register definitions */ +#define FRAMEBURSTENABLE (1 << 21) +#define MII_PORTSELECT (1 << 15) +#define FES_100 (1 << 14) +#define DISABLERXOWN (1 << 13) +#define FULLDPLXMODE (1 << 11) +#define RXENABLE (1 << 2) +#define TXENABLE (1 << 3) + +/* MII address register definitions */ +#define MII_BUSY (1 << 0) +#define MII_WRITE (1 << 1) +#define MII_CLKRANGE_60_100M (0) +#define MII_CLKRANGE_100_150M (0x4) +#define MII_CLKRANGE_20_35M (0x8) +#define MII_CLKRANGE_35_60M (0xC) +#define MII_CLKRANGE_150_250M (0x10) +#define MII_CLKRANGE_250_300M (0x14) + +#define MIIADDRSHIFT (11) +#define MIIREGSHIFT (6) +#define MII_REGMSK (0x1F << 6) +#define MII_ADDRMSK (0x1F << 11) + + +struct eth_dma_regs { + u32 busmode; /* 0x00 */ + u32 txpolldemand; /* 0x04 */ + u32 rxpolldemand; /* 0x08 */ + u32 rxdesclistaddr; /* 0x0c */ + u32 txdesclistaddr; /* 0x10 */ + u32 status; /* 0x14 */ + u32 opmode; /* 0x18 */ + u32 intenable; /* 0x1c */ + u8 reserved[40]; + u32 currhosttxdesc; /* 0x48 */ + u32 currhostrxdesc; /* 0x4c */ + u32 currhosttxbuffaddr; /* 0x50 */ + u32 currhostrxbuffaddr; /* 0x54 */ +}; + +#define DW_DMA_BASE_OFFSET (0x1000) + +/* Bus mode register definitions */ +#define FIXEDBURST (1 << 16) +#define PRIORXTX_41 (3 << 14) +#define PRIORXTX_31 (2 << 14) +#define PRIORXTX_21 (1 << 14) +#define PRIORXTX_11 (0 << 14) +#define BURST_1 (1 << 8) +#define BURST_2 (2 << 8) +#define BURST_4 (4 << 8) +#define BURST_8 (8 << 8) +#define BURST_16 (16 << 8) +#define BURST_32 (32 << 8) +#define RXHIGHPRIO (1 << 1) +#define DMAMAC_SRST (1 << 0) + +/* Poll demand definitions */ +#define POLL_DATA (0xFFFFFFFF) + +/* Operation mode definitions */ +#define STOREFORWARD (1 << 21) +#define FLUSHTXFIFO (1 << 20) +#define TXSTART (1 << 13) +#define TXSECONDFRAME (1 << 2) +#define RXSTART (1 << 1) + +/* Descriptior related definitions */ +#define MAC_MAX_FRAME_SZ (2048) + +struct dmamacdescr { + u32 txrx_status; + u32 dmamac_cntl; + void *dmamac_addr; + struct dmamacdescr *dmamac_next; +}; + +/* + * txrx_status definitions + */ + +/* tx status bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_TXSTS_OWNBYDMA (1 << 31) +#define DESC_TXSTS_TXINT (1 << 30) +#define DESC_TXSTS_TXLAST (1 << 29) +#define DESC_TXSTS_TXFIRST (1 << 28) +#define DESC_TXSTS_TXCRCDIS (1 << 27) + +#define DESC_TXSTS_TXPADDIS (1 << 26) +#define DESC_TXSTS_TXCHECKINSCTRL (3 << 22) +#define DESC_TXSTS_TXRINGEND (1 << 21) +#define DESC_TXSTS_TXCHAIN (1 << 20) +#define DESC_TXSTS_MSK (0x1FFFF << 0) + +#else + +#define DESC_TXSTS_OWNBYDMA (1 << 31) +#define DESC_TXSTS_MSK (0x1FFFF << 0) + +#endif + +/* rx status bits definitions */ +#define DESC_RXSTS_OWNBYDMA (1 << 31) +#define DESC_RXSTS_DAFILTERFAIL (1 << 30) +#define DESC_RXSTS_FRMLENMSK (0x3FFF << 16) +#define DESC_RXSTS_FRMLENSHFT (16) + +#define DESC_RXSTS_ERROR (1 << 15) +#define DESC_RXSTS_RXTRUNCATED (1 << 14) +#define DESC_RXSTS_SAFILTERFAIL (1 << 13) +#define DESC_RXSTS_RXIPC_GIANTFRAME (1 << 12) +#define DESC_RXSTS_RXDAMAGED (1 << 11) +#define DESC_RXSTS_RXVLANTAG (1 << 10) +#define DESC_RXSTS_RXFIRST (1 << 9) +#define DESC_RXSTS_RXLAST (1 << 8) +#define DESC_RXSTS_RXIPC_GIANT (1 << 7) +#define DESC_RXSTS_RXCOLLISION (1 << 6) +#define DESC_RXSTS_RXFRAMEETHER (1 << 5) +#define DESC_RXSTS_RXWATCHDOG (1 << 4) +#define DESC_RXSTS_RXMIIERROR (1 << 3) +#define DESC_RXSTS_RXDRIBBLING (1 << 2) +#define DESC_RXSTS_RXCRC (1 << 1) + +/* + * dmamac_cntl definitions + */ + +/* tx control bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_TXCTRL_SIZE1MASK (0x1FFF << 0) +#define DESC_TXCTRL_SIZE1SHFT (0) +#define DESC_TXCTRL_SIZE2MASK (0x1FFF << 16) +#define DESC_TXCTRL_SIZE2SHFT (16) + +#else + +#define DESC_TXCTRL_TXINT (1 << 31) +#define DESC_TXCTRL_TXLAST (1 << 30) +#define DESC_TXCTRL_TXFIRST (1 << 29) +#define DESC_TXCTRL_TXCHECKINSCTRL (3 << 27) +#define DESC_TXCTRL_TXCRCDIS (1 << 26) +#define DESC_TXCTRL_TXRINGEND (1 << 25) +#define DESC_TXCTRL_TXCHAIN (1 << 24) + +#define DESC_TXCTRL_SIZE1MASK (0x7FF << 0) +#define DESC_TXCTRL_SIZE1SHFT (0) +#define DESC_TXCTRL_SIZE2MASK (0x7FF << 11) +#define DESC_TXCTRL_SIZE2SHFT (11) + +#endif + +/* rx control bits definitions */ +#if defined(CONFIG_DW_ALTDESCRIPTOR) + +#define DESC_RXCTRL_RXINTDIS (1 << 31) +#define DESC_RXCTRL_RXRINGEND (1 << 15) +#define DESC_RXCTRL_RXCHAIN (1 << 14) + +#define DESC_RXCTRL_SIZE1MASK (0x1FFF << 0) +#define DESC_RXCTRL_SIZE1SHFT (0) +#define DESC_RXCTRL_SIZE2MASK (0x1FFF << 16) +#define DESC_RXCTRL_SIZE2SHFT (16) + +#else + +#define DESC_RXCTRL_RXINTDIS (1 << 31) +#define DESC_RXCTRL_RXRINGEND (1 << 25) +#define DESC_RXCTRL_RXCHAIN (1 << 24) + +#define DESC_RXCTRL_SIZE1MASK (0x7FF << 0) +#define DESC_RXCTRL_SIZE1SHFT (0) +#define DESC_RXCTRL_SIZE2MASK (0x7FF << 11) +#define DESC_RXCTRL_SIZE2SHFT (11) + +#endif + +struct dw_eth_dev { + u32 address; + u32 speed; + u32 duplex; + u32 tx_currdescnum; + u32 rx_currdescnum; + u32 padding; + + struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; + struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; + + char txbuffs[TX_TOTAL_BUFSIZE]; + char rxbuffs[RX_TOTAL_BUFSIZE]; + + struct eth_mac_regs *mac_regs_p; + struct eth_dma_regs *dma_regs_p; + + struct eth_device *dev; +} __attribute__ ((aligned(8))); + +/* Speed specific definitions */ +#define SPEED_10M 1 +#define SPEED_100M 2 +#define SPEED_1000M 3 + +/* Duplex mode specific definitions */ +#define HALF_DUPLEX 1 +#define FULL_DUPLEX 2 + +#endif diff --git a/include/netdev.h b/include/netdev.h index 882642a..3abc944 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -49,6 +49,7 @@ int bfin_EMAC_initialize(bd_t *bis); int cs8900_initialize(u8 dev_num, int base_addr); int dc21x4x_initialize(bd_t *bis); int davinci_emac_initialize(void); +int designware_initialize(u32 id, ulong base_addr, u32 phy_addr); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis); -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 07/18] SPEAr : Network support configured for spear SoCs 2010-06-29 5:23 ` [U-Boot] [PATCH v5 06/18] SPEAr : Network driver support added Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 08/18] SPEAr : macb driver support added for spear310 and spear320 Vipin KUMAR 2010-07-12 7:07 ` [U-Boot] [PATCH v5 06/18] SPEAr : Network " Ben Warren 1 sibling, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- arch/arm/include/asm/arch-spear/hardware.h | 1 + board/spear/spear300/spear300.c | 11 +++++++++++ board/spear/spear310/spear310.c | 11 +++++++++++ board/spear/spear320/spear320.c | 11 +++++++++++ board/spear/spear600/spear600.c | 11 +++++++++++ include/configs/spear-common.h | 14 ++++++++++++-- include/configs/spear3xx.h | 3 +++ 7 files changed, 60 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 818f36c..39d64b6 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -31,6 +31,7 @@ #define CONFIG_SPEAR_SYSCNTLBASE (0xFCA00000) #define CONFIG_SPEAR_TIMERBASE (0xFC800000) #define CONFIG_SPEAR_MISCBASE (0xFCA80000) +#define CONFIG_SPEAR_ETHBASE (0xE0800000) #define CONFIG_SYS_NAND_CLE (1 << 16) #define CONFIG_SYS_NAND_ALE (1 << 17) diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index 60ee544..744a17b 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -22,6 +22,7 @@ */ #include <common.h> +#include <netdev.h> #include <nand.h> #include <asm/io.h> #include <asm/arch/hardware.h> @@ -56,3 +57,13 @@ int board_nand_init(struct nand_chip *nand) return -1; } + +int board_eth_init(bd_t *bis) +{ + int ret = 0; +#if defined(CONFIG_DESIGNWARE_ETH) + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) >= 0) + ret++; +#endif + return ret; +} diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 03dfe16..666ed48 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -23,6 +23,7 @@ */ #include <common.h> +#include <netdev.h> #include <nand.h> #include <asm/io.h> #include <asm/arch/hardware.h> @@ -57,3 +58,13 @@ int board_nand_init(struct nand_chip *nand) return -1; } + +int board_eth_init(bd_t *bis) +{ + int ret = 0; +#if defined(CONFIG_DESIGNWARE_ETH) + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) >= 0) + ret++; +#endif + return ret; +} diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 2ba2dbb..89b074a 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -23,6 +23,7 @@ */ #include <common.h> +#include <netdev.h> #include <nand.h> #include <asm/io.h> #include <asm/arch/hardware.h> @@ -57,3 +58,13 @@ int board_nand_init(struct nand_chip *nand) return -1; } + +int board_eth_init(bd_t *bis) +{ + int ret = 0; +#if defined(CONFIG_DESIGNWARE_ETH) + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) >= 0) + ret++; +#endif + return ret; +} diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index eef9a37..759b4fa 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -22,6 +22,7 @@ */ #include <common.h> +#include <netdev.h> #include <nand.h> #include <asm/io.h> #include <asm/arch/hardware.h> @@ -51,3 +52,13 @@ int board_nand_init(struct nand_chip *nand) return -1; } + +int board_eth_init(bd_t *bis) +{ + int ret = 0; +#if defined(CONFIG_DESIGNWARE_ETH) + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) >= 0) + ret++; +#endif + return ret; +} diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 10beef7..1398837 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -27,6 +27,14 @@ * Common configurations used for both spear3xx as well as spear6xx */ +/* Ethernet driver configuration */ +#define CONFIG_MII +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_DW0_PHY 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_RESET_DELAY (10000) /* in usec */ + /* USBD driver configuration */ #define CONFIG_SPEARUDC #define CONFIG_USB_DEVICE @@ -99,11 +107,13 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_RUN #define CONFIG_CMD_SAVES +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP /* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <config_cmd_default.h> -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS /* * Default Environment Varible definitions diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index 0248aba..502c50f 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -41,6 +41,9 @@ #include <configs/spear-common.h> +/* Ethernet driver configuration */ +#define CONFIG_DW_ALTDESCRIPTOR 1 + /* Serial Configuration (PL011) */ #define CONFIG_SYS_SERIAL0 0xD0000000 -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 08/18] SPEAr : macb driver support added for spear310 and spear320 2010-06-29 5:23 ` [U-Boot] [PATCH v5 07/18] SPEAr : Network support configured for spear SoCs Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 09/18] SPEAr : FSMC driver support added Vipin KUMAR 0 siblings, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> SPEAr310 and SPEAr320 SoCs have an extra ethernet controller. The driver for this device is already supported by u-boot, so configuring board configuration file and defining base addresses etc to make use of the common driver Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- arch/arm/include/asm/arch-spear/clk.h | 27 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-spear/hardware.h | 7 +++++++ board/spear/spear310/spear310.c | 17 +++++++++++++++++ board/spear/spear320/spear320.c | 5 +++++ include/configs/spear3xx.h | 13 +++++++++++++ 5 files changed, 69 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-spear/clk.h diff --git a/arch/arm/include/asm/arch-spear/clk.h b/arch/arm/include/asm/arch-spear/clk.h new file mode 100644 index 0000000..a45ec18 --- /dev/null +++ b/arch/arm/include/asm/arch-spear/clk.h @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return 83000000; +} diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 39d64b6..9f1e154 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -56,6 +56,11 @@ #define CONFIG_SPEAR_EMIBASE (0x4F000000) #define CONFIG_SPEAR_RASBASE (0xB4000000) +#define CONFIG_SYS_MACB0_BASE (0xB0000000) +#define CONFIG_SYS_MACB1_BASE (0xB0800000) +#define CONFIG_SYS_MACB2_BASE (0xB1000000) +#define CONFIG_SYS_MACB3_BASE (0xB1800000) + #elif defined(CONFIG_SPEAR320) #define CONFIG_SYS_I2C_BASE (0xD0180000) #define CONFIG_SPEAR_FSMCBASE (0x4C000000) @@ -63,5 +68,7 @@ #define CONFIG_SPEAR_EMIBASE (0x40000000) #define CONFIG_SPEAR_RASBASE (0xB3000000) +#define CONFIG_SYS_MACB0_BASE (0xAA000000) + #endif #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 666ed48..193fa0c 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -66,5 +66,22 @@ int board_eth_init(bd_t *bis) if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) >= 0) ret++; #endif +#if defined(CONFIG_MACB) + if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, + CONFIG_MACB0_PHY) >= 0) + ret++; + + if (macb_eth_initialize(1, (void *)CONFIG_SYS_MACB1_BASE, + CONFIG_MACB1_PHY) >= 0) + ret++; + + if (macb_eth_initialize(2, (void *)CONFIG_SYS_MACB2_BASE, + CONFIG_MACB2_PHY) >= 0) + ret++; + + if (macb_eth_initialize(3, (void *)CONFIG_SYS_MACB3_BASE, + CONFIG_MACB3_PHY) >= 0) + ret++; +#endif return ret; } diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 89b074a..0d9eed4 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -66,5 +66,10 @@ int board_eth_init(bd_t *bis) if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) >= 0) ret++; #endif +#if defined(CONFIG_MACB) + if (macb_eth_initialize(0, (void *)CONFIG_SYS_MACB0_BASE, + CONFIG_MACB0_PHY) >= 0) + ret++; +#endif return ret; } diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index 502c50f..689d914 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -44,6 +44,19 @@ /* Ethernet driver configuration */ #define CONFIG_DW_ALTDESCRIPTOR 1 +#if defined(CONFIG_SPEAR310) +#define CONFIG_MACB 1 +#define CONFIG_MACB0_PHY 0x01 +#define CONFIG_MACB1_PHY 0x03 +#define CONFIG_MACB2_PHY 0x05 +#define CONFIG_MACB3_PHY 0x07 + +#elif defined(CONFIG_SPEAR320) +#define CONFIG_MACB 1 +#define CONFIG_MACB0_PHY 0x01 + +#endif + /* Serial Configuration (PL011) */ #define CONFIG_SYS_SERIAL0 0xD0000000 -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 09/18] SPEAr : FSMC driver support added 2010-06-29 5:23 ` [U-Boot] [PATCH v5 08/18] SPEAr : macb driver support added for spear310 and spear320 Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 10/18] SPEAr : Configuring FSMC driver for NAND interface Vipin KUMAR 2010-06-29 18:35 ` [U-Boot] [PATCH v5 09/18] SPEAr : FSMC driver support added Scott Wood 0 siblings, 2 replies; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> Flexible static memory controller is a peripheral provided by ST, which controls the access to NAND chips along with many other memory device chips eg NOR, SRAM. This patch adds the driver support for FSMC controller interfacing with NAND memory. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/fsmc_nand.c | 366 +++++++++++++++++++++++++++++++++++++++++ include/linux/mtd/fsmc_nand.h | 104 ++++++++++++ 3 files changed, 471 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/fsmc_nand.c create mode 100644 include/linux/mtd/fsmc_nand.h diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 28f27da..4c6b54f 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -38,6 +38,7 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o +COBJS-$(CONFIG_NAND_FSMC) += fsmc_nand.o COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c new file mode 100644 index 0000000..39c3213 --- /dev/null +++ b/drivers/mtd/nand/fsmc_nand.c @@ -0,0 +1,366 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/mtd/nand_ecc.h> +#include <linux/mtd/fsmc_nand.h> +#include <asm/arch/hardware.h> + +static u32 fsmc_version; +static struct fsmc_regs *const fsmc_regs_p = + (struct fsmc_regs *)CONFIG_SYS_FSMC_BASE; + +/* + * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of + * data. ECC4 can correct up to 8 bits in 512 bytes of data while ECC1 can + * correct 1 bit in 512 bytes + */ + +#if defined(CONFIG_SYS_FSMC_NAND_LP) +static struct nand_ecclayout fsmc_ecc4_layout = { + .eccbytes = 104, + .eccpos = { 2, 3, 4, 5, 6, 7, 8, + 9, 10, 11, 12, 13, 14, + 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, + 34, 35, 36, 37, 38, 39, 40, + 41, 42, 43, 44, 45, 46, + 50, 51, 52, 53, 54, 55, 56, + 57, 58, 59, 60, 61, 62, + 66, 67, 68, 69, 70, 71, 72, + 73, 74, 75, 76, 77, 78, + 82, 83, 84, 85, 86, 87, 88, + 89, 90, 91, 92, 93, 94, + 98, 99, 100, 101, 102, 103, 104, + 105, 106, 107, 108, 109, 110, + 114, 115, 116, 117, 118, 119, 120, + 121, 122, 123, 124, 125, 126 + }, + .oobfree = { + {.offset = 15, .length = 3}, + {.offset = 31, .length = 3}, + {.offset = 47, .length = 3}, + {.offset = 63, .length = 3}, + {.offset = 79, .length = 3}, + {.offset = 95, .length = 3}, + {.offset = 111, .length = 3}, + {.offset = 127, .length = 1} + } +}; + +/* + * ECC placement definitions in oobfree type format + * There are 13 bytes of ecc for every 512 byte block and it has to be read + * consecutively and immediately after the 512 byte data block for hardware to + * generate the error bit offsets in 512 byte data + * Managing the ecc bytes in the following way makes it easier for software to + * read ecc bytes consecutive to data bytes. This way is similar to + * oobfree structure maintained already in u-boot nand driver + */ +static struct fsmc_eccplace fsmc_eccpl = { + .eccplace = { + {.offset = 2, .length = 13}, + {.offset = 18, .length = 13}, + {.offset = 34, .length = 13}, + {.offset = 50, .length = 13}, + {.offset = 66, .length = 13}, + {.offset = 82, .length = 13}, + {.offset = 98, .length = 13}, + {.offset = 114, .length = 13} + } +}; + +#elif defined(CONFIG_SYS_FSMC_NAND_SP) +static struct nand_ecclayout fsmc_ecc4_layout = { + .eccbytes = 13, + .eccpos = { 0, 1, 2, 3, 6, 7, 8, + 9, 10, 11, 12, 13, 14 + }, + .oobfree = { + {.offset = 15, .length = 1}, + } +}; + +static struct fsmc_eccplace fsmc_eccpl = { + .eccplace = { + {.offset = 0, .length = 4}, + {.offset = 6, .length = 9} + } +}; + +#else +#error Please define one of CONFIG_SYS_FSMC_NAND_SP or CONFIG_SYS_FSMC_NAND_LP +#endif + +static struct nand_ecclayout fsmc_ecc1_layout = { + .eccbytes = 24, + .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, + 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, + .oobfree = { + {.offset = 8, .length = 8}, + {.offset = 24, .length = 8}, + {.offset = 40, .length = 8}, + {.offset = 56, .length = 8}, + {.offset = 72, .length = 8}, + {.offset = 88, .length = 8}, + {.offset = 104, .length = 8}, + {.offset = 120, .length = 8} + } +}; + +static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + IO_ADDR_W = (ulong)this->IO_ADDR_W; + + IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE); + if (ctrl & NAND_CLE) + IO_ADDR_W |= CONFIG_SYS_NAND_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= CONFIG_SYS_NAND_ALE; + + if (ctrl & NAND_NCE) { + writel(readl(&fsmc_regs_p->pc) | + FSMC_ENABLE, &fsmc_regs_p->pc); + } else { + writel(readl(&fsmc_regs_p->pc) & + ~FSMC_ENABLE, &fsmc_regs_p->pc); + } + this->IO_ADDR_W = (void *)IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int fsmc_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + /* The calculated ecc is actually the correction index in data */ + u16 err_idx[8]; + u64 ecc_data[2]; + u32 num_err, i; + + memcpy(ecc_data, calc_ecc, 13); + + for (i = 0; i < 8; i++) { + if (i == 4) { + err_idx[4] = ((ecc_data[1] & 0x1) << 12) | ecc_data[0]; + ecc_data[1] >>= 1; + continue; + } + err_idx[i] = (ecc_data[i/4] & 0x1FFF); + ecc_data[i/4] >>= 13; + } + + num_err = (readl(&fsmc_regs_p->sts) >> 10) & 0xF; + + if (num_err == 0xF) + return -EBADMSG; + + i = 0; + while (num_err--) { + change_bit(0, &err_idx[i]); + change_bit(1, &err_idx[i]); + + if (err_idx[i] <= 512 * 8) { + change_bit(err_idx[i], dat); + i++; + } + } + return i; +} + +static int fsmc_read_hwecc(struct mtd_info *mtd, + const u_char *data, u_char *ecc) +{ + u_int ecc_tmp; + + switch (fsmc_version) { + case FSMC_VER8: + /* Busy waiting for ecc computation to finish for 512 bytes */ + while (!(readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY)) + ; + + ecc_tmp = readl(&fsmc_regs_p->ecc1); + ecc[0] = (u_char) (ecc_tmp >> 0); + ecc[1] = (u_char) (ecc_tmp >> 8); + ecc[2] = (u_char) (ecc_tmp >> 16); + ecc[3] = (u_char) (ecc_tmp >> 24); + + ecc_tmp = readl(&fsmc_regs_p->ecc2); + ecc[4] = (u_char) (ecc_tmp >> 0); + ecc[5] = (u_char) (ecc_tmp >> 8); + ecc[6] = (u_char) (ecc_tmp >> 16); + ecc[7] = (u_char) (ecc_tmp >> 24); + + ecc_tmp = readl(&fsmc_regs_p->ecc3); + ecc[8] = (u_char) (ecc_tmp >> 0); + ecc[9] = (u_char) (ecc_tmp >> 8); + ecc[10] = (u_char) (ecc_tmp >> 16); + ecc[11] = (u_char) (ecc_tmp >> 24); + + ecc_tmp = readl(&fsmc_regs_p->sts); + ecc[12] = (u_char) (ecc_tmp >> 16); + break; + + default: + ecc_tmp = readl(&fsmc_regs_p->ecc1); + ecc[0] = (u_char) (ecc_tmp >> 0); + ecc[1] = (u_char) (ecc_tmp >> 8); + ecc[2] = (u_char) (ecc_tmp >> 16); + break; + } + + return 0; +} + +void fsmc_enable_hwecc(struct mtd_info *mtd, int mode) +{ + writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCPLEN_256, + &fsmc_regs_p->pc); + writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCEN, + &fsmc_regs_p->pc); + writel(readl(&fsmc_regs_p->pc) | FSMC_ECCEN, + &fsmc_regs_p->pc); +} + +/* + * fsmc_read_page_hwecc + * @mtd: mtd info structure + * @chip: nand chip info structure + * @buf: buffer to store read data + * @page: page number to read + * + * This routine is needed for fsmc verison 8 as reading from NAND chip has to be + * performed in a strict sequence as follows: + * data(512 byte) -> ecc(13 byte) + * After this read, fsmc hardware generates and reports error data bits(upto a + * max of 8 bits) + */ +static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf, int page) +{ + int i, j, s, stat, eccsize = chip->ecc.size; + int eccbytes = chip->ecc.bytes; + int eccsteps = chip->ecc.steps; + uint8_t *p = buf; + uint8_t *ecc_calc = chip->buffers->ecccalc; + uint8_t *ecc_code = chip->buffers->ecccode; + int off, len; + /* + * ecc_oob is intentionally taken as u16. In 16bit devices, we end up + * reading 14 bytes (7 words) from oob. The local array is to maintain + * word alignment + */ + uint16_t ecc_oob[7]; + + for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { + + chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page); + chip->ecc.hwctl(mtd, NAND_ECC_READ); + chip->read_buf(mtd, p, eccsize); + + for (j = 0; j < eccbytes;) { + off = fsmc_eccpl.eccplace[s].offset; + len = fsmc_eccpl.eccplace[s].length; + + /* + * length is intentionally kept a higher multiple of 2 + * to read@least 13 bytes even in case of 16 bit NAND + * devices + */ + len = roundup(len, 2); + chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page); + chip->read_buf(mtd, (uint8_t *)&ecc_oob[j], len); + j += len; + } + + memcpy(&ecc_code[i], ecc_oob, 13); + chip->ecc.calculate(mtd, p, &ecc_calc[i]); + + stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); + if (stat < 0) + mtd->ecc_stats.failed++; + else + mtd->ecc_stats.corrected += stat; + } + + return 0; +} + +int fsmc_nand_init(struct nand_chip *nand) +{ + u32 peripid2 = readl(&fsmc_regs_p->peripid2); + + fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) & + FSMC_REVISION_MSK; +#if defined(CONFIG_SYS_FSMC_NAND_16BIT) + writel(FSMC_DEVWID_16 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, + &fsmc_regs_p->pc); +#elif defined(CONFIG_SYS_FSMC_NAND_8BIT) + writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, + &fsmc_regs_p->pc); +#else +#error Please define CONFIG_SYS_FSMC_NAND_16BIT or CONFIG_SYS_FSMC_NAND_8BIT +#endif + writel(readl(&fsmc_regs_p->pc) | FSMC_TCLR_1 | FSMC_TAR_1, + &fsmc_regs_p->pc); + writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, + &fsmc_regs_p->comm); + writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, + &fsmc_regs_p->attrib); + + nand->options = 0; +#if defined(CONFIG_SYS_FSMC_NAND_16BIT) + nand->options |= NAND_BUSWIDTH_16; +#endif + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.size = 512; + nand->ecc.calculate = fsmc_read_hwecc; + nand->ecc.hwctl = fsmc_enable_hwecc; + nand->cmd_ctrl = fsmc_nand_hwcontrol; + + switch (fsmc_version) { + case FSMC_VER8: + nand->ecc.bytes = 13; + nand->ecc.layout = &fsmc_ecc4_layout; + nand->ecc.correct = fsmc_correct_data; + nand->ecc.read_page = fsmc_read_page_hwecc; + break; + default: + nand->ecc.bytes = 3; + nand->ecc.layout = &fsmc_ecc1_layout; + nand->ecc.correct = nand_correct_data; + break; + } + + return 0; +} diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h new file mode 100644 index 0000000..5eae0cc --- /dev/null +++ b/include/linux/mtd/fsmc_nand.h @@ -0,0 +1,104 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSMC_NAND_H__ +#define __FSMC_NAND_H__ + +struct fsmc_regs { + u8 reserved_1[0x40]; + u32 pc; /* 0x40 */ + u32 sts; /* 0x44 */ + u32 comm; /* 0x48 */ + u32 attrib; /* 0x4c */ + u32 ioata; /* 0x50 */ + u32 ecc1; /* 0x54 */ + u32 ecc2; /* 0x58 */ + u32 ecc3; /* 0x5c */ + u8 reserved_2[0xfe0 - 0x60]; + u32 peripid0; /* 0xfe0 */ + u32 peripid1; /* 0xfe4 */ + u32 peripid2; /* 0xfe8 */ + u32 peripid3; /* 0xfec */ + u32 pcellid0; /* 0xff0 */ + u32 pcellid1; /* 0xff4 */ + u32 pcellid2; /* 0xff8 */ + u32 pcellid3; /* 0xffc */ +}; + +/* pc register definitions */ +#define FSMC_RESET (1 << 0) +#define FSMC_WAITON (1 << 1) +#define FSMC_ENABLE (1 << 2) +#define FSMC_DEVTYPE_NAND (1 << 3) +#define FSMC_DEVWID_8 (0 << 4) +#define FSMC_DEVWID_16 (1 << 4) +#define FSMC_ECCEN (1 << 6) +#define FSMC_ECCPLEN_512 (0 << 7) +#define FSMC_ECCPLEN_256 (1 << 7) +#define FSMC_TCLR_1 (1 << 9) +#define FSMC_TAR_1 (1 << 13) + +/* sts register definitions */ +#define FSMC_CODE_RDY (1 << 15) + +/* comm register definitions */ +#define FSMC_TSET_0 (0 << 0) +#define FSMC_TWAIT_6 (6 << 8) +#define FSMC_THOLD_4 (4 << 16) +#define FSMC_THIZ_1 (1 << 24) + +/* peripid2 register definitions */ +#define FSMC_REVISION_MSK (0xf) +#define FSMC_REVISION_SHFT (0x4) + +enum { + FSMC_VER1 = 1, + FSMC_VER2, + FSMC_VER3, + FSMC_VER4, + FSMC_VER5, + FSMC_VER6, + FSMC_VER7, + FSMC_VER8, +}; + +/* + * There are 13 bytes of ecc for every 512 byte block and it has to be read + * consecutively and immediately after the 512 byte data block for hardware to + * generate the error bit offsets + * Managing the ecc bytes in the following way is easier. This way is similar to + * oobfree structure maintained already in u-boot nand driver + */ +#define MAX_ECCPLACE_ENTRIES 32 + +struct fsmc_nand_eccplace { + u32 offset; + u32 length; +}; + +struct fsmc_eccplace { + struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES]; +}; + +extern int fsmc_nand_init(struct nand_chip *nand); +#endif -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 10/18] SPEAr : Configuring FSMC driver for NAND interface 2010-06-29 5:23 ` [U-Boot] [PATCH v5 09/18] SPEAr : FSMC driver support added Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 11/18] SPEAr : i2c driver moved completely into drivers/i2c Vipin KUMAR 2010-06-29 18:36 ` [U-Boot] [PATCH v5 10/18] SPEAr : Configuring FSMC driver for NAND interface Scott Wood 2010-06-29 18:35 ` [U-Boot] [PATCH v5 09/18] SPEAr : FSMC driver support added Scott Wood 1 sibling, 2 replies; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> Since FSMC is a standard IP and it supports different memory interfaces, it is supported independent of spear platform and spear is configured to use that driver for interfacing with the NAND device Spear platform uses generic FSMC driver and spear specific files i.e drivers/mtd/nand/spr_nand.c, arch/arm/include/asm/arch-spear/spr_nand.h are removed Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- arch/arm/include/asm/arch-spear/hardware.h | 8 +- arch/arm/include/asm/arch-spear/spr_nand.h | 57 ------------- board/spear/spear300/spear300.c | 7 +- board/spear/spear310/spear310.c | 7 +- board/spear/spear320/spear320.c | 7 +- board/spear/spear600/spear600.c | 7 +- drivers/mtd/nand/Makefile | 1 - drivers/mtd/nand/spr_nand.c | 124 ---------------------------- include/configs/spear-common.h | 2 +- include/configs/spear3xx.h | 4 + include/configs/spear6xx.h | 3 + 11 files changed, 28 insertions(+), 199 deletions(-) delete mode 100644 arch/arm/include/asm/arch-spear/spr_nand.h delete mode 100644 drivers/mtd/nand/spr_nand.c diff --git a/arch/arm/include/asm/arch-spear/hardware.h b/arch/arm/include/asm/arch-spear/hardware.h index 9f1e154..52037b6 100644 --- a/arch/arm/include/asm/arch-spear/hardware.h +++ b/arch/arm/include/asm/arch-spear/hardware.h @@ -38,15 +38,15 @@ #if defined(CONFIG_SPEAR600) #define CONFIG_SYS_I2C_BASE (0xD0200000) -#define CONFIG_SPEAR_FSMCBASE (0xD1800000) +#define CONFIG_SYS_FSMC_BASE (0xD1800000) #elif defined(CONFIG_SPEAR300) #define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x94000000) +#define CONFIG_SYS_FSMC_BASE (0x94000000) #elif defined(CONFIG_SPEAR310) #define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x44000000) +#define CONFIG_SYS_FSMC_BASE (0x44000000) #undef CONFIG_SYS_NAND_CLE #undef CONFIG_SYS_NAND_ALE @@ -63,7 +63,7 @@ #elif defined(CONFIG_SPEAR320) #define CONFIG_SYS_I2C_BASE (0xD0180000) -#define CONFIG_SPEAR_FSMCBASE (0x4C000000) +#define CONFIG_SYS_FSMC_BASE (0x4C000000) #define CONFIG_SPEAR_EMIBASE (0x40000000) #define CONFIG_SPEAR_RASBASE (0xB3000000) diff --git a/arch/arm/include/asm/arch-spear/spr_nand.h b/arch/arm/include/asm/arch-spear/spr_nand.h deleted file mode 100644 index 2b63dc7..0000000 --- a/arch/arm/include/asm/arch-spear/spr_nand.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __SPR_NAND_H__ -#define __SPR_NAND_H__ - -struct fsmc_regs { - u32 reserved_1[0x10]; - u32 genmemctrl_pc; - u32 reserved_2; - u32 genmemctrl_comm; - u32 genmemctrl_attrib; - u32 reserved_3; - u32 genmemctrl_ecc; -}; - -/* genmemctrl_pc register definitions */ -#define FSMC_RESET (1 << 0) -#define FSMC_WAITON (1 << 1) -#define FSMC_ENABLE (1 << 2) -#define FSMC_DEVTYPE_NAND (1 << 3) -#define FSMC_DEVWID_8 (0 << 4) -#define FSMC_DEVWID_16 (1 << 4) -#define FSMC_ECCEN (1 << 6) -#define FSMC_ECCPLEN_512 (0 << 7) -#define FSMC_ECCPLEN_256 (1 << 7) -#define FSMC_TCLR_1 (1 << 9) -#define FSMC_TAR_1 (1 << 13) - -/* genmemctrl_comm register definitions */ -#define FSMC_TSET_0 (0 << 0) -#define FSMC_TWAIT_6 (6 << 8) -#define FSMC_THOLD_4 (4 << 16) -#define FSMC_THIZ_1 (1 << 24) - -extern int spear_nand_init(struct nand_chip *nand); -#endif diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index 744a17b..d9f9aca 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -25,10 +25,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h> int board_init(void) { @@ -47,14 +47,15 @@ int board_nand_init(struct nand_chip *nand) struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; +#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) { - return spear_nand_init(nand); + return fsmc_nand_init(nand); } - +#endif return -1; } diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 193fa0c..9543b19 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -26,10 +26,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h> int board_init(void) { @@ -48,14 +48,15 @@ int board_nand_init(struct nand_chip *nand) struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; +#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) { - return spear_nand_init(nand); + return fsmc_nand_init(nand); } - +#endif return -1; } diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index 0d9eed4..77f3bc5 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -26,10 +26,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h> int board_init(void) { @@ -48,14 +48,15 @@ int board_nand_init(struct nand_chip *nand) struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; +#if defined(CONFIG_NAND_FSMC) if (((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG30) || ((readl(&misc_regs_p->auto_cfg_reg) & MISC_SOCCFGMSK) == MISC_SOCCFG31)) { - return spear_nand_init(nand); + return fsmc_nand_init(nand); } - +#endif return -1; } diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index 759b4fa..ec10396 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -25,10 +25,10 @@ #include <netdev.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> #include <asm/arch/hardware.h> #include <asm/arch/spr_defs.h> #include <asm/arch/spr_misc.h> -#include <asm/arch/spr_nand.h> int board_init(void) { @@ -47,9 +47,10 @@ int board_nand_init(struct nand_chip *nand) struct misc_regs *const misc_regs_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; +#if defined(CONFIG_NAND_FSMC) if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) - return spear_nand_init(nand); - + return fsmc_nand_init(nand); +#endif return -1; } diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 4c6b54f..36fc8b3 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -48,7 +48,6 @@ COBJS-$(CONFIG_NAND_NDFC) += ndfc.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o -COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o endif diff --git a/drivers/mtd/nand/spr_nand.c b/drivers/mtd/nand/spr_nand.c deleted file mode 100644 index 097d0c6..0000000 --- a/drivers/mtd/nand/spr_nand.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <nand.h> -#include <linux/mtd/nand_ecc.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/spr_nand.h> - -static struct fsmc_regs *const fsmc_regs_p = - (struct fsmc_regs *)CONFIG_SPEAR_FSMCBASE; - -static struct nand_ecclayout spear_nand_ecclayout = { - .eccbytes = 24, - .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, - 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, - .oobfree = { - {.offset = 8, .length = 8}, - {.offset = 24, .length = 8}, - {.offset = 40, .length = 8}, - {.offset = 56, .length = 8}, - {.offset = 72, .length = 8}, - {.offset = 88, .length = 8}, - {.offset = 104, .length = 8}, - {.offset = 120, .length = 8} - } -}; - -static void spear_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) -{ - struct nand_chip *this = mtd->priv; - ulong IO_ADDR_W; - - if (ctrl & NAND_CTRL_CHANGE) { - IO_ADDR_W = (ulong)this->IO_ADDR_W; - - IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE); - if (ctrl & NAND_CLE) - IO_ADDR_W |= CONFIG_SYS_NAND_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= CONFIG_SYS_NAND_ALE; - - if (ctrl & NAND_NCE) { - writel(readl(&fsmc_regs_p->genmemctrl_pc) | - FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc); - } else { - writel(readl(&fsmc_regs_p->genmemctrl_pc) & - ~FSMC_ENABLE, &fsmc_regs_p->genmemctrl_pc); - } - this->IO_ADDR_W = (void *)IO_ADDR_W; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int spear_read_hwecc(struct mtd_info *mtd, - const u_char *data, u_char ecc[3]) -{ - u_int ecc_tmp; - - /* read the h/w ECC */ - ecc_tmp = readl(&fsmc_regs_p->genmemctrl_ecc); - - ecc[0] = (u_char) (ecc_tmp & 0xFF); - ecc[1] = (u_char) ((ecc_tmp & 0xFF00) >> 8); - ecc[2] = (u_char) ((ecc_tmp & 0xFF0000) >> 16); - - return 0; -} - -void spear_enable_hwecc(struct mtd_info *mtd, int mode) -{ - writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~0x80, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) & ~FSMC_ECCEN, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_ECCEN, - &fsmc_regs_p->genmemctrl_pc); -} - -int spear_nand_init(struct nand_chip *nand) -{ - writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, - &fsmc_regs_p->genmemctrl_pc); - writel(readl(&fsmc_regs_p->genmemctrl_pc) | FSMC_TCLR_1 | FSMC_TAR_1, - &fsmc_regs_p->genmemctrl_pc); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->genmemctrl_comm); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->genmemctrl_attrib); - - nand->options = 0; - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &spear_nand_ecclayout; - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.calculate = spear_read_hwecc; - nand->ecc.hwctl = spear_enable_hwecc; - nand->ecc.correct = nand_correct_data; - nand->cmd_ctrl = spear_nand_hwcontrol; - return 0; -} diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 1398837..a54d534 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -94,7 +94,7 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* NAND FLASH Configuration */ -#define CONFIG_NAND_SPEAR 1 +#define CONFIG_NAND_FSMC 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h index 689d914..fde505c 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx.h @@ -133,6 +133,10 @@ #endif +/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP 1 +#define CONFIG_SYS_FSMC_NAND_8BIT 1 + #if defined(CONFIG_SPEAR300) #define CONFIG_SYS_NAND_BASE (0x80000000) diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx.h index 2ad5beb..2532344 100644 --- a/include/configs/spear6xx.h +++ b/include/configs/spear6xx.h @@ -38,6 +38,9 @@ #define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ (void *)CONFIG_SYS_SERIAL1 } +/* NAND flash configuration */ +#define CONFIG_SYS_FSMC_NAND_SP 1 +#define CONFIG_SYS_FSMC_NAND_8BIT 1 #define CONFIG_SYS_NAND_BASE (0xD2000000) #endif /* __CONFIG_H */ -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 11/18] SPEAr : i2c driver moved completely into drivers/i2c 2010-06-29 5:23 ` [U-Boot] [PATCH v5 10/18] SPEAr : Configuring FSMC driver for NAND interface Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 12/18] SPEAr : smi driver moved completely into drivers/mtd Vipin KUMAR 2010-06-29 18:36 ` [U-Boot] [PATCH v5 10/18] SPEAr : Configuring FSMC driver for NAND interface Scott Wood 1 sibling, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> The earlier i2c driver was specific to spear platforms. This patch implements the i2c controller as a generic driver which can be used by multiple platforms The driver files are now renamed to designware_i2c.c and designware_i2c.h and these are moved into drivers/i2c folder for reusability by other platforms Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- drivers/i2c/Makefile | 2 +- drivers/i2c/{spr_i2c.c => designware_i2c.c} | 4 ++-- .../spr_i2c.h => drivers/i2c/designware_i2c.h | 6 +++--- include/configs/spear-common.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) rename drivers/i2c/{spr_i2c.c => designware_i2c.c} (98%) rename arch/arm/include/asm/arch-spear/spr_i2c.h => drivers/i2c/designware_i2c.h (98%) diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index d2c2515..099a6cd 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libi2c.a COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o +COBJS-$(CONFIG_DW_I2C) += designware_i2c.o COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o COBJS-$(CONFIG_I2C_KIRKWOOD) += kirkwood_i2c.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o @@ -38,7 +39,6 @@ COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o -COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o COBJS := $(COBJS-y) diff --git a/drivers/i2c/spr_i2c.c b/drivers/i2c/designware_i2c.c similarity index 98% rename from drivers/i2c/spr_i2c.c rename to drivers/i2c/designware_i2c.c index eabfe84..d352146 100644 --- a/drivers/i2c/spr_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -24,7 +24,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/spr_i2c.h> +#include "designware_i2c.h" static struct i2c_regs *const i2c_regs_p = (struct i2c_regs *)CONFIG_SYS_I2C_BASE; @@ -113,7 +113,7 @@ int i2c_get_bus_speed(void) /* * i2c_init - Init function * @speed: required i2c speed - * @slaveadd: slave address for the spear device + * @slaveadd: slave address for the device * * Initialization function. */ diff --git a/arch/arm/include/asm/arch-spear/spr_i2c.h b/drivers/i2c/designware_i2c.h similarity index 98% rename from arch/arm/include/asm/arch-spear/spr_i2c.h rename to drivers/i2c/designware_i2c.h index 7521ebc..03b520e 100644 --- a/arch/arm/include/asm/arch-spear/spr_i2c.h +++ b/drivers/i2c/designware_i2c.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */ -#ifndef __SPR_I2C_H_ -#define __SPR_I2C_H_ +#ifndef __DW_I2C_H_ +#define __DW_I2C_H_ struct i2c_regs { u32 ic_con; @@ -143,4 +143,4 @@ struct i2c_regs { #define I2C_FAST_SPEED 400000 #define I2C_STANDARD_SPEED 100000 -#endif /* __SPR_I2C_H_ */ +#endif /* __DW_I2C_H_ */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index a54d534..2393bdf 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -47,7 +47,7 @@ /* I2C driver configuration */ #define CONFIG_HARD_I2C -#define CONFIG_SPEAR_I2C +#define CONFIG_DW_I2C #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x02 -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 12/18] SPEAr : smi driver moved completely into drivers/mtd 2010-06-29 5:23 ` [U-Boot] [PATCH v5 11/18] SPEAr : i2c driver moved completely into drivers/i2c Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 13/18] SPEAr : USB Device Controller driver support added Vipin KUMAR 0 siblings, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> SMI is the serial memory interface controller provided by ST. The earlier driver was specific to spear platform. The driver files are renamed to st_smi.c and st_smi.h and moved into drivers/mtd folder for reusability by other platforms using smi controller peripheral. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- drivers/mtd/Makefile | 2 +- drivers/mtd/{spr_smi.c => st_smi.c} | 2 +- .../arch-spear/spr_smi.h => drivers/mtd/st_smi.h | 4 ++-- include/configs/spear-common.h | 6 +++--- 4 files changed, 7 insertions(+), 7 deletions(-) rename drivers/mtd/{spr_smi.c => st_smi.c} (99%) rename arch/arm/include/asm/arch-spear/spr_smi.h => drivers/mtd/st_smi.h (99%) diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index cbf6f15..d868d27 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -34,7 +34,7 @@ COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o -COBJS-$(CONFIG_SPEARSMI) += spr_smi.o +COBJS-$(CONFIG_ST_SMI) += st_smi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spr_smi.c b/drivers/mtd/st_smi.c similarity index 99% rename from drivers/mtd/spr_smi.c rename to drivers/mtd/st_smi.c index c6ba951..5193c1c 100644 --- a/drivers/mtd/spr_smi.c +++ b/drivers/mtd/st_smi.c @@ -27,7 +27,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/spr_smi.h> +#include "st_smi.h" #if !defined(CONFIG_SYS_NO_FLASH) diff --git a/arch/arm/include/asm/arch-spear/spr_smi.h b/drivers/mtd/st_smi.h similarity index 99% rename from arch/arm/include/asm/arch-spear/spr_smi.h rename to drivers/mtd/st_smi.h index 0cca000..afab546 100644 --- a/arch/arm/include/asm/arch-spear/spr_smi.h +++ b/drivers/mtd/st_smi.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */ -#ifndef SPR_SMI_H -#define SPR_SMI_H +#ifndef ST_SMI_H +#define ST_SMI_H /* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ /* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 2393bdf..4aa0c15 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -61,10 +61,10 @@ #if defined(CONFIG_FLASH_PNOR) #define CONFIG_SPEAR_EMI 1 #else -#define CONFIG_SPEARSMI 1 +#define CONFIG_ST_SMI 1 #endif -#if defined(CONFIG_SPEARSMI) +#if defined(CONFIG_ST_SMI) #define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_BASE (0xF8000000) @@ -130,7 +130,7 @@ * U-Boot Environment placing definitions. */ #if defined(CONFIG_ENV_IS_IN_FLASH) -#ifdef CONFIG_SPEARSMI +#ifdef CONFIG_ST_SMI /* * Environment is in serial NOR flash */ -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 13/18] SPEAr : USB Device Controller driver support added 2010-06-29 5:23 ` [U-Boot] [PATCH v5 12/18] SPEAr : smi driver moved completely into drivers/mtd Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 14/18] SPEAr : Supporting various configurations for spear3xx and spear6xx boards Vipin KUMAR 0 siblings, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> The earlier usb device controller driver was specific to spear platforms. This patch implements the usb device controller driver as a generic controller which can be reused by other platforms using this peripheral. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- drivers/serial/usbtty.h | 4 +- drivers/usb/gadget/Makefile | 2 +- drivers/usb/gadget/{spr_udc.c => designware_udc.c} | 57 ++++++++++---------- include/configs/spear-common.h | 4 +- include/usb/{spr_udc.h => designware_udc.h} | 6 +- 5 files changed, 37 insertions(+), 36 deletions(-) rename drivers/usb/gadget/{spr_udc.c => designware_udc.c} (94%) rename include/usb/{spr_udc.h => designware_udc.h} (98%) diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index a23169a..38b407f 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -33,8 +33,8 @@ #include <usb/musb_udc.h> #elif defined(CONFIG_PXA27X) #include <usb/pxa27x_udc.h> -#elif defined(CONFIG_SPEAR3XX) || defined(CONFIG_SPEAR600) -#include <usb/spr_udc.h> +#elif defined(CONFIG_DW_UDC) +#include <usb/designware_udc.h> #endif #include <version_autogenerated.h> diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 1d7362d..3820f36 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -28,11 +28,11 @@ LIB := $(obj)libusb_gadget.a ifdef CONFIG_USB_DEVICE COBJS-y += core.o COBJS-y += ep0.o +COBJS-$(CONFIG_DW_UDC) += designware_udc.o COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o COBJS-$(CONFIG_PXA27X) += pxa27x_udc.o -COBJS-$(CONFIG_SPEARUDC) += spr_udc.o endif COBJS := $(COBJS-y) diff --git a/drivers/usb/gadget/spr_udc.c b/drivers/usb/gadget/designware_udc.c similarity index 94% rename from drivers/usb/gadget/spr_udc.c rename to drivers/usb/gadget/designware_udc.c index f2b06d6..aee44aa 100644 --- a/drivers/usb/gadget/spr_udc.c +++ b/drivers/usb/gadget/designware_udc.c @@ -29,14 +29,13 @@ #include <usbdevice.h> #include "ep0.h" -#include <usb/spr_udc.h> +#include <usb/designware_udc.h> #include <asm/arch/hardware.h> -#include <asm/arch/spr_misc.h> #define UDC_INIT_MDELAY 80 /* Device settle delay */ /* Some kind of debugging output... */ -#ifndef DEBUG_SPRUSBTTY +#ifndef DEBUG_DWUSBTTY #define UDCDBG(str) #define UDCDBGA(fmt, args...) #else @@ -251,7 +250,7 @@ static void usbputpcktofifo(int epNum, u8 *bufp, u32 len) } /* - * spear_write_noniso_tx_fifo - Write the next packet to TxFIFO. + * dw_write_noniso_tx_fifo - Write the next packet to TxFIFO. * @endpoint: Endpoint pointer. * * If the endpoint has an active tx_urb, then the next packet of data from the @@ -263,7 +262,7 @@ static void usbputpcktofifo(int epNum, u8 *bufp, u32 len) * transmitted in this packet. * */ -static void spear_write_noniso_tx_fifo(struct usb_endpoint_instance +static void dw_write_noniso_tx_fifo(struct usb_endpoint_instance *endpoint) { struct urb *urb = endpoint->tx_urb; @@ -307,7 +306,7 @@ static void spear_write_noniso_tx_fifo(struct usb_endpoint_instance * Handle SETUP USB interrupt. * This function implements TRM Figure 14-14. */ -static void spear_udc_setup(struct usb_endpoint_instance *endpoint) +static void dw_udc_setup(struct usb_endpoint_instance *endpoint) { u8 *datap = (u8 *)&ep0_urb->device_request; int ep_addr = endpoint->endpoint_address; @@ -344,11 +343,11 @@ static void spear_udc_setup(struct usb_endpoint_instance *endpoint) endpoint->tx_urb = ep0_urb; endpoint->sent = 0; /* - * Write packet data to the FIFO. spear_write_noniso_tx_fifo + * Write packet data to the FIFO. dw_write_noniso_tx_fifo * will update endpoint->last with the number of bytes written * to the FIFO. */ - spear_write_noniso_tx_fifo(endpoint); + dw_write_noniso_tx_fifo(endpoint); writel(0x0, &inep_regs_p[ep_addr].write_done); } @@ -361,7 +360,7 @@ static void spear_udc_setup(struct usb_endpoint_instance *endpoint) /* * Handle endpoint 0 RX interrupt */ -static void spear_udc_ep0_rx(struct usb_endpoint_instance *endpoint) +static void dw_udc_ep0_rx(struct usb_endpoint_instance *endpoint) { u8 dummy[64]; @@ -395,7 +394,7 @@ static void spear_udc_ep0_rx(struct usb_endpoint_instance *endpoint) /* * Handle endpoint 0 TX interrupt */ -static void spear_udc_ep0_tx(struct usb_endpoint_instance *endpoint) +static void dw_udc_ep0_tx(struct usb_endpoint_instance *endpoint) { struct usb_device_request *request = &ep0_urb->device_request; int ep_addr; @@ -444,7 +443,7 @@ static void spear_udc_ep0_tx(struct usb_endpoint_instance *endpoint) * need a zero-length terminating packet. */ UDCDBG("ACK control read data stage packet"); - spear_write_noniso_tx_fifo(endpoint); + dw_write_noniso_tx_fifo(endpoint); ep_addr = endpoint->endpoint_address; writel(0x0, &inep_regs_p[ep_addr].write_done); @@ -452,7 +451,7 @@ static void spear_udc_ep0_tx(struct usb_endpoint_instance *endpoint) } } -static struct usb_endpoint_instance *spear_find_ep(int ep) +static struct usb_endpoint_instance *dw_find_ep(int ep) { int i; @@ -469,11 +468,11 @@ static struct usb_endpoint_instance *spear_find_ep(int ep) * The ep argument is a physical endpoint number for a non-ISO IN endpoint * in the range 1 to 15. */ -static void spear_udc_epn_rx(int ep) +static void dw_udc_epn_rx(int ep) { int nbytes = 0; struct urb *urb; - struct usb_endpoint_instance *endpoint = spear_find_ep(ep); + struct usb_endpoint_instance *endpoint = dw_find_ep(ep); if (endpoint) { urb = endpoint->rcv_urb; @@ -494,9 +493,9 @@ static void spear_udc_epn_rx(int ep) * The ep argument is a physical endpoint number for a non-ISO IN endpoint * in the range 16 to 30. */ -static void spear_udc_epn_tx(int ep) +static void dw_udc_epn_tx(int ep) { - struct usb_endpoint_instance *endpoint = spear_find_ep(ep); + struct usb_endpoint_instance *endpoint = dw_find_ep(ep); /* * We need to transmit a terminating zero-length packet now if @@ -516,7 +515,7 @@ static void spear_udc_epn_tx(int ep) */ if (endpoint->tx_urb && endpoint->tx_urb->actual_length) { /* write data to FIFO */ - spear_write_noniso_tx_fifo(endpoint); + dw_write_noniso_tx_fifo(endpoint); writel(0x0, &inep_regs_p[ep].write_done); } else if (endpoint->tx_urb @@ -765,7 +764,7 @@ void udc_startup_events(struct usb_device_instance *device) * DEVICE_HUB_CONFIGURED and DEVICE_RESET events here. * DEVICE_HUB_CONFIGURED causes a transition to the state STATE_POWERED, * and DEVICE_RESET causes a transition to the state STATE_DEFAULT. - * The SPEAr USB client controller has the capability to detect when the + * The DW USB client controller has the capability to detect when the * USB cable is connected to a powered USB bus, so we will defer the * DEVICE_HUB_CONFIGURED and DEVICE_RESET events until later. */ @@ -776,7 +775,7 @@ void udc_startup_events(struct usb_device_instance *device) /* * Plug detection interrupt handling */ -void spear_udc_plug_irq(void) +void dw_udc_plug_irq(void) { if (readl(&plug_regs_p->plug_state) & PLUG_STATUS_ATTACHED) { /* @@ -805,7 +804,7 @@ void spear_udc_plug_irq(void) /* * Device interrupt handling */ -void spear_udc_dev_irq(void) +void dw_udc_dev_irq(void) { if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) { writel(~0x0, &udc_regs_p->endp_int_mask); @@ -870,7 +869,7 @@ void spear_udc_dev_irq(void) /* * Endpoint interrupt handling */ -void spear_udc_endpoint_irq(void) +void dw_udc_endpoint_irq(void) { while (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLOUT) { @@ -878,13 +877,13 @@ void spear_udc_endpoint_irq(void) if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_SETUP) { - spear_udc_setup(udc_device->bus->endpoint_array + 0); + dw_udc_setup(udc_device->bus->endpoint_array + 0); writel(ENDP_STATUS_OUT_SETUP, &outep_regs_p[0].endp_status); } else if ((readl(&outep_regs_p[0].endp_status) & ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) { - spear_udc_ep0_rx(udc_device->bus->endpoint_array + 0); + dw_udc_ep0_rx(udc_device->bus->endpoint_array + 0); writel(ENDP_STATUS_OUT_DATA, &outep_regs_p[0].endp_status); @@ -897,7 +896,7 @@ void spear_udc_endpoint_irq(void) } if (readl(&udc_regs_p->endp_int) & ENDP0_INT_CTRLIN) { - spear_udc_ep0_tx(udc_device->bus->endpoint_array + 0); + dw_udc_ep0_tx(udc_device->bus->endpoint_array + 0); writel(ENDP_STATUS_IN, &inep_regs_p[0].endp_status); writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int); @@ -919,7 +918,7 @@ void spear_udc_endpoint_irq(void) if ((readl(&outep_regs_p[epnum].endp_status) & ENDP_STATUS_OUTMSK) == ENDP_STATUS_OUT_DATA) { - spear_udc_epn_rx(epnum); + dw_udc_epn_rx(epnum); writel(ENDP_STATUS_OUT_DATA, &outep_regs_p[epnum].endp_status); } else if ((readl(&outep_regs_p[epnum].endp_status) & @@ -941,7 +940,7 @@ void spear_udc_endpoint_irq(void) if (readl(&inep_regs_p[epnum].endp_status) & ENDP_STATUS_IN) { writel(ENDP_STATUS_IN, &outep_regs_p[epnum].endp_status); - spear_udc_epn_tx(epnum); + dw_udc_epn_tx(epnum); writel(ENDP_STATUS_IN, &outep_regs_p[epnum].endp_status); @@ -963,13 +962,13 @@ void udc_irq(void) * host requests. */ while (readl(&plug_regs_p->plug_pending)) - spear_udc_plug_irq(); + dw_udc_plug_irq(); while (readl(&udc_regs_p->dev_int)) - spear_udc_dev_irq(); + dw_udc_dev_irq(); if (readl(&udc_regs_p->endp_int)) - spear_udc_endpoint_irq(); + dw_udc_endpoint_irq(); } /* Flow control */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 4aa0c15..c03520b 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -36,14 +36,16 @@ #define CONFIG_PHY_RESET_DELAY (10000) /* in usec */ /* USBD driver configuration */ -#define CONFIG_SPEARUDC +#define CONFIG_DW_UDC #define CONFIG_USB_DEVICE #define CONFIG_USB_TTY #define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" #define CONFIG_USBD_MANUFACTURER "ST Microelectronics" +#if defined(CONFIG_USB_TTY) #define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" +#endif /* I2C driver configuration */ #define CONFIG_HARD_I2C diff --git a/include/usb/spr_udc.h b/include/usb/designware_udc.h similarity index 98% rename from include/usb/spr_udc.h rename to include/usb/designware_udc.h index 2c332d5..ae98e8c 100644 --- a/include/usb/spr_udc.h +++ b/include/usb/designware_udc.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */ -#ifndef __SPR_UDC_H -#define __SPR_UDC_H +#ifndef __DW_UDC_H +#define __DW_UDC_H /* * Defines for USBD @@ -227,4 +227,4 @@ void udc_startup_events(struct usb_device_instance *device); void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, struct usb_endpoint_instance *endpoint); -#endif /* __SPR_UDC_H */ +#endif /* __DW_UDC_H */ -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 14/18] SPEAr : Supporting various configurations for spear3xx and spear6xx boards 2010-06-29 5:23 ` [U-Boot] [PATCH v5 13/18] SPEAr : USB Device Controller driver support added Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 15/18] SPEAr : Basic spear1300 architecture support added Vipin KUMAR 0 siblings, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> spear3xx and 6xx boards can be compiled in following configurations 1. Environment placed in NAND 2. console on usb device 3. console on usb device with environment placed in NAND Also, renaming the include/configs/spearxxx.h files to spear3xx_evb.h, spear6xx_evb.h etc to depict evaluation board configuration. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- Makefile | 22 +++++++++++++---- board/spear/spear300/config.mk | 11 -------- board/spear/spear310/config.mk | 11 -------- board/spear/spear320/config.mk | 11 -------- board/spear/spear600/config.mk | 11 -------- doc/README.spear | 31 +++++++++++++++++------- include/configs/{spear3xx.h => spear3xx_evb.h} | 10 +++++++ include/configs/{spear6xx.h => spear6xx_evb.h} | 10 +++++++ 8 files changed, 59 insertions(+), 58 deletions(-) rename include/configs/{spear3xx.h => spear3xx_evb.h} (95%) rename include/configs/{spear6xx.h => spear6xx_evb.h} (88%) diff --git a/Makefile b/Makefile index 87d5214..f3e8641 100644 --- a/Makefile +++ b/Makefile @@ -3052,12 +3052,24 @@ smdk2410_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t smdk2410 samsung s3c24x0 spear300_config \ +spear300_nand_config \ +spear300_usbtty_config \ +spear300_usbtty_nand_config \ spear310_config \ -spear320_config : unconfig - @$(MKCONFIG) -n $@ -t $(@:_config=) spear3xx arm arm926ejs $(@:_config=) spear spear - -spear600_config : unconfig - @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx arm arm926ejs $(@:_config=) spear spear +spear310_nand_config \ +spear310_usbtty_config \ +spear310_usbtty_nand_config \ +spear320_config \ +spear320_nand_config \ +spear320_usbtty_config \ +spear320_usbtty_nand_config : unconfig + @$(MKCONFIG) -n $@ -t $(@:_config=) spear3xx_evb arm arm926ejs $(@:_config=) spear spear + +spear600_config \ +spear600_nand_config \ +spear600_usbtty_config \ +spear600_usbtty_nand_config : unconfig + @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx_evb arm arm926ejs $(@:_config=) spear spear suen3_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs km_arm keymile kirkwood diff --git a/board/spear/spear300/config.mk b/board/spear/spear300/config.mk index 35646f2..0bbb40f 100644 --- a/board/spear/spear300/config.mk +++ b/board/spear/spear300/config.mk @@ -26,14 +26,3 @@ TEXT_BASE = 0x00700000 ALL += $(obj)u-boot.img - -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear310/config.mk b/board/spear/spear310/config.mk index cba8436..c8264c3 100644 --- a/board/spear/spear310/config.mk +++ b/board/spear/spear310/config.mk @@ -27,18 +27,7 @@ TEXT_BASE = 0x00700000 ALL += $(obj)u-boot.img -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - # Support parallel flash ifeq ($(FLASH),PNOR) PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear320/config.mk b/board/spear/spear320/config.mk index cba8436..c8264c3 100644 --- a/board/spear/spear320/config.mk +++ b/board/spear/spear320/config.mk @@ -27,18 +27,7 @@ TEXT_BASE = 0x00700000 ALL += $(obj)u-boot.img -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - # Support parallel flash ifeq ($(FLASH),PNOR) PLATFORM_RELFLAGS += -DCONFIG_FLASH_PNOR endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/board/spear/spear600/config.mk b/board/spear/spear600/config.mk index 35646f2..0bbb40f 100644 --- a/board/spear/spear600/config.mk +++ b/board/spear/spear600/config.mk @@ -26,14 +26,3 @@ TEXT_BASE = 0x00700000 ALL += $(obj)u-boot.img - -# Environment variables in NAND -ifeq ($(ENV),NAND) -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND -else -PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH -endif - -ifeq ($(CONSOLE),USB) -PLATFORM_RELFLAGS += -DCONFIG_SPEAR_USBTTY -endif diff --git a/doc/README.spear b/doc/README.spear index a6ff7fd..3161e64 100644 --- a/doc/README.spear +++ b/doc/README.spear @@ -6,9 +6,9 @@ SPEAr600 is also known as SPEArPlus and SPEAr300 is also known as SPEArBasic The SPEAr SoC family embeds a customizable logic that can be programmed one-time by a customer at silicon mask level (i.e. not at runtime!). -We are now adding the support in u-boot for two SoC: SPEAr600 and SPEAr3xx. +U-Boot supports four SoCs: SPEAr600, SPEAr3xx -All 4 SoCs share common peripherals. +All 4 SoCs (SPEAr3xx and SPEAr600) share common peripherals. 1. ARM926ejs core based (sp600 has two cores, the 2nd handled only in Linux) 2. FastEthernet (sp600 has Gbit version, but same controller - GMAC) @@ -22,7 +22,7 @@ All 4 SoCs share common peripherals. 10. others .. Everything is supported in Linux. -u-boot is not currently supporting all peripeharls (just a few as listed below). +u-boot is currently not supporting all peripeharls (just a few as listed below). 1. USB Device 2. NAND controller (FSMC) 3. Serial Memory Interface @@ -32,17 +32,30 @@ u-boot is not currently supporting all peripeharls (just a few as listed below). Build options make spear600_config + spear600 build with environment variables placed at default + location i.e. Serial NOR device + make spear600_nand_config + spear600 build with environment variables placed in NAND device + make spear600_usbtty_config + spear600 build with usbtty terminal as default and environment + placed at default location + make spear600_usbtty_nand_config + Build with usbtty terminal as default and environment placed in + NAND device make spear300_config + make spear300_nand_config + make spear300_usbtty_config + make spear300_usbtty_nand_config make spear310_config + make spear310_nand_config + make spear310_usbtty_config + make spear310_usbtty_nand_config make spear320_config + make spear320_nand_config + make spear320_usbtty_config + make spear320_usbtty_nand_config Further options - make ENV=NAND (supported by all 4 SoCs) - - This option generates a uboot image that saves environment inn NAND - - make CONSOLE=USB (supported by all 4 SoCs) - - This option generates a uboot image for using usbdevice as a tty i/f - make FLASH=PNOR (supported by SPEAr310 and SPEAr320) - This option generates a uboot image that supports emi controller for CFI compliant parallel NOR flash diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx_evb.h similarity index 95% rename from include/configs/spear3xx.h rename to include/configs/spear3xx_evb.h index fde505c..f0c915e 100644 --- a/include/configs/spear3xx.h +++ b/include/configs/spear3xx_evb.h @@ -39,6 +39,16 @@ #define CONFIG_SPEAR320 1 #endif +#if defined(CONFIG_MK_usbtty) +#define CONFIG_SPEAR_USBTTY 1 +#endif + +#if defined(CONFIG_MK_nand) +#define CONFIG_ENV_IS_IN_NAND 1 +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + #include <configs/spear-common.h> /* Ethernet driver configuration */ diff --git a/include/configs/spear6xx.h b/include/configs/spear6xx_evb.h similarity index 88% rename from include/configs/spear6xx.h rename to include/configs/spear6xx_evb.h index 2532344..82d24df 100644 --- a/include/configs/spear6xx.h +++ b/include/configs/spear6xx_evb.h @@ -30,6 +30,16 @@ */ #define CONFIG_SPEAR600 1 +#if defined(CONFIG_MK_usbtty) +#define CONFIG_SPEAR_USBTTY 1 +#endif + +#if defined(CONFIG_MK_nand) +#define CONFIG_ENV_IS_IN_NAND 1 +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + #include <configs/spear-common.h> /* Serial Configuration (PL011) */ -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 15/18] SPEAr : Basic spear1300 architecture support added 2010-06-29 5:23 ` [U-Boot] [PATCH v5 14/18] SPEAr : Supporting various configurations for spear3xx and spear6xx boards Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 16/18] SPEAr : spear1300 SoC " Vipin KUMAR 0 siblings, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> SPEAr1300 is an ARMCortexA9 dual core based SoC which supports multiple peripherals such as 1. Ethernet Controller 2. USB Device Controller 3. USB Host Controllers 4. MTD interfaces for NAND and NOR(serial and parallel) flash devices etc For more information, visit www.st.com/spear This patch adds the architecture support for spear1300. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- arch/arm/cpu/arm_cortexa8/spear13xx/Makefile | 52 ++++ arch/arm/cpu/arm_cortexa8/spear13xx/cache.S | 114 ++++++++ arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c | 96 +++++++ arch/arm/cpu/arm_cortexa8/spear13xx/reset.c | 47 ++++ arch/arm/cpu/arm_cortexa8/spear13xx/timer.c | 138 ++++++++++ arch/arm/include/asm/arch-spear13xx/hardware.h | 40 +++ arch/arm/include/asm/arch-spear13xx/spr_gpt.h | 85 ++++++ arch/arm/include/asm/arch-spear13xx/spr_misc.h | 317 +++++++++++++++++++++++ arch/arm/include/asm/arch-spear13xx/sys_proto.h | 34 +++ 9 files changed, 923 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/Makefile create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/cache.S create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c create mode 100755 arch/arm/cpu/arm_cortexa8/spear13xx/reset.c create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/timer.c create mode 100644 arch/arm/include/asm/arch-spear13xx/hardware.h create mode 100644 arch/arm/include/asm/arch-spear13xx/spr_gpt.h create mode 100644 arch/arm/include/asm/arch-spear13xx/spr_misc.h create mode 100644 arch/arm/include/asm/arch-spear13xx/sys_proto.h diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/Makefile b/arch/arm/cpu/arm_cortexa8/spear13xx/Makefile new file mode 100644 index 0000000..4157164 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS += timer.o +COBJS += reset.o +COBJS += cpu.o + +SOBJS = cache.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/cache.S b/arch/arm/cpu/arm_cortexa8/spear13xx/cache.S new file mode 100644 index 0000000..4b3db08 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/cache.S @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. + * + * Based on arch/arm/cpu/arm_cortexa8/s5pc1xx/cache.S + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +.global invalidate_dcache + +/* + * invalidate_dcache() + * + * Invalidate the whole D-cache. + * + * Corrupted registers: r0-r5, r7, r9-r11 + * + * - mm - mm_struct describing address space + */ +invalidate_dcache: + stmfd r13!, {r0 - r5, r7, r9 - r12, r14} + + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished_inval @ if loc is 0, then no need to + @ clean + mov r10, #0 @ start clean at cache level 0 +inval_loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache + @ level + mov r1, r0, lsr r2 @ extract cache type bits from + @ clidr + and r1, r1, #7 @ mask of the bits for current + @ cache only + cmp r1, #2 @ see what cache we have at + @ this level + blt skip_inval @ skip if no cache, or just + @ i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mov r2, #0 @ operand for mcr SBZ + mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to + @ sych the new cssr&csidr, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the + @ cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the + @ way size + clz r5, r4 @ find bit position of way + @ size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the + @ index size +inval_loop2: + mov r9, r4 @ create working copy of max + @ way size +inval_loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number + @ into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge inval_loop3 + subs r7, r7, #1 @ decrement the index + bge inval_loop2 +skip_inval: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt inval_loop1 +finished_inval: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + + ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} + +.global l2_cache_enable +/* + * l2_cache_enable + */ +l2_cache_enable: + bx r14 + +.global l2_cache_disable +/* + * l2_cache_disable + */ +l2_cache_disable: + bx r14 diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c b/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c new file mode 100644 index 0000000..550661c --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h> + +u32 get_device_type(void) +{ + return 0; +} + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + struct misc_regs *const misc_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + u32 perip1_clk_enb, perip2_clk_enb; +#if defined(CONFIG_NAND_FSMC) + u32 fsmc_cfg; +#endif + perip1_clk_enb = readl(&misc_p->perip1_clk_enb); + perip2_clk_enb = readl(&misc_p->perip2_clk_enb); + + perip1_clk_enb |= GPT1_CLKEN; + +#if defined(CONFIG_PL011_SERIAL) + perip1_clk_enb |= UART_CLKEN; +#endif + +#if defined(CONFIG_DESIGNWARE_ETH) + writel(PHY_IF_GMII | CLK_SEL_OSCI3, &misc_p->gmac_clk_cfg); + perip1_clk_enb |= GETH_CLKEN; +#endif + +#if defined(CONFIG_DW_UDC) + perip1_clk_enb |= UDC_UPD_CLKEN; +#endif + +#if defined(CONFIG_DW_I2C) + perip1_clk_enb |= I2C_CLKEN; +#endif + +#if defined(CONFIG_ST_SMI) + perip1_clk_enb |= SMI_CLKEN; +#endif + +#if defined(CONFIG_NAND_FSMC) + fsmc_cfg = readl(&misc_p->fsmc_cfg); + fsmc_cfg &= ~DEV_SEL_MSK; + fsmc_cfg |= DEV_SEL_NAND; +#if defined(CONFIG_SYS_FSMC_NAND_16BIT) + fsmc_cfg |= DEV_WIDTH_16; +#elif defined(CONFIG_SYS_FSMC_NAND_8BIT) + fsmc_cfg |= DEV_WIDTH_8; +#endif + writel(fsmc_cfg, &misc_p->fsmc_cfg); + + perip1_clk_enb |= FSMC_CLKEN; +#endif + + writel(perip1_clk_enb, &misc_p->perip1_clk_enb); + writel(perip2_clk_enb, &misc_p->perip2_clk_enb); + + return 0; +} +#endif + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + printf("CPU: SPEAr1300\n"); + return 0; +} +#endif diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/reset.c b/arch/arm/cpu/arm_cortexa8/spear13xx/reset.c new file mode 100755 index 0000000..6f5ce14 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/reset.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h> + +void reset_cpu(ulong ignored) +{ + struct misc_regs *misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + printf("System is going to reboot ...\n"); + + /* + * This 1 second delay will allow the above message + * to be printed before reset + */ + udelay((1000 * 1000)); + + writel(0x01, &misc_regs_p->sys_sw_res); + + /* system will restart */ + while (1) + ; +} diff --git a/arch/arm/cpu/arm_cortexa8/spear13xx/timer.c b/arch/arm/cpu/arm_cortexa8/spear13xx/timer.c new file mode 100644 index 0000000..f5c3660 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/spear13xx/timer.c @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. + * + * Based on arch/arm/cpu/arm926ejs/spear/timer.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_gpt.h> +#include <asm/arch/spr_misc.h> + +#define GPT_TICKS (CONFIG_SPEAR_HZ_CLOCK / (1 << prescaler)) +#define GPT_RESOLUTION (GPT_TICKS / CONFIG_SPEAR_HZ) +#define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING) + +static struct gpt_regs *const gpt_regs_p = + (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE; + +static ulong timestamp; +static ulong lastdec; +static const u32 prescaler = GPT_PRESCALER_16; + +int timer_init(void) +{ + /* disable timers */ + writel(prescaler | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control); + + /* load value for free running */ + writel(GPT_FREE_RUNNING, &gpt_regs_p->compare); + + /* auto reload, start timer */ + writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control); + + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return (get_timer_masked() / GPT_RESOLUTION) - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void __udelay(unsigned long usec) +{ + ulong tmo; + ulong start = get_timer_masked(); + ulong ticks_in_ten_us = GPT_TICKS / (1000 * 100); + ulong rndoff; + + rndoff = (usec % 10) ? 1 : 0; + + /* ticks_in_ten_us timer ticks give 10 microsecconds delay */ + tmo = ((usec / 10) + rndoff) * ticks_in_ten_us; + + while ((ulong) (get_timer_masked() - start) < tmo) + ; +} + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER(); + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER(); + + if (now >= lastdec) { + /* normal mode */ + timestamp += now - lastdec; + } else { + /* we have an overflow ... */ + timestamp += now + GPT_FREE_RUNNING - lastdec; + } + lastdec = now; + + return timestamp; +} + +void udelay_masked(unsigned long usec) +{ + return udelay(usec); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SPEAR_HZ; +} diff --git a/arch/arm/include/asm/arch-spear13xx/hardware.h b/arch/arm/include/asm/arch-spear13xx/hardware.h new file mode 100644 index 0000000..020ab2a --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/hardware.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_ARCH_SPEAR13XX_HARDWARE_H +#define _ASM_ARCH_SPEAR13XX_HARDWARE_H + +#define CONFIG_SYS_USBD_BASE (0xE1100000) +#define CONFIG_SYS_PLUG_BASE (0xE1200000) +#define CONFIG_SYS_FIFO_BASE (0xE1000800) +#define CONFIG_SYS_SMI_BASE (0xFC000000) +#define CONFIG_SPEAR_TIMERBASE (0xE0380000) +#define CONFIG_SPEAR_MISCBASE (0xE0700000) +#define CONFIG_SYS_I2C_BASE (0xE0280000) +#define CONFIG_SPEAR_ETHBASE (0xE2000000) +#define CONFIG_SYS_FSMC_BASE (0xB0000000) + +#define CONFIG_SYS_NAND_CLE (1 << 16) +#define CONFIG_SYS_NAND_ALE (1 << 17) + +#endif /* _ASM_ARCH_SPEAR13XX_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-spear13xx/spr_gpt.h b/arch/arm/include/asm/arch-spear13xx/spr_gpt.h new file mode 100644 index 0000000..999628c --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/spr_gpt.h @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SPR_GPT_H +#define _SPR_GPT_H + +struct gpt_regs { + u8 reserved[0x80]; + u32 control; + u32 status; + u32 compare; + u32 count; + u32 capture_re; + u32 capture_fe; +}; + +/* + * TIMER_CONTROL register settings + */ + +#define GPT_PRESCALER_MASK 0x000F +#define GPT_PRESCALER_1 0x0000 +#define GPT_PRESCALER_2 0x0001 +#define GPT_PRESCALER_4 0x0002 +#define GPT_PRESCALER_8 0x0003 +#define GPT_PRESCALER_16 0x0004 +#define GPT_PRESCALER_32 0x0005 +#define GPT_PRESCALER_64 0x0006 +#define GPT_PRESCALER_128 0x0007 +#define GPT_PRESCALER_256 0x0008 + +#define GPT_MODE_SINGLE_SHOT 0x0010 +#define GPT_MODE_AUTO_RELOAD 0x0000 + +#define GPT_ENABLE 0x0020 + +#define GPT_CAPT_MODE_MASK 0x00C0 +#define GPT_CAPT_MODE_NONE 0x0000 +#define GPT_CAPT_MODE_RE 0x0040 +#define GPT_CAPT_MODE_FE 0x0080 +#define GPT_CAPT_MODE_BOTH 0x00C0 + +#define GPT_INT_MATCH 0x0100 +#define GPT_INT_FE 0x0200 +#define GPT_INT_RE 0x0400 + +/* + * TIMER_STATUS register settings + */ + +#define GPT_STS_MATCH 0x0001 +#define GPT_STS_FE 0x0002 +#define GPT_STS_RE 0x0004 + +/* + * TIMER_COMPARE register settings + */ + +#define GPT_FREE_RUNNING 0xFFFF + +/* Timer, HZ specific defines */ +#define CONFIG_SPEAR_HZ (1000) +#define CONFIG_SPEAR_HZ_CLOCK (24000000) + +#endif diff --git a/arch/arm/include/asm/arch-spear13xx/spr_misc.h b/arch/arm/include/asm/arch-spear13xx/spr_misc.h new file mode 100644 index 0000000..8287d3b --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/spr_misc.h @@ -0,0 +1,317 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Microelectronics, vipin.kumar at st.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SPR13XX_MISC_H +#define __SPR13XX_MISC_H + +struct misc_regs { + u32 soc_cfg; /* 0x000 */ + u32 bootstrap_cfg; /* 0x004 */ + u8 reserved_1[0x100 - 0x8]; + u32 pcm_cfg; /* 0x100 */ + u32 pcm_wkup_cfg; /* 0x104 */ + u32 switch_ctr; /* 0x108 */ + u8 reserved_2[0x200 - 0x10c]; + u32 sys_clk_ctrl; /* 0x200 */ + u32 sys_sw_res; /* 0x204 */ + u32 sys_clk_plltimer; /* 0x208 */ + u32 sys_clk_oscitimer; /* 0x20c */ + u32 pll_cfg; /* 0x210 */ + u32 pll1_ctr; /* 0x214 */ + u32 pll1_frq; /* 0x218 */ + u32 pll1_mod; /* 0x21c */ + u32 pll2_ctr; /* 0x220 */ + u32 pll2_frq; /* 0x224 */ + u32 pll2_mod; /* 0x228 */ + u32 pll3_ctr; /* 0x22c */ + u32 pll3_frq; /* 0x230 */ + u32 pll3_mod; /* 0x234 */ + u32 pll4_ctr; /* 0x238 */ + u32 pll4_frq; /* 0x23C */ + u32 pll4_mod; /* 0x240 */ + u32 perip_clk_cfg; /* 0x244 */ + u32 gmac_clk_cfg; /* 0x248 */ + u32 c3_clk_synt; /* 0x24c */ + u32 clcd_clk_synt; /* 0x250 */ + u32 uart_clk_synt; /* 0x254 */ + u32 gmac_clk_synt; /* 0x258 */ + u32 mcif_sd_clk_synt; /* 0x25c */ + u32 mcif_cfxd_clk_synt; /* 0x260 */ + u32 ras_clk_synt0; /* 0x264 */ + u32 ras_clk_synt1; /* 0x268 */ + u32 ras_clk_synt2; /* 0x26c */ + u32 ras_clk_synt3; /* 0x270 */ + u32 perip1_clk_enb; /* 0x274 */ + u32 perip2_clk_enb; /* 0x278 */ + u32 perip1_sw_rst; /* 0x27c */ + u32 perip2_sw_rst; /* 0x280 */ + u32 ras_clk_enb; /* 0x284 */ + u32 ras_sw_rst; /* 0x288 */ + u32 pll1_synt; /* 0x28c */ + u32 i2s_clk_cfg; /* 0x290 */ + u8 reserved_3[0x300 - 0x294]; + u32 dmac_hs_sel; /* 0x300 */ + u32 dmac_sel; /* 0x304 */ + u32 dmac_flow_sel; /* 0x308 */ + u32 dmac_dir_sel; /* 0x30c */ + u32 dmac_cfg; /* 0x310 */ + u32 usbphy_gen_cfg; /* 0x314 */ + u32 usbphy_p1_cfg; /* 0x318 */ + u32 usbphy_p2_cfg; /* 0x31c */ + u32 usbphy_p3_cfg; /* 0x320 */ + u32 pcie_cfg; /* 0x324 */ + u32 pcie_miphy_cfg; /* 0x328 */ + u32 perip_cfg; /* 0x32c */ + u32 fsmc_cfg; /* 0x330 */ + u32 mpmc_ctr_sts; /* 0x334 */ + u8 reserved_4[0x400 - 0x338]; + u32 expi_clk_cfg; /* 0x400 */ + u32 expi_cfg; /* 0x404 */ + u32 expi_dmachs_flex; /* 0x408 */ + u8 reserved_5[0x500 - 0x40C]; + u32 prc1_lock_ctr; /* 0x500 */ + u32 prc2_lock_ctr; /* 0x504 */ + u32 prc1_irq_ctr; /* 0x508 */ + u8 reserved_6[0x51c - 0x50c]; + u32 prc2_irq_ctr; /* 0x51c */ + u8 reserved_7[0x600 - 0x520]; + u32 pad_pu_cfg_1; /* 0x600 */ + u32 pad_pu_cfg_2; /* 0x604 */ + u32 pad_pu_cfg_3; /* 0x608 */ + u32 pad_pu_cfg_4; /* 0x60c */ + u32 pad_pu_cfg_5; /* 0x610 */ + u32 pad_pu_cfg_6; /* 0x614 */ + u32 pad_pu_cfg_7; /* 0x618 */ + u32 pad_pu_cfg_8; /* 0x61c */ + u32 pad_pd_cfg_1; /* 0x620 */ + u32 pad_pd_cfg_2; /* 0x624 */ + u32 pad_pd_cfg_3; /* 0x628 */ + u32 pad_pd_cfg_4; /* 0x62c */ + u32 pad_pd_cfg_5; /* 0x630 */ + u32 pad_pd_cfg_6; /* 0x634 */ + u32 pad_pd_cfg_7; /* 0x638 */ + u32 pad_pd_cfg_8; /* 0x63c */ + u32 pad_sleep_cfg; /* 0x640 */ + u32 pad_hyst_cfg; /* 0x644 */ + u32 pad_drv_cfg; /* 0x648 */ + u32 pad_slew_cfg; /* 0x64c */ + u32 pad_function_en_1; /* 0x650 */ + u32 pad_function_en_2; /* 0x654 */ + u32 pad_function_en_3; /* 0x658 */ + u32 ddr_pad_cfg; /* 0x65c */ + u8 reserved_8[0x6C4 - 0x660]; + u32 thsens_cfg; /* 0x6C4 */ + u8 reserved_9[0x700 - 0x6C8]; + u32 comp_1_cfg; /* 0x700 */ + u32 comp_2_cfg; /* 0x704 */ + u32 comp3v3_1_cfg; /* 0x708 */ + u32 comp3v3_2_cfg; /* 0x70c */ + u32 compddr_cfg; /* 0x710 */ + u8 reserved_10[0x800 - 0x714]; + u32 otp_prog_ctr; /* 0x800 */ + u32 otp_wdata1_1; /* 0x804 */ + u32 otp_wdata1_2; /* 0x808 */ + u32 otp_wdata1_3; /* 0x80c */ + u32 otp_wdata1_4; /* 0x810 */ + u32 otp_wdata1_5; /* 0x814 */ + u32 otp_wdata1_6; /* 0x818 */ + u32 otp_wdata1_7; /* 0x81c */ + u32 otp_wdata1_8; /* 0x820 */ + u32 otp_wdata2_1; /* 0x824 */ + u32 otp_wdata2_2; /* 0x828 */ + u32 otp_wdata2_3; /* 0x82c */ + u32 otp_wdata2_4; /* 0x830 */ + u32 otp_wdata2_5; /* 0x834 */ + u32 otp_wdata2_6; /* 0x838 */ + u32 otp_wdata2_7; /* 0x83c */ + u32 otp_wdata2_8; /* 0x840 */ + u32 otp_mask_1; /* 0x844 */ + u32 otp_mask_2; /* 0x848 */ + u32 otp_mask_3; /* 0x84c */ + u32 otp_mask_4; /* 0x850 */ + u32 otp_mask_5; /* 0x854 */ + u32 otp_mask_6; /* 0x858 */ + u32 otp_mask_7; /* 0x85c */ + u32 otp_mask_8; /* 0x860 */ + u32 otp_rdata1_1; /* 0x864 */ + u32 otp_rdata1_2; /* 0x868 */ + u32 otp_rdata1_3; /* 0x86c */ + u32 otp_rdata1_4; /* 0x870 */ + u32 otp_rdata1_5; /* 0x874 */ + u32 otp_rdata1_6; /* 0x878 */ + u32 otp_rdata1_7; /* 0x87c */ + u32 otp_rdata1_8; /* 0x880 */ + u32 otp_rdata2_1; /* 0x884 */ + u32 otp_rdata2_2; /* 0x888 */ + u32 otp_rdata2_3; /* 0x88c */ + u32 otp_rdata2_4; /* 0x890 */ + u32 otp_rdata2_5; /* 0x894 */ + u32 otp_rdata2_6; /* 0x898 */ + u32 otp_rdata2_7; /* 0x89c */ + u32 otp_rdata2_8; /* 0x8a0 */ + u32 otp_rdatam_1; /* 0x8a4 */ + u32 otp_rdatam_2; /* 0x8a8 */ + u32 otp_rdatam_3; /* 0x8ac */ + u32 otp_rdatam_4; /* 0x8b0 */ + u32 otp_rdatam_5; /* 0x8b4 */ + u32 otp_rdatam_6; /* 0x8b8 */ + u32 otp_rdatam_7; /* 0x8bc */ + u32 otp_rdatam_8; /* 0x8c0 */ + u8 reserved_11[0x900 - 0x8c4]; + u32 a9sm_clusterid; /* 0x900 */ + u32 a9sm_status; /* 0x904 */ + u32 a9sm_debug; /* 0x908 */ + u32 a9sm_filter; /* 0x90c */ + u32 a9sm_parity_cfg; /* 0x910 */ + u32 a9sm_parity_err; /* 0x914 */ + u8 reserved_12[0xa00 - 0x918]; + u32 die_id_1; /* 0xa00 */ + u32 die_id_2; /* 0xa04 */ + u32 die_id_3; /* 0xa08 */ + u32 die_id_4; /* 0xa0c */ + u32 die_id_valid; /* 0xa10 */ + u8 reserved_13[0xb00 - 0xa14]; + u32 ras1_gpp_inp; /* 0xb00 */ + u32 ras2_gpp_inp; /* 0xb04 */ + u32 ras1_gpp_out; /* 0xb08 */ + u32 ras2_gpp_out; /* 0xb0c */ + u8 reserved_14[0x1000 - 0xb10]; + u32 miphy_test; /* 0x1000 */ + u32 pcie_mstr_p1; /* 0x1004 */ + u32 pcie_awmisc_p1; /* 0x1008 */ + u32 pcie_armisc_p1; /* 0x100c */ + u32 pcie_mstr_p2; /* 0x1010 */ + u32 pcie_awmisc_p2; /* 0x1014 */ + u32 pcie_armisc_p2; /* 0x1018 */ + u32 pcie_mstr_p3; /* 0x101c */ + u32 pcie_awmisc_p3; /* 0x1020 */ + u32 pcie_armisc_p3; /* 0x1024 */ +}; + +/* sys_clk_ctrl definitions */ +#define SYS_MODE_MASK (7 << 0) +#define SYS_MODE_REQ_DOZE (1 << 0) +#define SYS_MODE_REQ_SLOW (2 << 0) +#define SYS_MODE_REQ_NORMAL (4 << 0) +#define PLL_TIMEOUT_ENB (1 << 3) +#define XTAL_TIMEOUT_ENB (1 << 4) +#define SYS_STATE_MASK (0xF << 16) +#define SYS_STATE_NORMAL (0xF << 16) + +/* sys_clk_*timer definitions */ +#define PLL_TIM (0xff << 3) +#define OSCI_TIM (0xff << 3) + +/* pll_freq definitions in MHz */ +#define FREQ_1000 (0xFA000106) +#define FREQ_996 (0x53000004) +#define FREQ_332 (0x53000203) + +/* pll_ctr definitions */ +#define PLLLOCK (1 << 0) +#define PLLENABLE (1 << 1) + +/* perip_clk_cfg definitions */ +#define MPMC_CLK_PLL4 (1 << 10) + +/* perip*_[clk_enb/sw_rst] definitions */ +#define BUS_CLKEN (1 << 0) /* perip1 */ +#define SYSROM_CLKEN (1 << 1) +#define AORAM_CLKEN (1 << 2) +#define SYSRAM_CLKEN (1 << 3) +#define FSMC_CLKEN (1 << 4) +#define SMI_CLKEN (1 << 5) +#define SD_CLKEN (1 << 6) +#define CFXD_CLKEN (1 << 7) +#define GETH_CLKEN (1 << 8) +#define UHC1_CLKEN (1 << 9) +#define UHC2_CLKEN (1 << 10) +#define UDC_UPD_CLKEN (1 << 11) +#define PCI1_CLKEN (1 << 12) +#define PCI2_CLKEN (1 << 13) +#define PCI3_CLKEN (1 << 14) +#define UART_CLKEN (1 << 15) +#define SSP_CLKEN (1 << 17) +#define I2C_CLKEN (1 << 18) +#define I2S_SLV_CLKEN (1 << 19) +#define I2S_MST_CLKEN (1 << 20) +#define GPT1_CLKEN (1 << 21) +#define GPT2_CLKEN (1 << 22) +#define GPIO1_CLKEN (1 << 23) +#define GPIO2_CLKEN (1 << 24) +#define DMA1_CLKEN (1 << 25) +#define DMA2_CLKEN (1 << 26) +#define CLCD_CLKEN (1 << 27) +#define JPEG_CLKEN (1 << 28) +#define C3_CLKEN (1 << 29) +#define ADC_CLKEN (1 << 30) +#define RTC_CLKEN (1 << 31) + +#define DDR_CTRL_CLKEN (1 << 0) /* perip2 */ +#define DDR_CORE_CLKEN (1 << 1) +#define CPU_DBG_CLKEN (1 << 2) +#define KBD_CLKEN (1 << 3) +#define GPT3_CLKEN (1 << 4) +#define GPT4_CLKEN (1 << 5) +#define ACP_CLKEN (1 << 6) +#define I2S_REFOUT_CLKEN (1 << 7) +#define THSENS_CLKEN (1 << 8) + +/* fsmc_cfg definitions */ +#define DEV_SEL_NOR (0 << 0) +#define DEV_SEL_NAND (1 << 0) +#define DEV_SEL_SRAM (2 << 0) +#define DEV_SEL_MSK (3 << 0) +#define NAND_BANK_0 (0 << 2) +#define NAND_BANK_1 (1 << 2) +#define NAND_BANK_2 (2 << 2) +#define NAND_BANK_3 (3 << 2) +#define DEV_WIDTH_8 (0 << 4) +#define DEV_WIDTH_16 (1 << 4) + +/* usbphy_gen_cfg definitions */ +#define COMMON_PWDN (1 << 0) +#define USBPHY_POR (1 << 12) +#define USBPHY_RST (1 << 13) +#define UTMI_XFER_RST0 (1 << 14) +#define UTMI_XFER_RST1 (1 << 15) +#define UTMI_XFER_RST2 (1 << 16) +#define USB_PLL_LOCK (1 << 27) + +/* synth registers definitions */ +#define SYNT_CLK_ENB (1 << 31) +#define SYNT_FIN_FULL (1 << 30) +#define SYNT_X_1 (1 << 16) +#define SYNT_Y_2 (2 << 0) +#define SYNT_Y_5 (5 << 0) + +/* gmac_clk_cfg definitions */ +#define PHY_IF_GMII (0 << 4) +#define PHY_IF_RGMII (1 << 4) +#define PHY_IF_RMII (4 << 4) +#define GMII_SYNT_ENB (1 << 3) +#define CLK_SEL_PAD (0 << 0) +#define CLK_SEL_PLL2 (1 << 0) +#define CLK_SEL_OSCI3 (2 << 0) + +#endif diff --git a/arch/arm/include/asm/arch-spear13xx/sys_proto.h b/arch/arm/include/asm/arch-spear13xx/sys_proto.h new file mode 100644 index 0000000..98b9a6b --- /dev/null +++ b/arch/arm/include/asm/arch-spear13xx/sys_proto.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> + * + * Based on arch/arm/include/asm/arch-omap3/sys_proto.h + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +u32 get_device_type(void); +void invalidate_dcache(u32); +void l2_cache_disable(void); +void l2_cache_enable(void); + +#endif -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 16/18] SPEAr : spear1300 SoC support added 2010-06-29 5:23 ` [U-Boot] [PATCH v5 15/18] SPEAr : Basic spear1300 architecture support added Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 17/18] SPEAr : Removing extraneous code Vipin KUMAR 0 siblings, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> SPEAr1300 SoC support contains basic spear1300 support along with the usage of following drivers - serial driver(UART) - i2c driver - smi driver - nand driver(FSMC) - usbd driver Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 6 + arch/arm/include/asm/arch-spear13xx/hardware.h | 8 +- board/spear/common/Makefile | 10 +- board/spear/spear1300/Makefile | 51 ++++++ board/spear/spear1300/config.mk | 28 ++++ board/spear/spear1300/spear1300.c | 88 ++++++++++ board/spear/spear1300/spr_lowlevel_init.S | 38 +++++ doc/README.spear | 11 +- include/configs/spear13xx_evb.h | 202 ++++++++++++++++++++++++ 11 files changed, 436 insertions(+), 8 deletions(-) create mode 100644 board/spear/spear1300/Makefile create mode 100644 board/spear/spear1300/config.mk create mode 100644 board/spear/spear1300/spear1300.c create mode 100644 board/spear/spear1300/spr_lowlevel_init.S create mode 100644 include/configs/spear13xx_evb.h diff --git a/MAINTAINERS b/MAINTAINERS index d7aec98..ee731a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -668,6 +668,7 @@ Prakash Kumar <prakash@embedx.com> Vipin Kumar <vipin.kumar@st.com> + spear1300 ARM CORTEX-A9 (spear1300 Soc) spear300 ARM926EJS (spear300 Soc) spear310 ARM926EJS (spear310 Soc) spear320 ARM926EJS (spear320 Soc) diff --git a/MAKEALL b/MAKEALL index d6d5f5b..7c00577 100755 --- a/MAKEALL +++ b/MAKEALL @@ -656,6 +656,7 @@ LIST_ARM_CORTEX_A8=" \ omap3_zoom2 \ s5p_goni \ smdkc100 \ + spear1300 \ " ######################################################################### diff --git a/Makefile b/Makefile index f3e8641..0e8db55 100644 --- a/Makefile +++ b/Makefile @@ -3071,6 +3071,12 @@ spear600_usbtty_config \ spear600_usbtty_nand_config : unconfig @$(MKCONFIG) -n $@ -t $(@:_config=) spear6xx_evb arm arm926ejs $(@:_config=) spear spear +spear1300_config \ +spear1300_nand_config \ +spear1300_usbtty_config \ +spear1300_usbtty_nand_config : unconfig + @$(MKCONFIG) -n $@ -t $(@:_config=) spear13xx_evb arm arm_cortexa8 spear1300 spear spear13xx + suen3_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs km_arm keymile kirkwood diff --git a/arch/arm/include/asm/arch-spear13xx/hardware.h b/arch/arm/include/asm/arch-spear13xx/hardware.h index 020ab2a..e3dd6e5 100644 --- a/arch/arm/include/asm/arch-spear13xx/hardware.h +++ b/arch/arm/include/asm/arch-spear13xx/hardware.h @@ -24,10 +24,10 @@ #ifndef _ASM_ARCH_SPEAR13XX_HARDWARE_H #define _ASM_ARCH_SPEAR13XX_HARDWARE_H -#define CONFIG_SYS_USBD_BASE (0xE1100000) -#define CONFIG_SYS_PLUG_BASE (0xE1200000) -#define CONFIG_SYS_FIFO_BASE (0xE1000800) -#define CONFIG_SYS_SMI_BASE (0xFC000000) +#define CONFIG_SYS_USBD_BASE (0xE3800000) +#define CONFIG_SYS_PLUG_BASE (0xE2800000) +#define CONFIG_SYS_FIFO_BASE (0xE3000800) +#define CONFIG_SYS_SMI_BASE (0xEA000000) #define CONFIG_SPEAR_TIMERBASE (0xE0380000) #define CONFIG_SPEAR_MISCBASE (0xE0700000) #define CONFIG_SYS_I2C_BASE (0xE0280000) diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile index 4f8959f..1ae4fd4 100644 --- a/board/spear/common/Makefile +++ b/board/spear/common/Makefile @@ -29,8 +29,14 @@ endif LIB = $(obj)lib$(VENDOR).a -COBJS := spr_misc.o -SOBJS := spr_lowlevel_init.o +COBJS-$(CONFIG_SPEAR3XX) += spr_misc.o +COBJS-$(CONFIG_SPEAR600) += spr_misc.o + +SOBJS-$(CONFIG_SPEAR3XX) += spr_lowlevel_init.o +SOBJS-$(CONFIG_SPEAR600) += spr_lowlevel_init.o + +COBJS := $(COBJS-y) +SOBJS := $(SOBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/spear/spear1300/Makefile b/board/spear/spear1300/Makefile new file mode 100644 index 0000000..fb66895 --- /dev/null +++ b/board/spear/spear1300/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := spear1300.o +SOBJS := spr_lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/spear1300/config.mk b/board/spear/spear1300/config.mk new file mode 100644 index 0000000..4bd519c --- /dev/null +++ b/board/spear/spear1300/config.mk @@ -0,0 +1,28 @@ +# +# (C) Copyright 2010 +# Vipin Kumar, ST Microelectronics <vipin.kumar@st.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +######################################################################### + +TEXT_BASE = 0x00700000 + +ALL += $(obj)u-boot.img diff --git a/board/spear/spear1300/spear1300.c b/board/spear/spear1300/spear1300.c new file mode 100644 index 0000000..f4c0ea5 --- /dev/null +++ b/board/spear/spear1300/spear1300.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <nand.h> +#include <asm/io.h> +#include <linux/mtd/fsmc_nand.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_SPEAR1300; + gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_ADDR; + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size(PHYS_SDRAM_1, + PHYS_SDRAM_1_MAXSIZE); + + return 0; +} + +int misc_init_r(void) +{ + setenv("verify", "n"); + +#if defined(CONFIG_SPEAR_USBTTY) + setenv("stdin", "usbtty"); + setenv("stdout", "usbtty"); + setenv("stderr", "usbtty"); +#endif + return 0; +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +int board_nand_init(struct nand_chip *nand) +{ +#if defined(CONFIG_NAND_FSMC) + return fsmc_nand_init(nand); +#else + return -1; +#endif +} + +#if defined(CONFIG_CMD_NET) +int board_eth_init(bd_t *bis) +{ + int ret = 0; +#if defined(CONFIG_DESIGNWARE_ETH) + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY) >= 0) + ret++; +#endif + return ret; +} +#endif diff --git a/board/spear/spear1300/spr_lowlevel_init.S b/board/spear/spear1300/spr_lowlevel_init.S new file mode 100644 index 0000000..13e0372 --- /dev/null +++ b/board/spear/spear1300/spr_lowlevel_init.S @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, ST Micoelectronics, vipin.kumar at st.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + +/* + * platform specific initializations are already done in Xloader + * Initializations already done include + * DDR, PLLs, IP's clock enable and reset release etc + */ +.globl lowlevel_init +lowlevel_init: + /* By default, U-Boot switches CPU to low-vector */ + /* Revert this as we work in high vector even in U-Boot */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00002000 + mcr p15, 0, r0, c1, c0, 0 + mov pc, lr diff --git a/doc/README.spear b/doc/README.spear index 3161e64..94b492f 100644 --- a/doc/README.spear +++ b/doc/README.spear @@ -6,9 +6,10 @@ SPEAr600 is also known as SPEArPlus and SPEAr300 is also known as SPEArBasic The SPEAr SoC family embeds a customizable logic that can be programmed one-time by a customer at silicon mask level (i.e. not at runtime!). -U-Boot supports four SoCs: SPEAr600, SPEAr3xx +U-Boot supports five spear SoCs: SPEAr600, SPEAr3xx, SPEAr1300 -All 4 SoCs (SPEAr3xx and SPEAr600) share common peripherals. +4 SoCs (SPEAr3xx and SPEAr600) share common peripherals. SPEAr1300 is based on +ARM CortexA9 core and other peripherals are common 1. ARM926ejs core based (sp600 has two cores, the 2nd handled only in Linux) 2. FastEthernet (sp600 has Gbit version, but same controller - GMAC) @@ -29,6 +30,7 @@ u-boot is currently not supporting all peripeharls (just a few as listed below). 4. EMI (Parallel NOR interface) 4. I2C 5. UART +6. Network Build options make spear600_config @@ -55,6 +57,11 @@ Build options make spear320_usbtty_config make spear320_usbtty_nand_config + make spear1300_config + make spear1300_nand_config + make spear1300_usbtty_config + make spear1300_usbtty_nand_config + Further options make FLASH=PNOR (supported by SPEAr310 and SPEAr320) - This option generates a uboot image that supports emi controller for diff --git a/include/configs/spear13xx_evb.h b/include/configs/spear13xx_evb.h new file mode 100644 index 0000000..82e30c6 --- /dev/null +++ b/include/configs/spear13xx_evb.h @@ -0,0 +1,202 @@ +/* + * (C) Copyright 2010 + * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if defined(CONFIG_MK_spear1300) +#define CONFIG_SPEAR13XX 1 +#define CONFIG_SPEAR1300 1 +#endif + +#if defined(CONFIG_MK_usbtty) +#define CONFIG_SPEAR_USBTTY 1 +#endif + +#if defined(CONFIG_MK_nand) +#define CONFIG_ENV_IS_IN_NAND 1 +#else +#define CONFIG_ENV_IS_IN_FLASH 1 +#endif + +/* Ethernet configuration */ +#define CONFIG_MII +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_NET_MULTI +#define CONFIG_DW_ALTDESCRIPTOR 1 +#define CONFIG_DW_SEARCH_PHY 1 +#define CONFIG_DW0_PHY 1 +#define CONFIG_PHY_RESET_DELAY (10000) /* in usec */ + +/* USBD driver configuration */ +#define CONFIG_DW_UDC +#define CONFIG_USB_DEVICE +#define CONFIG_USB_TTY + +#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" +#define CONFIG_USBD_MANUFACTURER "ST Microelectronics" + +#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" + +/* Timer, HZ specific defines */ +#define CONFIG_SYS_HZ (1000) + +/* Flash configuration */ +#define CONFIG_ST_SMI 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 +#define CONFIG_SYS_FLASH_BASE (0xE6000000) +#define CONFIG_SYS_CS1_FLASH_BASE (0xE7000000) +#define CONFIG_SYS_FLASH_BANK_SIZE (0x01000000) +#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_CS1_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) + +/* + * Serial Configuration (PL011) + */ +#define CONFIG_PL011_SERIAL +#define CONFIG_SYS_SERIAL0 0xE0000000 +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ + 57600, 115200 } + +#define CONFIG_SYS_LOADS_BAUD_CHANGE +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} + +/* + * NAND FLASH Configuration + */ +#define CONFIG_NAND_FSMC 1 +#define CONFIG_SYS_FSMC_NAND_LP 1 +#define CONFIG_SYS_FSMC_NAND_8BIT 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_SYS_NAND_BASE (0xA0000000) + +/* + * Command support defines + */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_RUN +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <config_cmd_default.h> + +/* + * Default Environment Varible definitions + */ +#if defined(CONFIG_SPEAR_USBTTY) +/* This disbales autobooting and stops at uboot prompt */ +#define CONFIG_BOOTDELAY -1 +#else +#define CONFIG_BOOTDELAY 1 +#endif + +/* + * Environment placing + */ +#if defined(CONFIG_ENV_IS_IN_FLASH) +/* + * Environment is in serial NOR flash + */ +#define CONFIG_SYS_MONITOR_LEN 0x00040000 +#define CONFIG_ENV_SECT_SIZE 0x00010000 +#define CONFIG_FSMTDBLK "/dev/mtdblock8 " + +#define CONFIG_BOOTCOMMAND "bootm 0xe6050000" + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#elif defined(CONFIG_ENV_IS_IN_NAND) +/* + * Environment is in NAND + */ + +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_RANGE 0x10000 +#define CONFIG_FSMTDBLK "/dev/mtdblock12 " + +#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \ + "0x80000 0x4C0000; " \ + "bootm 0x1600000" +#endif + +#define CONFIG_BOOTARGS_NFS "root=/dev/nfs ip=dhcp " \ + "console=ttyAMA0 init=/bin/sh" +#define CONFIG_BOOTARGS "console=ttyAMA0 mem=128M " \ + "root="CONFIG_FSMTDBLK \ + "rootfstype=jffs2" + +#define CONFIG_ENV_SIZE 0x02000 + +/* Miscellaneous configurable options */ +#define CONFIG_ARCH_CPU_INIT 1 +#define CONFIG_DISPLAY_CPUINFO 1 + +#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_PROMPT \ + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay + +#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x04000000 +#define CONFIG_SYS_MALLOC_LEN (1024*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_IDENT_STRING "-SPEAr" +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "u-boot> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 +#define CONFIG_SYS_64BIT_VSPRINTF 1 + +#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_MAXSIZE 0x40000000 + +#endif -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 17/18] SPEAr : Removing extraneous code 2010-06-29 5:23 ` [U-Boot] [PATCH v5 16/18] SPEAr : spear1300 SoC " Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 18/18] SPEAr : USB device controller bugfixes Vipin KUMAR 0 siblings, 1 reply; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> This sub-patch removes extraneous code from the spear platform code Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- include/configs/spear-common.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index c03520b..1f7aff7 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -57,7 +57,6 @@ /* Timer, HZ specific defines */ #define CONFIG_SYS_HZ (1000) -#define CONFIG_SYS_HZ_CLOCK (8300000) /* Flash configuration */ #if defined(CONFIG_FLASH_PNOR) -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 18/18] SPEAr : USB device controller bugfixes 2010-06-29 5:23 ` [U-Boot] [PATCH v5 17/18] SPEAr : Removing extraneous code Vipin KUMAR @ 2010-06-29 5:23 ` Vipin KUMAR 0 siblings, 0 replies; 23+ messages in thread From: Vipin KUMAR @ 2010-06-29 5:23 UTC (permalink / raw) To: u-boot From: Vipin KUMAR <vipin.kumar@st.com> This patch fixes a few bugs in USB device controller driver. The fixes are as follows 1. Adding error condition checks eg. NULL return 2. Endpoint other than endpoint 0 (control endpoint) are initialized only if usb state machine reaches STATE_ADDRESSED or above 3. Zero length packet handling corrected 4. Dead code removed 5. Bulk out endpoint returns after servicing 1 interrupt and returns back to service if more interrupts are pending Signed-off-by: Vipin Kumar <vipin.kumar@st.com> --- drivers/usb/gadget/designware_udc.c | 59 ++++++++++++++++++++++------------ 1 files changed, 38 insertions(+), 21 deletions(-) diff --git a/drivers/usb/gadget/designware_udc.c b/drivers/usb/gadget/designware_udc.c index aee44aa..3c20f3d 100644 --- a/drivers/usb/gadget/designware_udc.c +++ b/drivers/usb/gadget/designware_udc.c @@ -497,16 +497,24 @@ static void dw_udc_epn_tx(int ep) { struct usb_endpoint_instance *endpoint = dw_find_ep(ep); + if (!endpoint) + return; + /* * We need to transmit a terminating zero-length packet now if * we have sent all of the data in this URB and the transfer * size was an exact multiple of the packet size. */ - if (endpoint && endpoint->tx_urb && endpoint->tx_urb->actual_length) { - if (endpoint->last == endpoint->tx_packetSize) { - /* handle zero length packet here */ - writel(0x0, &inep_regs_p[ep].write_done); - } + if (endpoint->tx_urb && + (endpoint->last == endpoint->tx_packetSize) && + (endpoint->tx_urb->actual_length - endpoint->sent - + endpoint->last == 0)) { + /* handle zero length packet here */ + writel(0x0, &inep_regs_p[ep].write_done); + + } + + if (endpoint->tx_urb && endpoint->tx_urb->actual_length) { /* retire the data that was just sent */ usbd_tx_complete(endpoint); /* @@ -548,8 +556,6 @@ int udc_init(void) readl(&plug_regs_p->plug_pending); - udc_disconnect(); - for (i = 0; i < UDC_INIT_MDELAY; i++) udelay(1000); @@ -561,10 +567,9 @@ int udc_init(void) writel(~0x0, &udc_regs_p->endp_int_mask); writel(DEV_CONF_FS_SPEED | DEV_CONF_REMWAKEUP | DEV_CONF_SELFPOW | - /* Dev_Conf_SYNCFRAME | */ DEV_CONF_PHYINT_16, &udc_regs_p->dev_conf); - writel(0x0, &udc_regs_p->dev_cntl); + writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl); /* Clear all interrupts pending */ writel(DEV_INT_MSK, &udc_regs_p->dev_int); @@ -588,6 +593,9 @@ void udc_setup_ep(struct usb_device_instance *device, char *tt; u32 endp_intmask; + if ((ep != 0) && (udc_device->device_state < STATE_ADDRESSED)) + return; + tt = getenv("usbtty"); if (!tt) tt = "generic"; @@ -647,9 +655,6 @@ void udc_setup_ep(struct usb_device_instance *device, writel(packet_size | ((buffer_size / sizeof(int)) << 16), &out_p->endp_maxpacksize); - writel((packet_size << 19) | ENDP_EPTYPE_CNTL, - &udc_regs_p->udc_endp_reg[ep_num]); - } else if ((ep_addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) { /* Setup the IN endpoint */ writel(0x0, &in_p->endp_status); @@ -708,7 +713,17 @@ void udc_setup_ep(struct usb_device_instance *device, /* Turn on the USB connection by enabling the pullup resistor */ void udc_connect(void) { - u32 plug_st; + u32 plug_st, dev_cntl; + + dev_cntl = readl(&udc_regs_p->dev_cntl); + dev_cntl |= DEV_CNTL_SOFTDISCONNECT; + writel(dev_cntl, &udc_regs_p->dev_cntl); + + udelay(1000); + + dev_cntl = readl(&udc_regs_p->dev_cntl); + dev_cntl &= ~DEV_CNTL_SOFTDISCONNECT; + writel(dev_cntl, &udc_regs_p->dev_cntl); plug_st = readl(&plug_regs_p->plug_state); plug_st &= ~(PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); @@ -720,6 +735,8 @@ void udc_disconnect(void) { u32 plug_st; + writel(DEV_CNTL_SOFTDISCONNECT, &udc_regs_p->dev_cntl); + plug_st = readl(&plug_regs_p->plug_state); plug_st |= (PLUG_STATUS_PHY_RESET | PLUG_STATUS_PHY_MODE); writel(plug_st, &plug_regs_p->plug_state); @@ -789,11 +806,6 @@ void dw_udc_plug_irq(void) UDCDBG("device attached and powered"); udc_state_transition(udc_device->device_state, STATE_POWERED); } else { - /* - * USB cable detached - * Reset the PHY and switch the mode. - */ - udc_disconnect(); writel(~0x0, &udc_regs_p->dev_int_mask); UDCDBG("device detached or unpowered"); @@ -809,13 +821,18 @@ void dw_udc_dev_irq(void) if (readl(&udc_regs_p->dev_int) & DEV_INT_USBRESET) { writel(~0x0, &udc_regs_p->endp_int_mask); - udc_connect(); - writel(readl(&inep_regs_p[0].endp_cntl) | ENDP_CNTL_FLUSH, &inep_regs_p[0].endp_cntl); writel(DEV_INT_USBRESET, &udc_regs_p->dev_int); + /* + * This endpoint0 specific register can be programmed only + * after the phy clock is initialized + */ + writel((EP0_MAX_PACKET_SIZE << 19) | ENDP_EPTYPE_CNTL, + &udc_regs_p->udc_endp_reg[0]); + UDCDBG("device reset in progess"); udc_state_transition(udc_device->device_state, STATE_DEFAULT); } @@ -902,7 +919,7 @@ void dw_udc_endpoint_irq(void) writel(ENDP0_INT_CTRLIN, &udc_regs_p->endp_int); } - while (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) { + if (readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK) { u32 epnum = 0; u32 ep_int = readl(&udc_regs_p->endp_int) & ENDP_INT_NONISOOUT_MSK; -- 1.6.0.2 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 10/18] SPEAr : Configuring FSMC driver for NAND interface 2010-06-29 5:23 ` [U-Boot] [PATCH v5 10/18] SPEAr : Configuring FSMC driver for NAND interface Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 11/18] SPEAr : i2c driver moved completely into drivers/i2c Vipin KUMAR @ 2010-06-29 18:36 ` Scott Wood 1 sibling, 0 replies; 23+ messages in thread From: Scott Wood @ 2010-06-29 18:36 UTC (permalink / raw) To: u-boot On Tue, Jun 29, 2010 at 10:53:38AM +0530, Vipin KUMAR wrote: > From: Vipin KUMAR <vipin.kumar@st.com> > > Since FSMC is a standard IP and it supports different memory interfaces, it > is supported independent of spear platform and spear is configured to use that > driver for interfacing with the NAND device > > Spear platform uses generic FSMC driver and spear specific files i.e > drivers/mtd/nand/spr_nand.c, arch/arm/include/asm/arch-spear/spr_nand.h are > removed > > Signed-off-by: Vipin Kumar <vipin.kumar@st.com> > --- > arch/arm/include/asm/arch-spear/hardware.h | 8 +- > arch/arm/include/asm/arch-spear/spr_nand.h | 57 ------------- > board/spear/spear300/spear300.c | 7 +- > board/spear/spear310/spear310.c | 7 +- > board/spear/spear320/spear320.c | 7 +- > board/spear/spear600/spear600.c | 7 +- > drivers/mtd/nand/Makefile | 1 - > drivers/mtd/nand/spr_nand.c | 124 ---------------------------- > include/configs/spear-common.h | 2 +- > include/configs/spear3xx.h | 4 + > include/configs/spear6xx.h | 3 + > 11 files changed, 28 insertions(+), 199 deletions(-) > delete mode 100644 arch/arm/include/asm/arch-spear/spr_nand.h > delete mode 100644 drivers/mtd/nand/spr_nand.c Acked-by: Scott Wood <scottwood@freescale.com> -Scott ^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 09/18] SPEAr : FSMC driver support added 2010-06-29 5:23 ` [U-Boot] [PATCH v5 09/18] SPEAr : FSMC driver support added Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 10/18] SPEAr : Configuring FSMC driver for NAND interface Vipin KUMAR @ 2010-06-29 18:35 ` Scott Wood 1 sibling, 0 replies; 23+ messages in thread From: Scott Wood @ 2010-06-29 18:35 UTC (permalink / raw) To: u-boot On Tue, Jun 29, 2010 at 10:53:37AM +0530, Vipin KUMAR wrote: > From: Vipin KUMAR <vipin.kumar@st.com> > > Flexible static memory controller is a peripheral provided by ST, > which controls the access to NAND chips along with many other > memory device chips eg NOR, SRAM. > > This patch adds the driver support for FSMC controller interfacing > with NAND memory. > > Signed-off-by: Vipin Kumar <vipin.kumar@st.com> > --- > drivers/mtd/nand/Makefile | 1 + > drivers/mtd/nand/fsmc_nand.c | 366 +++++++++++++++++++++++++++++++++++++++++ > include/linux/mtd/fsmc_nand.h | 104 ++++++++++++ > 3 files changed, 471 insertions(+), 0 deletions(-) > create mode 100644 drivers/mtd/nand/fsmc_nand.c > create mode 100644 include/linux/mtd/fsmc_nand.h Acked-by: Scott Wood <scottwood@freescale.com> -Scott ^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 06/18] SPEAr : Network driver support added 2010-06-29 5:23 ` [U-Boot] [PATCH v5 06/18] SPEAr : Network driver support added Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 07/18] SPEAr : Network support configured for spear SoCs Vipin KUMAR @ 2010-07-12 7:07 ` Ben Warren 1 sibling, 0 replies; 23+ messages in thread From: Ben Warren @ 2010-07-12 7:07 UTC (permalink / raw) To: u-boot Hi Vipin, On 6/28/2010 10:23 PM, Vipin KUMAR wrote: > From: Vipin KUMAR<vipin.kumar@st.com> > > Designware network driver support added. > This is a Synopsys ethernet controller > > Signed-off-by: Vipin Kumar<vipin.kumar@st.com> > --- Applied to net repo. thanks, Ben ^ permalink raw reply [flat|nested] 23+ messages in thread
* [U-Boot] [PATCH v5 00/18] Network support for spear platforms and SPEAr1300 2010-06-29 5:23 [U-Boot] [PATCH v5 00/18] Network support for spear platforms and SPEAr1300 Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 01/18] change_bit routine defined Vipin KUMAR @ 2010-06-30 13:35 ` Armando VISCONTI 1 sibling, 0 replies; 23+ messages in thread From: Armando VISCONTI @ 2010-06-30 13:35 UTC (permalink / raw) To: u-boot Tom, Wolfgang, THis time everything should be ok. Thks for your attention, Arm Vipin KUMAR wrote: > Dear Wolfgang, Tom, > > The following set of patches is the fifth iteration of patches for the following > changes > -> Network device driver for synopsys designware peripheral > -> SPEAr1300 SoC support > -> A few other misc changes and bugfixes > > These also include the feedbacks given by Tom and Ben > These set of patches are rebased on e5ed138a23923ebe61843244748d98d3dbc04777 > > Please include these changes in the mainline u-boot > > Regards > Vipin > > Vipin KUMAR (18): > change_bit routine defined > SPEAr : SMI erase and write timeouts increased > SPEAr : Placing ethaddr write and read within CONFIG_CMD_NET > SPEAr : Reducing the max RAM size to 128MB > SPEAr : Basic arch related support added for SPEAr SoCs > SPEAr : Network driver support added > SPEAr : Network support configured for spear SoCs > SPEAr : macb driver support added for spear310 and spear320 > SPEAr : FSMC driver support added > SPEAr : Configuring FSMC driver for NAND interface > SPEAr : i2c driver moved completely into drivers/i2c > SPEAr : smi driver moved completely into drivers/mtd > SPEAr : USB Device Controller driver support added > SPEAr : Supporting various configurations for spear3xx and spear6xx > boards > SPEAr : Basic spear1300 architecture support added > SPEAr : spear1300 SoC support added > SPEAr : Removing extraneous code > SPEAr : USB device controller bugfixes > > MAINTAINERS | 1 + > MAKEALL | 1 + > Makefile | 28 +- > arch/arm/cpu/arm926ejs/spear/Makefile | 3 +- > arch/arm/cpu/arm926ejs/spear/cpu.c | 78 +++ > arch/arm/cpu/arm_cortexa8/spear13xx/Makefile | 52 ++ > arch/arm/cpu/arm_cortexa8/spear13xx/cache.S | 114 +++++ > arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c | 96 ++++ > .../arm_cortexa8/spear13xx/reset.c} | 52 +-- > arch/arm/cpu/arm_cortexa8/spear13xx/timer.c | 138 +++++ > .../arm/include/asm/arch-spear/clk.h | 26 +- > arch/arm/include/asm/arch-spear/hardware.h | 16 +- > arch/arm/include/asm/arch-spear/spr_misc.h | 5 + > .../arm/include/asm/arch-spear13xx/hardware.h | 33 +- > arch/arm/include/asm/arch-spear13xx/spr_gpt.h | 85 ++++ > arch/arm/include/asm/arch-spear13xx/spr_misc.h | 317 ++++++++++++ > .../arm/include/asm/arch-spear13xx/sys_proto.h | 29 +- > arch/arm/include/asm/bitops.h | 11 +- > board/spear/common/Makefile | 10 +- > board/spear/common/spr_misc.c | 32 +- > board/spear/spear1300/Makefile | 51 ++ > board/spear/spear1300/config.mk | 28 + > board/spear/spear1300/spear1300.c | 88 ++++ > .../spear/spear1300/spr_lowlevel_init.S | 35 +- > board/spear/spear300/config.mk | 11 - > board/spear/spear300/spear300.c | 18 +- > board/spear/spear310/config.mk | 11 - > board/spear/spear310/spear310.c | 35 ++- > board/spear/spear320/config.mk | 11 - > board/spear/spear320/spear320.c | 23 +- > board/spear/spear600/config.mk | 11 - > board/spear/spear600/spear600.c | 18 +- > doc/README.designware_eth | 25 + > doc/README.spear | 46 ++- > drivers/i2c/Makefile | 2 +- > drivers/i2c/{spr_i2c.c => designware_i2c.c} | 4 +- > .../spr_i2c.h => drivers/i2c/designware_i2c.h | 6 +- > drivers/mtd/Makefile | 2 +- > drivers/mtd/nand/Makefile | 2 +- > drivers/mtd/nand/fsmc_nand.c | 366 ++++++++++++++ > drivers/mtd/nand/spr_nand.c | 124 ----- > drivers/mtd/{spr_smi.c => st_smi.c} | 59 ++- > .../arch-spear/spr_smi.h => drivers/mtd/st_smi.h | 8 +- > drivers/net/Makefile | 1 + > drivers/net/designware.c | 531 ++++++++++++++++++++ > drivers/net/designware.h | 264 ++++++++++ > drivers/serial/usbtty.h | 4 +- > drivers/usb/gadget/Makefile | 2 +- > drivers/usb/gadget/{spr_udc.c => designware_udc.c} | 116 +++-- > include/configs/spear-common.h | 33 +- > include/configs/spear13xx_evb.h | 202 ++++++++ > include/configs/{spear3xx.h => spear3xx_evb.h} | 30 ++ > include/configs/{spear6xx.h => spear6xx_evb.h} | 13 + > include/linux/mtd/fsmc_nand.h | 104 ++++ > include/netdev.h | 1 + > include/usb/{spr_udc.h => designware_udc.h} | 6 +- > 56 files changed, 2997 insertions(+), 421 deletions(-) > create mode 100644 arch/arm/cpu/arm926ejs/spear/cpu.c > create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/Makefile > create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/cache.S > create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/cpu.c > rename arch/arm/{include/asm/arch-spear/spr_nand.h => cpu/arm_cortexa8/spear13xx/reset.c} (50%) > mode change 100644 => 100755 > create mode 100644 arch/arm/cpu/arm_cortexa8/spear13xx/timer.c > copy include/configs/spear6xx.h => arch/arm/include/asm/arch-spear/clk.h (64%) > copy include/configs/spear6xx.h => arch/arm/include/asm/arch-spear13xx/hardware.h (58%) > create mode 100644 arch/arm/include/asm/arch-spear13xx/spr_gpt.h > create mode 100644 arch/arm/include/asm/arch-spear13xx/spr_misc.h > copy include/configs/spear6xx.h => arch/arm/include/asm/arch-spear13xx/sys_proto.h (64%) > create mode 100644 board/spear/spear1300/Makefile > create mode 100644 board/spear/spear1300/config.mk > create mode 100644 board/spear/spear1300/spear1300.c > copy include/configs/spear6xx.h => board/spear/spear1300/spr_lowlevel_init.S (56%) > create mode 100644 doc/README.designware_eth > rename drivers/i2c/{spr_i2c.c => designware_i2c.c} (98%) > rename arch/arm/include/asm/arch-spear/spr_i2c.h => drivers/i2c/designware_i2c.h (98%) > create mode 100644 drivers/mtd/nand/fsmc_nand.c > delete mode 100644 drivers/mtd/nand/spr_nand.c > rename drivers/mtd/{spr_smi.c => st_smi.c} (94%) > rename arch/arm/include/asm/arch-spear/spr_smi.h => drivers/mtd/st_smi.h (96%) > create mode 100644 drivers/net/designware.c > create mode 100644 drivers/net/designware.h > rename drivers/usb/gadget/{spr_udc.c => designware_udc.c} (91%) > create mode 100644 include/configs/spear13xx_evb.h > rename include/configs/{spear3xx.h => spear3xx_evb.h} (85%) > rename include/configs/{spear6xx.h => spear6xx_evb.h} (82%) > create mode 100644 include/linux/mtd/fsmc_nand.h > rename include/usb/{spr_udc.h => designware_udc.h} (98%) > > > ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2010-07-12 7:07 UTC | newest] Thread overview: 23+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2010-06-29 5:23 [U-Boot] [PATCH v5 00/18] Network support for spear platforms and SPEAr1300 Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 01/18] change_bit routine defined Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 02/18] SPEAr : SMI erase and write timeouts increased Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 03/18] SPEAr : Placing ethaddr write and read within CONFIG_CMD_NET Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 04/18] SPEAr : Reducing the max RAM size to 128MB Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 05/18] SPEAr : Basic arch related support added for SPEAr SoCs Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 06/18] SPEAr : Network driver support added Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 07/18] SPEAr : Network support configured for spear SoCs Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 08/18] SPEAr : macb driver support added for spear310 and spear320 Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 09/18] SPEAr : FSMC driver support added Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 10/18] SPEAr : Configuring FSMC driver for NAND interface Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 11/18] SPEAr : i2c driver moved completely into drivers/i2c Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 12/18] SPEAr : smi driver moved completely into drivers/mtd Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 13/18] SPEAr : USB Device Controller driver support added Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 14/18] SPEAr : Supporting various configurations for spear3xx and spear6xx boards Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 15/18] SPEAr : Basic spear1300 architecture support added Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 16/18] SPEAr : spear1300 SoC " Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 17/18] SPEAr : Removing extraneous code Vipin KUMAR 2010-06-29 5:23 ` [U-Boot] [PATCH v5 18/18] SPEAr : USB device controller bugfixes Vipin KUMAR 2010-06-29 18:36 ` [U-Boot] [PATCH v5 10/18] SPEAr : Configuring FSMC driver for NAND interface Scott Wood 2010-06-29 18:35 ` [U-Boot] [PATCH v5 09/18] SPEAr : FSMC driver support added Scott Wood 2010-07-12 7:07 ` [U-Boot] [PATCH v5 06/18] SPEAr : Network " Ben Warren 2010-06-30 13:35 ` [U-Boot] [PATCH v5 00/18] Network support for spear platforms and SPEAr1300 Armando VISCONTI
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