[U-Boot] guys, can you see some init code for davinci's chipselect bit width driving DM9000A?

[U-Boot] guys, can you see some init code for davinci's chipselect bit width driving DM9000A?

[yaojin liu]

hi:
dm9000a works as 16bit bus width. however, i have not seen any init code for
the dm355's chipselect.
and by default ,the cs1 is 8bit bus width at reset. how doew it work?

[U-Boot] guys, can you see some init code for davinci's chipselect bit width driving DM9000A?

[Stefano Babic]

yaojin liu wrote:
> hi:
> dm9000a works as 16bit bus width. however, i have not seen any init code for
> the dm355's chipselect.
> and by default ,the cs1 is 8bit bus width at reset. how doew it work?

I think the setup is done by the UBL provided by TI. U-boot is a 3-rd
stage bootloader for DM355. The RBL (Rom Bootloader) loads the UBL from
storage, that sets up the required peripherals (RAM / AEMIF), and then
loads u-boot.

u-boot does not set the a2cr register in the AEMIF interface, but the
UBL has already configured it for 16-bit access.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
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[U-Boot] guys, can you see some init code for davinci's chipselect bit width driving DM9000A?

[yaojin liu]

thanks?you are right, it really init the chip through UBL.
BUT, there is also one question:
DM9000a 's driver has 8 bit accessing function:

#define CONFIG_DM9000_BASE    0x04000000
#define DM9000_IO            CONFIG_DM9000_BASE
#define DM9000_DATA        (CONFIG_DM9000_BASE+2) // (BA1,it's the 16bit
least significant bit (effective)  )
#define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
#define DM9000_inb(r) (*(volatile u8 *)r)
static u8 DM9000_ior(int reg)
{
    DM9000_outb(reg, DM9000_IO);
    return DM9000_inb(DM9000_DATA);
}

/*
   Write a byte to I/O port
*/
static void DM9000_iow(int reg, u8 value)
{
    DM9000_outb(reg, DM9000_IO);
    DM9000_outb(value, DM9000_DATA);
}
and the davinci's chipselect space is 16bit. when accessing it as 8bit ,the
last bit(may be A-2 ?) will be effective, but the least significant bit(BA1)
will not be effective, am i wrong? how does it work?

2010/7/19 Stefano Babic <sbabic@denx.de>

> yaojin liu wrote:
> > hi:
> > dm9000a works as 16bit bus width. however, i have not seen any init code
> for
> > the dm355's chipselect.
> > and by default ,the cs1 is 8bit bus width at reset. how doew it work?
>
> I think the setup is done by the UBL provided by TI. U-boot is a 3-rd
> stage bootloader for DM355. The RBL (Rom Bootloader) loads the UBL from
> storage, that sets up the required peripherals (RAM / AEMIF), and then
> loads u-boot.
>
> u-boot does not set the a2cr register in the AEMIF interface, but the
> UBL has already configured it for 16-bit access.
>
> Best regards,
> Stefano Babic
>
> --
> =====================================================================
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
> =====================================================================
>

[U-Boot] guys, can you see some init code for davinci's chipselect bit width driving DM9000A?

[Stefano Babic]

yaojin liu wrote:
> thanks?you are right, it really init the chip through UBL.
> BUT, there is also one question:
> DM9000a 's driver has 8 bit accessing function:
> 
> #define CONFIG_DM9000_BASE    0x04000000   
> #define DM9000_IO            CONFIG_DM9000_BASE
> #define DM9000_DATA        (CONFIG_DM9000_BASE+2) // (BA1,it's the 16bit
> least significant bit (effective)  )
> #define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
> #define DM9000_inb(r) (*(volatile u8 *)r)
> static u8 DM9000_ior(int reg)
> {
>     DM9000_outb(reg, DM9000_IO);
>     return DM9000_inb(DM9000_DATA);
> }
> 
> /*
>    Write a byte to I/O port
> */
> static void DM9000_iow(int reg, u8 value)
> {
>     DM9000_outb(reg, DM9000_IO);
>     DM9000_outb(value, DM9000_DATA);
> }
> and the davinci's chipselect space is 16bit. when accessing it as 8bit
> ,the last bit(may be A-2 ?) will be effective, but the least significant
> bit(BA1) will not be effective, am i wrong? how does it work?
> 

I think this is a no-problem, because the DM9000 has two separate area
for registers and data. As you check in the driver, the bus width is
checked and the driver has internal accessors (dm9000_outblk_*) to adapt
itself to the different bus size.

To access internal registers, it is required to write to DM9000_IO the
registers offset, and the DM9000 store the register index internally
that should be read/changed with the next access.  So registers are not
accessed directly, you have to program which you want. And the DM9000
takes the LSB of the data bus as register offset.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================